[AArch64] Tidy up in aarch64_mem_op_p().
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@ -1,3 +1,8 @@
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2015-03-23 Marcus Shawcroft <marcus.shawcroft@arm.com>
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(aarch64_mem_op_p): Update comment. Rename rtn to rt2.
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(aarch64_erratum_seqeunce): Rename rtn to rt2.
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2015-03-23 Marcus Shawcroft <marcus.shawcroft@arm.com>
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* elfnn-aarch64.c (elfNN_aarch64_write_section): Adjust layout.
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@ -2755,12 +2755,19 @@ group_sections (struct elf_aarch64_link_hash_table *htab,
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#define AARCH64_LDST_SIMD_S(insn) (((insn) & 0xbf9f0000) == 0x0d000000)
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#define AARCH64_LDST_SIMD_S_PI(insn) (((insn) & 0xbf800000) == 0x0d800000)
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/* Classify an INSN if it is indeed a load/store. Return TRUE if INSN
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is a load/store along with the Rt and Rtn. Return FALSE if not a
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load/store. */
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/* Classify an INSN if it is indeed a load/store.
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Return TRUE if INSN is a LD/ST instruction otherwise return FALSE.
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For scalar LD/ST instructions PAIR is FALSE, RT is returned and RT2
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is set equal to RT.
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For LD/ST pair instructions PAIR is TRUE, RT and RT2 are returned.
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*/
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static bfd_boolean
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aarch64_mem_op_p (uint32_t insn, unsigned int *rt, unsigned int *rtn,
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aarch64_mem_op_p (uint32_t insn, unsigned int *rt, unsigned int *rt2,
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bfd_boolean *pair, bfd_boolean *load)
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{
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uint32_t opcode;
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@ -2779,11 +2786,11 @@ aarch64_mem_op_p (uint32_t insn, unsigned int *rt, unsigned int *rtn,
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if (AARCH64_LDST_EX (insn))
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{
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*rt = AARCH64_RT (insn);
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*rtn = *rt;
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*rt2 = *rt;
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if (AARCH64_BIT (insn, 21) == 1)
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{
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*pair = TRUE;
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*rtn = AARCH64_RT2 (insn);
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*rt2 = AARCH64_RT2 (insn);
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}
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*load = AARCH64_LD (insn);
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return TRUE;
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@ -2795,7 +2802,7 @@ aarch64_mem_op_p (uint32_t insn, unsigned int *rt, unsigned int *rtn,
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{
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*pair = TRUE;
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*rt = AARCH64_RT (insn);
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*rtn = AARCH64_RT2 (insn);
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*rt2 = AARCH64_RT2 (insn);
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*load = AARCH64_LD (insn);
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return TRUE;
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}
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@ -2808,7 +2815,7 @@ aarch64_mem_op_p (uint32_t insn, unsigned int *rt, unsigned int *rtn,
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|| AARCH64_LDST_UIMM (insn))
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{
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*rt = AARCH64_RT (insn);
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*rtn = *rt;
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*rt2 = *rt;
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if (AARCH64_LDST_PCREL (insn))
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*load = TRUE;
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opc = AARCH64_BITS (insn, 22, 2);
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@ -2828,21 +2835,21 @@ aarch64_mem_op_p (uint32_t insn, unsigned int *rt, unsigned int *rtn,
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{
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case 0:
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case 2:
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*rtn = *rt + 3;
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*rt2 = *rt + 3;
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break;
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case 4:
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case 6:
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*rtn = *rt + 2;
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*rt2 = *rt + 2;
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break;
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case 7:
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*rtn = *rt;
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*rt2 = *rt;
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break;
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case 8:
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case 10:
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*rtn = *rt + 1;
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*rt2 = *rt + 1;
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break;
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default:
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@ -2862,21 +2869,21 @@ aarch64_mem_op_p (uint32_t insn, unsigned int *rt, unsigned int *rtn,
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case 0:
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case 2:
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case 4:
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*rtn = *rt + r;
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*rt2 = *rt + r;
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break;
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case 1:
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case 3:
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case 5:
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*rtn = *rt + (r == 0 ? 2 : 3);
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*rt2 = *rt + (r == 0 ? 2 : 3);
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break;
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case 6:
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*rtn = *rt + r;
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*rt2 = *rt + r;
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break;
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case 7:
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*rtn = *rt + (r == 0 ? 2 : 3);
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*rt2 = *rt + (r == 0 ? 2 : 3);
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break;
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default:
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@ -2922,7 +2929,7 @@ static bfd_boolean
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aarch64_erratum_sequence (uint32_t insn_1, uint32_t insn_2)
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{
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uint32_t rt;
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uint32_t rtn;
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uint32_t rt2;
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uint32_t rn;
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uint32_t rm;
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uint32_t ra;
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@ -2930,7 +2937,7 @@ aarch64_erratum_sequence (uint32_t insn_1, uint32_t insn_2)
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bfd_boolean load;
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if (aarch64_mlxl_p (insn_2)
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&& aarch64_mem_op_p (insn_1, &rt, &rtn, &pair, &load))
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&& aarch64_mem_op_p (insn_1, &rt, &rt2, &pair, &load))
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{
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/* Any SIMD memory op is independent of the subsequent MLA
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by definition of the erratum. */
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@ -2946,7 +2953,7 @@ aarch64_erratum_sequence (uint32_t insn_1, uint32_t insn_2)
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and this is not an erratum sequence. */
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if (load &&
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(rt == rn || rt == rm || rt == ra
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|| (pair && (rtn == rn || rtn == rm || rtn == ra))))
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|| (pair && (rt2 == rn || rt2 == rm || rt2 == ra))))
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return FALSE;
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/* We conservatively put out stubs for all other cases (including
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