aarch64: [SME] Add SME mode selection and state access instructions
This patch is adding new SME mode selection and state access instructions: * Add SMSTART and SMSTOP instructions. * Add SVCR system register. gas/ChangeLog: * config/tc-aarch64.c (parse_sme_sm_za): New parser. (parse_operands): New parser. * testsuite/gas/aarch64/sme-8-illegal.d: New test. * testsuite/gas/aarch64/sme-8-illegal.l: New test. * testsuite/gas/aarch64/sme-8-illegal.s: New test. * testsuite/gas/aarch64/sme-8.d: New test. * testsuite/gas/aarch64/sme-8.s: New test. include/ChangeLog: * opcode/aarch64.h (enum aarch64_opnd): New operand AARCH64_OPND_SME_SM_ZA. (enum aarch64_insn_class): New instruction classes sme_start and sme_stop. opcodes/ChangeLog: * aarch64-asm.c (aarch64_ins_pstatefield): New inserter. (aarch64_ins_sme_sm_za): New inserter. * aarch64-dis.c (aarch64_ext_imm): New extractor. (aarch64_ext_pstatefield): New extractor. (aarch64_ext_sme_sm_za): New extractor. * aarch64-opc.c (operand_general_constraint_met_p): New pstatefield value for SME instructions. (aarch64_print_operand): Printout for OPND_SME_SM_ZA. (SR_SME): New register SVCR. * aarch64-opc.h (F_REG_IN_CRM): New register endcoding. * aarch64-opc.h (F_IMM_IN_CRM): New immediate endcoding. (PSTATE_ENCODE_CRM): Encode CRm field. (PSTATE_DECODE_CRM): Decode CRm field. (PSTATE_ENCODE_CRM_IMM): Encode CRm immediate field. (PSTATE_DECODE_CRM_IMM): Decode CRm immediate field. (PSTATE_ENCODE_CRM_AND_IMM): Encode CRm and immediate field. * aarch64-tbl.h (struct aarch64_opcode): New SMSTART and SMSTOP instructions. aarch64-asm-2.c: Regenerate. aarch64-dis-2.c: Regenerate. aarch64-opc-2.c: Regenerate.
This commit is contained in:
Przemyslaw Wirkus
parent
01a4d08220
commit
3dd032c5fb
@ -4629,6 +4629,32 @@ parse_sme_za_array (char **str, int *imm)
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return regno;
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}
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/* Parse streaming mode operand for SMSTART and SMSTOP.
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{SM | ZA}
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Function returns 's' if SM or 'z' if ZM is parsed. Otherwise PARSE_FAIL.
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*/
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static int
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parse_sme_sm_za (char **str)
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{
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char *p, *q;
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p = q = *str;
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while (ISALPHA (*q))
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q++;
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if ((q - p != 2)
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|| (strncasecmp ("sm", p, 2) != 0 && strncasecmp ("za", p, 2) != 0))
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{
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set_syntax_error (_("expected SM or ZA operand"));
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return PARSE_FAIL;
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}
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*str = q;
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return TOLOWER (p[0]);
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}
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/* Parse a system register or a PSTATE field name for an MSR/MRS instruction.
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Returns the encoding for the option, or PARSE_FAIL.
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@ -7032,6 +7058,16 @@ parse_operands (char *str, const aarch64_opcode *opcode)
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/* No qualifier. */
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break;
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case AARCH64_OPND_SME_SM_ZA:
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/* { SM | ZA } */
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if ((val = parse_sme_sm_za (&str)) == PARSE_FAIL)
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{
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set_syntax_error (_("unknown or missing PSTATE field name"));
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goto failure;
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}
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info->reg.regno = val;
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break;
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case AARCH64_OPND_SVE_ADDR_RI_S4x16:
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case AARCH64_OPND_SVE_ADDR_RI_S4x32:
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case AARCH64_OPND_SVE_ADDR_RI_S4xVL:
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@ -7221,14 +7257,18 @@ parse_operands (char *str, const aarch64_opcode *opcode)
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}
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case AARCH64_OPND_PSTATEFIELD:
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if ((val = parse_sys_reg (&str, aarch64_pstatefield_hsh, 0, 1, NULL))
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== PARSE_FAIL)
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{
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set_syntax_error (_("unknown or missing PSTATE field name"));
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goto failure;
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}
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inst.base.operands[i].pstatefield = val;
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break;
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{
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uint32_t sysreg_flags;
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if ((val = parse_sys_reg (&str, aarch64_pstatefield_hsh, 0, 1,
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&sysreg_flags)) == PARSE_FAIL)
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{
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set_syntax_error (_("unknown or missing PSTATE field name"));
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goto failure;
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}
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inst.base.operands[i].pstatefield = val;
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inst.base.operands[i].sysreg.flags = sysreg_flags;
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break;
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}
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case AARCH64_OPND_SYSREG_IC:
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inst.base.operands[i].sysins_op =
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3
gas/testsuite/gas/aarch64/sme-8-illegal.d
Normal file
3
gas/testsuite/gas/aarch64/sme-8-illegal.d
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@ -0,0 +1,3 @@
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#as: -march=armv8-a+sme
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#source: sme-8-illegal.s
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#error_output: sme-8-illegal.l
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7
gas/testsuite/gas/aarch64/sme-8-illegal.l
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7
gas/testsuite/gas/aarch64/sme-8-illegal.l
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@ -0,0 +1,7 @@
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[^:]*: Assembler messages:
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[^:]*:[0-9]+: Error: unexpected characters following instruction -- `smstart x0'
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[^:]*:[0-9]+: Error: unexpected characters following instruction -- `smstart sa'
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[^:]*:[0-9]+: Error: unexpected characters following instruction -- `smstart zm'
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[^:]*:[0-9]+: Error: unexpected characters following instruction -- `smstop x0'
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[^:]*:[0-9]+: Error: unexpected characters following instruction -- `smstop sa'
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[^:]*:[0-9]+: Error: unexpected characters following instruction -- `smstop zm'
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9
gas/testsuite/gas/aarch64/sme-8-illegal.s
Normal file
9
gas/testsuite/gas/aarch64/sme-8-illegal.s
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@ -0,0 +1,9 @@
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/* Scalable Matrix Extension (SME). */
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smstart x0
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smstart sa
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smstart zm
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smstop x0
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smstop sa
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smstop zm
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27
gas/testsuite/gas/aarch64/sme-8.d
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27
gas/testsuite/gas/aarch64/sme-8.d
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@ -0,0 +1,27 @@
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#name: SME mode selection and state access instructions
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#as: -march=armv8-a+sme
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#objdump: -dr
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.*: file format .*
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Disassembly of section \.text:
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0+ <.*>:
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0: d53b4240 mrs x0, svcr
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4: d51b4240 msr svcr, x0
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8: d503427f smstop sm
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c: d503447f smstop za
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10: d503467f smstop
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14: d503437f smstart sm
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18: d503457f smstart za
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1c: d503477f smstart
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20: d503477f smstart
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24: d503437f smstart sm
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28: d503457f smstart za
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2c: d503437f smstart sm
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30: d503457f smstart za
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34: d503467f smstop
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38: d503427f smstop sm
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3c: d503447f smstop za
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40: d503427f smstop sm
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44: d503447f smstop za
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28
gas/testsuite/gas/aarch64/sme-8.s
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28
gas/testsuite/gas/aarch64/sme-8.s
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@ -0,0 +1,28 @@
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/* SME mode selection and state access instructions. */
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/* SVCR system register access. */
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mrs x0, svcr
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msr svcr, x0
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/* MSR SVCR Immediate access. */
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msr svcrsm, #0
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msr svcrza, #0
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msr svcrsmza, #0
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msr svcrsm, #1
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msr svcrza, #1
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msr svcrsmza, #1
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/* SMSTART. */
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smstart
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smstart sm
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smstart za
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smstart SM
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smstart ZA
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/* SMSTOP. */
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smstop
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smstop sm
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smstop za
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smstop SM
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smstop ZA
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@ -454,6 +454,7 @@ enum aarch64_opnd
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AARCH64_OPND_SME_ZA_HV_idx_ldstr, /* SME destination ZA tile vector. */
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AARCH64_OPND_SME_ZA_array, /* SME ZA[<Wv>{, #<imm>}]. */
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AARCH64_OPND_SME_ADDR_RI_U4xVL, /* SME [<Xn|SP>{, #<imm>, MUL VL}]. */
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AARCH64_OPND_SME_SM_ZA, /* SME {SM | ZA}. */
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AARCH64_OPND_TME_UIMM16, /* TME unsigned 16-bit immediate. */
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AARCH64_OPND_SM3_IMM2, /* SM3 encodes lane in bits [13, 14]. */
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};
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@ -621,6 +622,8 @@ enum aarch64_insn_class
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sme_misc,
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sme_ldr,
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sme_str,
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sme_start,
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sme_stop,
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sve_cpy,
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sve_index,
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sve_limm,
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@ -426,176 +426,176 @@ aarch64_find_real_opcode (const aarch64_opcode *opcode)
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case 1188: /* movz */
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value = 1188; /* --> movz. */
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break;
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case 1246: /* autibsp */
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case 1245: /* autibz */
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case 1244: /* autiasp */
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case 1243: /* autiaz */
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case 1242: /* pacibsp */
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case 1241: /* pacibz */
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case 1240: /* paciasp */
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case 1239: /* paciaz */
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case 1215: /* tsb */
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case 1214: /* psb */
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case 1213: /* esb */
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case 1212: /* autib1716 */
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case 1211: /* autia1716 */
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case 1210: /* pacib1716 */
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case 1209: /* pacia1716 */
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case 1208: /* xpaclri */
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case 1206: /* sevl */
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case 1205: /* sev */
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case 1204: /* wfi */
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case 1203: /* wfe */
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case 1202: /* yield */
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case 1201: /* bti */
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case 1200: /* csdb */
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case 1199: /* nop */
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case 1198: /* hint */
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value = 1198; /* --> hint. */
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case 1250: /* autibsp */
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case 1249: /* autibz */
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case 1248: /* autiasp */
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case 1247: /* autiaz */
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case 1246: /* pacibsp */
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case 1245: /* pacibz */
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case 1244: /* paciasp */
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case 1243: /* paciaz */
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case 1219: /* tsb */
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case 1218: /* psb */
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case 1217: /* esb */
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case 1216: /* autib1716 */
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case 1215: /* autia1716 */
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case 1214: /* pacib1716 */
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case 1213: /* pacia1716 */
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case 1212: /* xpaclri */
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case 1210: /* sevl */
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case 1209: /* sev */
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case 1208: /* wfi */
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case 1207: /* wfe */
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case 1206: /* yield */
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case 1205: /* bti */
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case 1204: /* csdb */
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case 1203: /* nop */
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case 1202: /* hint */
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value = 1202; /* --> hint. */
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break;
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case 1221: /* pssbb */
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case 1220: /* ssbb */
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case 1219: /* dfb */
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case 1217: /* dsb */
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value = 1217; /* --> dsb. */
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case 1225: /* pssbb */
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case 1224: /* ssbb */
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case 1223: /* dfb */
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case 1221: /* dsb */
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value = 1221; /* --> dsb. */
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break;
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case 1218: /* dsb */
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value = 1218; /* --> dsb. */
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case 1222: /* dsb */
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value = 1222; /* --> dsb. */
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break;
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case 1234: /* cpp */
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case 1233: /* dvp */
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case 1232: /* cfp */
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case 1229: /* tlbi */
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case 1228: /* ic */
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case 1227: /* dc */
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case 1226: /* at */
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case 1225: /* sys */
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value = 1225; /* --> sys. */
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case 1238: /* cpp */
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case 1237: /* dvp */
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case 1236: /* cfp */
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case 1233: /* tlbi */
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case 1232: /* ic */
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case 1231: /* dc */
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case 1230: /* at */
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case 1229: /* sys */
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value = 1229; /* --> sys. */
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break;
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case 1230: /* wfet */
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value = 1230; /* --> wfet. */
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case 1234: /* wfet */
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value = 1234; /* --> wfet. */
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break;
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case 1231: /* wfit */
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value = 1231; /* --> wfit. */
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case 1235: /* wfit */
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value = 1235; /* --> wfit. */
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break;
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case 2044: /* bic */
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case 1294: /* and */
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value = 1294; /* --> and. */
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case 2048: /* bic */
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case 1298: /* and */
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value = 1298; /* --> and. */
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break;
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case 1277: /* mov */
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case 1296: /* and */
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value = 1296; /* --> and. */
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case 1281: /* mov */
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case 1300: /* and */
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value = 1300; /* --> and. */
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break;
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case 1281: /* movs */
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case 1297: /* ands */
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value = 1297; /* --> ands. */
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case 1285: /* movs */
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case 1301: /* ands */
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value = 1301; /* --> ands. */
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break;
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case 2045: /* cmple */
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case 1332: /* cmpge */
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value = 1332; /* --> cmpge. */
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case 2049: /* cmple */
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case 1336: /* cmpge */
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value = 1336; /* --> cmpge. */
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break;
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case 2048: /* cmplt */
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case 1335: /* cmpgt */
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value = 1335; /* --> cmpgt. */
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case 2052: /* cmplt */
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case 1339: /* cmpgt */
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value = 1339; /* --> cmpgt. */
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break;
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case 2046: /* cmplo */
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case 1337: /* cmphi */
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value = 1337; /* --> cmphi. */
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case 2050: /* cmplo */
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case 1341: /* cmphi */
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value = 1341; /* --> cmphi. */
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break;
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case 2047: /* cmpls */
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case 1340: /* cmphs */
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value = 1340; /* --> cmphs. */
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break;
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case 1274: /* mov */
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case 1362: /* cpy */
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value = 1362; /* --> cpy. */
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break;
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case 1276: /* mov */
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case 1363: /* cpy */
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value = 1363; /* --> cpy. */
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break;
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case 2055: /* fmov */
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case 1279: /* mov */
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case 1364: /* cpy */
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value = 1364; /* --> cpy. */
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break;
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case 1269: /* mov */
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case 1376: /* dup */
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value = 1376; /* --> dup. */
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break;
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case 1271: /* mov */
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case 1268: /* mov */
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case 1377: /* dup */
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value = 1377; /* --> dup. */
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break;
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case 2054: /* fmov */
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case 1273: /* mov */
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case 1378: /* dup */
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value = 1378; /* --> dup. */
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break;
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case 1272: /* mov */
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case 1379: /* dupm */
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value = 1379; /* --> dupm. */
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break;
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case 2049: /* eon */
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case 1381: /* eor */
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value = 1381; /* --> eor. */
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break;
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case 1282: /* not */
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case 1383: /* eor */
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value = 1383; /* --> eor. */
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break;
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case 1283: /* nots */
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case 1384: /* eors */
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value = 1384; /* --> eors. */
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break;
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case 2050: /* facle */
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case 1389: /* facge */
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value = 1389; /* --> facge. */
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break;
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case 2051: /* faclt */
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case 1390: /* facgt */
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value = 1390; /* --> facgt. */
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break;
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case 2052: /* fcmle */
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case 1403: /* fcmge */
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value = 1403; /* --> fcmge. */
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break;
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case 2053: /* fcmlt */
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case 1405: /* fcmgt */
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value = 1405; /* --> fcmgt. */
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break;
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case 1266: /* fmov */
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case 1411: /* fcpy */
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value = 1411; /* --> fcpy. */
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break;
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case 1265: /* fmov */
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case 1434: /* fdup */
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value = 1434; /* --> fdup. */
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break;
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case 1267: /* mov */
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case 1765: /* orr */
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value = 1765; /* --> orr. */
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break;
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case 2056: /* orn */
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case 1766: /* orr */
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value = 1766; /* --> orr. */
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break;
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case 1270: /* mov */
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case 1768: /* orr */
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value = 1768; /* --> orr. */
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break;
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case 1280: /* movs */
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case 1769: /* orrs */
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value = 1769; /* --> orrs. */
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break;
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case 1275: /* mov */
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case 1831: /* sel */
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value = 1831; /* --> sel. */
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case 2051: /* cmpls */
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case 1344: /* cmphs */
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value = 1344; /* --> cmphs. */
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break;
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case 1278: /* mov */
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case 1832: /* sel */
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value = 1832; /* --> sel. */
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case 1366: /* cpy */
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value = 1366; /* --> cpy. */
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break;
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case 1280: /* mov */
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case 1367: /* cpy */
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value = 1367; /* --> cpy. */
|
||||
break;
|
||||
case 2059: /* fmov */
|
||||
case 1283: /* mov */
|
||||
case 1368: /* cpy */
|
||||
value = 1368; /* --> cpy. */
|
||||
break;
|
||||
case 1273: /* mov */
|
||||
case 1380: /* dup */
|
||||
value = 1380; /* --> dup. */
|
||||
break;
|
||||
case 1275: /* mov */
|
||||
case 1272: /* mov */
|
||||
case 1381: /* dup */
|
||||
value = 1381; /* --> dup. */
|
||||
break;
|
||||
case 2058: /* fmov */
|
||||
case 1277: /* mov */
|
||||
case 1382: /* dup */
|
||||
value = 1382; /* --> dup. */
|
||||
break;
|
||||
case 1276: /* mov */
|
||||
case 1383: /* dupm */
|
||||
value = 1383; /* --> dupm. */
|
||||
break;
|
||||
case 2053: /* eon */
|
||||
case 1385: /* eor */
|
||||
value = 1385; /* --> eor. */
|
||||
break;
|
||||
case 1286: /* not */
|
||||
case 1387: /* eor */
|
||||
value = 1387; /* --> eor. */
|
||||
break;
|
||||
case 1287: /* nots */
|
||||
case 1388: /* eors */
|
||||
value = 1388; /* --> eors. */
|
||||
break;
|
||||
case 2054: /* facle */
|
||||
case 1393: /* facge */
|
||||
value = 1393; /* --> facge. */
|
||||
break;
|
||||
case 2055: /* faclt */
|
||||
case 1394: /* facgt */
|
||||
value = 1394; /* --> facgt. */
|
||||
break;
|
||||
case 2056: /* fcmle */
|
||||
case 1407: /* fcmge */
|
||||
value = 1407; /* --> fcmge. */
|
||||
break;
|
||||
case 2057: /* fcmlt */
|
||||
case 1409: /* fcmgt */
|
||||
value = 1409; /* --> fcmgt. */
|
||||
break;
|
||||
case 1270: /* fmov */
|
||||
case 1415: /* fcpy */
|
||||
value = 1415; /* --> fcpy. */
|
||||
break;
|
||||
case 1269: /* fmov */
|
||||
case 1438: /* fdup */
|
||||
value = 1438; /* --> fdup. */
|
||||
break;
|
||||
case 1271: /* mov */
|
||||
case 1769: /* orr */
|
||||
value = 1769; /* --> orr. */
|
||||
break;
|
||||
case 2060: /* orn */
|
||||
case 1770: /* orr */
|
||||
value = 1770; /* --> orr. */
|
||||
break;
|
||||
case 1274: /* mov */
|
||||
case 1772: /* orr */
|
||||
value = 1772; /* --> orr. */
|
||||
break;
|
||||
case 1284: /* movs */
|
||||
case 1773: /* orrs */
|
||||
value = 1773; /* --> orrs. */
|
||||
break;
|
||||
case 1279: /* mov */
|
||||
case 1835: /* sel */
|
||||
value = 1835; /* --> sel. */
|
||||
break;
|
||||
case 1282: /* mov */
|
||||
case 1836: /* sel */
|
||||
value = 1836; /* --> sel. */
|
||||
break;
|
||||
default: return NULL;
|
||||
}
|
||||
@ -675,7 +675,7 @@ aarch64_insert_operand (const aarch64_operand *self,
|
||||
case 33:
|
||||
case 34:
|
||||
case 35:
|
||||
case 220:
|
||||
case 221:
|
||||
return aarch64_ins_reglane (self, info, code, inst, errors);
|
||||
case 36:
|
||||
return aarch64_ins_reglist (self, info, code, inst, errors);
|
||||
@ -721,7 +721,7 @@ aarch64_insert_operand (const aarch64_operand *self,
|
||||
case 189:
|
||||
case 190:
|
||||
case 215:
|
||||
case 219:
|
||||
case 220:
|
||||
return aarch64_ins_imm (self, info, code, inst, errors);
|
||||
case 44:
|
||||
case 45:
|
||||
@ -889,6 +889,8 @@ aarch64_insert_operand (const aarch64_operand *self,
|
||||
return aarch64_ins_sme_za_array (self, info, code, inst, errors);
|
||||
case 218:
|
||||
return aarch64_ins_sme_addr_ri_u4xvl (self, info, code, inst, errors);
|
||||
case 219:
|
||||
return aarch64_ins_sme_sm_za (self, info, code, inst, errors);
|
||||
default: assert (0); abort ();
|
||||
}
|
||||
}
|
||||
|
||||
@ -848,6 +848,10 @@ aarch64_ins_pstatefield (const aarch64_operand *self ATTRIBUTE_UNUSED,
|
||||
/* op1:op2 */
|
||||
insert_fields (code, info->pstatefield, inst->opcode->mask, 2,
|
||||
FLD_op2, FLD_op1);
|
||||
|
||||
/* Extra CRm mask. */
|
||||
if (info->sysreg.flags | F_REG_IN_CRM)
|
||||
insert_field (FLD_CRm, code, PSTATE_DECODE_CRM (info->sysreg.flags), 0);
|
||||
return true;
|
||||
}
|
||||
|
||||
@ -1427,6 +1431,27 @@ aarch64_ins_sme_addr_ri_u4xvl (const aarch64_operand *self,
|
||||
return true;
|
||||
}
|
||||
|
||||
/* Encode in SMSTART and SMSTOP {SM | ZA } mode. */
|
||||
bool
|
||||
aarch64_ins_sme_sm_za (const aarch64_operand *self,
|
||||
const aarch64_opnd_info *info,
|
||||
aarch64_insn *code,
|
||||
const aarch64_inst *inst ATTRIBUTE_UNUSED,
|
||||
aarch64_operand_error *errors ATTRIBUTE_UNUSED)
|
||||
{
|
||||
aarch64_insn fld_crm;
|
||||
/* Set CRm[3:1] bits. */
|
||||
if (info->reg.regno == 's')
|
||||
fld_crm = 0x02 ; /* SVCRSM. */
|
||||
else if (info->reg.regno == 'z')
|
||||
fld_crm = 0x04; /* SVCRZA. */
|
||||
else
|
||||
assert (0);
|
||||
|
||||
insert_field (self->fields[0], code, fld_crm, 0);
|
||||
return true;
|
||||
}
|
||||
|
||||
/* Miscellaneous encoding functions. */
|
||||
|
||||
/* Encode size[0], i.e. bit 22, for
|
||||
|
||||
@ -102,6 +102,7 @@ AARCH64_DECL_OPD_INSERTER (ins_sme_za_hv_tiles);
|
||||
AARCH64_DECL_OPD_INSERTER (ins_sme_za_list);
|
||||
AARCH64_DECL_OPD_INSERTER (ins_sme_za_array);
|
||||
AARCH64_DECL_OPD_INSERTER (ins_sme_addr_ri_u4xvl);
|
||||
AARCH64_DECL_OPD_INSERTER (ins_sme_sm_za);
|
||||
AARCH64_DECL_OPD_INSERTER (ins_imm_rotate1);
|
||||
AARCH64_DECL_OPD_INSERTER (ins_imm_rotate2);
|
||||
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -664,7 +664,7 @@ aarch64_ext_shll_imm (const aarch64_operand *self ATTRIBUTE_UNUSED,
|
||||
bool
|
||||
aarch64_ext_imm (const aarch64_operand *self, aarch64_opnd_info *info,
|
||||
const aarch64_insn code,
|
||||
const aarch64_inst *inst ATTRIBUTE_UNUSED,
|
||||
const aarch64_inst *inst,
|
||||
aarch64_operand_error *errors ATTRIBUTE_UNUSED)
|
||||
{
|
||||
uint64_t imm;
|
||||
@ -682,6 +682,10 @@ aarch64_ext_imm (const aarch64_operand *self, aarch64_opnd_info *info,
|
||||
if (info->type == AARCH64_OPND_ADDR_ADRP)
|
||||
imm <<= 12;
|
||||
|
||||
if (inst->operands[0].type == AARCH64_OPND_PSTATEFIELD
|
||||
&& inst->operands[0].sysreg.flags & F_IMM_IN_CRM)
|
||||
imm &= PSTATE_DECODE_CRM_IMM (inst->operands[0].sysreg.flags);
|
||||
|
||||
info->imm.value = imm;
|
||||
return true;
|
||||
}
|
||||
@ -1226,11 +1230,20 @@ aarch64_ext_pstatefield (const aarch64_operand *self ATTRIBUTE_UNUSED,
|
||||
aarch64_operand_error *errors ATTRIBUTE_UNUSED)
|
||||
{
|
||||
int i;
|
||||
aarch64_insn fld_crm = extract_field (FLD_CRm, code, 0);
|
||||
/* op1:op2 */
|
||||
info->pstatefield = extract_fields (code, 0, 2, FLD_op1, FLD_op2);
|
||||
for (i = 0; aarch64_pstatefields[i].name != NULL; ++i)
|
||||
if (aarch64_pstatefields[i].value == (aarch64_insn)info->pstatefield)
|
||||
return true;
|
||||
{
|
||||
/* PSTATEFIELD name can be encoded partially in CRm[3:1]. */
|
||||
uint32_t flags = aarch64_pstatefields[i].flags;
|
||||
if ((flags & F_REG_IN_CRM)
|
||||
&& ((fld_crm & 0xe) != PSTATE_DECODE_CRM (flags)))
|
||||
continue;
|
||||
info->sysreg.flags = flags;
|
||||
return true;
|
||||
}
|
||||
/* Reserved value in <pstatefield>. */
|
||||
return false;
|
||||
}
|
||||
@ -1856,6 +1869,27 @@ aarch64_ext_sme_addr_ri_u4xvl (const aarch64_operand *self,
|
||||
return true;
|
||||
}
|
||||
|
||||
/* Decode {SM|ZA} filed for SMSTART and SMSTOP instructions. */
|
||||
bool
|
||||
aarch64_ext_sme_sm_za (const aarch64_operand *self,
|
||||
aarch64_opnd_info *info, aarch64_insn code,
|
||||
const aarch64_inst *inst ATTRIBUTE_UNUSED,
|
||||
aarch64_operand_error *errors ATTRIBUTE_UNUSED)
|
||||
{
|
||||
info->pstatefield = 0x1b;
|
||||
aarch64_insn fld_crm = extract_field (self->fields[0], code, 0);
|
||||
fld_crm >>= 1; /* CRm[3:1]. */
|
||||
|
||||
if (fld_crm == 0x1)
|
||||
info->reg.regno = 's';
|
||||
else if (fld_crm == 0x2)
|
||||
info->reg.regno = 'z';
|
||||
else
|
||||
assert (0);
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
/* Decode Zn[MM], where MM has a 7-bit triangular encoding. The fields
|
||||
array specifies which field to use for Zn. MM is encoded in the
|
||||
concatenation of imm5 and SVE_tszh, with imm5 being the less
|
||||
|
||||
@ -126,6 +126,7 @@ AARCH64_DECL_OPD_EXTRACTOR (ext_sme_za_hv_tiles);
|
||||
AARCH64_DECL_OPD_EXTRACTOR (ext_sme_za_list);
|
||||
AARCH64_DECL_OPD_EXTRACTOR (ext_sme_za_array);
|
||||
AARCH64_DECL_OPD_EXTRACTOR (ext_sme_addr_ri_u4xvl);
|
||||
AARCH64_DECL_OPD_EXTRACTOR (ext_sme_sm_za);
|
||||
AARCH64_DECL_OPD_EXTRACTOR (ext_imm_rotate1);
|
||||
AARCH64_DECL_OPD_EXTRACTOR (ext_imm_rotate2);
|
||||
|
||||
|
||||
@ -243,6 +243,7 @@ const struct aarch64_operand aarch64_operands[] =
|
||||
{AARCH64_OPND_CLASS_SVE_REG, "SME_ZA_HV_idx_ldstr", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_size_10,FLD_index2,FLD_SME_V,FLD_SME_Rv,FLD_imm4_2}, "an SME horizontal or vertical vector access register"},
|
||||
{AARCH64_OPND_CLASS_SVE_REG, "SME_ZA_array", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Rv,FLD_imm4_2}, "ZA array"},
|
||||
{AARCH64_OPND_CLASS_ADDRESS, "SME_ADDR_RI_U4xVL", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_imm4_2}, "memory offset"},
|
||||
{AARCH64_OPND_CLASS_ADDRESS, "SME_SM_ZA", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_CRm}, "streaming mode"},
|
||||
{AARCH64_OPND_CLASS_IMMEDIATE, "TME_UIMM16", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm16}, "a 16-bit unsigned immediate for TME tcancel"},
|
||||
{AARCH64_OPND_CLASS_SIMD_ELEMENT, "SM3_IMM2", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SM3_imm2}, "an indexed SM3 vector immediate"},
|
||||
{AARCH64_OPND_CLASS_NIL, "", 0, {0}, "DUMMY"},
|
||||
@ -322,17 +323,17 @@ static const unsigned op_enum_table [] =
|
||||
391,
|
||||
413,
|
||||
415,
|
||||
1270,
|
||||
1275,
|
||||
1268,
|
||||
1267,
|
||||
1274,
|
||||
1279,
|
||||
1272,
|
||||
1271,
|
||||
1278,
|
||||
1280,
|
||||
1281,
|
||||
1277,
|
||||
1283,
|
||||
1275,
|
||||
1282,
|
||||
1284,
|
||||
1285,
|
||||
1281,
|
||||
1287,
|
||||
1286,
|
||||
131,
|
||||
};
|
||||
|
||||
|
||||
@ -1520,7 +1520,7 @@ operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx,
|
||||
if (!aarch64_stack_pointer_p (opnd))
|
||||
{
|
||||
set_other_error (mismatch_detail, idx,
|
||||
_("stack pointer register expected"));
|
||||
_("stack pointer register expected"));
|
||||
return 0;
|
||||
}
|
||||
break;
|
||||
@ -2592,11 +2592,15 @@ operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx,
|
||||
/* MSR UAO, #uimm4
|
||||
MSR PAN, #uimm4
|
||||
MSR SSBS,#uimm4
|
||||
MSR SVCRSM, #uimm4
|
||||
MSR SVCRZA, #uimm4
|
||||
MSR SVCRSMZA, #uimm4
|
||||
The immediate must be #0 or #1. */
|
||||
if ((opnd->pstatefield == 0x03 /* UAO. */
|
||||
|| opnd->pstatefield == 0x04 /* PAN. */
|
||||
|| opnd->pstatefield == 0x19 /* SSBS. */
|
||||
|| opnd->pstatefield == 0x1a) /* DIT. */
|
||||
|| opnd->pstatefield == 0x1a /* DIT. */
|
||||
|| opnd->pstatefield == 0x1b) /* SVCRSM, SVCRZA or SVCRSMZA. */
|
||||
&& opnds[1].imm.value > 1)
|
||||
{
|
||||
set_imm_out_of_range_error (mismatch_detail, idx, 0, 1);
|
||||
@ -3465,6 +3469,10 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc,
|
||||
opnd->za_tile_vector.index.imm);
|
||||
break;
|
||||
|
||||
case AARCH64_OPND_SME_SM_ZA:
|
||||
snprintf (buf, size, "%s", opnd->reg.regno == 's' ? "sm" : "za");
|
||||
break;
|
||||
|
||||
case AARCH64_OPND_CRn:
|
||||
case AARCH64_OPND_CRm:
|
||||
snprintf (buf, size, "C%" PRIi64, opnd->imm.value);
|
||||
@ -3861,8 +3869,17 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc,
|
||||
|
||||
case AARCH64_OPND_PSTATEFIELD:
|
||||
for (i = 0; aarch64_pstatefields[i].name; ++i)
|
||||
if (aarch64_pstatefields[i].value == opnd->pstatefield)
|
||||
break;
|
||||
if (aarch64_pstatefields[i].value == opnd->pstatefield)
|
||||
{
|
||||
/* PSTATEFIELD name is encoded partially in CRm[3:1] for SVCRSM,
|
||||
SVCRZA and SVCRSMZA. */
|
||||
uint32_t flags = aarch64_pstatefields[i].flags;
|
||||
if (flags & F_REG_IN_CRM
|
||||
&& (PSTATE_DECODE_CRM (opnd->sysreg.flags)
|
||||
!= PSTATE_DECODE_CRM (flags)))
|
||||
continue;
|
||||
break;
|
||||
}
|
||||
assert (aarch64_pstatefields[i].name);
|
||||
snprintf (buf, size, "%s", aarch64_pstatefields[i].name);
|
||||
break;
|
||||
@ -3958,6 +3975,7 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc,
|
||||
#define SR_V8_4(n,e,f) SR_FEAT (n,e,f,V8_4)
|
||||
#define SR_PAN(n,e,f) SR_FEAT (n,e,f,PAN)
|
||||
#define SR_RAS(n,e,f) SR_FEAT (n,e,f,RAS)
|
||||
#define SR_SME(n,e,f) SR_FEAT (n,e,f,SME)
|
||||
#define SR_SSBS(n,e,f) SR_FEAT (n,e,f,SSBS)
|
||||
#define SR_SVE(n,e,f) SR_FEAT (n,e,f,SVE)
|
||||
#define SR_ID_PFR2(n,e,f) SR_FEAT (n,e,f,ID_PFR2)
|
||||
@ -4808,6 +4826,8 @@ const aarch64_sys_reg aarch64_sys_regs [] =
|
||||
SR_CORE ("gpccr_el3", CPENC (3,6,C2,C1,6), 0),
|
||||
SR_CORE ("gptbr_el3", CPENC (3,6,C2,C1,4), 0),
|
||||
|
||||
SR_SME ("svcr", CPENC (3,3,C4,C2,2), 0),
|
||||
|
||||
{ 0, CPENC (0,0,0,0,0), 0, 0 }
|
||||
};
|
||||
|
||||
@ -4834,6 +4854,9 @@ const aarch64_sys_reg aarch64_pstatefields [] =
|
||||
SR_SSBS ("ssbs", 0x19, 0),
|
||||
SR_V8_4 ("dit", 0x1a, 0),
|
||||
SR_MEMTAG ("tco", 0x1c, 0),
|
||||
SR_SME ("svcrsm", 0x1b, PSTATE_ENCODE_CRM_AND_IMM(0x2,0x1)),
|
||||
SR_SME ("svcrza", 0x1b, PSTATE_ENCODE_CRM_AND_IMM(0x4,0x1)),
|
||||
SR_SME ("svcrsmza", 0x1b, PSTATE_ENCODE_CRM_AND_IMM(0x6,0x1)),
|
||||
{ 0, CPENC (0,0,0,0,0), 0, 0 },
|
||||
};
|
||||
|
||||
|
||||
@ -243,6 +243,32 @@ verify_constraints (const struct aarch64_inst *, const aarch64_insn, bfd_vma,
|
||||
#define F_REG_WRITE (1 << 4) /* Register can only be written to but not
|
||||
read from. */
|
||||
|
||||
#undef F_REG_IN_CRM
|
||||
#define F_REG_IN_CRM (1 << 5) /* Register extra encoding in CRm. */
|
||||
|
||||
/* PSTATE field name for the MSR instruction this is encoded in "op1:op2:CRm".
|
||||
Part of CRm can be used to encode <pstatefield>. E.g. CRm[3:1] for SME.
|
||||
In order to set/get full PSTATE field name use flag F_REG_IN_CRM and below
|
||||
macros to encode and decode CRm encoding.
|
||||
*/
|
||||
#define PSTATE_ENCODE_CRM(val) (val << 6)
|
||||
#define PSTATE_DECODE_CRM(flags) ((flags >> 6) & 0x0f)
|
||||
|
||||
#undef F_IMM_IN_CRM
|
||||
#define F_IMM_IN_CRM (1 << 10) /* Immediate extra encoding in CRm. */
|
||||
|
||||
/* Also CRm may contain, in addition to <pstatefield> immediate.
|
||||
E.g. CRm[0] <imm1> at bit 0 for SME. Use below macros to encode and decode
|
||||
immediate mask.
|
||||
*/
|
||||
#define PSTATE_ENCODE_CRM_IMM(mask) (mask << 11)
|
||||
#define PSTATE_DECODE_CRM_IMM(mask) ((mask >> 11) & 0x0f)
|
||||
|
||||
/* Helper macro to ENCODE CRm and its immediate. */
|
||||
#define PSTATE_ENCODE_CRM_AND_IMM(CVAL,IMASK) \
|
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(F_REG_IN_CRM | PSTATE_ENCODE_CRM(CVAL) \
|
||||
| F_IMM_IN_CRM | PSTATE_ENCODE_CRM_IMM(IMASK))
|
||||
|
||||
/* HINT operand flags. */
|
||||
#define HINT_OPD_F_NOPRINT (1 << 0) /* Should not be printed. */
|
||||
|
||||
|
||||
@ -3933,6 +3933,11 @@ const struct aarch64_opcode aarch64_opcode_table[] =
|
||||
_TME_INSN ("tcommit", 0xd503307f, 0xffffffff, 0, 0, OP0 (), {}, 0),
|
||||
_TME_INSN ("ttest", 0xd5233160, 0xffffffe0, 0, 0, OP1 (Rd), QL_I1X, 0),
|
||||
_TME_INSN ("tcancel", 0xd4600000, 0xffe0001f, 0, 0, OP1 (TME_UIMM16), QL_IMM_NIL, 0),
|
||||
/* SME instructions (aliases for MSR <sysreg> operations. */
|
||||
SME_INSN ("smstart", 0xd503477f, 0xffffffff, sme_start, 0, OP0 (), {}, F_SYS_WRITE, 0),
|
||||
SME_INSN ("smstop", 0xd503467f, 0xffffffff, sme_stop, 0, OP0 (), {}, F_SYS_WRITE, 0),
|
||||
SME_INSN ("smstart", 0xd503417f, 0xfffff1ff, sme_start, 0, OP1 (SME_SM_ZA), {}, F_SYS_WRITE, 0),
|
||||
SME_INSN ("smstop", 0xd503407f, 0xfffff1ff, sme_stop, 0, OP1 (SME_SM_ZA), {}, F_SYS_WRITE, 0),
|
||||
/* System. */
|
||||
CORE_INSN ("msr", 0xd500401f, 0xfff8f01f, ic_system, 0, OP2 (PSTATEFIELD, UIMM4), {}, F_SYS_WRITE),
|
||||
CORE_INSN ("hint",0xd503201f, 0xfffff01f, ic_system, 0, OP1 (UIMM7), {}, F_HAS_ALIAS),
|
||||
@ -5765,6 +5770,9 @@ const struct aarch64_opcode aarch64_opcode_table[] =
|
||||
Y(ADDRESS, sme_addr_ri_u4xvl, "SME_ADDR_RI_U4xVL", 0 << OPD_F_OD_LSB, \
|
||||
F(FLD_Rn,FLD_imm4_2), \
|
||||
"memory offset") \
|
||||
Y(ADDRESS, sme_sm_za, "SME_SM_ZA", 0, \
|
||||
F(FLD_CRm), \
|
||||
"streaming mode") \
|
||||
Y(IMMEDIATE, imm, "TME_UIMM16", 0, F(FLD_imm16), \
|
||||
"a 16-bit unsigned immediate for TME tcancel") \
|
||||
Y(SIMD_ELEMENT, reglane, "SM3_IMM2", 0, F(FLD_SM3_imm2), \
|
||||
|
||||
Loading…
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Reference in New Issue
Block a user