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RISC-V: Add T-Head MAC vendor extension

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T-Head has a range of vendor-specific instructions.
Therefore it makes sense to group them into smaller chunks
in form of vendor extensions.

This patch adds the XTheadMac extension, a collection of
T-Head-specific multiply-accumulate instructions.
The 'th' prefix and the "XTheadMac" extension are documented
in a PR for the RISC-V toolchain conventions ([1]).

[1] https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19

Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
This commit is contained in:
Christoph Müllner 2022-06-28 17:44:46 +02:00 committed by Philipp Tomsich
parent 7344223096
commit 4041e11db3
7 changed files with 61 additions and 0 deletions
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5
bfd/elfxx-riscv.c
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@ -1229,6 +1229,7 @@ static struct riscv_supported_ext riscv_supported_vendor_x_ext[] =
{"xtheadbs", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"xtheadcmo", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"xtheadcondmov", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"xtheadmac", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"xtheadsync", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{NULL, 0, 0, 0, 0}
};
@ -2402,6 +2403,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps,
return riscv_subset_supports (rps, "xtheadcmo");
case INSN_CLASS_XTHEADCONDMOV:
return riscv_subset_supports (rps, "xtheadcondmov");
case INSN_CLASS_XTHEADMAC:
return riscv_subset_supports (rps, "xtheadmac");
case INSN_CLASS_XTHEADSYNC:
return riscv_subset_supports (rps, "xtheadsync");
default:
@ -2541,6 +2544,8 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps,
return "xtheadcmo";
case INSN_CLASS_XTHEADCONDMOV:
return "xtheadcondmov";
case INSN_CLASS_XTHEADMAC:
return "xtheadmac";
case INSN_CLASS_XTHEADSYNC:
return "xtheadsync";
default:

5
gas/doc/c-riscv.texi
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@ -729,6 +729,11 @@ The XTheadCondMov extension provides instructions for conditional moves.
It is documented in @url{https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.0.0/xthead-2022-09-05-2.0.0.pdf}.
@item XTheadMac
The XTheadMac extension provides multiply-accumulate instructions.
It is documented in @url{https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.0.0/xthead-2022-09-05-2.0.0.pdf}.
@item XTheadSync
The XTheadSync extension provides instructions for multi-processor synchronization.

15
gas/testsuite/gas/riscv/x-thead-mac.d Normal file
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@ -0,0 +1,15 @@
#as: -march=rv64i_xtheadmac
#source: x-thead-mac.s
#objdump: -dr
.*:[ ]+file format .*
Disassembly of section .text:
0+000 <target>:
[ ]+[0-9a-f]+:[ ]+20c5950b[ ]+th.mula[ ]+a0,a1,a2
[ ]+[0-9a-f]+:[ ]+28c5950b[ ]+th.mulah[ ]+a0,a1,a2
[ ]+[0-9a-f]+:[ ]+24c5950b[ ]+th.mulaw[ ]+a0,a1,a2
[ ]+[0-9a-f]+:[ ]+22c5950b[ ]+th.muls[ ]+a0,a1,a2
[ ]+[0-9a-f]+:[ ]+2ac5950b[ ]+th.mulsh[ ]+a0,a1,a2
[ ]+[0-9a-f]+:[ ]+26c5950b[ ]+th.mulsw[ ]+a0,a1,a2

7
gas/testsuite/gas/riscv/x-thead-mac.s Normal file
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@ -0,0 +1,7 @@
target:
th.mula a0, a1, a2
th.mulah a0, a1, a2
th.mulaw a0, a1, a2
th.muls a0, a1, a2
th.mulsh a0, a1, a2
th.mulsw a0, a1, a2

20
include/opcode/riscv-opc.h
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@ -2186,6 +2186,19 @@
#define MASK_TH_MVEQZ 0xfe00707f
#define MATCH_TH_MVNEZ 0x4200100b
#define MASK_TH_MVNEZ 0xfe00707f
/* Vendor-specific (T-Head) XTheadMac instructions. */
#define MATCH_TH_MULA 0x2000100b
#define MASK_TH_MULA 0xfe00707f
#define MATCH_TH_MULAH 0x2800100b
#define MASK_TH_MULAH 0xfe00707f
#define MATCH_TH_MULAW 0x2400100b
#define MASK_TH_MULAW 0xfe00707f
#define MATCH_TH_MULS 0x2200100b
#define MASK_TH_MULS 0xfe00707f
#define MATCH_TH_MULSH 0x2a00100b
#define MASK_TH_MULSH 0xfe00707f
#define MATCH_TH_MULSW 0x2600100b
#define MASK_TH_MULSW 0xfe00707f
/* Vendor-specific (T-Head) XTheadSync instructions. */
#define MATCH_TH_SFENCE_VMAS 0x0400000b
#define MASK_TH_SFENCE_VMAS 0xfe007fff
@ -2975,6 +2988,13 @@ DECLARE_INSN(th_l2cache_iall, MATCH_TH_L2CACHE_IALL, MASK_TH_L2CACHE_IALL)
/* Vendor-specific (T-Head) XTheadCondMov instructions. */
DECLARE_INSN(th_mveqz, MATCH_TH_MVEQZ, MASK_TH_MVEQZ)
DECLARE_INSN(th_mvnez, MATCH_TH_MVNEZ, MASK_TH_MVNEZ)
/* Vendor-specific (T-Head) XTheadMac instructions. */
DECLARE_INSN(th_mula, MATCH_TH_MULA, MASK_TH_MULA)
DECLARE_INSN(th_mulah, MATCH_TH_MULAH, MASK_TH_MULAH)
DECLARE_INSN(th_mulaw, MATCH_TH_MULAW, MASK_TH_MULAW)
DECLARE_INSN(th_muls, MATCH_TH_MULS, MASK_TH_MULS)
DECLARE_INSN(th_mulsh, MATCH_TH_MULSH, MASK_TH_MULSH)
DECLARE_INSN(th_mulsw, MATCH_TH_MULSW, MASK_TH_MULSW)
/* Vendor-specific (T-Head) XTheadSync instructions. */
DECLARE_INSN(th_sfence_vmas, MATCH_TH_SFENCE_VMAS, MASK_TH_SFENCE_VMAS)
DECLARE_INSN(th_sync, MATCH_TH_SYNC, MASK_TH_SYNC)

1
include/opcode/riscv.h
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@ -420,6 +420,7 @@ enum riscv_insn_class
INSN_CLASS_XTHEADBS,
INSN_CLASS_XTHEADCMO,
INSN_CLASS_XTHEADCONDMOV,
INSN_CLASS_XTHEADMAC,
INSN_CLASS_XTHEADSYNC,
};

8
opcodes/riscv-opc.c
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@ -1871,6 +1871,14 @@ const struct riscv_opcode riscv_opcodes[] =
{"th.mveqz", 0, INSN_CLASS_XTHEADCONDMOV, "d,s,t", MATCH_TH_MVEQZ, MASK_TH_MVEQZ, match_opcode, 0},
{"th.mvnez", 0, INSN_CLASS_XTHEADCONDMOV, "d,s,t", MATCH_TH_MVNEZ, MASK_TH_MVNEZ, match_opcode, 0},
/* Vendor-specific (T-Head) XTheadMac instructions. */
{"th.mula", 0, INSN_CLASS_XTHEADMAC, "d,s,t", MATCH_TH_MULA, MASK_TH_MULA, match_opcode, 0},
{"th.mulah", 0, INSN_CLASS_XTHEADMAC, "d,s,t", MATCH_TH_MULAH, MASK_TH_MULAH, match_opcode, 0},
{"th.mulaw", 64, INSN_CLASS_XTHEADMAC, "d,s,t", MATCH_TH_MULAW, MASK_TH_MULAW, match_opcode, 0},
{"th.muls", 0, INSN_CLASS_XTHEADMAC, "d,s,t", MATCH_TH_MULS, MASK_TH_MULS, match_opcode, 0},
{"th.mulsh", 0, INSN_CLASS_XTHEADMAC, "d,s,t", MATCH_TH_MULSH, MASK_TH_MULSH, match_opcode, 0},
{"th.mulsw", 64, INSN_CLASS_XTHEADMAC, "d,s,t", MATCH_TH_MULSW, MASK_TH_MULSW, match_opcode, 0},
/* Vendor-specific (T-Head) XTheadSync instructions. */
{"th.sfence.vmas", 0, INSN_CLASS_XTHEADSYNC, "s,t",MATCH_TH_SFENCE_VMAS, MASK_TH_SFENCE_VMAS, match_opcode, 0},
{"th.sync", 0, INSN_CLASS_XTHEADSYNC, "", MATCH_TH_SYNC, MASK_TH_SYNC, match_opcode, 0},