bfd ChangeLog
* elf32-xtensa.c (elf32xtensa_size_opt): New global variable.
(xtensa_default_isa): Global variable moved here from xtensa-isa.c.
(elf32xtensa_no_literal_movement): New global variable.
(elf_howto_table): Add entries for new relocations.
(elf_xtensa_reloc_type_lookup): Handle new relocations.
(property_table_compare): When addresses are equal, compare sizes and
various property flags.
(property_table_matches): New.
(xtensa_read_table_entries): Extend to read new property tables. Add
output_addr parameter to indicate that output addresses should be used.
Use bfd_get_section_limit.
(elf_xtensa_find_property_entry): New.
(elf_xtensa_in_literal_pool): Use elf_xtensa_find_property_entry.
(elf_xtensa_check_relocs): Handle new relocations.
(elf_xtensa_do_reloc): Use bfd_get_section_limit. Handle new
relocations. Use new xtensa-isa.h functions.
(build_encoding_error_message): Remove encode_result parameter. Add
new target_address parameter used to detect alignment errors.
(elf_xtensa_relocate_section): Use bfd_get_section_limit. Clean up
error handling. Use new is_operand_relocation function.
(elf_xtensa_combine_prop_entries, elf_xtensa_merge_private_bfd_data):
Use underbar macro for error messages. Formatting.
(get_const16_opcode): New.
(get_l32r_opcode): Add a separate flag for initialization.
(get_relocation_opnd): Operand number is no longer explicit in the
relocation. Change to decode the opcode and analyze its operands.
(get_relocation_slot): New.
(get_relocation_opcode): Add bfd parameter. Use bfd_get_section_limit.
Use new xtensa-isa.h functions to handle multislot instructions.
(is_l32r_relocation): Add bfd parameter. Use is_operand_relocation.
(get_asm_simplify_size, is_alt_relocation, is_operand_relocation,
insn_decode_len, insn_decode_opcode, check_branch_target_aligned,
check_loop_aligned, check_branch_target_aligned_address, narrowable,
widenable, narrow_instruction, widen_instruction, op_single_fmt_table,
get_single_format, init_op_single_format_table): New.
(elf_xtensa_do_asm_simplify): Add error_message parameter and use it
instead of calling _bfd_error_handler. Use new xtensa-isa.h functions.
(contract_asm_expansion): Add error_message parameter and pass it to
elf_xtensa_do_asm_simplify. Replace use of R_XTENSA_OP0 relocation
with R_XTENSA_SLOT0_OP.
(get_expanded_call_opcode): Extend to handle either L32R or CONST16
instructions. Use new xtensa-isa.h functions.
(r_reloc struct): Add new virtual_offset field.
(r_reloc_init): Add contents and content_length parameters. Set
virtual_offset field to zero. Add contents to target_offset field for
partial_inplace relocations.
(r_reloc_is_defined): Check for null.
(print_r_reloc): New debug function.
(source_reloc struct): Replace xtensa_operand field with pair of the
opcode and the operand position. Add is_abs_literal field.
(init_source_reloc): Specify operand by opcode/position pair. Set
is_abs_literal field.
(source_reloc_compare): When target_offsets are equal, compare other
fields to make sorting predictable.
(literal_value struct): Add is_abs_literal field.
(value_map_hash_table struct): Add has_last_loc and last_loc fields.
(init_literal_value): New.
(is_same_value): Replace with ...
(literal_value_equal): ... this function. Add comparisons of
virtual_offset and is_abs_literal fields.
(value_map_hash_table_init): Use bfd_zmalloc. Check for allocation
failure. Initialize has_last_loc field.
(value_map_hash_table_delete): New.
(hash_literal_value): Rename to ...
(literal_value_hash): ... this. Include is_abs_literal flag and
virtual_offset field in the hash value.
(get_cached_value): Rename to ...
(value_map_get_cached_value): ... this. Update calls to
literal_value_hash and literal_value_equal.
(add_value_map): Check for allocation failure. Update calls to
value_map_get_cached_value and literal_value_hash.
(text_action, text_action_list, text_action_t): New types.
(find_fill_action, compute_removed_action_diff, adjust_fill_action,
text_action_add, text_action_add_literal, offset_with_removed_text,
offset_with_removed_text_before_fill, find_insn_action,
print_action_list, print_removed_literals): New.
(offset_with_removed_literals): Delete.
(xtensa_relax_info struct): Add is_relaxable_asm_section, action_list,
fix_array, fix_array_count, allocated_relocs, relocs_count, and
allocated_relocs_count fields.
(init_xtensa_relax_info): Initialize new fields.
(reloc_bfd_fix struct): Add new translated field.
(reloc_bfd_fix_init): Add translated parameter and use it to set the
translated field.
(fix_compare, cache_fix_array): New.
(get_bfd_fix): Remove fix_list parameter and get all relax_info for the
section via get_xtensa_relax_info. Use cache_fix_array to set up
sorted fix_array and use bsearch instead of linear search.
(section_cache_t): New struct.
(init_section_cache, section_cache_section, clear_section_cache): New.
(ebb_t, ebb_target_enum, proposed_action, ebb_constraint): New types.
(init_ebb_constraint, free_ebb_constraint, init_ebb, extend_ebb_bounds,
extend_ebb_bounds_forward, extend_ebb_bounds_backward,
insn_block_decodable_len, ebb_propose_action, ebb_add_proposed_action):
New.
(retrieve_contents): Use bfd_get_section_limit.
(elf_xtensa_relax_section): Add relocations_analyzed flag. Update call
to compute_removed_literals. Free value_map_hash_table when no longer
needed.
(analyze_relocations): Check is_relaxable_asm_section flag. Call
compute_text_actions for all sections.
(find_relaxable_sections): Mark sections as relaxable if they contain
ASM_EXPAND relocations that can be optimized. Adjust r_reloc_init
call. Increment relax_info src_count field only for appropriate
relocation types. Remove is_literal_section check.
(collect_source_relocs): Use bfd_get_section_limit. Adjust calls to
r_reloc_init and find_associated_l32r_irel. Check
is_relaxable_asm_section flag. Handle L32R instructions with absolute
literals. Pass is_abs_literal flag to init_source_reloc.
(is_resolvable_asm_expansion): Use bfd_get_section_limit. Check for
CONST16 instructions. Adjust calls to r_reloc_init and
pcrel_reloc_fits. Handle weak symbols conservatively.
(find_associated_l32r_irel): Add bfd parameter and pass it to
is_l32r_relocation.
(compute_text_actions, compute_ebb_proposed_actions,
compute_ebb_actions, check_section_ebb_pcrels_fit,
check_section_ebb_reduces, text_action_add_proposed,
compute_fill_extra_space): New.
(remove_literals): Replace with ...
(compute_removed_literals): ... this function. Call
init_section_cache. Use bfd_get_section_limit. Sort internal_relocs.
Call xtensa_read_table_entries to get the property table. Skip
relocations other than R_XTENSA_32 and R_XTENSA_PLT. Use new
is_removable_literal, remove_dead_literal, and
identify_literal_placement functions.
(get_irel_at_offset): Rewrite to use bsearch on sorted relocations
instead of linear search.
(is_removable_literal, remove_dead_literal,
identify_literal_placement): New.
(relocations_reach): Update check for literal not referenced by any
PC-relative relocations. Adjust call to pcrel_reloc_fits.
(coalesce_shared_literal, move_shared_literal): New.
(relax_section): Use bfd_get_section_limit. Call
translate_section_fixes. Update calls to r_reloc_init and
offset_with_removed_text. Check new is_relaxable_asm_section flag.
Add call to pin_internal_relocs. Add special handling for
R_XTENSA_ASM_SIMPLIFY and R_XTENSA_DIFF* relocs. Use virtual_offset
info to calculate new addend_displacement variable. Replace code for
deleting literals with more general code to perform the actions
determined by the action_list for the section.
(translate_section_fixes, translate_reloc_bfd_fix): New.
(translate_reloc): Check new is_relaxable_asm_section flag. Call
find_removed_literal only if is_operand_relocation. Update call to
offset_with_removed_text. Use new target_offset and removed_bytes
variables.
(move_literal): New.
(relax_property_section): Use bfd_get_section_limit. Set new
is_full_prop_section flag and handle new property tables. Update calls
to r_reloc_init and offset_with_removed_text. Check
is_relaxable_asm_section flag. Handle expansion of zero-sized
unreachable entries, with use of offset_with_removed_text_before_fill.
For relocatable links, combine entries only for literal tables.
(relax_section_symbols): Check is_relaxable_asm_section flag. Update
calls to offset_with_removed_text. Translate st_size field for
function symbols.
(do_fix_for_relocatable_link): Change to return bfd_boolean to indicate
failure. Add contents parameter. Update call to get_bfd_fix. Update
call to r_reloc_init. Call _bfd_error_handler and return FALSE for
R_XTENSA_ASM_EXPAND relocs.
(do_fix_for_final_link): Add input_bfd and contents parameters. Update
call to get_bfd_fix. Include offset from contents for partial_inplace
relocations.
(is_reloc_sym_weak): New.
(pcrel_reloc_fits): Use new xtensa-isa.h functions.
(prop_sec_len): New.
(xtensa_is_property_section): Handle new property sections.
(is_literal_section): Delete.
(internal_reloc_compare): When r_offset matches, compare r_info and
r_addend to make sorting predictable.
(internal_reloc_matches): New.
(xtensa_get_property_section_name): Handle new property sections.
(xtensa_get_property_predef_flags): New.
(xtensa_callback_required_dependence): Use bfd_get_section_limit.
Update calls to xtensa_isa_init, is_l32r_relocation, and r_reloc_init.
* xtensa-isa.c (xtensa_default_isa): Moved to elf32-xtensa.c.
(xtisa_errno, xtisa_error_msg): New variables.
(xtensa_isa_errno, xtensa_isa_error_msg): New.
(xtensa_insnbuf_alloc): Add error handling.
(xtensa_insnbuf_to_chars): Add num_chars parameter. Update to
use xtensa_format_decode. Add error handling.
(xtensa_insnbuf_from_chars): Add num_chars parameter. Decode the
instruction length to find the number of bytes to copy.
(xtensa_isa_init): Add error handling. Replace calls to
xtensa_load_isa and xtensa_extend_isa with code to initialize lookup
tables in the xtensa_modules structure.
(xtensa_check_isa_config, xtensa_add_isa, xtensa_load_isa,
xtensa_extend_isa): Delete.
(xtensa_isa_free): Change to only free lookup tables.
(opname_lookup_compare): Replace with ...
(xtensa_isa_name_compare): ... this function. Use strcasecmp.
(xtensa_insn_maxlength): Rename to ...
(xtensa_isa_maxlength): ... this.
(xtensa_insn_length): Delete.
(xtensa_insn_length_from_first_byte): Replace with ...
(xtensa_isa_length_from_chars): ... this function.
(xtensa_num_opcodes): Rename to ...
(xtensa_isa_num_opcodes): ... this.
(xtensa_isa_num_pipe_stages, xtensa_isa_num_formats,
xtensa_isa_num_regfiles, xtensa_isa_num_stages,
xtensa_isa_num_sysregs, xtensa_isa_num_interfaces,
xtensa_isa_num_funcUnits, xtensa_format_name, xtensa_format_lookup,
xtensa_format_decode, xtensa_format_encode, xtensa_format_length,
xtensa_format_num_slots, xtensa_format_slot_nop_opcode,
xtensa_format_get_slot, xtensa_format_set_slot): New functions.
(xtensa_opcode_lookup): Add error handling.
(xtensa_decode_insn): Replace with ...
(xtensa_opcode_decode): ... this function, with new format and
slot parameters. Add error handling.
(xtensa_encode_insn): Replace with ...
(xtensa_opcode_encode): ... this function, which does the encoding via
one of the entries in the "encode_fns" array. Add error handling.
(xtensa_opcode_name): Add error handling.
(xtensa_opcode_is_branch, xtensa_opcode_is_jump, xtensa_opcode_is_loop,
xtensa_opcode_is_call): New.
(xtensa_num_operands): Replace with ...
(xtensa_opcode_num_operands): ... this function. Add error handling.
(xtensa_opcode_num_stateOperands,
xtensa_opcode_num_interfaceOperands, xtensa_opcode_num_funcUnit_uses,
xtensa_opcode_funcUnit_use, xtensa_operand_name,
xtensa_operand_is_visible): New.
(xtensa_get_operand, xtensa_operand_kind): Delete.
(xtensa_operand_inout): Add error handling and special-case for
"sout" operands.
(xtensa_operand_get_field, xtensa_operand_set_field): Rewritten to
operate on one slot of an instruction. Added error handling.
(xtensa_operand_encode): Handle default operands with no encoding
functions. Check for success by comparing against decoded value.
Add error handling.
(xtensa_operand_decode): Handle default operands. Return decoded value
through argument pointer. Add error handling.
(xtensa_operand_is_register, xtensa_operand_regfile,
xtensa_operand_num_regs, xtensa_operand_is_known_reg): New.
(xtensa_operand_isPCRelative): Rename to ...
(xtensa_operand_is_PCrelative): ... this. Add error handling.
(xtensa_operand_do_reloc, xtensa_operand_undo_reloc): Return value
through argument pointer. Add error handling.
(xtensa_stateOperand_state, xtensa_stateOperand_inout,
xtensa_interfaceOperand_interface, xtensa_regfile_lookup,
xtensa_regfile_lookup_shortname, xtensa_regfile_name,
xtensa_regfile_shortname, xtensa_regfile_view_parent,
xtensa_regfile_num_bits, xtensa_regfile_num_entries,
xtensa_state_lookup, xtensa_state_name, xtensa_state_num_bits,
xtensa_state_is_exported, xtensa_sysreg_lookup,
xtensa_sysreg_lookup_name, xtensa_sysreg_name, xtensa_sysreg_number,
xtensa_sysreg_is_user, xtensa_interface_lookup, xtensa_interface_name,
xtensa_interface_num_bits, xtensa_interface_inout,
xtensa_interface_has_side_effect, xtensa_funcUnit_lookup,
xtensa_funcUnit_name, xtensa_funcUnit_num_copies): New.
* xtensa-modules.c: Rewrite to use new data structures.
* reloc.c (BFD_RELOC_XTENSA_DIFF8, BFD_RELOC_XTENSA_DIFF16,
BFD_RELOC_XTENSA_DIFF32, BFD_RELOC_XTENSA_SLOT0_OP,
BFD_RELOC_XTENSA_SLOT1_OP, BFD_RELOC_XTENSA_SLOT2_OP,
BFD_RELOC_XTENSA_SLOT3_OP, BFD_RELOC_XTENSA_SLOT4_OP,
BFD_RELOC_XTENSA_SLOT5_OP, BFD_RELOC_XTENSA_SLOT6_OP,
BFD_RELOC_XTENSA_SLOT7_OP, BFD_RELOC_XTENSA_SLOT8_OP,
BFD_RELOC_XTENSA_SLOT9_OP, BFD_RELOC_XTENSA_SLOT10_OP,
BFD_RELOC_XTENSA_SLOT11_OP, BFD_RELOC_XTENSA_SLOT12_OP,
BFD_RELOC_XTENSA_SLOT13_OP, BFD_RELOC_XTENSA_SLOT14_OP,
BFD_RELOC_XTENSA_SLOT0_ALT, BFD_RELOC_XTENSA_SLOT1_ALT,
BFD_RELOC_XTENSA_SLOT2_ALT, BFD_RELOC_XTENSA_SLOT3_ALT,
BFD_RELOC_XTENSA_SLOT4_ALT, BFD_RELOC_XTENSA_SLOT5_ALT,
BFD_RELOC_XTENSA_SLOT6_ALT, BFD_RELOC_XTENSA_SLOT7_ALT,
BFD_RELOC_XTENSA_SLOT8_ALT, BFD_RELOC_XTENSA_SLOT9_ALT,
BFD_RELOC_XTENSA_SLOT10_ALT, BFD_RELOC_XTENSA_SLOT11_ALT,
BFD_RELOC_XTENSA_SLOT12_ALT, BFD_RELOC_XTENSA_SLOT13_ALT,
BFD_RELOC_XTENSA_SLOT14_ALT): Add new relocations.
* Makefile.am (xtensa-isa.lo, xtensa-modules.lo): Update dependencies.
* Makefile.in: Regenerate.
* bfd-in2.h: Likewise.
* libbfd.h: Likewise.
gas ChangeLog
* config/tc-xtensa.c (absolute_literals_supported): New global flag.
(UNREACHABLE_MAX_WIDTH): Define.
(XTENSA_FETCH_WIDTH): Delete.
(cur_vinsn, xtensa_fetch_width, xt_saved_debug_type, past_xtensa_end,
prefer_const16, prefer_l32r): New global variables.
(LIT4_SECTION_NAME): Define.
(lit4_state struct): Add lit4_seg_name and lit4_seg fields.
(XTENSA_PROP_*, GET_XTENSA_PROP_*, SET_XTENSA_PROP_*): Define.
(frag_flags struct): New.
(xtensa_block_info struct): Move from tc-xtensa.h. Add flags field.
(subseg_map struct): Add cur_total_freq and cur_target_freq fields.
(bitfield, bit_is_set, set_bit, clear_bit): Define.
(MAX_FORMATS): Define.
(op_placement_info struct, op_placement_table): New.
(O_pltrel, O_hi16, O_lo16): Define.
(directiveE enum): Rename directive_generics to directive_transform.
Delete directive_relax. Add directive_schedule,
directive_absolute_literals, and directive_last_directive.
(directive_info): Rename "generics" to "transform". Delete "relax".
Add "schedule" and "absolute-literals".
(directive_state): Adjust entries to match changes in directive_info.
(xtensa_relax_statesE, RELAX_IMMED_MAXSTEPS): Move to tc-xtensa.h.
(xtensa_const16_opcode, xtensa_movi_opcode, xtensa_movi_n_opcode,
xtensa_l32r_opcode, xtensa_nop_opcode, xtensa_rsr_lcount_opcode): New.
(xtensa_j_opcode, xtensa_rsr_opcode): Delete.
(align_only_targets, software_a0_b_retw_interlock,
software_avoid_b_j_loop_end, maybe_has_b_j_loop_end,
software_avoid_short_loop, software_avoid_close_loop_end,
software_avoid_all_short_loops, specific_opcode): Delete.
(warn_unaligned_branch_targets): New.
(workaround_a0_b_retw, workaround_b_j_loop_end, workaround_short_loop,
workaround_close_loop_end, workaround_all_short_loops): Default FALSE.
(option_[no_]link_relax, option_[no_]transform,
option_[no_]absolute_literals, option_warn_unaligned_targets,
option_prefer_l32r, option_prefer_const16, option_target_hardware):
New enum values.
(option_[no_]align_only_targets, option_literal_section_name,
option_text_section_name, option_data_section_name,
option_bss_section_name, option_eb, option_el): Delete.
(md_longopts): Add entries for: [no-]transform, [no-]absolute-literals,
warn-unaligned-targets, prefer-l32r, prefer-const16, [no-]link-relax,
and target-hardware. Delete entries for [no-]target-align-only,
literal-section-name, text-section-name, data-section-name, and
bss-section-name.
(md_parse_option): Handle new options and remove old ones. Accept but
ignore [no-]density options. Warn for [no-]generics and [no-]relax
and treat them as [no-]transform.
(md_show_usage): Add new options and remove old ones.
(xtensa_setup_hw_workarounds): New.
(md_pseudo_table): Change "word" entry to use xtensa_elf_cons. Add
"long", "short", "loc" and "frequency" entries.
(use_generics): Rename to ...
(use_transform): ... this function. Add past_xtensa_end check.
(use_longcalls): Add past_xtensa_end check.
(code_density_available, can_relax): Delete.
(do_align_targets): New.
(get_directive): Accept dashes in directive names. Warn about
[no-]generics and [no-]relax directives and treat them as
[no-]transform.
(xtensa_begin_directive): Call md_flush_pending_output only for some
directives. Check for directives inside instruction bundles. Warn
about deprecated ".begin literal" usage. Warn and ignore [no-]density
directives. Handle new directives. Check generating_literals flag
for literal_prefix.
(xtensa_end_directive): Check for directives inside instruction
bundles. Warn and ignore [no-]density directives. Handle new
directives. Call xtensa_set_frag_assembly_state.
(xtensa_loc_directive_seen, xtensa_dwarf2_directive_loc,
xtensa_dwarf2_emit_insn): New.
(xtensa_literal_position): Call md_flush_pending_output. Do not check
use_literal_section flag.
(xtensa_literal_pseudo): Call md_flush_pending_output. Handle absolute
literals. Use xtensa_elf_cons to parse the expression.
(xtensa_literal_prefix): Do not check use_literal_section. Support
".lit4" sections for absolute literals. Change prefix convention to
replace ".text" (or ".t" in a linkonce section). No need to call
subseg_set.
(xtensa_frequency_pseudo, xtensa_elf_cons, xtensa_elf_suffix): New.
(expression_end): Handle closing braces and colons.
(PLT_SUFFIX, plt_suffix): Delete.
(expression_maybe_register): Use new xtensa-isa.h functions. Use
xtensa_elf_suffix instead of checking for plt suffix, and handle O_lo16
and O_hi16 expressions as well.
(tokenize_arguments): Handle closing braces and colons.
(parse_arguments): Use new xtensa-isa.h functions. Handle "invisible"
operands and paired register syntax.
(get_invisible_operands): New.
(xg_translate_sysreg_op): Handle new Xtensa LX RSR/WSR/XSR syntax. Use
new xtensa-isa.h functions.
(xtensa_translate_old_userreg_ops, xtensa_translate_zero_immed): New.
(xg_translate_idioms): Check if inside bundle. Use use_transform.
Handle new Xtensa LX RSR/WSR/XSR syntax. Remove code to widen density
instructions. Use xtensa_translate_zero_immed.
(operand_is_immed, operand_is_pcrel_label): Delete.
(get_relaxable_immed): Use new xtensa-isa.h functions.
(get_opcode_from_buf): Add slot parameter. Use new xtensa-isa.h
functions.
(xtensa_print_insn_table, print_vliw_insn): New.
(is_direct_call_opcode): Use new xtensa-isa.h functions.
(is_call_opcode, is_loop_opcode, is_conditional_branch_opcode,
is_branch_or_jump_opcode): Delete.
(is_movi_opcode, decode_reloc, encode_reloc, encode_alt_reloc): New.
(opnum_to_reloc, reloc_to_opnum): Delete.
(xtensa_insnbuf_set_operand, xtensa_insnbuf_get_operand): Use new
xtensa-isa.h functions. Operate on one slot of an instruction.
(xtensa_insnbuf_set_immediate_field, is_negatable_branch,
xg_get_insn_size): Delete.
(xg_get_build_instr_size): Use xg_get_single_size.
(xg_is_narrow_insn, xg_is_single_relaxable_insn): Update calls to
xg_build_widen_table. Use xg_get_single_size.
(xg_get_max_narrow_insn_size): Delete.
(xg_get_max_insn_widen_size, xg_get_max_insn_widen_literal_size,
xg_is_relaxable_insn): Update calls to xg_build_widen_table. Use
xg_get_single_size.
(xg_build_to_insn): Record the loc field. Handle OP_OPERAND_HI16U and
OP_OPERAND_LOW16U. Check xg_valid_literal_expression.
(xg_expand_to_stack, xg_expand_narrow): Update calls to
xg_build_widen_table. Use xg_get_single_size.
(xg_immeds_fit): Use new xtensa-isa.h functions. Update call to
xg_check_operand.
(xg_symbolic_immeds_fit): Likewise. Also handle O_lo16 and O_hi16, and
treat weak symbols conservatively.
(xg_check_operand): Use new xtensa-isa.h functions.
(is_dnrange): Delete.
(xg_assembly_relax): Inline previous calls to tinsn_copy.
(xg_finish_frag): Specify separate relax states for the frag and slot0.
(is_branch_jmp_to_next, xg_add_branch_and_loop_targets): Use new
xtensa-isa.h functions.
(xg_instruction_matches_option_term, xg_instruction_matches_or_options,
xg_instruction_matches_options): New.
(xg_instruction_matches_rule): Handle O_register expressions. Call
xg_instruction_matches_options.
(transition_rule_cmp): New.
(xg_instruction_match): Update call to xg_build_simplify_table.
(xg_build_token_insn): Record loc fields.
(xg_simplify_insn): Check is_specific_opcode field and
density_supported flag.
(xg_expand_assembly_insn): Skip checking code_density_available. Use
new xtensa-isa.h functions. Call use_transform instead of can_relax.
(xg_assemble_literal): Add error handling for O_big. Call
record_alignment. Handle O_pltrel.
(xg_valid_literal_expression): New.
(xg_assemble_literal_space): Add slot parameter. Remove call to
set_expr_symbol_offset. Add call to record_alignment. Update call to
xg_finish_frag.
(xg_emit_insn): Delete.
(xg_emit_insn_to_buf): Add format parameter. Update calls to
xg_add_opcode_fix and xtensa_insnbuf_to_chars.
(xg_add_opcode_fix): Change opcode parameter to tinsn and add format
and slot parameters. Handle new "alternate" relocations for absolute
literals and CONST16 instructions. Check for bad uses of O_lo16 and
O_hi16. Use new xtensa-isa.h functions.
(xg_assemble_tokens): Delete.
(is_register_writer): Use new xtensa-isa.h functions.
(is_bad_loopend_opcode): Check for xtensa_rsr_lcount_opcode instead of
old-style RSR from LCOUNT.
(next_frag_opcode): Delete.
(next_frag_opcode_is_loop, next_frag_format_size, frag_format_size,
update_next_frag_state): New.
(update_next_frag_nop_state): Delete.
(next_frag_pre_opcode_bytes): Use next_frag_opcode_is_loop.
(xtensa_mark_literal_pool_location): Check use_literal_section flag and
the state of the absolute-literals directive. Add calls to
record_alignment and xtensa_set_frag_assembly_state. Call
xtensa_switch_to_non_abs_literal_fragment instead of
xtensa_switch_to_literal_fragment.
(build_nop): New.
(assemble_nop): Use build_nop. Update call to xtensa_insnbuf_to_chars.
(get_expanded_loop_offset): Change check for undefined opcode to an
assertion.
(xtensa_set_frag_assembly_state, relaxable_section,
xtensa_find_unmarked_state_frags, xtensa_find_unaligned_branch_targets,
xtensa_find_unaligned_loops, xg_apply_tentative_value): New.
(md_begin): Update call to xtensa_isa_init. Initialize linkrelax to 1.
Set lit4_seg_name. Call xg_init_vinsn. Initialize new global opcodes.
Call init_op_placement_info_table and xtensa_set_frag_assembly_state.
(xtensa_init_fix_data): New.
(xtensa_frob_label): Reset label symbol to the current frag. Check
do_align_targets and generating_literals flag. Propagate frequency
info to new alignment frag. Call xtensa_set_frag_assembly_state.
(xtensa_unrecognized_line): New.
(xtensa_flush_pending_output): Check if inside a bundle. Add a call
to xtensa_set_frag_assembly_state.
(error_reset_cur_vinsn): New.
(md_assemble): Remove check for literal frag. Remove call to
istack_init. Call use_transform instead of use_generics. Parse
explicit instruction format specifiers. Move code for
a0_b_retw_interlock workaround to xg_assemble_vliw_tokens. Call
error_reset_cur_vinsn on errors. Add call to get_invisible_operands.
Add dwarf2_where call. Remote automatic alignment for ENTRY
instructions. Move call to xtensa_clear_insn_labels to the end.
Rearrange to handle bundles.
(xtensa_cons_fix_new): Delete.
(xtensa_handle_align): New.
(xtensa_frag_init): Call xtensa_set_frag_assembly_state. Remove
assignment to is_no_density field.
(md_pcrel_from): Use new xtensa-isa.h functions. Use decode_reloc
instead of reloc_to_opnum. Handle "alternate" relocations.
(xtensa_force_relocation, xtensa_check_inside_bundle,
xtensa_elf_section_change_hook): New.
(xtensa_symbol_new_hook): Delete.
(xtensa_fix_adjustable): Check for difference of symbols with an
offset. Check for external and weak symbols.
(md_apply_fix3): Remove cases for XTENSA_OP{0,1,2} relocs.
(md_estimate_size_before_relax): Return expansion for the first slot.
(tc_gen_reloc): Handle difference of symbols by producing
XTENSA_DIFF{8,16,32} relocs and by writing the value of the difference
into the output. Handle new XTENSA_SLOT*_OP relocs by storing the
tentative values into the output when linkrelax is set.
(XTENSA_PROP_SEC_NAME): Define.
(xtensa_post_relax_hook): Call xtensa_find_unmarked_state_frags.
Create literal tables only if using literal sections. Create new
property tables instead of old instruction tables. Check for unaligned
branch targets and loops.
(finish_vinsn, find_vinsn_conflicts, check_t1_t2_reads_and_writes,
new_resource_table, clear_resource_table, resize_resource_table,
resources_available, reserve_resources, release_resources,
opcode_funcUnit_use_unit, opcode_funcUnit_use_stage,
resources_conflict, xg_find_narrowest_format, relaxation_requirements,
bundle_single_op, emit_single_op, xg_assemble_vliw_tokens): New.
(xtensa_end): Call xtensa_flush_pending_output. Set past_xtensa_end
flag. Update checks for workaround options. Call
xtensa_mark_narrow_branches and xtensa_mark_zcl_first_insns.
(xtensa_cleanup_align_frags): Add special case for branch targets.
Check for and mark unreachable frags.
(xtensa_fix_target_frags): Remove use of align_only_targets flag.
Use RELAX_LOOP_END_BYTES in special case for negatable branch at the
end of a zero-overhead loop body.
(frag_can_negate_branch): Handle instructions with multiple slots.
Use new xtensa-isa.h functions
(xtensa_mark_narrow_branches, is_narrow_branch_guaranteed_in_range,
xtensa_mark_zcl_first_insns): New.
(xtensa_fix_a0_b_retw_frags, xtensa_fix_b_j_loop_end_frags): Error if
transformations are disabled.
(next_instrs_are_b_retw): Use new xtensa-isa.h functions. Handle
multislot instructions.
(xtensa_fix_close_loop_end_frags, xtensa_fix_short_loop_frags):
Likewise. Also error if transformations are disabled.
(unrelaxed_frag_max_size): New.
(unrelaxed_frag_min_insn_count, unrelax_frag_has_b_j): Use new
xtensa-isa.h functions.
(xtensa_sanity_check, is_empty_loop, is_local_forward_loop): Use
xtensa_opcode_is_loop instead of is_loop_opcode.
(get_text_align_power): Replace as_fatal with assertion.
(get_text_align_fill_size): Iterate instead of using modulus when
use_nops is false.
(get_noop_aligned_address): Assert that this is for a machine-dependent
RELAX_ALIGN_NEXT_OPCODE frag. Use next_frag_opcode_is_loop,
xg_get_single_size, and frag_format_size.
(get_widen_aligned_address): Rename to ...
(get_aligned_diff): ... this function. Add max_diff parameter.
Remove handling of rs_align/rs_align_code frags. Use
next_frag_format_size, get_text_align_power, get_text_align_fill_size,
next_frag_opcode_is_loop, and xg_get_single_size. Compute max_diff
and pass it back to caller.
(xtensa_relax_frag): Use relax_frag_loop_align. Add code for new
RELAX_SLOTS, RELAX_MAYBE_UNREACHABLE, RELAX_MAYBE_DESIRE_ALIGN,
RELAX_FILL_NOP, and RELAX_UNREACHABLE frag types. Check relax_seen.
(relax_frag_text_align): Rename to ...
(relax_frag_loop_align): ... this function. Assume loops can only be
in the first slot of an instruction.
(relax_frag_add_nop): Use assemble_nop instead of constructing an OR
instruction. Remove call to frag_wane.
(relax_frag_narrow): Rename to ...
(relax_frag_for_align): ... this function. Extend to handle
RELAX_FILL_NOP and RELAX_UNREACHABLE, as well as RELAX_SLOTS with
RELAX_NARROW for the first slot.
(find_address_of_next_align_frag, bytes_to_stretch): New.
(future_alignment_required): Use find_address_of_next_align_frag and
bytes_to_stretch. Look ahead to subsequent frags to make smarter
alignment decisions.
(relax_frag_immed): Add format, slot, and estimate_only parameters.
Check if transformations are enabled for b_j_loop_end workaround.
Use new xtensa-isa.h functions and handle multislot instructions.
Update call to xg_assembly_relax.
(md_convert_frag): Handle new RELAX_SLOTS, RELAX_UNREACHABLE,
RELAX_MAYBE_UNREACHABLE, RELAX_MAYBE_DESIRE_ALIGN, and RELAX_FILL_NOP
frag types.
(convert_frag_narrow): Add segP, format and slot parameters. Call
convert_frag_immed for branch instructions. Adjust calls to
tinsn_from_chars, tinsn_immed_from_frag, and xg_emit_insn_to_buf. Use
xg_get_single_size and xg_get_single_format.
(convert_frag_fill_nop): New.
(convert_frag_immed): Add format and slot parameters. Handle multislot
instructions and use new xtensa-isa.h functions. Update calls to
tinsn_immed_from_frag and xg_assembly_relax. Check if transformations
enabled for b_j_loop_end workaround. Use build_nop instead of
assemble_nop. Check is_specific_opcode flag. Check for unreachable
frags. Use xg_get_single_size. Handle O_pltrel.
(fix_new_exp_in_seg): Remove check for old plt flag.
(convert_frag_immed_finish_loop): Update calls to tinsn_from_chars and
xtensa_insnbuf_to_chars. Call tinsn_immed_from_frag. Change check
for loop opcode to an assertion. Mark all frags up to the end of the
loop as not transformable.
(get_last_insn_flags, set_last_insn_flags): Use get_subseg_info.
(get_subseg_info): New.
(xtensa_move_literals): Call xtensa_set_frag_assembly_state. Add null
check for dest_seg.
(xtensa_switch_to_literal_fragment): Rewrite to handle absolute
literals and use xtensa_switch_to_non_abs_literal_fragment otherwise.
(xtensa_switch_to_non_abs_literal_fragment): New.
(cache_literal_section): Add is_code parameter and pass it through to
retrieve_literal_seg.
(retrieve_literal_seg): Add is_code parameter and use it to set the
flags on the literal section. Handle case where head parameter is 0.
(get_frag_is_no_transform, set_frag_is_specific_opcode,
set_frag_is_no_transform): New.
(xtensa_create_property_segments): Add end_property_function parameter
and pass it through to add_xt_block_frags. Call bfd_get_section_flags
and skip SEC_DEBUGGING and !SEC_ALLOC sections.
(xtensa_create_xproperty_segments, section_has_xproperty): New.
(add_xt_block_frags): Add end_property_function parameter and call it
if it is non-zero. Call xtensa_frag_flags_init.
(xtensa_frag_flags_is_empty, xtensa_frag_flags_init,
get_frag_property_flags, frag_flags_to_number,
xtensa_frag_flags_combinable, xt_block_aligned_size,
xtensa_xt_block_combine, add_xt_prop_frags,
init_op_placement_info_table, opcode_fits_format_slot,
xg_get_single_size, xg_get_single_format): New.
(istack_push): Inline call to tinsn_copy.
(tinsn_copy): Delete.
(tinsn_has_invalid_symbolic_operands): Handle O_hi16 and O_lo16 and
CONST16 opcodes. Handle O_big, O_illegal, and O_absent.
(tinsn_has_complex_operands): Handle O_hi16 and O_lo16.
(tinsn_to_insnbuf): Use xg_get_single_format and new xtensa-isa.h
functions. Handle invisible operands.
(tinsn_to_slotbuf): New.
(tinsn_check_arguments): Use new xtensa-isa.h functions.
(tinsn_from_chars): Add slot parameter. Rewrite using xg_init_vinsn,
vinsn_from_chars, and xg_free_vinsn.
(tinsn_from_insnbuf): New.
(tinsn_immed_from_frag): Add slot parameter and handle multislot
instructions. Handle symbol differences.
(get_num_stack_text_bytes): Use xg_get_single_size.
(xg_init_vinsn, xg_clear_vinsn, vinsn_has_specific_opcodes,
xg_free_vinsn, vinsn_to_insnbuf, vinsn_from_chars, expr_is_register,
get_expr_register, set_expr_symbol_offset_diff): New.
* config/tc-xtensa.h (MAX_SLOTS): Define.
(xtensa_relax_statesE): Move from tc-xtensa.c. Add
RELAX_CHECK_ALIGN_NEXT_OPCODE, RELAX_MAYBE_DESIRE_ALIGN, RELAX_SLOTS,
RELAX_FILL_NOP, RELAX_UNREACHABLE, RELAX_MAYBE_UNREACHABLE, and
RELAX_NONE types.
(RELAX_IMMED_MAXSTEPS): Move from tc-xtensa.c.
(xtensa_frag_type struct): Add is_assembly_state_set,
use_absolute_literals, relax_seen, is_unreachable, is_specific_opcode,
is_align, is_text_align, alignment, and is_first_loop_insn fields.
Replace is_generics and is_relax fields by is_no_transform field.
Delete is_text and is_longcalls fields. Change text_expansion and
literal_expansion to arrays of MAX_SLOTS entries. Add arrays of
per-slot information: literal_frags, slot_subtypes, slot_symbols,
slot_sub_symbols, and slot_offsets. Add fr_prev field.
(xtensa_fix_data struct): New.
(xtensa_symfield_type struct): Delete plt field.
(xtensa_block_info struct): Move definition to tc-xtensa.h. Add
forward declaration here.
(xt_section_type enum): Delete xt_insn_sec. Add xt_prop_sec.
(XTENSA_SECTION_RENAME): Undefine.
(TC_FIX_TYPE, TC_INIT_FIX_DATA, TC_FORCE_RELOCATION, NO_PSEUDO_DOT,
tc_unrecognized_line, md_do_align, md_elf_section_change_hook,
HANDLE_ALIGN, TC_LINKRELAX_FIXUP, SUB_SEGMENT_ALIGN): Define.
(TC_CONS_FIX_NEW, tc_symbol_new_hook): Delete.
(unit_num_copies_func, opcode_num_units_func,
opcode_funcUnit_use_unit_func, opcode_funcUnit_use_stage_func): New.
(resource_table struct): New.
* config/xtensa-istack.h (MAX_INSN_ARGS): Increase from 6 to 10.
(TInsn struct): Add keep_wide, loc, fixup, record_fix, subtype,
literal_space, symbol, sub_symbol, offset, and literal_frag fields.
(tinsn_copy): Delete prototype.
(vliw_insn struct): New.
* config/xtensa-relax.c (insn_pattern_struct): Add options field.
(widen_spec_list): Add option conditions for density and boolean
instructions. Add expansions using CONST16 and conditions for using
CONST16 vs. L32R. Use new Xtensa LX RSR/WSR syntax. Add entries for
predicted branches.
(simplify_spec_list): Add option conditions for density instructions.
Add entry for NOP instruction.
(append_transition): Add cmp function pointer parameter and use it to
insert the new entry in order.
(operand_function_LOW16U, operand_function_HI16U): New.
(xg_has_userdef_op_fn, xg_apply_userdef_op_fn): Handle
OP_OPERAND_LOW16U and OP_OPERAND_HI16U.
(enter_opname, split_string): Use xstrdup instead of strdup.
(init_insn_pattern): Initialize new options field.
(clear_req_or_option_list, clear_req_option_list,
clone_req_or_option_list, clone_req_option_list, parse_option_cond):
New.
(parse_insn_pattern): Parse option conditions.
(transition_applies): New.
(build_transition): Use new xtensa-isa.h functions. Fix incorrectly
swapped last arguments in calls to append_constant_value_condition.
Call clone_req_option_list. Add warning about invalid opcode.
Handle LOW16U and HI16U function names.
(build_transition_table): Add cmp parameter and use it in calls to
append_transition. Use new xtensa-isa.h functions. Check
transition_applies before adding entries.
(xg_build_widen_table, xg_build_simplify_table): Add cmp parameter and
pass it through to build_transition_table.
* config/xtensa-relax.h (ReqOrOptionList, ReqOrOption, ReqOptionList,
ReqOption, transition_cmp_fn): New types.
(OpType enum): Add OP_OPERAND_LOW16U and OP_OPERAND_HI16U.
(transition_rule struct): Add options field.
* doc/as.texinfo (Overview): Update Xtensa options.
* doc/c-xtensa.texi (Xtensa Options): Delete --[no-]density,
--[no-]relax, and --[no-]generics options. Update descriptions of
--text-section-literals and --[no-]longcalls. Add
--[no-]absolute-literals and --[no-]transform.
(Xtensa Syntax): Add description of syntax for FLIX instructions.
Remove use of "generic" and "specific" terminology for opcodes.
(Xtensa Registers): Generalize the syntax description to include
user-defined register files.
(Xtensa Automatic Alignment): Update.
(Xtensa Branch Relaxation): Mention limitation of unconditional jumps.
(Xtensa Call Relaxation): Linker can now remove most of the overhead.
(Xtensa Directives): Remove confusing rules about precedence.
(Density Directive, Relax Directive): Delete.
(Schedule Directive): New.
(Generics Directive): Rename to ...
(Transform Directive): ... this node.
(Literal Directive): Update for absolute literals. Missing
literal_position directive is now an error.
(Literal Position Directive): Update for absolute literals.
(Freeregs Directive): Delete.
(Absolute Literals Directive): New.
(Frame Directive): Minor editing.
* Makefile.am (DEPTC_xtensa_elf, DEPOBJ_xtensa_elf, DEP_xtensa_elf):
Update dependencies.
* Makefile.in: Regenerate.
gas/testsuite ChangeLog
* gas/xtensa/all.exp: Adjust expected error message for j_too_far.
Change entry_align test to expect an error.
* gas/xtensa/entry_misalign2.s: Use no-transform instead of
no-generics directives.
include ChangeLog
* xtensa-config.h (XSHAL_USE_ABSOLUTE_LITERALS,
XCHAL_HAVE_PREDICTED_BRANCHES, XCHAL_INST_FETCH_WIDTH): New.
(XCHAL_EXTRA_SA_SIZE, XCHAL_EXTRA_SA_ALIGN): Delete.
* xtensa-isa-internal.h (ISA_INTERFACE_VERSION): Delete.
(config_sturct struct): Delete.
(XTENSA_OPERAND_IS_REGISTER, XTENSA_OPERAND_IS_PCRELATIVE,
XTENSA_OPERAND_IS_INVISIBLE, XTENSA_OPERAND_IS_UNKNOWN,
XTENSA_OPCODE_IS_BRANCH, XTENSA_OPCODE_IS_JUMP,
XTENSA_OPCODE_IS_LOOP, XTENSA_OPCODE_IS_CALL,
XTENSA_STATE_IS_EXPORTED, XTENSA_INTERFACE_HAS_SIDE_EFFECT): Define.
(xtensa_format_encode_fn, xtensa_get_slot_fn, xtensa_set_slot_fn): New.
(xtensa_insn_decode_fn): Rename to ...
(xtensa_opcode_decode_fn): ... this.
(xtensa_immed_decode_fn, xtensa_immed_encode_fn, xtensa_do_reloc_fn,
xtensa_undo_reloc_fn): Update.
(xtensa_encoding_template_fn): Delete.
(xtensa_opcode_encode_fn, xtensa_format_decode_fn,
xtensa_length_decode_fn): New.
(xtensa_format_internal, xtensa_slot_internal): New types.
(xtensa_operand_internal): Delete operand_kind, inout, isPCRelative,
get_field, and set_field fields. Add name, field_id, regfile,
num_regs, and flags fields.
(xtensa_arg_internal): New type.
(xtensa_iclass_internal): Change operands field to array of
xtensa_arg_internal. Add num_stateOperands, stateOperands,
num_interfaceOperands, and interfaceOperands fields.
(xtensa_opcode_internal): Delete length, template, and iclass fields.
Add iclass_id, flags, encode_fns, num_funcUnit_uses, and funcUnit_uses.
(opname_lookup_entry): Delete.
(xtensa_regfile_internal, xtensa_interface_internal,
xtensa_funcUnit_internal, xtensa_state_internal,
xtensa_sysreg_internal, xtensa_lookup_entry): New.
(xtensa_isa_internal): Replace opcode_table field with opcodes field.
Change type of opname_lookup_table. Delete num_modules,
module_opcode_base, module_decode_fn, config, and has_density fields.
Add num_formats, formats, format_decode_fn, length_decode_fn,
num_slots, slots, num_fields, num_operands, operands, num_iclasses,
iclasses, num_regfiles, regfiles, num_states, states,
state_lookup_table, num_sysregs, sysregs, sysreg_lookup_table,
max_sysreg_num, sysreg_table, num_interfaces, interfaces,
interface_lookup_table, num_funcUnits, funcUnits and
funcUnit_lookup_table fields.
(xtensa_isa_module, xtensa_isa_modules): Delete.
(xtensa_isa_name_compare): New prototype.
(xtisa_errno, xtisa_error_msg): New.
* xtensa-isa.h (XTENSA_ISA_VERSION): Define.
(xtensa_isa): Change type.
(xtensa_operand): Delete.
(xtensa_format, xtensa_regfile, xtensa_state, xtensa_sysreg,
xtensa_interface, xtensa_funcUnit, xtensa_isa_status,
xtensa_funcUnit_use): New types.
(libisa_module_specifier): Delete.
(xtensa_isa_errno, xtensa_isa_error_msg): New prototypes.
(xtensa_insnbuf_free, xtensa_insnbuf_to_chars,
xtensa_insnbuf_from_chars): Update prototypes.
(xtensa_load_isa, xtensa_extend_isa, xtensa_default_isa,
xtensa_insn_maxlength, xtensa_num_opcodes, xtensa_decode_insn,
xtensa_encode_insn, xtensa_insn_length,
xtensa_insn_length_from_first_byte, xtensa_num_operands,
xtensa_operand_kind, xtensa_encode_result,
xtensa_operand_isPCRelative): Delete.
(xtensa_isa_init, xtensa_operand_inout, xtensa_operand_get_field,
xtensa_operand_set_field, xtensa_operand_encode,
xtensa_operand_decode, xtensa_operand_do_reloc,
xtensa_operand_undo_reloc): Update prototypes.
(xtensa_isa_maxlength, xtensa_isa_length_from_chars,
xtensa_isa_num_pipe_stages, xtensa_isa_num_formats,
xtensa_isa_num_opcodes, xtensa_isa_num_regfiles, xtensa_isa_num_states,
xtensa_isa_num_sysregs, xtensa_isa_num_interfaces,
xtensa_isa_num_funcUnits, xtensa_format_name, xtensa_format_lookup,
xtensa_format_decode, xtensa_format_encode, xtensa_format_length,
xtensa_format_num_slots, xtensa_format_slot_nop_opcode,
xtensa_format_get_slot, xtensa_format_set_slot, xtensa_opcode_decode,
xtensa_opcode_encode, xtensa_opcode_is_branch, xtensa_opcode_is_jump,
xtensa_opcode_is_loop, xtensa_opcode_is_call,
xtensa_opcode_num_operands, xtensa_opcode_num_stateOperands,
xtensa_opcode_num_interfaceOperands, xtensa_opcode_num_funcUnit_uses,
xtensa_opcode_funcUnit_use, xtensa_operand_name,
xtensa_operand_is_visible, xtensa_operand_is_register,
xtensa_operand_regfile, xtensa_operand_num_regs,
xtensa_operand_is_known_reg, xtensa_operand_is_PCrelative,
xtensa_stateOperand_state, xtensa_stateOperand_inout,
xtensa_interfaceOperand_interface, xtensa_regfile_lookup,
xtensa_regfile_lookup_shortname, xtensa_regfile_name,
xtensa_regfile_shortname, xtensa_regfile_view_parent,
xtensa_regfile_num_bits, xtensa_regfile_num_entries,
xtensa_state_lookup, xtensa_state_name, xtensa_state_num_bits,
xtensa_state_is_exported, xtensa_sysreg_lookup,
xtensa_sysreg_lookup_name, xtensa_sysreg_name, xtensa_sysreg_number,
xtensa_sysreg_is_user, xtensa_interface_lookup, xtensa_interface_name,
xtensa_interface_num_bits, xtensa_interface_inout,
xtensa_interface_has_side_effect, xtensa_funcUnit_lookup,
xtensa_funcUnit_name, xtensa_funcUnit_num_copies): New prototypes.
* elf/xtensa.h (R_XTENSA_DIFF8, R_XTENSA_DIFF16, R_XTENSA_DIFF32,
R_XTENSA_SLOT*_OP, R_XTENSA_SLOT*_ALT): New relocations.
(XTENSA_PROP_SEC_NAME): Define.
(property_table_entry): Add flags field.
(XTENSA_PROP_*, GET_XTENSA_PROP_*, SET_XTENSA_PROP_*): Define.
ld ChangeLog
* ld.texinfo (Xtensa): Describe new linker relaxation to optimize
assembler-generated longcall sequences. Describe new --size-opt
option.
* emulparams/elf32xtensa.sh (OTHER_SECTIONS): Add .xt.prop section.
* emultempl/xtensaelf.em (remove_section,
replace_insn_sec_with_prop_sec, replace_instruction_table_sections,
elf_xtensa_after_open): New.
(OPTION_OPT_SIZEOPT, OPTION_LITERAL_MOVEMENT,
OPTION_NO_LITERAL_MOVEMENT): Define.
(elf32xtensa_size_opt, elf32xtensa_no_literal_movement): New globals.
(PARSE_AND_LIST_LONGOPTS): Add size-opt and [no-]literal-movement.
(PARSE_AND_LIST_OPTIONS): Add --size-opt.
(PARSE_AND_LIST_ARGS_CASES): Handle OPTION_OPT_SIZEOPT,
OPTION_LITERAL_MOVEMENT, and OPTION_NO_LITERAL_MOVEMENT.
(LDEMUL_AFTER_OPEN): Set to elf_xtensa_after_open.
* scripttempl/elfxtensa.sc: Update with changes from elf.sc.
* Makefile.am (eelf32xtensa.c): Update dependencies.
* Makefile.in: Regenerate.
ld/testsuite ChangeLog
* ld-xtensa/lcall1.s: Use .literal directive.
* ld-xtensa/lcall2.s: Align function entry.
* ld-xtensa/coalesce2.s: Likewise.
opcodes ChangeLog
* xtensa-dis.c (state_names): Delete.
(fetch_data): Use xtensa_isa_maxlength.
(print_xtensa_operand): Replace operand parameter with opcode/operand
pair. Remove print_sr_name parameter. Use new xtensa-isa.h functions.
(print_insn_xtensa): Use new xtensa-isa.h functions. Handle multislot
instruction bundles. Use xmalloc instead of malloc.
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Bob Wilson
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@ -1,3 +1,276 @@
|
||||
2004-10-07 Bob Wilson <bob.wilson@acm.org>
|
||||
|
||||
* elf32-xtensa.c (elf32xtensa_size_opt): New global variable.
|
||||
(xtensa_default_isa): Global variable moved here from xtensa-isa.c.
|
||||
(elf32xtensa_no_literal_movement): New global variable.
|
||||
(elf_howto_table): Add entries for new relocations.
|
||||
(elf_xtensa_reloc_type_lookup): Handle new relocations.
|
||||
(property_table_compare): When addresses are equal, compare sizes and
|
||||
various property flags.
|
||||
(property_table_matches): New.
|
||||
(xtensa_read_table_entries): Extend to read new property tables. Add
|
||||
output_addr parameter to indicate that output addresses should be used.
|
||||
Use bfd_get_section_limit.
|
||||
(elf_xtensa_find_property_entry): New.
|
||||
(elf_xtensa_in_literal_pool): Use elf_xtensa_find_property_entry.
|
||||
(elf_xtensa_check_relocs): Handle new relocations.
|
||||
(elf_xtensa_do_reloc): Use bfd_get_section_limit. Handle new
|
||||
relocations. Use new xtensa-isa.h functions.
|
||||
(build_encoding_error_message): Remove encode_result parameter. Add
|
||||
new target_address parameter used to detect alignment errors.
|
||||
(elf_xtensa_relocate_section): Use bfd_get_section_limit. Clean up
|
||||
error handling. Use new is_operand_relocation function.
|
||||
(elf_xtensa_combine_prop_entries, elf_xtensa_merge_private_bfd_data):
|
||||
Use underbar macro for error messages. Formatting.
|
||||
(get_const16_opcode): New.
|
||||
(get_l32r_opcode): Add a separate flag for initialization.
|
||||
(get_relocation_opnd): Operand number is no longer explicit in the
|
||||
relocation. Change to decode the opcode and analyze its operands.
|
||||
(get_relocation_slot): New.
|
||||
(get_relocation_opcode): Add bfd parameter. Use bfd_get_section_limit.
|
||||
Use new xtensa-isa.h functions to handle multislot instructions.
|
||||
(is_l32r_relocation): Add bfd parameter. Use is_operand_relocation.
|
||||
(get_asm_simplify_size, is_alt_relocation, is_operand_relocation,
|
||||
insn_decode_len, insn_decode_opcode, check_branch_target_aligned,
|
||||
check_loop_aligned, check_branch_target_aligned_address, narrowable,
|
||||
widenable, narrow_instruction, widen_instruction, op_single_fmt_table,
|
||||
get_single_format, init_op_single_format_table): New.
|
||||
(elf_xtensa_do_asm_simplify): Add error_message parameter and use it
|
||||
instead of calling _bfd_error_handler. Use new xtensa-isa.h functions.
|
||||
(contract_asm_expansion): Add error_message parameter and pass it to
|
||||
elf_xtensa_do_asm_simplify. Replace use of R_XTENSA_OP0 relocation
|
||||
with R_XTENSA_SLOT0_OP.
|
||||
(get_expanded_call_opcode): Extend to handle either L32R or CONST16
|
||||
instructions. Use new xtensa-isa.h functions.
|
||||
(r_reloc struct): Add new virtual_offset field.
|
||||
(r_reloc_init): Add contents and content_length parameters. Set
|
||||
virtual_offset field to zero. Add contents to target_offset field for
|
||||
partial_inplace relocations.
|
||||
(r_reloc_is_defined): Check for null.
|
||||
(print_r_reloc): New debug function.
|
||||
(source_reloc struct): Replace xtensa_operand field with pair of the
|
||||
opcode and the operand position. Add is_abs_literal field.
|
||||
(init_source_reloc): Specify operand by opcode/position pair. Set
|
||||
is_abs_literal field.
|
||||
(source_reloc_compare): When target_offsets are equal, compare other
|
||||
fields to make sorting predictable.
|
||||
(literal_value struct): Add is_abs_literal field.
|
||||
(value_map_hash_table struct): Add has_last_loc and last_loc fields.
|
||||
(init_literal_value): New.
|
||||
(is_same_value): Replace with ...
|
||||
(literal_value_equal): ... this function. Add comparisons of
|
||||
virtual_offset and is_abs_literal fields.
|
||||
(value_map_hash_table_init): Use bfd_zmalloc. Check for allocation
|
||||
failure. Initialize has_last_loc field.
|
||||
(value_map_hash_table_delete): New.
|
||||
(hash_literal_value): Rename to ...
|
||||
(literal_value_hash): ... this. Include is_abs_literal flag and
|
||||
virtual_offset field in the hash value.
|
||||
(get_cached_value): Rename to ...
|
||||
(value_map_get_cached_value): ... this. Update calls to
|
||||
literal_value_hash and literal_value_equal.
|
||||
(add_value_map): Check for allocation failure. Update calls to
|
||||
value_map_get_cached_value and literal_value_hash.
|
||||
(text_action, text_action_list, text_action_t): New types.
|
||||
(find_fill_action, compute_removed_action_diff, adjust_fill_action,
|
||||
text_action_add, text_action_add_literal, offset_with_removed_text,
|
||||
offset_with_removed_text_before_fill, find_insn_action,
|
||||
print_action_list, print_removed_literals): New.
|
||||
(offset_with_removed_literals): Delete.
|
||||
(xtensa_relax_info struct): Add is_relaxable_asm_section, action_list,
|
||||
fix_array, fix_array_count, allocated_relocs, relocs_count, and
|
||||
allocated_relocs_count fields.
|
||||
(init_xtensa_relax_info): Initialize new fields.
|
||||
(reloc_bfd_fix struct): Add new translated field.
|
||||
(reloc_bfd_fix_init): Add translated parameter and use it to set the
|
||||
translated field.
|
||||
(fix_compare, cache_fix_array): New.
|
||||
(get_bfd_fix): Remove fix_list parameter and get all relax_info for the
|
||||
section via get_xtensa_relax_info. Use cache_fix_array to set up
|
||||
sorted fix_array and use bsearch instead of linear search.
|
||||
(section_cache_t): New struct.
|
||||
(init_section_cache, section_cache_section, clear_section_cache): New.
|
||||
(ebb_t, ebb_target_enum, proposed_action, ebb_constraint): New types.
|
||||
(init_ebb_constraint, free_ebb_constraint, init_ebb, extend_ebb_bounds,
|
||||
extend_ebb_bounds_forward, extend_ebb_bounds_backward,
|
||||
insn_block_decodable_len, ebb_propose_action, ebb_add_proposed_action):
|
||||
New.
|
||||
(retrieve_contents): Use bfd_get_section_limit.
|
||||
(elf_xtensa_relax_section): Add relocations_analyzed flag. Update call
|
||||
to compute_removed_literals. Free value_map_hash_table when no longer
|
||||
needed.
|
||||
(analyze_relocations): Check is_relaxable_asm_section flag. Call
|
||||
compute_text_actions for all sections.
|
||||
(find_relaxable_sections): Mark sections as relaxable if they contain
|
||||
ASM_EXPAND relocations that can be optimized. Adjust r_reloc_init
|
||||
call. Increment relax_info src_count field only for appropriate
|
||||
relocation types. Remove is_literal_section check.
|
||||
(collect_source_relocs): Use bfd_get_section_limit. Adjust calls to
|
||||
r_reloc_init and find_associated_l32r_irel. Check
|
||||
is_relaxable_asm_section flag. Handle L32R instructions with absolute
|
||||
literals. Pass is_abs_literal flag to init_source_reloc.
|
||||
(is_resolvable_asm_expansion): Use bfd_get_section_limit. Check for
|
||||
CONST16 instructions. Adjust calls to r_reloc_init and
|
||||
pcrel_reloc_fits. Handle weak symbols conservatively.
|
||||
(find_associated_l32r_irel): Add bfd parameter and pass it to
|
||||
is_l32r_relocation.
|
||||
(compute_text_actions, compute_ebb_proposed_actions,
|
||||
compute_ebb_actions, check_section_ebb_pcrels_fit,
|
||||
check_section_ebb_reduces, text_action_add_proposed,
|
||||
compute_fill_extra_space): New.
|
||||
(remove_literals): Replace with ...
|
||||
(compute_removed_literals): ... this function. Call
|
||||
init_section_cache. Use bfd_get_section_limit. Sort internal_relocs.
|
||||
Call xtensa_read_table_entries to get the property table. Skip
|
||||
relocations other than R_XTENSA_32 and R_XTENSA_PLT. Use new
|
||||
is_removable_literal, remove_dead_literal, and
|
||||
identify_literal_placement functions.
|
||||
(get_irel_at_offset): Rewrite to use bsearch on sorted relocations
|
||||
instead of linear search.
|
||||
(is_removable_literal, remove_dead_literal,
|
||||
identify_literal_placement): New.
|
||||
(relocations_reach): Update check for literal not referenced by any
|
||||
PC-relative relocations. Adjust call to pcrel_reloc_fits.
|
||||
(coalesce_shared_literal, move_shared_literal): New.
|
||||
(relax_section): Use bfd_get_section_limit. Call
|
||||
translate_section_fixes. Update calls to r_reloc_init and
|
||||
offset_with_removed_text. Check new is_relaxable_asm_section flag.
|
||||
Add call to pin_internal_relocs. Add special handling for
|
||||
R_XTENSA_ASM_SIMPLIFY and R_XTENSA_DIFF* relocs. Use virtual_offset
|
||||
info to calculate new addend_displacement variable. Replace code for
|
||||
deleting literals with more general code to perform the actions
|
||||
determined by the action_list for the section.
|
||||
(translate_section_fixes, translate_reloc_bfd_fix): New.
|
||||
(translate_reloc): Check new is_relaxable_asm_section flag. Call
|
||||
find_removed_literal only if is_operand_relocation. Update call to
|
||||
offset_with_removed_text. Use new target_offset and removed_bytes
|
||||
variables.
|
||||
(move_literal): New.
|
||||
(relax_property_section): Use bfd_get_section_limit. Set new
|
||||
is_full_prop_section flag and handle new property tables. Update calls
|
||||
to r_reloc_init and offset_with_removed_text. Check
|
||||
is_relaxable_asm_section flag. Handle expansion of zero-sized
|
||||
unreachable entries, with use of offset_with_removed_text_before_fill.
|
||||
For relocatable links, combine entries only for literal tables.
|
||||
(relax_section_symbols): Check is_relaxable_asm_section flag. Update
|
||||
calls to offset_with_removed_text. Translate st_size field for
|
||||
function symbols.
|
||||
(do_fix_for_relocatable_link): Change to return bfd_boolean to indicate
|
||||
failure. Add contents parameter. Update call to get_bfd_fix. Update
|
||||
call to r_reloc_init. Call _bfd_error_handler and return FALSE for
|
||||
R_XTENSA_ASM_EXPAND relocs.
|
||||
(do_fix_for_final_link): Add input_bfd and contents parameters. Update
|
||||
call to get_bfd_fix. Include offset from contents for partial_inplace
|
||||
relocations.
|
||||
(is_reloc_sym_weak): New.
|
||||
(pcrel_reloc_fits): Use new xtensa-isa.h functions.
|
||||
(prop_sec_len): New.
|
||||
(xtensa_is_property_section): Handle new property sections.
|
||||
(is_literal_section): Delete.
|
||||
(internal_reloc_compare): When r_offset matches, compare r_info and
|
||||
r_addend to make sorting predictable.
|
||||
(internal_reloc_matches): New.
|
||||
(xtensa_get_property_section_name): Handle new property sections.
|
||||
(xtensa_get_property_predef_flags): New.
|
||||
(xtensa_callback_required_dependence): Use bfd_get_section_limit.
|
||||
Update calls to xtensa_isa_init, is_l32r_relocation, and r_reloc_init.
|
||||
* xtensa-isa.c (xtensa_default_isa): Moved to elf32-xtensa.c.
|
||||
(xtisa_errno, xtisa_error_msg): New variables.
|
||||
(xtensa_isa_errno, xtensa_isa_error_msg): New.
|
||||
(xtensa_insnbuf_alloc): Add error handling.
|
||||
(xtensa_insnbuf_to_chars): Add num_chars parameter. Update to
|
||||
use xtensa_format_decode. Add error handling.
|
||||
(xtensa_insnbuf_from_chars): Add num_chars parameter. Decode the
|
||||
instruction length to find the number of bytes to copy.
|
||||
(xtensa_isa_init): Add error handling. Replace calls to
|
||||
xtensa_load_isa and xtensa_extend_isa with code to initialize lookup
|
||||
tables in the xtensa_modules structure.
|
||||
(xtensa_check_isa_config, xtensa_add_isa, xtensa_load_isa,
|
||||
xtensa_extend_isa): Delete.
|
||||
(xtensa_isa_free): Change to only free lookup tables.
|
||||
(opname_lookup_compare): Replace with ...
|
||||
(xtensa_isa_name_compare): ... this function. Use strcasecmp.
|
||||
(xtensa_insn_maxlength): Rename to ...
|
||||
(xtensa_isa_maxlength): ... this.
|
||||
(xtensa_insn_length): Delete.
|
||||
(xtensa_insn_length_from_first_byte): Replace with ...
|
||||
(xtensa_isa_length_from_chars): ... this function.
|
||||
(xtensa_num_opcodes): Rename to ...
|
||||
(xtensa_isa_num_opcodes): ... this.
|
||||
(xtensa_isa_num_pipe_stages, xtensa_isa_num_formats,
|
||||
xtensa_isa_num_regfiles, xtensa_isa_num_stages,
|
||||
xtensa_isa_num_sysregs, xtensa_isa_num_interfaces,
|
||||
xtensa_isa_num_funcUnits, xtensa_format_name, xtensa_format_lookup,
|
||||
xtensa_format_decode, xtensa_format_encode, xtensa_format_length,
|
||||
xtensa_format_num_slots, xtensa_format_slot_nop_opcode,
|
||||
xtensa_format_get_slot, xtensa_format_set_slot): New functions.
|
||||
(xtensa_opcode_lookup): Add error handling.
|
||||
(xtensa_decode_insn): Replace with ...
|
||||
(xtensa_opcode_decode): ... this function, with new format and
|
||||
slot parameters. Add error handling.
|
||||
(xtensa_encode_insn): Replace with ...
|
||||
(xtensa_opcode_encode): ... this function, which does the encoding via
|
||||
one of the entries in the "encode_fns" array. Add error handling.
|
||||
(xtensa_opcode_name): Add error handling.
|
||||
(xtensa_opcode_is_branch, xtensa_opcode_is_jump, xtensa_opcode_is_loop,
|
||||
xtensa_opcode_is_call): New.
|
||||
(xtensa_num_operands): Replace with ...
|
||||
(xtensa_opcode_num_operands): ... this function. Add error handling.
|
||||
(xtensa_opcode_num_stateOperands,
|
||||
xtensa_opcode_num_interfaceOperands, xtensa_opcode_num_funcUnit_uses,
|
||||
xtensa_opcode_funcUnit_use, xtensa_operand_name,
|
||||
xtensa_operand_is_visible): New.
|
||||
(xtensa_get_operand, xtensa_operand_kind): Delete.
|
||||
(xtensa_operand_inout): Add error handling and special-case for
|
||||
"sout" operands.
|
||||
(xtensa_operand_get_field, xtensa_operand_set_field): Rewritten to
|
||||
operate on one slot of an instruction. Added error handling.
|
||||
(xtensa_operand_encode): Handle default operands with no encoding
|
||||
functions. Check for success by comparing against decoded value.
|
||||
Add error handling.
|
||||
(xtensa_operand_decode): Handle default operands. Return decoded value
|
||||
through argument pointer. Add error handling.
|
||||
(xtensa_operand_is_register, xtensa_operand_regfile,
|
||||
xtensa_operand_num_regs, xtensa_operand_is_known_reg): New.
|
||||
(xtensa_operand_isPCRelative): Rename to ...
|
||||
(xtensa_operand_is_PCrelative): ... this. Add error handling.
|
||||
(xtensa_operand_do_reloc, xtensa_operand_undo_reloc): Return value
|
||||
through argument pointer. Add error handling.
|
||||
(xtensa_stateOperand_state, xtensa_stateOperand_inout,
|
||||
xtensa_interfaceOperand_interface, xtensa_regfile_lookup,
|
||||
xtensa_regfile_lookup_shortname, xtensa_regfile_name,
|
||||
xtensa_regfile_shortname, xtensa_regfile_view_parent,
|
||||
xtensa_regfile_num_bits, xtensa_regfile_num_entries,
|
||||
xtensa_state_lookup, xtensa_state_name, xtensa_state_num_bits,
|
||||
xtensa_state_is_exported, xtensa_sysreg_lookup,
|
||||
xtensa_sysreg_lookup_name, xtensa_sysreg_name, xtensa_sysreg_number,
|
||||
xtensa_sysreg_is_user, xtensa_interface_lookup, xtensa_interface_name,
|
||||
xtensa_interface_num_bits, xtensa_interface_inout,
|
||||
xtensa_interface_has_side_effect, xtensa_funcUnit_lookup,
|
||||
xtensa_funcUnit_name, xtensa_funcUnit_num_copies): New.
|
||||
* xtensa-modules.c: Rewrite to use new data structures.
|
||||
* reloc.c (BFD_RELOC_XTENSA_DIFF8, BFD_RELOC_XTENSA_DIFF16,
|
||||
BFD_RELOC_XTENSA_DIFF32, BFD_RELOC_XTENSA_SLOT0_OP,
|
||||
BFD_RELOC_XTENSA_SLOT1_OP, BFD_RELOC_XTENSA_SLOT2_OP,
|
||||
BFD_RELOC_XTENSA_SLOT3_OP, BFD_RELOC_XTENSA_SLOT4_OP,
|
||||
BFD_RELOC_XTENSA_SLOT5_OP, BFD_RELOC_XTENSA_SLOT6_OP,
|
||||
BFD_RELOC_XTENSA_SLOT7_OP, BFD_RELOC_XTENSA_SLOT8_OP,
|
||||
BFD_RELOC_XTENSA_SLOT9_OP, BFD_RELOC_XTENSA_SLOT10_OP,
|
||||
BFD_RELOC_XTENSA_SLOT11_OP, BFD_RELOC_XTENSA_SLOT12_OP,
|
||||
BFD_RELOC_XTENSA_SLOT13_OP, BFD_RELOC_XTENSA_SLOT14_OP,
|
||||
BFD_RELOC_XTENSA_SLOT0_ALT, BFD_RELOC_XTENSA_SLOT1_ALT,
|
||||
BFD_RELOC_XTENSA_SLOT2_ALT, BFD_RELOC_XTENSA_SLOT3_ALT,
|
||||
BFD_RELOC_XTENSA_SLOT4_ALT, BFD_RELOC_XTENSA_SLOT5_ALT,
|
||||
BFD_RELOC_XTENSA_SLOT6_ALT, BFD_RELOC_XTENSA_SLOT7_ALT,
|
||||
BFD_RELOC_XTENSA_SLOT8_ALT, BFD_RELOC_XTENSA_SLOT9_ALT,
|
||||
BFD_RELOC_XTENSA_SLOT10_ALT, BFD_RELOC_XTENSA_SLOT11_ALT,
|
||||
BFD_RELOC_XTENSA_SLOT12_ALT, BFD_RELOC_XTENSA_SLOT13_ALT,
|
||||
BFD_RELOC_XTENSA_SLOT14_ALT): Add new relocations.
|
||||
* Makefile.am (xtensa-isa.lo, xtensa-modules.lo): Update dependencies.
|
||||
* Makefile.in: Regenerate.
|
||||
* bfd-in2.h: Likewise.
|
||||
* libbfd.h: Likewise.
|
||||
|
||||
2004-10-07 Richard Sandiford <rsandifo@redhat.com>
|
||||
|
||||
* elf64-mips.c (mips_elf64_write_rel): Use STN_UNDEF for relocs
|
||||
|
||||
@ -1557,10 +1557,9 @@ xcofflink.lo: xcofflink.c $(INCDIR)/filenames.h $(INCDIR)/bfdlink.h \
|
||||
$(INCDIR)/coff/internal.h $(INCDIR)/coff/xcoff.h libcoff.h \
|
||||
libxcoff.h
|
||||
xsym.lo: xsym.c xsym.h $(INCDIR)/filenames.h
|
||||
xtensa-isa.lo: xtensa-isa.c $(INCDIR)/xtensa-isa.h \
|
||||
$(INCDIR)/xtensa-isa-internal.h
|
||||
xtensa-modules.lo: xtensa-modules.c $(INCDIR)/xtensa-isa.h \
|
||||
xtensa-isa.lo: xtensa-isa.c $(INCDIR)/filenames.h $(INCDIR)/xtensa-isa.h \
|
||||
$(INCDIR)/xtensa-isa-internal.h
|
||||
xtensa-modules.lo: xtensa-modules.c $(INCDIR)/xtensa-isa-internal.h
|
||||
aix5ppc-core.lo: aix5ppc-core.c
|
||||
aout64.lo: aout64.c aoutx.h $(INCDIR)/filenames.h $(INCDIR)/safe-ctype.h \
|
||||
$(INCDIR)/bfdlink.h libaout.h $(INCDIR)/aout/aout64.h \
|
||||
|
||||
@ -2112,10 +2112,9 @@ xcofflink.lo: xcofflink.c $(INCDIR)/filenames.h $(INCDIR)/bfdlink.h \
|
||||
$(INCDIR)/coff/internal.h $(INCDIR)/coff/xcoff.h libcoff.h \
|
||||
libxcoff.h
|
||||
xsym.lo: xsym.c xsym.h $(INCDIR)/filenames.h
|
||||
xtensa-isa.lo: xtensa-isa.c $(INCDIR)/xtensa-isa.h \
|
||||
$(INCDIR)/xtensa-isa-internal.h
|
||||
xtensa-modules.lo: xtensa-modules.c $(INCDIR)/xtensa-isa.h \
|
||||
xtensa-isa.lo: xtensa-isa.c $(INCDIR)/filenames.h $(INCDIR)/xtensa-isa.h \
|
||||
$(INCDIR)/xtensa-isa-internal.h
|
||||
xtensa-modules.lo: xtensa-modules.c $(INCDIR)/xtensa-isa-internal.h
|
||||
aix5ppc-core.lo: aix5ppc-core.c
|
||||
aout64.lo: aout64.c aoutx.h $(INCDIR)/filenames.h $(INCDIR)/safe-ctype.h \
|
||||
$(INCDIR)/bfdlink.h libaout.h $(INCDIR)/aout/aout64.h \
|
||||
|
||||
@ -3621,9 +3621,56 @@ to one of its own internal functions or data structures. */
|
||||
PLT entries. Otherwise, this is just a generic 32-bit relocation. */
|
||||
BFD_RELOC_XTENSA_PLT,
|
||||
|
||||
/* Generic Xtensa relocations. Only the operand number is encoded
|
||||
in the relocation. The details are determined by extracting the
|
||||
instruction opcode. */
|
||||
/* Xtensa relocations to mark the difference of two local symbols.
|
||||
These are only needed to support linker relaxation and can be ignored
|
||||
when not relaxing. The field is set to the value of the difference
|
||||
assuming no relaxation. The relocation encodes the position of the
|
||||
first symbol so the linker can determine whether to adjust the field
|
||||
value. */
|
||||
BFD_RELOC_XTENSA_DIFF8,
|
||||
BFD_RELOC_XTENSA_DIFF16,
|
||||
BFD_RELOC_XTENSA_DIFF32,
|
||||
|
||||
/* Generic Xtensa relocations for instruction operands. Only the slot
|
||||
number is encoded in the relocation. The relocation applies to the
|
||||
last PC-relative immediate operand, or if there are no PC-relative
|
||||
immediates, to the last immediate operand. */
|
||||
BFD_RELOC_XTENSA_SLOT0_OP,
|
||||
BFD_RELOC_XTENSA_SLOT1_OP,
|
||||
BFD_RELOC_XTENSA_SLOT2_OP,
|
||||
BFD_RELOC_XTENSA_SLOT3_OP,
|
||||
BFD_RELOC_XTENSA_SLOT4_OP,
|
||||
BFD_RELOC_XTENSA_SLOT5_OP,
|
||||
BFD_RELOC_XTENSA_SLOT6_OP,
|
||||
BFD_RELOC_XTENSA_SLOT7_OP,
|
||||
BFD_RELOC_XTENSA_SLOT8_OP,
|
||||
BFD_RELOC_XTENSA_SLOT9_OP,
|
||||
BFD_RELOC_XTENSA_SLOT10_OP,
|
||||
BFD_RELOC_XTENSA_SLOT11_OP,
|
||||
BFD_RELOC_XTENSA_SLOT12_OP,
|
||||
BFD_RELOC_XTENSA_SLOT13_OP,
|
||||
BFD_RELOC_XTENSA_SLOT14_OP,
|
||||
|
||||
/* Alternate Xtensa relocations. Only the slot is encoded in the
|
||||
relocation. The meaning of these relocations is opcode-specific. */
|
||||
BFD_RELOC_XTENSA_SLOT0_ALT,
|
||||
BFD_RELOC_XTENSA_SLOT1_ALT,
|
||||
BFD_RELOC_XTENSA_SLOT2_ALT,
|
||||
BFD_RELOC_XTENSA_SLOT3_ALT,
|
||||
BFD_RELOC_XTENSA_SLOT4_ALT,
|
||||
BFD_RELOC_XTENSA_SLOT5_ALT,
|
||||
BFD_RELOC_XTENSA_SLOT6_ALT,
|
||||
BFD_RELOC_XTENSA_SLOT7_ALT,
|
||||
BFD_RELOC_XTENSA_SLOT8_ALT,
|
||||
BFD_RELOC_XTENSA_SLOT9_ALT,
|
||||
BFD_RELOC_XTENSA_SLOT10_ALT,
|
||||
BFD_RELOC_XTENSA_SLOT11_ALT,
|
||||
BFD_RELOC_XTENSA_SLOT12_ALT,
|
||||
BFD_RELOC_XTENSA_SLOT13_ALT,
|
||||
BFD_RELOC_XTENSA_SLOT14_ALT,
|
||||
|
||||
/* Xtensa relocations for backward compatibility. These have all been
|
||||
replaced by BFD_RELOC_XTENSA_SLOT0_OP. */
|
||||
BFD_RELOC_XTENSA_OP0,
|
||||
BFD_RELOC_XTENSA_OP1,
|
||||
BFD_RELOC_XTENSA_OP2,
|
||||
|
||||
5665
bfd/elf32-xtensa.c
5665
bfd/elf32-xtensa.c
File diff suppressed because it is too large
Load Diff
33
bfd/libbfd.h
33
bfd/libbfd.h
@ -1650,6 +1650,39 @@ static const char *const bfd_reloc_code_real_names[] = { "@@uninitialized@@",
|
||||
"BFD_RELOC_XTENSA_JMP_SLOT",
|
||||
"BFD_RELOC_XTENSA_RELATIVE",
|
||||
"BFD_RELOC_XTENSA_PLT",
|
||||
"BFD_RELOC_XTENSA_DIFF8",
|
||||
"BFD_RELOC_XTENSA_DIFF16",
|
||||
"BFD_RELOC_XTENSA_DIFF32",
|
||||
"BFD_RELOC_XTENSA_SLOT0_OP",
|
||||
"BFD_RELOC_XTENSA_SLOT1_OP",
|
||||
"BFD_RELOC_XTENSA_SLOT2_OP",
|
||||
"BFD_RELOC_XTENSA_SLOT3_OP",
|
||||
"BFD_RELOC_XTENSA_SLOT4_OP",
|
||||
"BFD_RELOC_XTENSA_SLOT5_OP",
|
||||
"BFD_RELOC_XTENSA_SLOT6_OP",
|
||||
"BFD_RELOC_XTENSA_SLOT7_OP",
|
||||
"BFD_RELOC_XTENSA_SLOT8_OP",
|
||||
"BFD_RELOC_XTENSA_SLOT9_OP",
|
||||
"BFD_RELOC_XTENSA_SLOT10_OP",
|
||||
"BFD_RELOC_XTENSA_SLOT11_OP",
|
||||
"BFD_RELOC_XTENSA_SLOT12_OP",
|
||||
"BFD_RELOC_XTENSA_SLOT13_OP",
|
||||
"BFD_RELOC_XTENSA_SLOT14_OP",
|
||||
"BFD_RELOC_XTENSA_SLOT0_ALT",
|
||||
"BFD_RELOC_XTENSA_SLOT1_ALT",
|
||||
"BFD_RELOC_XTENSA_SLOT2_ALT",
|
||||
"BFD_RELOC_XTENSA_SLOT3_ALT",
|
||||
"BFD_RELOC_XTENSA_SLOT4_ALT",
|
||||
"BFD_RELOC_XTENSA_SLOT5_ALT",
|
||||
"BFD_RELOC_XTENSA_SLOT6_ALT",
|
||||
"BFD_RELOC_XTENSA_SLOT7_ALT",
|
||||
"BFD_RELOC_XTENSA_SLOT8_ALT",
|
||||
"BFD_RELOC_XTENSA_SLOT9_ALT",
|
||||
"BFD_RELOC_XTENSA_SLOT10_ALT",
|
||||
"BFD_RELOC_XTENSA_SLOT11_ALT",
|
||||
"BFD_RELOC_XTENSA_SLOT12_ALT",
|
||||
"BFD_RELOC_XTENSA_SLOT13_ALT",
|
||||
"BFD_RELOC_XTENSA_SLOT14_ALT",
|
||||
"BFD_RELOC_XTENSA_OP0",
|
||||
"BFD_RELOC_XTENSA_OP1",
|
||||
"BFD_RELOC_XTENSA_OP2",
|
||||
|
||||
86
bfd/reloc.c
86
bfd/reloc.c
@ -4142,6 +4142,87 @@ ENUM
|
||||
ENUMDOC
|
||||
Xtensa relocation used in ELF object files for symbols that may require
|
||||
PLT entries. Otherwise, this is just a generic 32-bit relocation.
|
||||
ENUM
|
||||
BFD_RELOC_XTENSA_DIFF8
|
||||
ENUMX
|
||||
BFD_RELOC_XTENSA_DIFF16
|
||||
ENUMX
|
||||
BFD_RELOC_XTENSA_DIFF32
|
||||
ENUMDOC
|
||||
Xtensa relocations to mark the difference of two local symbols.
|
||||
These are only needed to support linker relaxation and can be ignored
|
||||
when not relaxing. The field is set to the value of the difference
|
||||
assuming no relaxation. The relocation encodes the position of the
|
||||
first symbol so the linker can determine whether to adjust the field
|
||||
value.
|
||||
ENUM
|
||||
BFD_RELOC_XTENSA_SLOT0_OP
|
||||
ENUMX
|
||||
BFD_RELOC_XTENSA_SLOT1_OP
|
||||
ENUMX
|
||||
BFD_RELOC_XTENSA_SLOT2_OP
|
||||
ENUMX
|
||||
BFD_RELOC_XTENSA_SLOT3_OP
|
||||
ENUMX
|
||||
BFD_RELOC_XTENSA_SLOT4_OP
|
||||
ENUMX
|
||||
BFD_RELOC_XTENSA_SLOT5_OP
|
||||
ENUMX
|
||||
BFD_RELOC_XTENSA_SLOT6_OP
|
||||
ENUMX
|
||||
BFD_RELOC_XTENSA_SLOT7_OP
|
||||
ENUMX
|
||||
BFD_RELOC_XTENSA_SLOT8_OP
|
||||
ENUMX
|
||||
BFD_RELOC_XTENSA_SLOT9_OP
|
||||
ENUMX
|
||||
BFD_RELOC_XTENSA_SLOT10_OP
|
||||
ENUMX
|
||||
BFD_RELOC_XTENSA_SLOT11_OP
|
||||
ENUMX
|
||||
BFD_RELOC_XTENSA_SLOT12_OP
|
||||
ENUMX
|
||||
BFD_RELOC_XTENSA_SLOT13_OP
|
||||
ENUMX
|
||||
BFD_RELOC_XTENSA_SLOT14_OP
|
||||
ENUMDOC
|
||||
Generic Xtensa relocations for instruction operands. Only the slot
|
||||
number is encoded in the relocation. The relocation applies to the
|
||||
last PC-relative immediate operand, or if there are no PC-relative
|
||||
immediates, to the last immediate operand.
|
||||
ENUM
|
||||
BFD_RELOC_XTENSA_SLOT0_ALT
|
||||
ENUMX
|
||||
BFD_RELOC_XTENSA_SLOT1_ALT
|
||||
ENUMX
|
||||
BFD_RELOC_XTENSA_SLOT2_ALT
|
||||
ENUMX
|
||||
BFD_RELOC_XTENSA_SLOT3_ALT
|
||||
ENUMX
|
||||
BFD_RELOC_XTENSA_SLOT4_ALT
|
||||
ENUMX
|
||||
BFD_RELOC_XTENSA_SLOT5_ALT
|
||||
ENUMX
|
||||
BFD_RELOC_XTENSA_SLOT6_ALT
|
||||
ENUMX
|
||||
BFD_RELOC_XTENSA_SLOT7_ALT
|
||||
ENUMX
|
||||
BFD_RELOC_XTENSA_SLOT8_ALT
|
||||
ENUMX
|
||||
BFD_RELOC_XTENSA_SLOT9_ALT
|
||||
ENUMX
|
||||
BFD_RELOC_XTENSA_SLOT10_ALT
|
||||
ENUMX
|
||||
BFD_RELOC_XTENSA_SLOT11_ALT
|
||||
ENUMX
|
||||
BFD_RELOC_XTENSA_SLOT12_ALT
|
||||
ENUMX
|
||||
BFD_RELOC_XTENSA_SLOT13_ALT
|
||||
ENUMX
|
||||
BFD_RELOC_XTENSA_SLOT14_ALT
|
||||
ENUMDOC
|
||||
Alternate Xtensa relocations. Only the slot is encoded in the
|
||||
relocation. The meaning of these relocations is opcode-specific.
|
||||
ENUM
|
||||
BFD_RELOC_XTENSA_OP0
|
||||
ENUMX
|
||||
@ -4149,9 +4230,8 @@ ENUMX
|
||||
ENUMX
|
||||
BFD_RELOC_XTENSA_OP2
|
||||
ENUMDOC
|
||||
Generic Xtensa relocations. Only the operand number is encoded
|
||||
in the relocation. The details are determined by extracting the
|
||||
instruction opcode.
|
||||
Xtensa relocations for backward compatibility. These have all been
|
||||
replaced by BFD_RELOC_XTENSA_SLOT0_OP.
|
||||
ENUM
|
||||
BFD_RELOC_XTENSA_ASM_EXPAND
|
||||
ENUMDOC
|
||||
|
||||
2088
bfd/xtensa-isa.c
2088
bfd/xtensa-isa.c
File diff suppressed because it is too large
Load Diff
15093
bfd/xtensa-modules.c
15093
bfd/xtensa-modules.c
File diff suppressed because it is too large
Load Diff
430
gas/ChangeLog
430
gas/ChangeLog
@ -1,3 +1,433 @@
|
||||
2004-10-07 Bob Wilson <bob.wilson@acm.org>
|
||||
|
||||
* config/tc-xtensa.c (absolute_literals_supported): New global flag.
|
||||
(UNREACHABLE_MAX_WIDTH): Define.
|
||||
(XTENSA_FETCH_WIDTH): Delete.
|
||||
(cur_vinsn, xtensa_fetch_width, xt_saved_debug_type, past_xtensa_end,
|
||||
prefer_const16, prefer_l32r): New global variables.
|
||||
(LIT4_SECTION_NAME): Define.
|
||||
(lit4_state struct): Add lit4_seg_name and lit4_seg fields.
|
||||
(XTENSA_PROP_*, GET_XTENSA_PROP_*, SET_XTENSA_PROP_*): Define.
|
||||
(frag_flags struct): New.
|
||||
(xtensa_block_info struct): Move from tc-xtensa.h. Add flags field.
|
||||
(subseg_map struct): Add cur_total_freq and cur_target_freq fields.
|
||||
(bitfield, bit_is_set, set_bit, clear_bit): Define.
|
||||
(MAX_FORMATS): Define.
|
||||
(op_placement_info struct, op_placement_table): New.
|
||||
(O_pltrel, O_hi16, O_lo16): Define.
|
||||
(directiveE enum): Rename directive_generics to directive_transform.
|
||||
Delete directive_relax. Add directive_schedule,
|
||||
directive_absolute_literals, and directive_last_directive.
|
||||
(directive_info): Rename "generics" to "transform". Delete "relax".
|
||||
Add "schedule" and "absolute-literals".
|
||||
(directive_state): Adjust entries to match changes in directive_info.
|
||||
(xtensa_relax_statesE, RELAX_IMMED_MAXSTEPS): Move to tc-xtensa.h.
|
||||
(xtensa_const16_opcode, xtensa_movi_opcode, xtensa_movi_n_opcode,
|
||||
xtensa_l32r_opcode, xtensa_nop_opcode, xtensa_rsr_lcount_opcode): New.
|
||||
(xtensa_j_opcode, xtensa_rsr_opcode): Delete.
|
||||
(align_only_targets, software_a0_b_retw_interlock,
|
||||
software_avoid_b_j_loop_end, maybe_has_b_j_loop_end,
|
||||
software_avoid_short_loop, software_avoid_close_loop_end,
|
||||
software_avoid_all_short_loops, specific_opcode): Delete.
|
||||
(warn_unaligned_branch_targets): New.
|
||||
(workaround_a0_b_retw, workaround_b_j_loop_end, workaround_short_loop,
|
||||
workaround_close_loop_end, workaround_all_short_loops): Default FALSE.
|
||||
(option_[no_]link_relax, option_[no_]transform,
|
||||
option_[no_]absolute_literals, option_warn_unaligned_targets,
|
||||
option_prefer_l32r, option_prefer_const16, option_target_hardware):
|
||||
New enum values.
|
||||
(option_[no_]align_only_targets, option_literal_section_name,
|
||||
option_text_section_name, option_data_section_name,
|
||||
option_bss_section_name, option_eb, option_el): Delete.
|
||||
(md_longopts): Add entries for: [no-]transform, [no-]absolute-literals,
|
||||
warn-unaligned-targets, prefer-l32r, prefer-const16, [no-]link-relax,
|
||||
and target-hardware. Delete entries for [no-]target-align-only,
|
||||
literal-section-name, text-section-name, data-section-name, and
|
||||
bss-section-name.
|
||||
(md_parse_option): Handle new options and remove old ones. Accept but
|
||||
ignore [no-]density options. Warn for [no-]generics and [no-]relax
|
||||
and treat them as [no-]transform.
|
||||
(md_show_usage): Add new options and remove old ones.
|
||||
(xtensa_setup_hw_workarounds): New.
|
||||
(md_pseudo_table): Change "word" entry to use xtensa_elf_cons. Add
|
||||
"long", "short", "loc" and "frequency" entries.
|
||||
(use_generics): Rename to ...
|
||||
(use_transform): ... this function. Add past_xtensa_end check.
|
||||
(use_longcalls): Add past_xtensa_end check.
|
||||
(code_density_available, can_relax): Delete.
|
||||
(do_align_targets): New.
|
||||
(get_directive): Accept dashes in directive names. Warn about
|
||||
[no-]generics and [no-]relax directives and treat them as
|
||||
[no-]transform.
|
||||
(xtensa_begin_directive): Call md_flush_pending_output only for some
|
||||
directives. Check for directives inside instruction bundles. Warn
|
||||
about deprecated ".begin literal" usage. Warn and ignore [no-]density
|
||||
directives. Handle new directives. Check generating_literals flag
|
||||
for literal_prefix.
|
||||
(xtensa_end_directive): Check for directives inside instruction
|
||||
bundles. Warn and ignore [no-]density directives. Handle new
|
||||
directives. Call xtensa_set_frag_assembly_state.
|
||||
(xtensa_loc_directive_seen, xtensa_dwarf2_directive_loc,
|
||||
xtensa_dwarf2_emit_insn): New.
|
||||
(xtensa_literal_position): Call md_flush_pending_output. Do not check
|
||||
use_literal_section flag.
|
||||
(xtensa_literal_pseudo): Call md_flush_pending_output. Handle absolute
|
||||
literals. Use xtensa_elf_cons to parse the expression.
|
||||
(xtensa_literal_prefix): Do not check use_literal_section. Support
|
||||
".lit4" sections for absolute literals. Change prefix convention to
|
||||
replace ".text" (or ".t" in a linkonce section). No need to call
|
||||
subseg_set.
|
||||
(xtensa_frequency_pseudo, xtensa_elf_cons, xtensa_elf_suffix): New.
|
||||
(expression_end): Handle closing braces and colons.
|
||||
(PLT_SUFFIX, plt_suffix): Delete.
|
||||
(expression_maybe_register): Use new xtensa-isa.h functions. Use
|
||||
xtensa_elf_suffix instead of checking for plt suffix, and handle O_lo16
|
||||
and O_hi16 expressions as well.
|
||||
(tokenize_arguments): Handle closing braces and colons.
|
||||
(parse_arguments): Use new xtensa-isa.h functions. Handle "invisible"
|
||||
operands and paired register syntax.
|
||||
(get_invisible_operands): New.
|
||||
(xg_translate_sysreg_op): Handle new Xtensa LX RSR/WSR/XSR syntax. Use
|
||||
new xtensa-isa.h functions.
|
||||
(xtensa_translate_old_userreg_ops, xtensa_translate_zero_immed): New.
|
||||
(xg_translate_idioms): Check if inside bundle. Use use_transform.
|
||||
Handle new Xtensa LX RSR/WSR/XSR syntax. Remove code to widen density
|
||||
instructions. Use xtensa_translate_zero_immed.
|
||||
(operand_is_immed, operand_is_pcrel_label): Delete.
|
||||
(get_relaxable_immed): Use new xtensa-isa.h functions.
|
||||
(get_opcode_from_buf): Add slot parameter. Use new xtensa-isa.h
|
||||
functions.
|
||||
(xtensa_print_insn_table, print_vliw_insn): New.
|
||||
(is_direct_call_opcode): Use new xtensa-isa.h functions.
|
||||
(is_call_opcode, is_loop_opcode, is_conditional_branch_opcode,
|
||||
is_branch_or_jump_opcode): Delete.
|
||||
(is_movi_opcode, decode_reloc, encode_reloc, encode_alt_reloc): New.
|
||||
(opnum_to_reloc, reloc_to_opnum): Delete.
|
||||
(xtensa_insnbuf_set_operand, xtensa_insnbuf_get_operand): Use new
|
||||
xtensa-isa.h functions. Operate on one slot of an instruction.
|
||||
(xtensa_insnbuf_set_immediate_field, is_negatable_branch,
|
||||
xg_get_insn_size): Delete.
|
||||
(xg_get_build_instr_size): Use xg_get_single_size.
|
||||
(xg_is_narrow_insn, xg_is_single_relaxable_insn): Update calls to
|
||||
xg_build_widen_table. Use xg_get_single_size.
|
||||
(xg_get_max_narrow_insn_size): Delete.
|
||||
(xg_get_max_insn_widen_size, xg_get_max_insn_widen_literal_size,
|
||||
xg_is_relaxable_insn): Update calls to xg_build_widen_table. Use
|
||||
xg_get_single_size.
|
||||
(xg_build_to_insn): Record the loc field. Handle OP_OPERAND_HI16U and
|
||||
OP_OPERAND_LOW16U. Check xg_valid_literal_expression.
|
||||
(xg_expand_to_stack, xg_expand_narrow): Update calls to
|
||||
xg_build_widen_table. Use xg_get_single_size.
|
||||
(xg_immeds_fit): Use new xtensa-isa.h functions. Update call to
|
||||
xg_check_operand.
|
||||
(xg_symbolic_immeds_fit): Likewise. Also handle O_lo16 and O_hi16, and
|
||||
treat weak symbols conservatively.
|
||||
(xg_check_operand): Use new xtensa-isa.h functions.
|
||||
(is_dnrange): Delete.
|
||||
(xg_assembly_relax): Inline previous calls to tinsn_copy.
|
||||
(xg_finish_frag): Specify separate relax states for the frag and slot0.
|
||||
(is_branch_jmp_to_next, xg_add_branch_and_loop_targets): Use new
|
||||
xtensa-isa.h functions.
|
||||
(xg_instruction_matches_option_term, xg_instruction_matches_or_options,
|
||||
xg_instruction_matches_options): New.
|
||||
(xg_instruction_matches_rule): Handle O_register expressions. Call
|
||||
xg_instruction_matches_options.
|
||||
(transition_rule_cmp): New.
|
||||
(xg_instruction_match): Update call to xg_build_simplify_table.
|
||||
(xg_build_token_insn): Record loc fields.
|
||||
(xg_simplify_insn): Check is_specific_opcode field and
|
||||
density_supported flag.
|
||||
(xg_expand_assembly_insn): Skip checking code_density_available. Use
|
||||
new xtensa-isa.h functions. Call use_transform instead of can_relax.
|
||||
(xg_assemble_literal): Add error handling for O_big. Call
|
||||
record_alignment. Handle O_pltrel.
|
||||
(xg_valid_literal_expression): New.
|
||||
(xg_assemble_literal_space): Add slot parameter. Remove call to
|
||||
set_expr_symbol_offset. Add call to record_alignment. Update call to
|
||||
xg_finish_frag.
|
||||
(xg_emit_insn): Delete.
|
||||
(xg_emit_insn_to_buf): Add format parameter. Update calls to
|
||||
xg_add_opcode_fix and xtensa_insnbuf_to_chars.
|
||||
(xg_add_opcode_fix): Change opcode parameter to tinsn and add format
|
||||
and slot parameters. Handle new "alternate" relocations for absolute
|
||||
literals and CONST16 instructions. Check for bad uses of O_lo16 and
|
||||
O_hi16. Use new xtensa-isa.h functions.
|
||||
(xg_assemble_tokens): Delete.
|
||||
(is_register_writer): Use new xtensa-isa.h functions.
|
||||
(is_bad_loopend_opcode): Check for xtensa_rsr_lcount_opcode instead of
|
||||
old-style RSR from LCOUNT.
|
||||
(next_frag_opcode): Delete.
|
||||
(next_frag_opcode_is_loop, next_frag_format_size, frag_format_size,
|
||||
update_next_frag_state): New.
|
||||
(update_next_frag_nop_state): Delete.
|
||||
(next_frag_pre_opcode_bytes): Use next_frag_opcode_is_loop.
|
||||
(xtensa_mark_literal_pool_location): Check use_literal_section flag and
|
||||
the state of the absolute-literals directive. Add calls to
|
||||
record_alignment and xtensa_set_frag_assembly_state. Call
|
||||
xtensa_switch_to_non_abs_literal_fragment instead of
|
||||
xtensa_switch_to_literal_fragment.
|
||||
(build_nop): New.
|
||||
(assemble_nop): Use build_nop. Update call to xtensa_insnbuf_to_chars.
|
||||
(get_expanded_loop_offset): Change check for undefined opcode to an
|
||||
assertion.
|
||||
(xtensa_set_frag_assembly_state, relaxable_section,
|
||||
xtensa_find_unmarked_state_frags, xtensa_find_unaligned_branch_targets,
|
||||
xtensa_find_unaligned_loops, xg_apply_tentative_value): New.
|
||||
(md_begin): Update call to xtensa_isa_init. Initialize linkrelax to 1.
|
||||
Set lit4_seg_name. Call xg_init_vinsn. Initialize new global opcodes.
|
||||
Call init_op_placement_info_table and xtensa_set_frag_assembly_state.
|
||||
(xtensa_init_fix_data): New.
|
||||
(xtensa_frob_label): Reset label symbol to the current frag. Check
|
||||
do_align_targets and generating_literals flag. Propagate frequency
|
||||
info to new alignment frag. Call xtensa_set_frag_assembly_state.
|
||||
(xtensa_unrecognized_line): New.
|
||||
(xtensa_flush_pending_output): Check if inside a bundle. Add a call
|
||||
to xtensa_set_frag_assembly_state.
|
||||
(error_reset_cur_vinsn): New.
|
||||
(md_assemble): Remove check for literal frag. Remove call to
|
||||
istack_init. Call use_transform instead of use_generics. Parse
|
||||
explicit instruction format specifiers. Move code for
|
||||
a0_b_retw_interlock workaround to xg_assemble_vliw_tokens. Call
|
||||
error_reset_cur_vinsn on errors. Add call to get_invisible_operands.
|
||||
Add dwarf2_where call. Remote automatic alignment for ENTRY
|
||||
instructions. Move call to xtensa_clear_insn_labels to the end.
|
||||
Rearrange to handle bundles.
|
||||
(xtensa_cons_fix_new): Delete.
|
||||
(xtensa_handle_align): New.
|
||||
(xtensa_frag_init): Call xtensa_set_frag_assembly_state. Remove
|
||||
assignment to is_no_density field.
|
||||
(md_pcrel_from): Use new xtensa-isa.h functions. Use decode_reloc
|
||||
instead of reloc_to_opnum. Handle "alternate" relocations.
|
||||
(xtensa_force_relocation, xtensa_check_inside_bundle,
|
||||
xtensa_elf_section_change_hook): New.
|
||||
(xtensa_symbol_new_hook): Delete.
|
||||
(xtensa_fix_adjustable): Check for difference of symbols with an
|
||||
offset. Check for external and weak symbols.
|
||||
(md_apply_fix3): Remove cases for XTENSA_OP{0,1,2} relocs.
|
||||
(md_estimate_size_before_relax): Return expansion for the first slot.
|
||||
(tc_gen_reloc): Handle difference of symbols by producing
|
||||
XTENSA_DIFF{8,16,32} relocs and by writing the value of the difference
|
||||
into the output. Handle new XTENSA_SLOT*_OP relocs by storing the
|
||||
tentative values into the output when linkrelax is set.
|
||||
(XTENSA_PROP_SEC_NAME): Define.
|
||||
(xtensa_post_relax_hook): Call xtensa_find_unmarked_state_frags.
|
||||
Create literal tables only if using literal sections. Create new
|
||||
property tables instead of old instruction tables. Check for unaligned
|
||||
branch targets and loops.
|
||||
(finish_vinsn, find_vinsn_conflicts, check_t1_t2_reads_and_writes,
|
||||
new_resource_table, clear_resource_table, resize_resource_table,
|
||||
resources_available, reserve_resources, release_resources,
|
||||
opcode_funcUnit_use_unit, opcode_funcUnit_use_stage,
|
||||
resources_conflict, xg_find_narrowest_format, relaxation_requirements,
|
||||
bundle_single_op, emit_single_op, xg_assemble_vliw_tokens): New.
|
||||
(xtensa_end): Call xtensa_flush_pending_output. Set past_xtensa_end
|
||||
flag. Update checks for workaround options. Call
|
||||
xtensa_mark_narrow_branches and xtensa_mark_zcl_first_insns.
|
||||
(xtensa_cleanup_align_frags): Add special case for branch targets.
|
||||
Check for and mark unreachable frags.
|
||||
(xtensa_fix_target_frags): Remove use of align_only_targets flag.
|
||||
Use RELAX_LOOP_END_BYTES in special case for negatable branch at the
|
||||
end of a zero-overhead loop body.
|
||||
(frag_can_negate_branch): Handle instructions with multiple slots.
|
||||
Use new xtensa-isa.h functions
|
||||
(xtensa_mark_narrow_branches, is_narrow_branch_guaranteed_in_range,
|
||||
xtensa_mark_zcl_first_insns): New.
|
||||
(xtensa_fix_a0_b_retw_frags, xtensa_fix_b_j_loop_end_frags): Error if
|
||||
transformations are disabled.
|
||||
(next_instrs_are_b_retw): Use new xtensa-isa.h functions. Handle
|
||||
multislot instructions.
|
||||
(xtensa_fix_close_loop_end_frags, xtensa_fix_short_loop_frags):
|
||||
Likewise. Also error if transformations are disabled.
|
||||
(unrelaxed_frag_max_size): New.
|
||||
(unrelaxed_frag_min_insn_count, unrelax_frag_has_b_j): Use new
|
||||
xtensa-isa.h functions.
|
||||
(xtensa_sanity_check, is_empty_loop, is_local_forward_loop): Use
|
||||
xtensa_opcode_is_loop instead of is_loop_opcode.
|
||||
(get_text_align_power): Replace as_fatal with assertion.
|
||||
(get_text_align_fill_size): Iterate instead of using modulus when
|
||||
use_nops is false.
|
||||
(get_noop_aligned_address): Assert that this is for a machine-dependent
|
||||
RELAX_ALIGN_NEXT_OPCODE frag. Use next_frag_opcode_is_loop,
|
||||
xg_get_single_size, and frag_format_size.
|
||||
(get_widen_aligned_address): Rename to ...
|
||||
(get_aligned_diff): ... this function. Add max_diff parameter.
|
||||
Remove handling of rs_align/rs_align_code frags. Use
|
||||
next_frag_format_size, get_text_align_power, get_text_align_fill_size,
|
||||
next_frag_opcode_is_loop, and xg_get_single_size. Compute max_diff
|
||||
and pass it back to caller.
|
||||
(xtensa_relax_frag): Use relax_frag_loop_align. Add code for new
|
||||
RELAX_SLOTS, RELAX_MAYBE_UNREACHABLE, RELAX_MAYBE_DESIRE_ALIGN,
|
||||
RELAX_FILL_NOP, and RELAX_UNREACHABLE frag types. Check relax_seen.
|
||||
(relax_frag_text_align): Rename to ...
|
||||
(relax_frag_loop_align): ... this function. Assume loops can only be
|
||||
in the first slot of an instruction.
|
||||
(relax_frag_add_nop): Use assemble_nop instead of constructing an OR
|
||||
instruction. Remove call to frag_wane.
|
||||
(relax_frag_narrow): Rename to ...
|
||||
(relax_frag_for_align): ... this function. Extend to handle
|
||||
RELAX_FILL_NOP and RELAX_UNREACHABLE, as well as RELAX_SLOTS with
|
||||
RELAX_NARROW for the first slot.
|
||||
(find_address_of_next_align_frag, bytes_to_stretch): New.
|
||||
(future_alignment_required): Use find_address_of_next_align_frag and
|
||||
bytes_to_stretch. Look ahead to subsequent frags to make smarter
|
||||
alignment decisions.
|
||||
(relax_frag_immed): Add format, slot, and estimate_only parameters.
|
||||
Check if transformations are enabled for b_j_loop_end workaround.
|
||||
Use new xtensa-isa.h functions and handle multislot instructions.
|
||||
Update call to xg_assembly_relax.
|
||||
(md_convert_frag): Handle new RELAX_SLOTS, RELAX_UNREACHABLE,
|
||||
RELAX_MAYBE_UNREACHABLE, RELAX_MAYBE_DESIRE_ALIGN, and RELAX_FILL_NOP
|
||||
frag types.
|
||||
(convert_frag_narrow): Add segP, format and slot parameters. Call
|
||||
convert_frag_immed for branch instructions. Adjust calls to
|
||||
tinsn_from_chars, tinsn_immed_from_frag, and xg_emit_insn_to_buf. Use
|
||||
xg_get_single_size and xg_get_single_format.
|
||||
(convert_frag_fill_nop): New.
|
||||
(convert_frag_immed): Add format and slot parameters. Handle multislot
|
||||
instructions and use new xtensa-isa.h functions. Update calls to
|
||||
tinsn_immed_from_frag and xg_assembly_relax. Check if transformations
|
||||
enabled for b_j_loop_end workaround. Use build_nop instead of
|
||||
assemble_nop. Check is_specific_opcode flag. Check for unreachable
|
||||
frags. Use xg_get_single_size. Handle O_pltrel.
|
||||
(fix_new_exp_in_seg): Remove check for old plt flag.
|
||||
(convert_frag_immed_finish_loop): Update calls to tinsn_from_chars and
|
||||
xtensa_insnbuf_to_chars. Call tinsn_immed_from_frag. Change check
|
||||
for loop opcode to an assertion. Mark all frags up to the end of the
|
||||
loop as not transformable.
|
||||
(get_last_insn_flags, set_last_insn_flags): Use get_subseg_info.
|
||||
(get_subseg_info): New.
|
||||
(xtensa_move_literals): Call xtensa_set_frag_assembly_state. Add null
|
||||
check for dest_seg.
|
||||
(xtensa_switch_to_literal_fragment): Rewrite to handle absolute
|
||||
literals and use xtensa_switch_to_non_abs_literal_fragment otherwise.
|
||||
(xtensa_switch_to_non_abs_literal_fragment): New.
|
||||
(cache_literal_section): Add is_code parameter and pass it through to
|
||||
retrieve_literal_seg.
|
||||
(retrieve_literal_seg): Add is_code parameter and use it to set the
|
||||
flags on the literal section. Handle case where head parameter is 0.
|
||||
(get_frag_is_no_transform, set_frag_is_specific_opcode,
|
||||
set_frag_is_no_transform): New.
|
||||
(xtensa_create_property_segments): Add end_property_function parameter
|
||||
and pass it through to add_xt_block_frags. Call bfd_get_section_flags
|
||||
and skip SEC_DEBUGGING and !SEC_ALLOC sections.
|
||||
(xtensa_create_xproperty_segments, section_has_xproperty): New.
|
||||
(add_xt_block_frags): Add end_property_function parameter and call it
|
||||
if it is non-zero. Call xtensa_frag_flags_init.
|
||||
(xtensa_frag_flags_is_empty, xtensa_frag_flags_init,
|
||||
get_frag_property_flags, frag_flags_to_number,
|
||||
xtensa_frag_flags_combinable, xt_block_aligned_size,
|
||||
xtensa_xt_block_combine, add_xt_prop_frags,
|
||||
init_op_placement_info_table, opcode_fits_format_slot,
|
||||
xg_get_single_size, xg_get_single_format): New.
|
||||
(istack_push): Inline call to tinsn_copy.
|
||||
(tinsn_copy): Delete.
|
||||
(tinsn_has_invalid_symbolic_operands): Handle O_hi16 and O_lo16 and
|
||||
CONST16 opcodes. Handle O_big, O_illegal, and O_absent.
|
||||
(tinsn_has_complex_operands): Handle O_hi16 and O_lo16.
|
||||
(tinsn_to_insnbuf): Use xg_get_single_format and new xtensa-isa.h
|
||||
functions. Handle invisible operands.
|
||||
(tinsn_to_slotbuf): New.
|
||||
(tinsn_check_arguments): Use new xtensa-isa.h functions.
|
||||
(tinsn_from_chars): Add slot parameter. Rewrite using xg_init_vinsn,
|
||||
vinsn_from_chars, and xg_free_vinsn.
|
||||
(tinsn_from_insnbuf): New.
|
||||
(tinsn_immed_from_frag): Add slot parameter and handle multislot
|
||||
instructions. Handle symbol differences.
|
||||
(get_num_stack_text_bytes): Use xg_get_single_size.
|
||||
(xg_init_vinsn, xg_clear_vinsn, vinsn_has_specific_opcodes,
|
||||
xg_free_vinsn, vinsn_to_insnbuf, vinsn_from_chars, expr_is_register,
|
||||
get_expr_register, set_expr_symbol_offset_diff): New.
|
||||
* config/tc-xtensa.h (MAX_SLOTS): Define.
|
||||
(xtensa_relax_statesE): Move from tc-xtensa.c. Add
|
||||
RELAX_CHECK_ALIGN_NEXT_OPCODE, RELAX_MAYBE_DESIRE_ALIGN, RELAX_SLOTS,
|
||||
RELAX_FILL_NOP, RELAX_UNREACHABLE, RELAX_MAYBE_UNREACHABLE, and
|
||||
RELAX_NONE types.
|
||||
(RELAX_IMMED_MAXSTEPS): Move from tc-xtensa.c.
|
||||
(xtensa_frag_type struct): Add is_assembly_state_set,
|
||||
use_absolute_literals, relax_seen, is_unreachable, is_specific_opcode,
|
||||
is_align, is_text_align, alignment, and is_first_loop_insn fields.
|
||||
Replace is_generics and is_relax fields by is_no_transform field.
|
||||
Delete is_text and is_longcalls fields. Change text_expansion and
|
||||
literal_expansion to arrays of MAX_SLOTS entries. Add arrays of
|
||||
per-slot information: literal_frags, slot_subtypes, slot_symbols,
|
||||
slot_sub_symbols, and slot_offsets. Add fr_prev field.
|
||||
(xtensa_fix_data struct): New.
|
||||
(xtensa_symfield_type struct): Delete plt field.
|
||||
(xtensa_block_info struct): Move definition to tc-xtensa.h. Add
|
||||
forward declaration here.
|
||||
(xt_section_type enum): Delete xt_insn_sec. Add xt_prop_sec.
|
||||
(XTENSA_SECTION_RENAME): Undefine.
|
||||
(TC_FIX_TYPE, TC_INIT_FIX_DATA, TC_FORCE_RELOCATION, NO_PSEUDO_DOT,
|
||||
tc_unrecognized_line, md_do_align, md_elf_section_change_hook,
|
||||
HANDLE_ALIGN, TC_LINKRELAX_FIXUP, SUB_SEGMENT_ALIGN): Define.
|
||||
(TC_CONS_FIX_NEW, tc_symbol_new_hook): Delete.
|
||||
(unit_num_copies_func, opcode_num_units_func,
|
||||
opcode_funcUnit_use_unit_func, opcode_funcUnit_use_stage_func): New.
|
||||
(resource_table struct): New.
|
||||
* config/xtensa-istack.h (MAX_INSN_ARGS): Increase from 6 to 10.
|
||||
(TInsn struct): Add keep_wide, loc, fixup, record_fix, subtype,
|
||||
literal_space, symbol, sub_symbol, offset, and literal_frag fields.
|
||||
(tinsn_copy): Delete prototype.
|
||||
(vliw_insn struct): New.
|
||||
* config/xtensa-relax.c (insn_pattern_struct): Add options field.
|
||||
(widen_spec_list): Add option conditions for density and boolean
|
||||
instructions. Add expansions using CONST16 and conditions for using
|
||||
CONST16 vs. L32R. Use new Xtensa LX RSR/WSR syntax. Add entries for
|
||||
predicted branches.
|
||||
(simplify_spec_list): Add option conditions for density instructions.
|
||||
Add entry for NOP instruction.
|
||||
(append_transition): Add cmp function pointer parameter and use it to
|
||||
insert the new entry in order.
|
||||
(operand_function_LOW16U, operand_function_HI16U): New.
|
||||
(xg_has_userdef_op_fn, xg_apply_userdef_op_fn): Handle
|
||||
OP_OPERAND_LOW16U and OP_OPERAND_HI16U.
|
||||
(enter_opname, split_string): Use xstrdup instead of strdup.
|
||||
(init_insn_pattern): Initialize new options field.
|
||||
(clear_req_or_option_list, clear_req_option_list,
|
||||
clone_req_or_option_list, clone_req_option_list, parse_option_cond):
|
||||
New.
|
||||
(parse_insn_pattern): Parse option conditions.
|
||||
(transition_applies): New.
|
||||
(build_transition): Use new xtensa-isa.h functions. Fix incorrectly
|
||||
swapped last arguments in calls to append_constant_value_condition.
|
||||
Call clone_req_option_list. Add warning about invalid opcode.
|
||||
Handle LOW16U and HI16U function names.
|
||||
(build_transition_table): Add cmp parameter and use it in calls to
|
||||
append_transition. Use new xtensa-isa.h functions. Check
|
||||
transition_applies before adding entries.
|
||||
(xg_build_widen_table, xg_build_simplify_table): Add cmp parameter and
|
||||
pass it through to build_transition_table.
|
||||
* config/xtensa-relax.h (ReqOrOptionList, ReqOrOption, ReqOptionList,
|
||||
ReqOption, transition_cmp_fn): New types.
|
||||
(OpType enum): Add OP_OPERAND_LOW16U and OP_OPERAND_HI16U.
|
||||
(transition_rule struct): Add options field.
|
||||
* doc/as.texinfo (Overview): Update Xtensa options.
|
||||
* doc/c-xtensa.texi (Xtensa Options): Delete --[no-]density,
|
||||
--[no-]relax, and --[no-]generics options. Update descriptions of
|
||||
--text-section-literals and --[no-]longcalls. Add
|
||||
--[no-]absolute-literals and --[no-]transform.
|
||||
(Xtensa Syntax): Add description of syntax for FLIX instructions.
|
||||
Remove use of "generic" and "specific" terminology for opcodes.
|
||||
(Xtensa Registers): Generalize the syntax description to include
|
||||
user-defined register files.
|
||||
(Xtensa Automatic Alignment): Update.
|
||||
(Xtensa Branch Relaxation): Mention limitation of unconditional jumps.
|
||||
(Xtensa Call Relaxation): Linker can now remove most of the overhead.
|
||||
(Xtensa Directives): Remove confusing rules about precedence.
|
||||
(Density Directive, Relax Directive): Delete.
|
||||
(Schedule Directive): New.
|
||||
(Generics Directive): Rename to ...
|
||||
(Transform Directive): ... this node.
|
||||
(Literal Directive): Update for absolute literals. Missing
|
||||
literal_position directive is now an error.
|
||||
(Literal Position Directive): Update for absolute literals.
|
||||
(Freeregs Directive): Delete.
|
||||
(Absolute Literals Directive): New.
|
||||
(Frame Directive): Minor editing.
|
||||
* Makefile.am (DEPTC_xtensa_elf, DEPOBJ_xtensa_elf, DEP_xtensa_elf):
|
||||
Update dependencies.
|
||||
* Makefile.in: Regenerate.
|
||||
|
||||
2004-10-07 Richard Sandiford <rsandifo@redhat.com>
|
||||
|
||||
* config/tc-mips.c (append_insn): Use fix_new rather than fix_new_exp
|
||||
|
||||
@ -1552,9 +1552,9 @@ DEPTC_xstormy16_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
|
||||
DEPTC_xtensa_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
|
||||
$(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
|
||||
$(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-xtensa.h \
|
||||
$(INCDIR)/xtensa-config.h sb.h $(INCDIR)/safe-ctype.h \
|
||||
subsegs.h $(INCDIR)/obstack.h $(srcdir)/config/xtensa-relax.h \
|
||||
$(INCDIR)/xtensa-isa.h $(srcdir)/config/xtensa-istack.h \
|
||||
$(INCDIR)/xtensa-isa.h $(INCDIR)/xtensa-config.h sb.h \
|
||||
$(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
|
||||
$(srcdir)/config/xtensa-relax.h $(srcdir)/config/xtensa-istack.h \
|
||||
dwarf2dbg.h struc-symbol.h
|
||||
DEPTC_z8k_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
|
||||
$(srcdir)/config/tc-z8k.h $(INCDIR)/coff/internal.h \
|
||||
@ -2074,8 +2074,9 @@ DEPOBJ_xstormy16_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
|
||||
DEPOBJ_xtensa_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
|
||||
$(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
|
||||
$(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-xtensa.h \
|
||||
$(INCDIR)/xtensa-config.h $(INCDIR)/safe-ctype.h subsegs.h \
|
||||
$(INCDIR)/obstack.h struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
|
||||
$(INCDIR)/xtensa-isa.h $(INCDIR)/xtensa-config.h $(INCDIR)/safe-ctype.h \
|
||||
subsegs.h $(INCDIR)/obstack.h struc-symbol.h dwarf2dbg.h \
|
||||
$(INCDIR)/aout/aout64.h
|
||||
DEPOBJ_z8k_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
|
||||
$(srcdir)/config/tc-z8k.h $(INCDIR)/coff/internal.h \
|
||||
$(INCDIR)/coff/z8k.h $(INCDIR)/coff/external.h $(BFDDIR)/libcoff.h \
|
||||
@ -2423,7 +2424,7 @@ DEP_xstormy16_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
|
||||
DEP_xtensa_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
|
||||
$(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
|
||||
$(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-xtensa.h \
|
||||
$(INCDIR)/xtensa-config.h
|
||||
$(INCDIR)/xtensa-isa.h $(INCDIR)/xtensa-config.h
|
||||
DEP_z8k_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-z8k.h \
|
||||
$(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(INCDIR)/coff/z8k.h \
|
||||
$(INCDIR)/coff/external.h $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h
|
||||
|
||||
@ -1443,9 +1443,9 @@ DEPTC_xstormy16_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
|
||||
DEPTC_xtensa_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
|
||||
$(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
|
||||
$(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-xtensa.h \
|
||||
$(INCDIR)/xtensa-config.h sb.h $(INCDIR)/safe-ctype.h \
|
||||
subsegs.h $(INCDIR)/obstack.h $(srcdir)/config/xtensa-relax.h \
|
||||
$(INCDIR)/xtensa-isa.h $(srcdir)/config/xtensa-istack.h \
|
||||
$(INCDIR)/xtensa-isa.h $(INCDIR)/xtensa-config.h sb.h \
|
||||
$(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
|
||||
$(srcdir)/config/xtensa-relax.h $(srcdir)/config/xtensa-istack.h \
|
||||
dwarf2dbg.h struc-symbol.h
|
||||
|
||||
DEPTC_z8k_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
|
||||
@ -2084,8 +2084,9 @@ DEPOBJ_xstormy16_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
|
||||
DEPOBJ_xtensa_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
|
||||
$(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
|
||||
$(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-xtensa.h \
|
||||
$(INCDIR)/xtensa-config.h $(INCDIR)/safe-ctype.h subsegs.h \
|
||||
$(INCDIR)/obstack.h struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
|
||||
$(INCDIR)/xtensa-isa.h $(INCDIR)/xtensa-config.h $(INCDIR)/safe-ctype.h \
|
||||
subsegs.h $(INCDIR)/obstack.h struc-symbol.h dwarf2dbg.h \
|
||||
$(INCDIR)/aout/aout64.h
|
||||
|
||||
DEPOBJ_z8k_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
|
||||
$(srcdir)/config/tc-z8k.h $(INCDIR)/coff/internal.h \
|
||||
@ -2550,7 +2551,7 @@ DEP_xstormy16_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
|
||||
DEP_xtensa_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
|
||||
$(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
|
||||
$(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-xtensa.h \
|
||||
$(INCDIR)/xtensa-config.h
|
||||
$(INCDIR)/xtensa-isa.h $(INCDIR)/xtensa-config.h
|
||||
|
||||
DEP_z8k_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-z8k.h \
|
||||
$(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(INCDIR)/coff/z8k.h \
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -1,5 +1,5 @@
|
||||
/* tc-xtensa.h -- Header file for tc-xtensa.c.
|
||||
Copyright (C) 2003 Free Software Foundation, Inc.
|
||||
Copyright (C) 2003, 2004 Free Software Foundation, Inc.
|
||||
|
||||
This file is part of GAS, the GNU Assembler.
|
||||
|
||||
@ -33,61 +33,250 @@ struct fix;
|
||||
#error Xtensa support requires ELF object format
|
||||
#endif
|
||||
|
||||
#include "xtensa-isa.h"
|
||||
#include "xtensa-config.h"
|
||||
|
||||
#define TARGET_BYTES_BIG_ENDIAN XCHAL_HAVE_BE
|
||||
|
||||
|
||||
/* Maximum number of opcode slots in a VLIW instruction. */
|
||||
#define MAX_SLOTS 31
|
||||
|
||||
|
||||
/* For all xtensa relax states except RELAX_DESIRE_ALIGN and
|
||||
RELAX_DESIRE_ALIGN_IF_TARGET, the amount a frag might grow is stored
|
||||
in the fr_var field. For the two exceptions, fr_var is a float value
|
||||
that records the frequency with which the following instruction is
|
||||
executed as a branch target. The aligner uses this information to
|
||||
tell which targets are most important to be aligned. */
|
||||
|
||||
enum xtensa_relax_statesE
|
||||
{
|
||||
RELAX_ALIGN_NEXT_OPCODE,
|
||||
/* Use the first opcode of the next fragment to determine the
|
||||
alignment requirements. This is ONLY used for LOOPs currently. */
|
||||
|
||||
RELAX_CHECK_ALIGN_NEXT_OPCODE,
|
||||
/* The next non-empty frag contains a loop instruction. Check to see
|
||||
if it is correctly aligned, but do not align it. */
|
||||
|
||||
RELAX_DESIRE_ALIGN_IF_TARGET,
|
||||
/* These are placed in front of labels and converted to either
|
||||
RELAX_DESIRE_ALIGN / RELAX_LOOP_END or rs_fill of 0 before
|
||||
relaxation begins. */
|
||||
|
||||
RELAX_ADD_NOP_IF_A0_B_RETW,
|
||||
/* These are placed in front of conditional branches. Before
|
||||
relaxation begins, they are turned into either NOPs for branches
|
||||
immediately followed by RETW or RETW.N or rs_fills of 0. This is
|
||||
used to avoid a hardware bug in some early versions of the
|
||||
processor. */
|
||||
|
||||
RELAX_ADD_NOP_IF_PRE_LOOP_END,
|
||||
/* These are placed after JX instructions. Before relaxation begins,
|
||||
they are turned into either NOPs, if the JX is one instruction
|
||||
before a loop end label, or rs_fills of 0. This is used to avoid a
|
||||
hardware interlock issue prior to Xtensa version T1040. */
|
||||
|
||||
RELAX_ADD_NOP_IF_SHORT_LOOP,
|
||||
/* These are placed after LOOP instructions and turned into NOPs when:
|
||||
(1) there are less than 3 instructions in the loop; we place 2 of
|
||||
these in a row to add up to 2 NOPS in short loops; or (2) the
|
||||
instructions in the loop do not include a branch or jump.
|
||||
Otherwise they are turned into rs_fills of 0 before relaxation
|
||||
begins. This is used to avoid hardware bug PR3830. */
|
||||
|
||||
RELAX_ADD_NOP_IF_CLOSE_LOOP_END,
|
||||
/* These are placed after LOOP instructions and turned into NOPs if
|
||||
there are less than 12 bytes to the end of some other loop's end.
|
||||
Otherwise they are turned into rs_fills of 0 before relaxation
|
||||
begins. This is used to avoid hardware bug PR3830. */
|
||||
|
||||
RELAX_DESIRE_ALIGN,
|
||||
/* The next fragment would like its first instruction to NOT cross an
|
||||
instruction fetch boundary. */
|
||||
|
||||
RELAX_MAYBE_DESIRE_ALIGN,
|
||||
/* The next fragment might like its first instruction to NOT cross an
|
||||
instruction fetch boundary. These are placed after a branch that
|
||||
might be relaxed. If the branch is relaxed, then this frag will be
|
||||
a branch target and this frag will be changed to RELAX_DESIRE_ALIGN
|
||||
frag. */
|
||||
|
||||
RELAX_LOOP_END,
|
||||
/* This will be turned into a NOP or NOP.N if the previous instruction
|
||||
is expanded to negate a loop. */
|
||||
|
||||
RELAX_LOOP_END_ADD_NOP,
|
||||
/* When the code density option is available, this will generate a
|
||||
NOP.N marked RELAX_NARROW. Otherwise, it will create an rs_fill
|
||||
fragment with a NOP in it. */
|
||||
|
||||
RELAX_LITERAL,
|
||||
/* Another fragment could generate an expansion here but has not yet. */
|
||||
|
||||
RELAX_LITERAL_NR,
|
||||
/* Expansion has been generated by an instruction that generates a
|
||||
literal. However, the stretch has NOT been reported yet in this
|
||||
fragment. */
|
||||
|
||||
RELAX_LITERAL_FINAL,
|
||||
/* Expansion has been generated by an instruction that generates a
|
||||
literal. */
|
||||
|
||||
RELAX_LITERAL_POOL_BEGIN,
|
||||
RELAX_LITERAL_POOL_END,
|
||||
/* Technically these are not relaxations at all but mark a location
|
||||
to store literals later. Note that fr_var stores the frchain for
|
||||
BEGIN frags and fr_var stores now_seg for END frags. */
|
||||
|
||||
RELAX_NARROW,
|
||||
/* The last instruction in this fragment (at->fr_opcode) can be
|
||||
freely replaced with a single wider instruction if a future
|
||||
alignment desires or needs it. */
|
||||
|
||||
RELAX_IMMED,
|
||||
/* The last instruction in this fragment (at->fr_opcode) contains
|
||||
the value defined by fr_symbol (fr_offset = 0). If the value
|
||||
does not fit, use the specified expansion. This is similar to
|
||||
"NARROW", except that these may not be expanded in order to align
|
||||
code. */
|
||||
|
||||
RELAX_IMMED_STEP1,
|
||||
/* The last instruction in this fragment (at->fr_opcode) contains a
|
||||
literal. It has already been expanded at least 1 step. */
|
||||
|
||||
RELAX_IMMED_STEP2,
|
||||
/* The last instruction in this fragment (at->fr_opcode) contains a
|
||||
literal. It has already been expanded at least 2 steps. */
|
||||
|
||||
RELAX_SLOTS,
|
||||
/* There are instructions within the last VLIW instruction that need
|
||||
relaxation. Find the relaxation based on the slot info in
|
||||
xtensa_frag_type. Relaxations that deal with particular opcodes
|
||||
are slot-based (e.g., converting a MOVI to an L32R). Relaxations
|
||||
that deal with entire instructions, such as alignment, are not
|
||||
slot-based. */
|
||||
|
||||
RELAX_FILL_NOP,
|
||||
/* This marks the location of a pipeline stall. We can fill these guys
|
||||
in for alignment of any size. */
|
||||
|
||||
RELAX_UNREACHABLE,
|
||||
/* This marks the location as unreachable. The assembler may widen or
|
||||
narrow this area to meet alignment requirements of nearby
|
||||
instructions. */
|
||||
|
||||
RELAX_MAYBE_UNREACHABLE,
|
||||
/* This marks the location as possibly unreachable. These are placed
|
||||
after a branch that may be relaxed into a branch and jump. If the
|
||||
branch is relaxed, then this frag will be converted to a
|
||||
RELAX_UNREACHABLE frag. */
|
||||
|
||||
RELAX_NONE
|
||||
};
|
||||
|
||||
/* This is used as a stopper to bound the number of steps that
|
||||
can be taken. */
|
||||
#define RELAX_IMMED_MAXSTEPS (RELAX_IMMED_STEP2 - RELAX_IMMED)
|
||||
|
||||
struct xtensa_frag_type
|
||||
{
|
||||
unsigned is_literal:1;
|
||||
unsigned is_text:1;
|
||||
unsigned is_loop_target:1;
|
||||
unsigned is_branch_target:1;
|
||||
unsigned is_insn:1;
|
||||
/* Info about the current state of assembly, e.g., transform,
|
||||
absolute_literals, etc. These need to be passed to the backend and
|
||||
then to the object file.
|
||||
|
||||
/* Info about the current state of assembly, i.e., density, relax,
|
||||
generics, freeregs, longcalls. These need to be passed to the
|
||||
backend and then to the linking file. */
|
||||
When is_assembly_state_set is false, the frag inherits some of the
|
||||
state settings from the previous frag in this segment. Because it
|
||||
is not possible to intercept all fragment closures (frag_more and
|
||||
frag_append_1_char can close a frag), we use a pass after initial
|
||||
assembly to fill in the assembly states. */
|
||||
|
||||
unsigned is_no_density:1;
|
||||
unsigned is_relax:1;
|
||||
unsigned is_generics:1;
|
||||
unsigned is_longcalls:1;
|
||||
unsigned int is_assembly_state_set : 1;
|
||||
unsigned int is_no_density : 1;
|
||||
unsigned int is_no_transform : 1;
|
||||
unsigned int use_absolute_literals : 1;
|
||||
|
||||
/* Inhibits relaxation of machine-dependent alignment frags the
|
||||
first time through a relaxation.... */
|
||||
unsigned int relax_seen : 1;
|
||||
|
||||
/* Infomation that is needed in the object file and set when known. */
|
||||
unsigned int is_literal : 1;
|
||||
unsigned int is_loop_target : 1;
|
||||
unsigned int is_branch_target : 1;
|
||||
unsigned int is_insn : 1;
|
||||
unsigned int is_unreachable : 1;
|
||||
|
||||
unsigned int is_specific_opcode : 1; /* also implies no_transform */
|
||||
|
||||
unsigned int is_align : 1;
|
||||
unsigned int is_text_align : 1;
|
||||
unsigned int alignment : 5;
|
||||
|
||||
/* A frag with this bit set is the first in a loop that actually
|
||||
contains an instruction. */
|
||||
unsigned int is_first_loop_insn : 1;
|
||||
|
||||
/* For text fragments that can generate literals at relax time, this
|
||||
variable points to the frag where the literal will be stored. For
|
||||
literal frags, this variable points to the nearest literal pool
|
||||
location frag. This literal frag will be moved to after this
|
||||
location. */
|
||||
|
||||
fragS *literal_frag;
|
||||
|
||||
/* The destination segment for literal frags. (Note that this is only
|
||||
valid after xtensa_move_literals. */
|
||||
|
||||
segT lit_seg;
|
||||
|
||||
/* For the relaxation scheme, some literal fragments can have their
|
||||
expansions modified by an instruction that relaxes. */
|
||||
int text_expansion[MAX_SLOTS];
|
||||
int literal_expansion[MAX_SLOTS];
|
||||
int unreported_expansion;
|
||||
|
||||
unsigned text_expansion;
|
||||
unsigned literal_expansion;
|
||||
unsigned unreported_expansion;
|
||||
/* For text fragments that can generate literals at relax time: */
|
||||
fragS *literal_frags[MAX_SLOTS];
|
||||
enum xtensa_relax_statesE slot_subtypes[MAX_SLOTS];
|
||||
symbolS *slot_symbols[MAX_SLOTS];
|
||||
symbolS *slot_sub_symbols[MAX_SLOTS];
|
||||
offsetT slot_offsets[MAX_SLOTS];
|
||||
|
||||
/* The global aligner needs to walk backward through the list of
|
||||
frags. This field is only valid after xtensa_end. */
|
||||
fragS *fr_prev;
|
||||
};
|
||||
|
||||
typedef struct xtensa_block_info_struct
|
||||
{
|
||||
segT sec;
|
||||
bfd_vma offset;
|
||||
size_t size;
|
||||
struct xtensa_block_info_struct *next;
|
||||
} xtensa_block_info;
|
||||
|
||||
/* For VLIW support, we need to know what slot a fixup applies to. */
|
||||
typedef struct xtensa_fix_data_struct
|
||||
{
|
||||
int slot;
|
||||
symbolS *X_add_symbol;
|
||||
offsetT X_add_number;
|
||||
} xtensa_fix_data;
|
||||
|
||||
|
||||
/* Structure to record xtensa-specific symbol information. */
|
||||
typedef struct xtensa_symfield_type
|
||||
{
|
||||
unsigned int is_loop_target : 1;
|
||||
unsigned int is_branch_target : 1;
|
||||
} xtensa_symfield_type;
|
||||
|
||||
|
||||
/* Structure for saving information about a block of property data
|
||||
for frags that have the same flags. The forward reference is
|
||||
in this header file. The actual definition is in tc-xtensa.c. */
|
||||
struct xtensa_block_info_struct;
|
||||
typedef struct xtensa_block_info_struct xtensa_block_info;
|
||||
|
||||
|
||||
/* Property section types. */
|
||||
typedef enum
|
||||
{
|
||||
xt_insn_sec,
|
||||
xt_literal_sec,
|
||||
xt_prop_sec,
|
||||
max_xt_sec
|
||||
} xt_section_type;
|
||||
|
||||
@ -97,17 +286,9 @@ typedef struct xtensa_segment_info_struct
|
||||
xtensa_block_info *blocks[max_xt_sec];
|
||||
} xtensa_segment_info;
|
||||
|
||||
typedef struct xtensa_symfield_type_struct
|
||||
{
|
||||
unsigned int plt : 1;
|
||||
unsigned int is_loop_target : 1;
|
||||
unsigned int is_branch_target : 1;
|
||||
} xtensa_symfield_type;
|
||||
|
||||
|
||||
/* Section renaming is only supported in Tensilica's version of GAS. */
|
||||
#define XTENSA_SECTION_RENAME 1
|
||||
#ifdef XTENSA_SECTION_RENAME
|
||||
#ifdef XTENSA_SECTION_RENAME
|
||||
extern const char *xtensa_section_rename
|
||||
PARAMS ((const char *));
|
||||
#else
|
||||
@ -118,10 +299,12 @@ extern const char *xtensa_section_rename
|
||||
|
||||
extern const char *xtensa_target_format
|
||||
PARAMS ((void));
|
||||
extern void xtensa_init_fix_data
|
||||
PARAMS ((struct fix *));
|
||||
extern void xtensa_frag_init
|
||||
PARAMS ((fragS *));
|
||||
extern void xtensa_cons_fix_new
|
||||
PARAMS ((fragS *, int, int, expressionS *));
|
||||
extern int xtensa_force_relocation
|
||||
PARAMS ((struct fix *));
|
||||
extern void xtensa_frob_label
|
||||
PARAMS ((struct symbol *));
|
||||
extern void xtensa_end
|
||||
@ -138,19 +321,32 @@ extern void xtensa_symbol_new_hook
|
||||
PARAMS ((symbolS *));
|
||||
extern long xtensa_relax_frag
|
||||
PARAMS ((fragS *, long, int *));
|
||||
extern void xtensa_elf_section_change_hook
|
||||
PARAMS ((void));
|
||||
extern int xtensa_unrecognized_line
|
||||
PARAMS ((int));
|
||||
extern bfd_boolean xtensa_check_inside_bundle
|
||||
PARAMS ((void));
|
||||
extern void xtensa_handle_align
|
||||
PARAMS ((fragS *));
|
||||
|
||||
#define TARGET_FORMAT xtensa_target_format ()
|
||||
#define TARGET_ARCH bfd_arch_xtensa
|
||||
#define TC_SEGMENT_INFO_TYPE xtensa_segment_info
|
||||
#define TC_SYMFIELD_TYPE xtensa_symfield_type
|
||||
#define TC_SYMFIELD_TYPE struct xtensa_symfield_type
|
||||
#define TC_FIX_TYPE xtensa_fix_data
|
||||
#define TC_INIT_FIX_DATA(x) xtensa_init_fix_data (x)
|
||||
#define TC_FRAG_TYPE struct xtensa_frag_type
|
||||
#define TC_FRAG_INIT(frag) xtensa_frag_init (frag)
|
||||
#define TC_CONS_FIX_NEW xtensa_cons_fix_new
|
||||
#define TC_FORCE_RELOCATION(fix) xtensa_force_relocation (fix)
|
||||
#define NO_PSEUDO_DOT xtensa_check_inside_bundle ()
|
||||
#define tc_canonicalize_symbol_name(s) xtensa_section_rename (s)
|
||||
#define tc_init_after_args() xtensa_file_arch_init (stdoutput)
|
||||
#define tc_fix_adjustable(fix) xtensa_fix_adjustable (fix)
|
||||
#define tc_frob_label(sym) xtensa_frob_label (sym)
|
||||
#define tc_symbol_new_hook(s) xtensa_symbol_new_hook (s)
|
||||
#define tc_unrecognized_line(ch) xtensa_unrecognized_line (ch)
|
||||
#define md_do_align(a,b,c,d,e) xtensa_flush_pending_output ()
|
||||
#define md_elf_section_change_hook xtensa_elf_section_change_hook
|
||||
#define md_elf_section_rename(name) xtensa_section_rename (name)
|
||||
#define md_end xtensa_end
|
||||
#define md_flush_pending_output() xtensa_flush_pending_output ()
|
||||
@ -158,6 +354,7 @@ extern long xtensa_relax_frag
|
||||
#define TEXT_SECTION_NAME xtensa_section_rename (".text")
|
||||
#define DATA_SECTION_NAME xtensa_section_rename (".data")
|
||||
#define BSS_SECTION_NAME xtensa_section_rename (".bss")
|
||||
#define HANDLE_ALIGN(fragP) xtensa_handle_align (fragP)
|
||||
|
||||
|
||||
/* The renumber_section function must be mapped over all the sections
|
||||
@ -188,7 +385,66 @@ extern long xtensa_relax_frag
|
||||
#define DOUBLESLASH_LINE_COMMENTS
|
||||
#define TC_HANDLES_FX_DONE
|
||||
#define TC_FINALIZE_SYMS_BEFORE_SIZE_SEG 0
|
||||
|
||||
#define TC_LINKRELAX_FIXUP(SEG) 0
|
||||
#define MD_APPLY_SYM_VALUE(FIX) 0
|
||||
#define SUB_SEGMENT_ALIGN(SEG, FRCHAIN) 0
|
||||
|
||||
|
||||
/* Resource reservation info functions. */
|
||||
|
||||
/* Returns the number of copies of a particular unit. */
|
||||
typedef int (*unit_num_copies_func) (void *, xtensa_funcUnit);
|
||||
|
||||
/* Returns the number of units the opcode uses. */
|
||||
typedef int (*opcode_num_units_func) (void *, xtensa_opcode);
|
||||
|
||||
/* Given an opcode and an index into the opcode's funcUnit list,
|
||||
returns the unit used for the index. */
|
||||
typedef int (*opcode_funcUnit_use_unit_func) (void *, xtensa_opcode, int);
|
||||
|
||||
/* Given an opcode and an index into the opcode's funcUnit list,
|
||||
returns the cycle during which the unit is used. */
|
||||
typedef int (*opcode_funcUnit_use_stage_func) (void *, xtensa_opcode, int);
|
||||
|
||||
/* The above typedefs parameterize the resource_table so that the
|
||||
optional scheduler doesn't need its own resource reservation system.
|
||||
|
||||
For simple resource checking, which is all that happens normally,
|
||||
the functions will be as follows (with some wrapping to make the
|
||||
interface more convenient):
|
||||
|
||||
unit_num_copies_func = xtensa_funcUnit_num_copies
|
||||
opcode_num_units_func = xtensa_opcode_num_funcUnit_uses
|
||||
opcode_funcUnit_use_unit_func = xtensa_opcode_funcUnit_use->unit
|
||||
opcode_funcUnit_use_stage_func = xtensa_opcode_funcUnit_use->stage
|
||||
|
||||
Of course the optional scheduler has its own reservation table
|
||||
and functions. */
|
||||
|
||||
int opcode_funcUnit_use_unit PARAMS ((void *, xtensa_opcode, int));
|
||||
int opcode_funcUnit_use_stage PARAMS ((void *, xtensa_opcode, int));
|
||||
|
||||
typedef struct
|
||||
{
|
||||
void *data;
|
||||
int cycles;
|
||||
int allocated_cycles;
|
||||
int num_units;
|
||||
unit_num_copies_func unit_num_copies;
|
||||
opcode_num_units_func opcode_num_units;
|
||||
opcode_funcUnit_use_unit_func opcode_unit_use;
|
||||
opcode_funcUnit_use_stage_func opcode_unit_stage;
|
||||
char **units;
|
||||
} resource_table;
|
||||
|
||||
resource_table *new_resource_table
|
||||
PARAMS ((void *, int, int, unit_num_copies_func, opcode_num_units_func,
|
||||
opcode_funcUnit_use_unit_func, opcode_funcUnit_use_stage_func));
|
||||
void resize_resource_table PARAMS ((resource_table *, int));
|
||||
void clear_resource_table PARAMS ((resource_table *));
|
||||
bfd_boolean resources_available
|
||||
PARAMS ((resource_table *, xtensa_opcode, int));
|
||||
void reserve_resources PARAMS ((resource_table *, xtensa_opcode, int));
|
||||
void release_resources PARAMS ((resource_table *, xtensa_opcode, int));
|
||||
|
||||
#endif /* TC_XTENSA */
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
/* Declarations for stacks of tokenized Xtensa instructions.
|
||||
Copyright (C) 2003 Free Software Foundation, Inc.
|
||||
Copyright (C) 2003, 2004 Free Software Foundation, Inc.
|
||||
|
||||
This file is part of GAS, the GNU Assembler.
|
||||
|
||||
@ -21,10 +21,11 @@
|
||||
#ifndef XTENSA_ISTACK_H
|
||||
#define XTENSA_ISTACK_H
|
||||
|
||||
#include "dwarf2dbg.h"
|
||||
#include "xtensa-isa.h"
|
||||
|
||||
#define MAX_ISTACK 12
|
||||
#define MAX_INSN_ARGS 6
|
||||
#define MAX_INSN_ARGS 10
|
||||
|
||||
enum itype_enum
|
||||
{
|
||||
@ -40,11 +41,25 @@ enum itype_enum
|
||||
typedef struct tinsn_struct
|
||||
{
|
||||
enum itype_enum insn_type;
|
||||
|
||||
bfd_boolean is_specific_opcode;
|
||||
|
||||
xtensa_opcode opcode; /* Literals have an invalid opcode. */
|
||||
bfd_boolean is_specific_opcode;
|
||||
bfd_boolean keep_wide;
|
||||
int ntok;
|
||||
expressionS tok[MAX_INSN_ARGS];
|
||||
struct dwarf2_line_info loc;
|
||||
|
||||
struct fixP *fixup;
|
||||
|
||||
/* Filled out by relaxation_requirements: */
|
||||
bfd_boolean record_fix;
|
||||
enum xtensa_relax_statesE subtype;
|
||||
int literal_space;
|
||||
/* Filled out by vinsn_to_insnbuf: */
|
||||
symbolS *symbol;
|
||||
symbolS *sub_symbol;
|
||||
offsetT offset;
|
||||
fragS *literal_frag;
|
||||
} TInsn;
|
||||
|
||||
|
||||
@ -57,17 +72,29 @@ typedef struct tinsn_stack
|
||||
} IStack;
|
||||
|
||||
|
||||
void istack_init PARAMS ((IStack *));
|
||||
bfd_boolean istack_empty PARAMS ((IStack *));
|
||||
bfd_boolean istack_full PARAMS ((IStack *));
|
||||
TInsn * istack_top PARAMS ((IStack *));
|
||||
void istack_push PARAMS ((IStack *, TInsn *));
|
||||
TInsn * istack_push_space PARAMS ((IStack *));
|
||||
void istack_pop PARAMS ((IStack *));
|
||||
void istack_init PARAMS ((IStack *));
|
||||
bfd_boolean istack_empty PARAMS ((IStack *));
|
||||
bfd_boolean istack_full PARAMS ((IStack *));
|
||||
TInsn *istack_top PARAMS ((IStack *));
|
||||
void istack_push PARAMS ((IStack *, TInsn *));
|
||||
TInsn *istack_push_space PARAMS ((IStack *));
|
||||
void istack_pop PARAMS ((IStack *));
|
||||
|
||||
/* TInsn utilities. */
|
||||
void tinsn_init PARAMS ((TInsn *));
|
||||
void tinsn_copy PARAMS ((TInsn *, const TInsn *));
|
||||
expressionS *tinsn_get_tok PARAMS ((TInsn *, int));
|
||||
void tinsn_init PARAMS ((TInsn *));
|
||||
expressionS *tinsn_get_tok PARAMS ((TInsn *, int));
|
||||
|
||||
|
||||
/* vliw_insn: bundles of TInsns. */
|
||||
|
||||
typedef struct vliw_insn
|
||||
{
|
||||
xtensa_format format;
|
||||
xtensa_insnbuf insnbuf;
|
||||
int num_slots;
|
||||
unsigned int inside_bundle;
|
||||
TInsn slots[MAX_SLOTS];
|
||||
xtensa_insnbuf slotbuf[MAX_SLOTS];
|
||||
} vliw_insn;
|
||||
|
||||
#endif /* !XTENSA_ISTACK_H */
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -1,5 +1,5 @@
|
||||
/* Table of relaxations for Xtensa assembly.
|
||||
Copyright 2003 Free Software Foundation, Inc.
|
||||
Copyright 2003, 2004 Free Software Foundation, Inc.
|
||||
|
||||
This file is part of GAS, the GNU Assembler.
|
||||
|
||||
@ -33,6 +33,11 @@ typedef struct transition_rule TransitionRule;
|
||||
typedef struct precondition_list PreconditionList;
|
||||
typedef struct precondition Precondition;
|
||||
|
||||
typedef struct req_or_option_list ReqOrOptionList;
|
||||
typedef struct req_or_option_list ReqOrOption;
|
||||
typedef struct req_option_list ReqOptionList;
|
||||
typedef struct req_option_list ReqOption;
|
||||
|
||||
struct transition_table
|
||||
{
|
||||
int num_opcodes;
|
||||
@ -52,6 +57,38 @@ struct precondition_list
|
||||
};
|
||||
|
||||
|
||||
/* The required options for a rule are represented with a two-level
|
||||
structure, with leaf expressions combined by logical ORs at the
|
||||
lower level, and the results then combined by logical ANDs at the
|
||||
top level. The AND terms are linked in a list, and each one can
|
||||
contain a reference to a list of OR terms. The leaf expressions,
|
||||
i.e., the OR options, can be negated by setting the is_true field
|
||||
to FALSE. There are two classes of leaf expressions: (1) those
|
||||
that are properties of the Xtensa configuration and can be
|
||||
evaluated once when building the tables, and (2) those that depend
|
||||
of the state of directives or other settings that may vary during
|
||||
the assembly. The following expressions may be used in group (1):
|
||||
|
||||
IsaUse*: Xtensa configuration settings.
|
||||
realnop: TRUE if the instruction set includes a NOP instruction.
|
||||
|
||||
There are currently no expressions in group (2), but they are still
|
||||
supported since there is a good chance they'll be needed again for
|
||||
something. */
|
||||
|
||||
struct req_option_list
|
||||
{
|
||||
ReqOrOptionList *or_option_terms;
|
||||
ReqOptionList *next;
|
||||
};
|
||||
|
||||
struct req_or_option_list
|
||||
{
|
||||
char *option_name;
|
||||
bfd_boolean is_true;
|
||||
ReqOrOptionList *next;
|
||||
};
|
||||
|
||||
/* Operand types and constraints on operands: */
|
||||
|
||||
typedef enum op_type OpType;
|
||||
@ -62,9 +99,11 @@ enum op_type
|
||||
OP_CONSTANT,
|
||||
OP_OPERAND,
|
||||
OP_OPERAND_LOW8, /* Sign-extended low 8 bits of immed. */
|
||||
OP_OPERAND_HI24S, /* high 24 bits of immed,
|
||||
OP_OPERAND_HI24S, /* High 24 bits of immed,
|
||||
plus 0x100 if low 8 bits are signed. */
|
||||
OP_OPERAND_F32MINUS, /* 32 - immed. */
|
||||
OP_OPERAND_LOW16U, /* Low 16 bits of immed. */
|
||||
OP_OPERAND_HI16U, /* High 16 bits of immed. */
|
||||
OP_LITERAL,
|
||||
OP_LABEL
|
||||
};
|
||||
@ -85,6 +124,7 @@ struct precondition
|
||||
int op_data;
|
||||
};
|
||||
|
||||
|
||||
typedef struct build_op BuildOp;
|
||||
|
||||
struct build_op
|
||||
@ -117,7 +157,7 @@ struct build_instr
|
||||
InstrType typ;
|
||||
unsigned id; /* LITERAL_DEF or LABEL_DEF: an ordinal to
|
||||
identify which one. */
|
||||
xtensa_opcode opcode; /* unused for LITERAL_DEF or LABEL_DEF. */
|
||||
xtensa_opcode opcode; /* Unused for LITERAL_DEF or LABEL_DEF. */
|
||||
BuildOp *ops;
|
||||
BuildInstr *next;
|
||||
};
|
||||
@ -126,17 +166,17 @@ struct transition_rule
|
||||
{
|
||||
xtensa_opcode opcode;
|
||||
PreconditionList *conditions;
|
||||
ReqOptionList *options;
|
||||
BuildInstr *to_instr;
|
||||
};
|
||||
|
||||
extern TransitionTable *xg_build_simplify_table
|
||||
PARAMS ((void));
|
||||
extern TransitionTable *xg_build_widen_table
|
||||
PARAMS ((void));
|
||||
typedef int (*transition_cmp_fn) (const TransitionRule *,
|
||||
const TransitionRule *);
|
||||
|
||||
extern bfd_boolean xg_has_userdef_op_fn
|
||||
PARAMS ((OpType));
|
||||
extern long xg_apply_userdef_op_fn
|
||||
PARAMS ((OpType, long));
|
||||
extern TransitionTable *xg_build_simplify_table PARAMS ((transition_cmp_fn));
|
||||
extern TransitionTable *xg_build_widen_table PARAMS ((transition_cmp_fn));
|
||||
|
||||
extern bfd_boolean xg_has_userdef_op_fn PARAMS ((OpType));
|
||||
extern long xg_apply_userdef_op_fn PARAMS ((OpType, long));
|
||||
|
||||
#endif /* !XTENSA_RELAX_H */
|
||||
|
||||
@ -420,9 +420,9 @@ gcc(1), ld(1), and the Info entries for @file{binutils} and @file{ld}.
|
||||
@ifset XTENSA
|
||||
|
||||
@emph{Target Xtensa options:}
|
||||
[@b{--[no-]density}] [@b{--[no-]relax}] [@b{--[no-]generics}]
|
||||
[@b{--[no-]text-section-literals}]
|
||||
[@b{--[no-]text-section-literals}] [@b{--[no-]absolute-literals}]
|
||||
[@b{--[no-]target-align}] [@b{--[no-]longcalls}]
|
||||
[@b{--[no-]transform}]
|
||||
@end ifset
|
||||
@c man end
|
||||
@end smallexample
|
||||
@ -1061,28 +1061,19 @@ The following options are available when @value{AS} is configured for
|
||||
an Xtensa processor.
|
||||
|
||||
@table @gcctabopt
|
||||
@item --density | --no-density
|
||||
Enable or disable use of instructions from the Xtensa code density
|
||||
option. This is enabled by default when the Xtensa processor supports
|
||||
the code density option.
|
||||
|
||||
@item --relax | --no-relax
|
||||
Enable or disable instruction relaxation. This is enabled by default.
|
||||
Note: In the current implementation, these options also control whether
|
||||
assembler optimizations are performed, making these options equivalent
|
||||
to @option{--generics} and @option{--no-generics}.
|
||||
|
||||
@item --generics | --no-generics
|
||||
Enable or disable all assembler transformations of Xtensa instructions.
|
||||
The default is @option{--generics};
|
||||
@option{--no-generics} should be used only in the rare cases when the
|
||||
instructions must be exactly as specified in the assembly source.
|
||||
|
||||
@item --text-section-literals | --no-text-section-literals
|
||||
With @option{--text-@-section-@-literals}, literal pools are interspersed
|
||||
in the text section. The default is
|
||||
@option{--no-@-text-@-section-@-literals}, which places literals in a
|
||||
separate section in the output file.
|
||||
separate section in the output file. These options only affect literals
|
||||
referenced via PC-relative @code{L32R} instructions; literals for
|
||||
absolute mode @code{L32R} instructions are handled separately.
|
||||
|
||||
@item --absolute-literals | --no-absolute-literals
|
||||
Indicate to the assembler whether @code{L32R} instructions use absolute
|
||||
or PC-relative addressing. The default is to assume absolute addressing
|
||||
if the Xtensa processor includes the absolute @code{L32R} addressing
|
||||
option. Otherwise, only the PC-relative @code{L32R} mode can be used.
|
||||
|
||||
@item --target-align | --no-target-align
|
||||
Enable or disable automatic alignment to reduce branch penalties at the
|
||||
@ -1092,6 +1083,12 @@ expense of some code density. The default is @option{--target-@-align}.
|
||||
Enable or disable transformation of call instructions to allow calls
|
||||
across a greater range of addresses. The default is
|
||||
@option{--no-@-longcalls}.
|
||||
|
||||
@item --transform | --no-transform
|
||||
Enable or disable all assembler transformations of Xtensa instructions.
|
||||
The default is @option{--transform};
|
||||
@option{--no-transform} should be used only in the rare cases when the
|
||||
instructions must be exactly as specified in the assembly source.
|
||||
@end table
|
||||
@end ifset
|
||||
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
@c Copyright (C) 2002 Free Software Foundation, Inc.
|
||||
@c Copyright (C) 2002, 2004 Free Software Foundation, Inc.
|
||||
@c This is part of the GAS manual.
|
||||
@c For copying conditions, see the file as.texinfo.
|
||||
@c
|
||||
@ -33,54 +33,30 @@ The Xtensa version of the @sc{gnu} assembler supports these
|
||||
special options:
|
||||
|
||||
@table @code
|
||||
@item --density | --no-density
|
||||
@kindex --density
|
||||
@kindex --no-density
|
||||
@cindex Xtensa density option
|
||||
@cindex density option, Xtensa
|
||||
Enable or disable use of the Xtensa code density option (16-bit
|
||||
instructions). @xref{Density Instructions, ,Using Density
|
||||
Instructions}. If the processor is configured with the density option,
|
||||
this is enabled by default; otherwise, it is always disabled.
|
||||
|
||||
@item --relax | --no-relax
|
||||
@kindex --relax
|
||||
@kindex --no-relax
|
||||
Enable or disable relaxation of instructions with immediate operands
|
||||
that are outside the legal range for the instructions. @xref{Xtensa
|
||||
Relaxation, ,Xtensa Relaxation}. The default is @samp{--relax} and this
|
||||
default should almost always be used. If relaxation is disabled with
|
||||
@samp{--no-relax}, instruction operands that are out of range will cause
|
||||
errors. Note: In the current implementation, these options also control
|
||||
whether assembler optimizations are performed, making these options
|
||||
equivalent to @samp{--generics} and @samp{--no-generics}.
|
||||
|
||||
@item --generics | --no-generics
|
||||
@kindex --generics
|
||||
@kindex --no-generics
|
||||
Enable or disable all assembler transformations of Xtensa instructions,
|
||||
including both relaxation and optimization. The default is
|
||||
@samp{--generics}; @samp{--no-generics} should only be used in the rare
|
||||
cases when the instructions must be exactly as specified in the assembly
|
||||
source.
|
||||
@c The @samp{--no-generics} option is like @samp{--no-relax}
|
||||
@c except that it also disables assembler optimizations (@pxref{Xtensa
|
||||
@c Optimizations}).
|
||||
As with @samp{--no-relax}, using @samp{--no-generics}
|
||||
causes out of range instruction operands to be errors.
|
||||
|
||||
@item --text-section-literals | --no-text-section-literals
|
||||
@kindex --text-section-literals
|
||||
@kindex --no-text-section-literals
|
||||
Control the treatment of literal pools. The default is
|
||||
@samp{--no-@-text-@-section-@-literals}, which places literals in a
|
||||
separate section in the output file. This allows the literal pool to be
|
||||
placed in a data RAM/ROM, and it also allows the linker to combine literal
|
||||
pools from separate object files to remove redundant literals and
|
||||
improve code size. With @samp{--text-@-section-@-literals}, the
|
||||
placed in a data RAM/ROM. With @samp{--text-@-section-@-literals}, the
|
||||
literals are interspersed in the text section in order to keep them as
|
||||
close as possible to their references. This may be necessary for large
|
||||
assembly files.
|
||||
assembly files, where the literals would otherwise be out of range of the
|
||||
@code{L32R} instructions in the text section. These options only affect
|
||||
literals referenced via PC-relative @code{L32R} instructions; literals
|
||||
for absolute mode @code{L32R} instructions are handled separately.
|
||||
|
||||
@item --absolute-literals | --no-absolute-literals
|
||||
@kindex --absolute-literals
|
||||
@kindex --no-absolute-literals
|
||||
Indicate to the assembler whether @code{L32R} instructions use absolute
|
||||
or PC-relative addressing. If the processor includes the absolute
|
||||
addressing option, the default is to use absolute @code{L32R}
|
||||
relocations. Otherwise, only the PC-relative @code{L32R} relocations
|
||||
can be used. Literals referenced with absolute @code{L32R} relocations
|
||||
are always placed in the @code{.lit4} section, independent of the
|
||||
placement of PC-relative literals.
|
||||
|
||||
@item --target-align | --no-target-align
|
||||
@kindex --target-align
|
||||
@ -97,14 +73,27 @@ have fixed alignment requirements.
|
||||
Enable or disable transformation of call instructions to allow calls
|
||||
across a greater range of addresses. @xref{Xtensa Call Relaxation,
|
||||
,Function Call Relaxation}. This option should be used when call
|
||||
targets can potentially be out of range, but it degrades both code size
|
||||
and performance. The default is @samp{--no-@-longcalls}.
|
||||
targets can potentially be out of range. It may degrade both code size
|
||||
and performance, but the linker can generally optimize away the
|
||||
unnecessary overhead when a call ends up within range. The default is
|
||||
@samp{--no-@-longcalls}.
|
||||
|
||||
@item --transform | --no-transform
|
||||
@kindex --transform
|
||||
@kindex --no-transform
|
||||
Enable or disable all assembler transformations of Xtensa instructions,
|
||||
including both relaxation and optimization. The default is
|
||||
@samp{--transform}; @samp{--no-transform} should only be used in the
|
||||
rare cases when the instructions must be exactly as specified in the
|
||||
assembly source. Using @samp{--no-transform} causes out of range
|
||||
instruction operands to be errors.
|
||||
@end table
|
||||
|
||||
@node Xtensa Syntax
|
||||
@section Assembler Syntax
|
||||
@cindex syntax, Xtensa assembler
|
||||
@cindex Xtensa assembler syntax
|
||||
@cindex FLIX syntax
|
||||
|
||||
Block comments are delimited by @samp{/*} and @samp{*/}. End of line
|
||||
comments may be introduced with either @samp{#} or @samp{//}.
|
||||
@ -113,11 +102,45 @@ Instructions consist of a leading opcode or macro name followed by
|
||||
whitespace and an optional comma-separated list of operands:
|
||||
|
||||
@smallexample
|
||||
@var{opcode} [@var{operand},@dots{}]
|
||||
@var{opcode} [@var{operand}, @dots{}]
|
||||
@end smallexample
|
||||
|
||||
Instructions must be separated by a newline or semicolon.
|
||||
|
||||
FLIX instructions, which bundle multiple opcodes together in a single
|
||||
instruction, are specified by enclosing the bundled opcodes inside
|
||||
braces:
|
||||
|
||||
@smallexample
|
||||
@{
|
||||
[@var{format}]
|
||||
@var{opcode0} [@var{operands}]
|
||||
@var{opcode1} [@var{operands}]
|
||||
@var{opcode2} [@var{operands}]
|
||||
@dots{}
|
||||
@}
|
||||
@end smallexample
|
||||
|
||||
The opcodes in a FLIX instruction are listed in the same order as the
|
||||
corresponding instruction slots in the TIE format declaration.
|
||||
Directives and labels are not allowed inside the braces of a FLIX
|
||||
instruction. A particular TIE format name can optionally be specified
|
||||
immediately after the opening brace, but this is usually unnecessary.
|
||||
The assembler will automatically search for a format that can encode the
|
||||
specified opcodes, so the format name need only be specified in rare
|
||||
cases where there is more than one applicable format and where it
|
||||
matters which of those formats is used. A FLIX instruction can also be
|
||||
specified on a single line by separating the opcodes with semicolons:
|
||||
|
||||
@smallexample
|
||||
@{ [@var{format};] @var{opcode0} [@var{operands}]; @var{opcode1} [@var{operands}]; @var{opcode2} [@var{operands}]; @dots{} @}
|
||||
@end smallexample
|
||||
|
||||
The assembler can automatically bundle opcodes into FLIX instructions.
|
||||
It encodes the opcodes in order, one at a time,
|
||||
choosing the smallest format where each opcode can be encoded and
|
||||
filling unused instruction slots with no-ops.
|
||||
|
||||
@menu
|
||||
* Xtensa Opcodes:: Opcode Naming Conventions.
|
||||
* Xtensa Registers:: Register Naming.
|
||||
@ -126,41 +149,30 @@ Instructions must be separated by a newline or semicolon.
|
||||
@node Xtensa Opcodes
|
||||
@subsection Opcode Names
|
||||
@cindex Xtensa opcode names
|
||||
@cindex opcode names, Xtenxa
|
||||
@cindex opcode names, Xtensa
|
||||
|
||||
See the @cite{Xtensa Instruction Set Architecture (ISA) Reference
|
||||
Manual} for a complete list of opcodes and descriptions of their
|
||||
semantics.
|
||||
|
||||
@cindex generic opcodes
|
||||
@cindex specific opcodes
|
||||
@cindex _ opcode prefix
|
||||
The Xtensa assembler distinguishes between @dfn{generic} and
|
||||
@dfn{specific} opcodes. Specific opcodes correspond directly to Xtensa
|
||||
machine instructions. Prefixing an opcode with an underscore character
|
||||
(@samp{_}) identifies it as a specific opcode. Opcodes without a
|
||||
leading underscore are generic, which means the assembler is required to
|
||||
preserve their semantics but may not translate them directly to the
|
||||
specific opcodes with the same names. Instead, the assembler may
|
||||
optimize a generic opcode and select a better instruction to use in its
|
||||
place (@pxref{Xtensa Optimizations, ,Xtensa Optimizations}), or the
|
||||
assembler may relax the instruction to handle operands that are out of
|
||||
range for the corresponding specific opcode (@pxref{Xtensa Relaxation,
|
||||
,Xtensa Relaxation}).
|
||||
|
||||
Only use specific opcodes when it is essential to select
|
||||
the exact machine instructions produced by the assembler.
|
||||
Using specific opcodes unnecessarily only makes the code less
|
||||
efficient, by disabling assembler optimization, and less flexible, by
|
||||
disabling relaxation.
|
||||
If an opcode name is prefixed with an underscore character (@samp{_}),
|
||||
@command{@value{AS}} will not transform that instruction in any way. The
|
||||
underscore prefix disables both optimization (@pxref{Xtensa
|
||||
Optimizations, ,Xtensa Optimizations}) and relaxation (@pxref{Xtensa
|
||||
Relaxation, ,Xtensa Relaxation}) for that particular instruction. Only
|
||||
use the underscore prefix when it is essential to select the exact
|
||||
opcode produced by the assembler. Using this feature unnecessarily
|
||||
makes the code less efficient by disabling assembler optimization and
|
||||
less flexible by disabling relaxation.
|
||||
|
||||
Note that this special handling of underscore prefixes only applies to
|
||||
Xtensa opcodes, not to either built-in macros or user-defined macros.
|
||||
When an underscore prefix is used with a macro (e.g., @code{_NOP}), it
|
||||
When an underscore prefix is used with a macro (e.g., @code{_MOV}), it
|
||||
refers to a different macro. The assembler generally provides built-in
|
||||
macros both with and without the underscore prefix, where the underscore
|
||||
versions behave as if the underscore carries through to the instructions
|
||||
in the macros. For example, @code{_NOP} expands to @code{_OR a1,a1,a1}.
|
||||
in the macros. For example, @code{_MOV} may expand to @code{_MOV.N}@.
|
||||
|
||||
The underscore prefix only applies to individual instructions, not to
|
||||
series of instructions. For example, if a series of instructions have
|
||||
@ -168,7 +180,7 @@ underscore prefixes, the assembler will not transform the individual
|
||||
instructions, but it may insert other instructions between them (e.g.,
|
||||
to align a @code{LOOP} instruction). To prevent the assembler from
|
||||
modifying a series of instructions as a whole, use the
|
||||
@code{no-generics} directive. @xref{Generics Directive, ,generics}.
|
||||
@code{no-transform} directive. @xref{Transform Directive, ,transform}.
|
||||
|
||||
@node Xtensa Registers
|
||||
@subsection Register Names
|
||||
@ -176,20 +188,20 @@ modifying a series of instructions as a whole, use the
|
||||
@cindex register names, Xtensa
|
||||
@cindex sp register
|
||||
|
||||
An initial @samp{$} character is optional in all register names.
|
||||
General purpose registers are named @samp{a0}@dots{}@samp{a15}. Additional
|
||||
registers may be added by processor configuration options. In
|
||||
particular, the @sc{mac16} option adds a @sc{mr} register bank. Its
|
||||
registers are named @samp{m0}@dots{}@samp{m3}.
|
||||
|
||||
As a special feature, @samp{sp} is also supported as a synonym for
|
||||
@samp{a1}.
|
||||
The assembly syntax for a register file entry is the ``short'' name for
|
||||
a TIE register file followed by the index into that register file. For
|
||||
example, the general-purpose @code{AR} register file has a short name of
|
||||
@code{a}, so these registers are named @code{a0}@dots{}@code{a15}.
|
||||
As a special feature, @code{sp} is also supported as a synonym for
|
||||
@code{a1}. Additional registers may be added by processor configuration
|
||||
options and by designer-defined TIE extensions. An initial @samp{$}
|
||||
character is optional in all register names.
|
||||
|
||||
@node Xtensa Optimizations
|
||||
@section Xtensa Optimizations
|
||||
@cindex optimizations
|
||||
|
||||
The optimizations currently supported by @code{@value{AS}} are
|
||||
The optimizations currently supported by @command{@value{AS}} are
|
||||
generation of density instructions where appropriate and automatic
|
||||
branch target alignment.
|
||||
|
||||
@ -205,18 +217,18 @@ branch target alignment.
|
||||
The Xtensa instruction set has a code density option that provides
|
||||
16-bit versions of some of the most commonly used opcodes. Use of these
|
||||
opcodes can significantly reduce code size. When possible, the
|
||||
assembler automatically translates generic instructions from the core
|
||||
assembler automatically translates instructions from the core
|
||||
Xtensa instruction set into equivalent instructions from the Xtensa code
|
||||
density option. This translation can be disabled by using specific
|
||||
opcodes (@pxref{Xtensa Opcodes, ,Opcode Names}), by using the
|
||||
@samp{--no-density} command-line option (@pxref{Xtensa Options, ,Command
|
||||
Line Options}), or by using the @code{no-density} directive
|
||||
(@pxref{Density Directive, ,density}).
|
||||
density option. This translation can be disabled by using underscore
|
||||
prefixes (@pxref{Xtensa Opcodes, ,Opcode Names}), by using the
|
||||
@samp{--no-transform} command-line option (@pxref{Xtensa Options, ,Command
|
||||
Line Options}), or by using the @code{no-transform} directive
|
||||
(@pxref{Transform Directive, ,transform}).
|
||||
|
||||
It is a good idea @emph{not} to use the density instructions directly.
|
||||
The assembler will automatically select dense instructions where
|
||||
possible. If you later need to avoid using the code density option, you
|
||||
can disable it in the assembler without having to modify the code.
|
||||
possible. If you later need to use an Xtensa processor without the code
|
||||
density option, the same assembly code will then work without modification.
|
||||
|
||||
@node Xtensa Automatic Alignment
|
||||
@subsection Automatic Instruction Alignment
|
||||
@ -230,24 +242,42 @@ can disable it in the assembler without having to modify the code.
|
||||
The Xtensa assembler will automatically align certain instructions, both
|
||||
to optimize performance and to satisfy architectural requirements.
|
||||
|
||||
When the @code{--target-@-align} command-line option is enabled
|
||||
(@pxref{Xtensa Options, ,Command Line Options}), the assembler attempts
|
||||
to widen density instructions preceding a branch target so that the
|
||||
target instruction does not cross a 4-byte boundary. Similarly, the
|
||||
assembler also attempts to align each instruction following a call
|
||||
instruction. If there are not enough preceding safe density
|
||||
instructions to align a target, no widening will be performed. This
|
||||
alignment has the potential to reduce branch penalties at some expense
|
||||
in code size. The assembler will not attempt to align labels with the
|
||||
prefixes @code{.Ln} and @code{.LM}, since these labels are used for
|
||||
debugging information and are not typically branch targets.
|
||||
As an optimization to improve performance, the assembler attempts to
|
||||
align branch targets so they do not cross instruction fetch boundaries.
|
||||
(Xtensa processors can be configured with either 32-bit or 64-bit
|
||||
instruction fetch widths.) An
|
||||
instruction immediately following a call is treated as a branch target
|
||||
in this context, because it will be the target of a return from the
|
||||
call. This alignment has the potential to reduce branch penalties at
|
||||
some expense in code size. The assembler will not attempt to align
|
||||
labels with the prefixes @code{.Ln} and @code{.LM}, since these labels
|
||||
are used for debugging information and are not typically branch targets.
|
||||
This optimization is enabled by default. You can disable it with the
|
||||
@samp{--no-target-@-align} command-line option (@pxref{Xtensa Options,
|
||||
,Command Line Options}).
|
||||
|
||||
The @code{LOOP} family of instructions must be aligned on either a 1 or
|
||||
2 mod 4 byte boundary. The assembler knows about this restriction and
|
||||
inserts the minimal number of 2 or 3 byte no-op instructions
|
||||
to satisfy it. When no-op instructions are added, any label immediately
|
||||
preceding the original loop will be moved in order to refer to the loop
|
||||
instruction, not the newly generated no-op instruction.
|
||||
The target alignment optimization is done without adding instructions
|
||||
that could increase the execution time of the program. If there are
|
||||
density instructions in the code preceding a target, the assembler can
|
||||
change the target alignment by widening some of those instructions to
|
||||
the equivalent 24-bit instructions. Extra bytes of padding can be
|
||||
inserted immediately following unconditional jump and return
|
||||
instructions.
|
||||
This approach is usually successful in aligning many, but not all,
|
||||
branch targets.
|
||||
|
||||
The @code{LOOP} family of instructions must be aligned such that the
|
||||
first instruction in the loop body does not cross an instruction fetch
|
||||
boundary (e.g., with a 32-bit fetch width, a @code{LOOP} instruction
|
||||
must be on either a 1 or 2 mod 4 byte boundary). The assembler knows
|
||||
about this restriction and inserts the minimal number of 2 or 3 byte
|
||||
no-op instructions to satisfy it. When no-op instructions are added,
|
||||
any label immediately preceding the original loop will be moved in order
|
||||
to refer to the loop instruction, not the newly generated no-op
|
||||
instruction. To preserve binary compatibility across processors with
|
||||
different fetch widths, the assembler conservatively assumes a 32-bit
|
||||
fetch width when aligning @code{LOOP} instructions (except if the first
|
||||
instruction in the loop is a 64-bit instruction).
|
||||
|
||||
Similarly, the @code{ENTRY} instruction must be aligned on a 0 mod 4
|
||||
byte boundary. The assembler satisfies this requirement by inserting
|
||||
@ -260,7 +290,7 @@ location.
|
||||
@cindex relaxation
|
||||
|
||||
When an instruction operand is outside the range allowed for that
|
||||
particular instruction field, @code{@value{AS}} can transform the code
|
||||
particular instruction field, @command{@value{AS}} can transform the code
|
||||
to use a functionally-equivalent instruction or sequence of
|
||||
instructions. This process is known as @dfn{relaxation}. This is
|
||||
typically done for branch instructions because the distance of the
|
||||
@ -300,6 +330,19 @@ M:
|
||||
(The @code{BNEZ.N} instruction would be used in this example only if the
|
||||
density option is available. Otherwise, @code{BNEZ} would be used.)
|
||||
|
||||
This relaxation works well because the unconditional jump instruction
|
||||
has a much larger offset range than the various conditional branches.
|
||||
However, an error will occur if a branch target is beyond the range of a
|
||||
jump instruction. @command{@value{AS}} cannot relax unconditional jumps.
|
||||
Similarly, an error will occur if the original input contains an
|
||||
unconditional jump to a target that is out of range.
|
||||
|
||||
Branch relaxation is enabled by default. It can be disabled by using
|
||||
underscore prefixes (@pxref{Xtensa Opcodes, ,Opcode Names}), the
|
||||
@samp{--no-transform} command-line option (@pxref{Xtensa Options,
|
||||
,Command Line Options}), or the @code{no-transform} directive
|
||||
(@pxref{Transform Directive, ,transform}).
|
||||
|
||||
@node Xtensa Call Relaxation
|
||||
@subsection Function Call Relaxation
|
||||
@cindex relaxation of call instructions
|
||||
@ -332,21 +375,27 @@ Because the addresses of targets of function calls are not generally
|
||||
known until link-time, the assembler must assume the worst and relax all
|
||||
the calls to functions in other source files, not just those that really
|
||||
will be out of range. The linker can recognize calls that were
|
||||
unnecessarily relaxed, but it can only partially remove the overhead
|
||||
introduced by the assembler.
|
||||
unnecessarily relaxed, and it will remove the overhead introduced by the
|
||||
assembler for those cases where direct calls are sufficient.
|
||||
|
||||
Call relaxation has a negative effect
|
||||
on both code size and performance, so this relaxation is disabled by
|
||||
default. If a program is too large and some of the calls are out of
|
||||
range, function call relaxation can be enabled using the
|
||||
@samp{--longcalls} command-line option or the @code{longcalls} directive
|
||||
(@pxref{Longcalls Directive, ,longcalls}).
|
||||
Call relaxation is disabled by default because it can have a negative
|
||||
effect on both code size and performance, although the linker can
|
||||
usually eliminate the unnecessary overhead. If a program is too large
|
||||
and some of the calls are out of range, function call relaxation can be
|
||||
enabled using the @samp{--longcalls} command-line option or the
|
||||
@code{longcalls} directive (@pxref{Longcalls Directive, ,longcalls}).
|
||||
|
||||
@node Xtensa Immediate Relaxation
|
||||
@subsection Other Immediate Field Relaxation
|
||||
@cindex immediate fields, relaxation
|
||||
@cindex relaxation of immediate fields
|
||||
|
||||
The assembler normally performs the following other relaxations. They
|
||||
can be disabled by using underscore prefixes (@pxref{Xtensa Opcodes,
|
||||
,Opcode Names}), the @samp{--no-transform} command-line option
|
||||
(@pxref{Xtensa Options, ,Command Line Options}), or the
|
||||
@code{no-transform} directive (@pxref{Transform Directive, ,transform}).
|
||||
|
||||
@cindex @code{MOVI} instructions, relaxation
|
||||
@cindex relaxation of @code{MOVI} instructions
|
||||
The @code{MOVI} machine instruction can only materialize values in the
|
||||
@ -401,7 +450,7 @@ out-of-range offset causes an error.
|
||||
@cindex relaxation of @code{ADDI} instructions
|
||||
The Xtensa @code{ADDI} instruction only allows immediate operands in the
|
||||
range from -128 to 127. There are a number of alternate instruction
|
||||
sequences for the generic @code{ADDI} operation. First, if the
|
||||
sequences for the @code{ADDI} operation. First, if the
|
||||
immediate is 0, the @code{ADDI} will be turned into a @code{MOV.N}
|
||||
instruction (or the equivalent @code{OR} instruction if the code density
|
||||
option is not available). If the @code{ADDI} immediate is outside of
|
||||
@ -456,87 +505,49 @@ change the state of the directive without having to be aware of its
|
||||
outer state. For example, consider:
|
||||
|
||||
@smallexample
|
||||
.begin no-density
|
||||
.begin no-transform
|
||||
L: add a0, a1, a2
|
||||
.begin density
|
||||
.begin transform
|
||||
M: add a0, a1, a2
|
||||
.end density
|
||||
.end transform
|
||||
N: add a0, a1, a2
|
||||
.end no-density
|
||||
.end no-transform
|
||||
@end smallexample
|
||||
|
||||
The generic @code{ADD} opcodes at @code{L} and @code{N} in the outer
|
||||
@code{no-density} region both result in @code{ADD} machine instructions,
|
||||
but the assembler selects an @code{ADD.N} instruction for the generic
|
||||
@code{ADD} at @code{M} in the inner @code{density} region.
|
||||
The @code{ADD} opcodes at @code{L} and @code{N} in the outer
|
||||
@code{no-transform} region both result in @code{ADD} machine instructions,
|
||||
but the assembler selects an @code{ADD.N} instruction for the
|
||||
@code{ADD} at @code{M} in the inner @code{transform} region.
|
||||
|
||||
The advantage of this style is that it works well inside macros which can
|
||||
preserve the context of their callers.
|
||||
|
||||
@cindex precedence of directives
|
||||
@cindex directives, precedence
|
||||
When command-line options and assembler directives are used at the same
|
||||
time and conflict, the one that overrides a default behavior takes
|
||||
precedence over one that is the same as the default. For example, if
|
||||
the code density option is available, the default is to select density
|
||||
instructions whenever possible. So, if the above is assembled with the
|
||||
@samp{--no-density} flag, which overrides the default, all the generic
|
||||
@code{ADD} instructions result in @code{ADD} machine instructions. If
|
||||
assembled with the @samp{--density} flag, which is already the default,
|
||||
the @code{no-density} directive takes precedence and only one of
|
||||
the generic @code{ADD} instructions is optimized to be a @code{ADD.N}
|
||||
machine instruction. An underscore prefix identifying a specific opcode
|
||||
always takes precedence over directives and command-line flags.
|
||||
|
||||
The following directives are available:
|
||||
@menu
|
||||
* Density Directive:: Disable Use of Density Instructions.
|
||||
* Relax Directive:: Disable Assembler Relaxation.
|
||||
* Schedule Directive:: Enable instruction scheduling.
|
||||
* Longcalls Directive:: Use Indirect Calls for Greater Range.
|
||||
* Generics Directive:: Disable All Assembler Transformations.
|
||||
* Transform Directive:: Disable All Assembler Transformations.
|
||||
* Literal Directive:: Intermix Literals with Instructions.
|
||||
* Literal Position Directive:: Specify Inline Literal Pool Locations.
|
||||
* Literal Prefix Directive:: Specify Literal Section Name Prefix.
|
||||
* Freeregs Directive:: List Registers Available for Assembler Use.
|
||||
* Absolute Literals Directive:: Control PC-Relative vs. Absolute Literals.
|
||||
* Frame Directive:: Describe a stack frame.
|
||||
@end menu
|
||||
|
||||
@node Density Directive
|
||||
@subsection density
|
||||
@cindex @code{density} directive
|
||||
@cindex @code{no-density} directive
|
||||
@node Schedule Directive
|
||||
@subsection schedule
|
||||
@cindex @code{schedule} directive
|
||||
@cindex @code{no-schedule} directive
|
||||
|
||||
The @code{density} and @code{no-density} directives enable or disable
|
||||
optimization of generic instructions into density instructions within
|
||||
the region. @xref{Density Instructions, ,Using Density Instructions}.
|
||||
The @code{schedule} directive is recognized only for compatibility with
|
||||
Tensilica's assembler.
|
||||
|
||||
@smallexample
|
||||
.begin [no-]density
|
||||
.end [no-]density
|
||||
.begin [no-]schedule
|
||||
.end [no-]schedule
|
||||
@end smallexample
|
||||
|
||||
This optimization is enabled by default unless the Xtensa configuration
|
||||
does not support the code density option or the @samp{--no-density}
|
||||
command-line option was specified.
|
||||
|
||||
@node Relax Directive
|
||||
@subsection relax
|
||||
@cindex @code{relax} directive
|
||||
@cindex @code{no-relax} directive
|
||||
|
||||
The @code{relax} directive enables or disables relaxation
|
||||
within the region. @xref{Xtensa Relaxation, ,Xtensa Relaxation}.
|
||||
Note: In the current implementation, these directives also control
|
||||
whether assembler optimizations are performed, making them equivalent to
|
||||
the @code{generics} and @code{no-generics} directives.
|
||||
|
||||
@smallexample
|
||||
.begin [no-]relax
|
||||
.end [no-]relax
|
||||
@end smallexample
|
||||
|
||||
Relaxation is enabled by default unless the @samp{--no-relax}
|
||||
command-line option was specified.
|
||||
This directive is ignored and has no effect on @command{@value{AS}}.
|
||||
|
||||
@node Longcalls Directive
|
||||
@subsection longcalls
|
||||
@ -552,27 +563,28 @@ relaxation. @xref{Xtensa Call Relaxation, ,Function Call Relaxation}.
|
||||
@end smallexample
|
||||
|
||||
Call relaxation is disabled by default unless the @samp{--longcalls}
|
||||
command-line option is specified.
|
||||
command-line option is specified. The @code{longcalls} directive
|
||||
overrides the default determined by the command-line options.
|
||||
|
||||
@node Generics Directive
|
||||
@subsection generics
|
||||
@cindex @code{generics} directive
|
||||
@cindex @code{no-generics} directive
|
||||
@node Transform Directive
|
||||
@subsection transform
|
||||
@cindex @code{transform} directive
|
||||
@cindex @code{no-transform} directive
|
||||
|
||||
This directive enables or disables all assembler transformation,
|
||||
including relaxation (@pxref{Xtensa Relaxation, ,Xtensa Relaxation}) and
|
||||
optimization (@pxref{Xtensa Optimizations, ,Xtensa Optimizations}).
|
||||
|
||||
@smallexample
|
||||
.begin [no-]generics
|
||||
.end [no-]generics
|
||||
.begin [no-]transform
|
||||
.end [no-]transform
|
||||
@end smallexample
|
||||
|
||||
Disabling generics is roughly equivalent to adding an underscore prefix
|
||||
to every opcode within the region, so that every opcode is treated as a
|
||||
specific opcode. @xref{Xtensa Opcodes, ,Opcode Names}. In the current
|
||||
implementation of @code{@value{AS}}, built-in macros are also disabled
|
||||
within a @code{no-generics} region.
|
||||
Transformations are enabled by default unless the @samp{--no-transform}
|
||||
option is used. The @code{transform} directive overrides the default
|
||||
determined by the command-line options. An underscore opcode prefix,
|
||||
disabling transformation of that opcode, always takes precedence over
|
||||
both directives and command-line flags.
|
||||
|
||||
@node Literal Directive
|
||||
@subsection literal
|
||||
@ -603,17 +615,19 @@ can be used to load a pointer to the symbol @code{sym} into register
|
||||
@code{ENTRY} and @code{L32R} instructions; instead, the assembler puts
|
||||
the data in a literal pool.
|
||||
|
||||
By default literal pools are placed in a separate section; however, when
|
||||
Literal pools for absolute mode @code{L32R} instructions
|
||||
(@pxref{Absolute Literals Directive}) are always placed in the
|
||||
@code{.lit4} section. By default literal pools for PC-relative mode
|
||||
@code{L32R} instructions are placed in a separate section; however, when
|
||||
using the @samp{--text-@-section-@-literals} option (@pxref{Xtensa
|
||||
Options, ,Command Line Options}), the literal pools are placed in the
|
||||
current section. These text section literal pools are created
|
||||
automatically before @code{ENTRY} instructions and manually after
|
||||
@samp{.literal_position} directives (@pxref{Literal Position Directive,
|
||||
,literal_position}). If there are no preceding @code{ENTRY}
|
||||
instructions or @code{.literal_position} directives, the assembler will
|
||||
print a warning and place the literal pool at the beginning of the
|
||||
current section. In such cases, explicit @code{.literal_position}
|
||||
directives should be used to place the literal pools.
|
||||
instructions, explicit @code{.literal_position} directives
|
||||
must be used to place the text section literal pools; otherwise,
|
||||
@command{@value{AS}} will report an error.
|
||||
|
||||
@node Literal Position Directive
|
||||
@subsection literal_position
|
||||
@ -628,7 +642,8 @@ can be used to mark a potential location for a literal pool.
|
||||
@end smallexample
|
||||
|
||||
The @code{.literal_position} directive is ignored when the
|
||||
@samp{--text-@-section-@-literals} option is not used.
|
||||
@samp{--text-@-section-@-literals} option is not used or when
|
||||
@code{L32R} instructions use the absolute addressing mode.
|
||||
|
||||
The assembler will automatically place text section literal pools
|
||||
before @code{ENTRY} instructions, so the @code{.literal_position}
|
||||
@ -642,7 +657,8 @@ place to put a literal pool. Moreover, the code for the interrupt
|
||||
vector must be at a specific starting address, so the literal pool
|
||||
cannot come before the start of the code. The literal pool for the
|
||||
vector must be explicitly positioned in the middle of the vector (before
|
||||
any uses of the literals, of course). The @code{.literal_position}
|
||||
any uses of the literals, due to the negative offsets used by
|
||||
PC-relative @code{L32R} instructions). The @code{.literal_position}
|
||||
directive can be used to do this. In the following code, the literal
|
||||
for @samp{M} will automatically be aligned correctly and is placed after
|
||||
the unconditional jump.
|
||||
@ -663,6 +679,9 @@ continue:
|
||||
|
||||
The @code{literal_prefix} directive allows you to specify different
|
||||
sections to hold literals from different portions of an assembly file.
|
||||
This directive only applies to literals referenced from PC-relative
|
||||
@code{L32R} instructions; it has no effect for absolute literals
|
||||
(@pxref{Absolute Literals Directive}).
|
||||
With this directive, a single assembly file can be used to generate code
|
||||
into multiple sections, including literals generated by the assembler.
|
||||
|
||||
@ -679,31 +698,40 @@ the ``default'' for the file. This default is usually @code{.literal}
|
||||
but can be changed with the @samp{--rename-section} command-line
|
||||
argument.
|
||||
|
||||
@node Freeregs Directive
|
||||
@subsection freeregs
|
||||
@cindex @code{freeregs} directive
|
||||
@node Absolute Literals Directive
|
||||
@subsection absolute-literals
|
||||
@cindex @code{absolute-literals} directive
|
||||
@cindex @code{no-absolute-literals} directive
|
||||
|
||||
This directive tells the assembler that the given registers are unused
|
||||
in the region.
|
||||
The @code{absolute-@-literals} and @code{no-@-absolute-@-literals}
|
||||
directives control the absolute vs.@: PC-relative mode for @code{L32R}
|
||||
instructions. These are relevant only for Xtensa configurations that
|
||||
include the absolute addressing option for @code{L32R} instructions.
|
||||
|
||||
@smallexample
|
||||
.begin freeregs @var{ri}[,@var{ri}@dots{}]
|
||||
.end freeregs
|
||||
.begin [no-]absolute-literals
|
||||
.end [no-]absolute-literals
|
||||
@end smallexample
|
||||
|
||||
This allows the assembler to use these registers for relaxations or
|
||||
optimizations. (They are actually only for relaxations at present, but
|
||||
the possibility of optimizations exists in the future.)
|
||||
These directives do not change the @code{L32R} mode---they only cause
|
||||
the assembler to emit the appropriate kind of relocation for @code{L32R}
|
||||
instructions and to place the literal values in the appropriate section.
|
||||
To change the @code{L32R} mode, the program must write the
|
||||
@code{LITBASE} special register. It is the programmer's responsibility
|
||||
to keep track of the mode and indicate to the assembler which mode is
|
||||
used in each region of code.
|
||||
|
||||
Nested @code{freeregs} directives can be used to add additional registers
|
||||
to the list of those available to the assembler. For example:
|
||||
Literals referenced with absolute @code{L32R} instructions are always
|
||||
placed in the @code{.lit4} section. PC-relative literals may be placed
|
||||
in the current text section or in a separate literal section, as
|
||||
described elsewhere (@pxref{Literal Directive}).
|
||||
|
||||
@smallexample
|
||||
.begin freeregs a3, a4
|
||||
.begin freeregs a5
|
||||
@end smallexample
|
||||
|
||||
has the effect of declaring @code{a3}, @code{a4}, and @code{a5} all free.
|
||||
If the Xtensa configuration includes the absolute @code{L32R} addressing
|
||||
option, the default is to assume absolute @code{L32R} addressing unless
|
||||
the @samp{--no-@-absolute-@-literals} command-line option is specified.
|
||||
Otherwise, the default is to assume PC-relative @code{L32R} addressing.
|
||||
The @code{absolute-@-literals} directive can then be used to override
|
||||
the default determined by the command-line options.
|
||||
|
||||
@node Frame Directive
|
||||
@subsection frame
|
||||
@ -719,9 +747,9 @@ debugger to locate a function's stack frame. The syntax is:
|
||||
where @var{reg} is the register used to hold the frame pointer (usually
|
||||
the same as the stack pointer) and @var{size} is the size in bytes of
|
||||
the stack frame. The @code{.frame} directive is typically placed
|
||||
immediately after the @code{ENTRY} instruction for a function.
|
||||
near the @code{ENTRY} instruction for a function.
|
||||
|
||||
In almost all circumstances, this information just duplicates the
|
||||
In many circumstances, this information just duplicates the
|
||||
information given in the function's @code{ENTRY} instruction; however,
|
||||
there are two cases where this is not true:
|
||||
|
||||
|
||||
@ -1,3 +1,10 @@
|
||||
2004-10-07 Bob Wilson <bob.wilson@acm.org>
|
||||
|
||||
* gas/xtensa/all.exp: Adjust expected error message for j_too_far.
|
||||
Change entry_align test to expect an error.
|
||||
* gas/xtensa/entry_misalign2.s: Use no-transform instead of
|
||||
no-generics directives.
|
||||
|
||||
2004-10-07 Richard Sandiford <rsandifo@redhat.com>
|
||||
|
||||
* gas/mips/elf-rel{23,24}.[sd]: New tests.
|
||||
|
||||
@ -9,7 +9,7 @@ if [istarget xtensa*-*-*] then {
|
||||
set x1 0
|
||||
while 1 {
|
||||
expect {
|
||||
-re ":4: Error:.*too large" { set x1 1 }
|
||||
-re ":4: Error:.*out of range" { set x1 1 }
|
||||
timeout { perror "timeout\n"; break }
|
||||
eof { break }
|
||||
}
|
||||
@ -47,19 +47,7 @@ if [istarget xtensa*-*-*] then {
|
||||
objdump_finish
|
||||
if [all_ones $x1] then { pass $testname } else { fail $testname }
|
||||
|
||||
gas_test "entry_align.s" "" "" "Xtensa autoalign entry"
|
||||
set testname "entry_align.s: autoalign entry"
|
||||
objdump_start_no_subdir "a.out" "-d -j .text"
|
||||
set x1 0
|
||||
while 1 {
|
||||
expect {
|
||||
-re "^.*4:.*entry" { set x1 1 }
|
||||
timeout { perror "timeout\n"; break }
|
||||
eof { break }
|
||||
}
|
||||
}
|
||||
objdump_finish
|
||||
if [all_ones $x1] then { pass $testname } else { fail $testname }
|
||||
gas_test_error "entry_align.s" "" "Xtensa entry alignment error"
|
||||
|
||||
gas_test "loop_misalign.s" "" "" "Xtensa Loop misalignment"
|
||||
set testname "loop_misalign.s: Force loop misalignment"
|
||||
|
||||
@ -1,6 +1,6 @@
|
||||
.begin no-generics
|
||||
.begin no-transform
|
||||
nop.n
|
||||
l4:
|
||||
entry a5,16
|
||||
mov.n a4,a5
|
||||
.end no-generics
|
||||
.end no-transform
|
||||
|
||||
@ -1,3 +1,104 @@
|
||||
2004-10-07 Bob Wilson <bob.wilson@acm.org>
|
||||
|
||||
* xtensa-config.h (XSHAL_USE_ABSOLUTE_LITERALS,
|
||||
XCHAL_HAVE_PREDICTED_BRANCHES, XCHAL_INST_FETCH_WIDTH): New.
|
||||
(XCHAL_EXTRA_SA_SIZE, XCHAL_EXTRA_SA_ALIGN): Delete.
|
||||
* xtensa-isa-internal.h (ISA_INTERFACE_VERSION): Delete.
|
||||
(config_sturct struct): Delete.
|
||||
(XTENSA_OPERAND_IS_REGISTER, XTENSA_OPERAND_IS_PCRELATIVE,
|
||||
XTENSA_OPERAND_IS_INVISIBLE, XTENSA_OPERAND_IS_UNKNOWN,
|
||||
XTENSA_OPCODE_IS_BRANCH, XTENSA_OPCODE_IS_JUMP,
|
||||
XTENSA_OPCODE_IS_LOOP, XTENSA_OPCODE_IS_CALL,
|
||||
XTENSA_STATE_IS_EXPORTED, XTENSA_INTERFACE_HAS_SIDE_EFFECT): Define.
|
||||
(xtensa_format_encode_fn, xtensa_get_slot_fn, xtensa_set_slot_fn): New.
|
||||
(xtensa_insn_decode_fn): Rename to ...
|
||||
(xtensa_opcode_decode_fn): ... this.
|
||||
(xtensa_immed_decode_fn, xtensa_immed_encode_fn, xtensa_do_reloc_fn,
|
||||
xtensa_undo_reloc_fn): Update.
|
||||
(xtensa_encoding_template_fn): Delete.
|
||||
(xtensa_opcode_encode_fn, xtensa_format_decode_fn,
|
||||
xtensa_length_decode_fn): New.
|
||||
(xtensa_format_internal, xtensa_slot_internal): New types.
|
||||
(xtensa_operand_internal): Delete operand_kind, inout, isPCRelative,
|
||||
get_field, and set_field fields. Add name, field_id, regfile,
|
||||
num_regs, and flags fields.
|
||||
(xtensa_arg_internal): New type.
|
||||
(xtensa_iclass_internal): Change operands field to array of
|
||||
xtensa_arg_internal. Add num_stateOperands, stateOperands,
|
||||
num_interfaceOperands, and interfaceOperands fields.
|
||||
(xtensa_opcode_internal): Delete length, template, and iclass fields.
|
||||
Add iclass_id, flags, encode_fns, num_funcUnit_uses, and funcUnit_uses.
|
||||
(opname_lookup_entry): Delete.
|
||||
(xtensa_regfile_internal, xtensa_interface_internal,
|
||||
xtensa_funcUnit_internal, xtensa_state_internal,
|
||||
xtensa_sysreg_internal, xtensa_lookup_entry): New.
|
||||
(xtensa_isa_internal): Replace opcode_table field with opcodes field.
|
||||
Change type of opname_lookup_table. Delete num_modules,
|
||||
module_opcode_base, module_decode_fn, config, and has_density fields.
|
||||
Add num_formats, formats, format_decode_fn, length_decode_fn,
|
||||
num_slots, slots, num_fields, num_operands, operands, num_iclasses,
|
||||
iclasses, num_regfiles, regfiles, num_states, states,
|
||||
state_lookup_table, num_sysregs, sysregs, sysreg_lookup_table,
|
||||
max_sysreg_num, sysreg_table, num_interfaces, interfaces,
|
||||
interface_lookup_table, num_funcUnits, funcUnits and
|
||||
funcUnit_lookup_table fields.
|
||||
(xtensa_isa_module, xtensa_isa_modules): Delete.
|
||||
(xtensa_isa_name_compare): New prototype.
|
||||
(xtisa_errno, xtisa_error_msg): New.
|
||||
* xtensa-isa.h (XTENSA_ISA_VERSION): Define.
|
||||
(xtensa_isa): Change type.
|
||||
(xtensa_operand): Delete.
|
||||
(xtensa_format, xtensa_regfile, xtensa_state, xtensa_sysreg,
|
||||
xtensa_interface, xtensa_funcUnit, xtensa_isa_status,
|
||||
xtensa_funcUnit_use): New types.
|
||||
(libisa_module_specifier): Delete.
|
||||
(xtensa_isa_errno, xtensa_isa_error_msg): New prototypes.
|
||||
(xtensa_insnbuf_free, xtensa_insnbuf_to_chars,
|
||||
xtensa_insnbuf_from_chars): Update prototypes.
|
||||
(xtensa_load_isa, xtensa_extend_isa, xtensa_default_isa,
|
||||
xtensa_insn_maxlength, xtensa_num_opcodes, xtensa_decode_insn,
|
||||
xtensa_encode_insn, xtensa_insn_length,
|
||||
xtensa_insn_length_from_first_byte, xtensa_num_operands,
|
||||
xtensa_operand_kind, xtensa_encode_result,
|
||||
xtensa_operand_isPCRelative): Delete.
|
||||
(xtensa_isa_init, xtensa_operand_inout, xtensa_operand_get_field,
|
||||
xtensa_operand_set_field, xtensa_operand_encode,
|
||||
xtensa_operand_decode, xtensa_operand_do_reloc,
|
||||
xtensa_operand_undo_reloc): Update prototypes.
|
||||
(xtensa_isa_maxlength, xtensa_isa_length_from_chars,
|
||||
xtensa_isa_num_pipe_stages, xtensa_isa_num_formats,
|
||||
xtensa_isa_num_opcodes, xtensa_isa_num_regfiles, xtensa_isa_num_states,
|
||||
xtensa_isa_num_sysregs, xtensa_isa_num_interfaces,
|
||||
xtensa_isa_num_funcUnits, xtensa_format_name, xtensa_format_lookup,
|
||||
xtensa_format_decode, xtensa_format_encode, xtensa_format_length,
|
||||
xtensa_format_num_slots, xtensa_format_slot_nop_opcode,
|
||||
xtensa_format_get_slot, xtensa_format_set_slot, xtensa_opcode_decode,
|
||||
xtensa_opcode_encode, xtensa_opcode_is_branch, xtensa_opcode_is_jump,
|
||||
xtensa_opcode_is_loop, xtensa_opcode_is_call,
|
||||
xtensa_opcode_num_operands, xtensa_opcode_num_stateOperands,
|
||||
xtensa_opcode_num_interfaceOperands, xtensa_opcode_num_funcUnit_uses,
|
||||
xtensa_opcode_funcUnit_use, xtensa_operand_name,
|
||||
xtensa_operand_is_visible, xtensa_operand_is_register,
|
||||
xtensa_operand_regfile, xtensa_operand_num_regs,
|
||||
xtensa_operand_is_known_reg, xtensa_operand_is_PCrelative,
|
||||
xtensa_stateOperand_state, xtensa_stateOperand_inout,
|
||||
xtensa_interfaceOperand_interface, xtensa_regfile_lookup,
|
||||
xtensa_regfile_lookup_shortname, xtensa_regfile_name,
|
||||
xtensa_regfile_shortname, xtensa_regfile_view_parent,
|
||||
xtensa_regfile_num_bits, xtensa_regfile_num_entries,
|
||||
xtensa_state_lookup, xtensa_state_name, xtensa_state_num_bits,
|
||||
xtensa_state_is_exported, xtensa_sysreg_lookup,
|
||||
xtensa_sysreg_lookup_name, xtensa_sysreg_name, xtensa_sysreg_number,
|
||||
xtensa_sysreg_is_user, xtensa_interface_lookup, xtensa_interface_name,
|
||||
xtensa_interface_num_bits, xtensa_interface_inout,
|
||||
xtensa_interface_has_side_effect, xtensa_funcUnit_lookup,
|
||||
xtensa_funcUnit_name, xtensa_funcUnit_num_copies): New prototypes.
|
||||
* elf/xtensa.h (R_XTENSA_DIFF8, R_XTENSA_DIFF16, R_XTENSA_DIFF32,
|
||||
R_XTENSA_SLOT*_OP, R_XTENSA_SLOT*_ALT): New relocations.
|
||||
(XTENSA_PROP_SEC_NAME): Define.
|
||||
(property_table_entry): Add flags field.
|
||||
(XTENSA_PROP_*, GET_XTENSA_PROP_*, SET_XTENSA_PROP_*): Define.
|
||||
|
||||
2004-10-07 Jeff Baker <jbaker@qnx.com>
|
||||
|
||||
* bfdlink.h (bfd_link_info): Add bitfield: warn_shared_textrel.
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
/* Xtensa ELF support for BFD.
|
||||
Copyright 2003 Free Software Foundation, Inc.
|
||||
Copyright 2003, 2004 Free Software Foundation, Inc.
|
||||
Contributed by Bob Wilson (bwilson@tensilica.com) at Tensilica.
|
||||
|
||||
This file is part of BFD, the Binary File Descriptor library.
|
||||
@ -42,6 +42,39 @@ START_RELOC_NUMBERS (elf_xtensa_reloc_type)
|
||||
RELOC_NUMBER (R_XTENSA_ASM_SIMPLIFY, 12)
|
||||
RELOC_NUMBER (R_XTENSA_GNU_VTINHERIT, 15)
|
||||
RELOC_NUMBER (R_XTENSA_GNU_VTENTRY, 16)
|
||||
RELOC_NUMBER (R_XTENSA_DIFF8, 17)
|
||||
RELOC_NUMBER (R_XTENSA_DIFF16, 18)
|
||||
RELOC_NUMBER (R_XTENSA_DIFF32, 19)
|
||||
RELOC_NUMBER (R_XTENSA_SLOT0_OP, 20)
|
||||
RELOC_NUMBER (R_XTENSA_SLOT1_OP, 21)
|
||||
RELOC_NUMBER (R_XTENSA_SLOT2_OP, 22)
|
||||
RELOC_NUMBER (R_XTENSA_SLOT3_OP, 23)
|
||||
RELOC_NUMBER (R_XTENSA_SLOT4_OP, 24)
|
||||
RELOC_NUMBER (R_XTENSA_SLOT5_OP, 25)
|
||||
RELOC_NUMBER (R_XTENSA_SLOT6_OP, 26)
|
||||
RELOC_NUMBER (R_XTENSA_SLOT7_OP, 27)
|
||||
RELOC_NUMBER (R_XTENSA_SLOT8_OP, 28)
|
||||
RELOC_NUMBER (R_XTENSA_SLOT9_OP, 29)
|
||||
RELOC_NUMBER (R_XTENSA_SLOT10_OP, 30)
|
||||
RELOC_NUMBER (R_XTENSA_SLOT11_OP, 31)
|
||||
RELOC_NUMBER (R_XTENSA_SLOT12_OP, 32)
|
||||
RELOC_NUMBER (R_XTENSA_SLOT13_OP, 33)
|
||||
RELOC_NUMBER (R_XTENSA_SLOT14_OP, 34)
|
||||
RELOC_NUMBER (R_XTENSA_SLOT0_ALT, 35)
|
||||
RELOC_NUMBER (R_XTENSA_SLOT1_ALT, 36)
|
||||
RELOC_NUMBER (R_XTENSA_SLOT2_ALT, 37)
|
||||
RELOC_NUMBER (R_XTENSA_SLOT3_ALT, 38)
|
||||
RELOC_NUMBER (R_XTENSA_SLOT4_ALT, 39)
|
||||
RELOC_NUMBER (R_XTENSA_SLOT5_ALT, 40)
|
||||
RELOC_NUMBER (R_XTENSA_SLOT6_ALT, 41)
|
||||
RELOC_NUMBER (R_XTENSA_SLOT7_ALT, 42)
|
||||
RELOC_NUMBER (R_XTENSA_SLOT8_ALT, 43)
|
||||
RELOC_NUMBER (R_XTENSA_SLOT9_ALT, 44)
|
||||
RELOC_NUMBER (R_XTENSA_SLOT10_ALT, 45)
|
||||
RELOC_NUMBER (R_XTENSA_SLOT11_ALT, 46)
|
||||
RELOC_NUMBER (R_XTENSA_SLOT12_ALT, 47)
|
||||
RELOC_NUMBER (R_XTENSA_SLOT13_ALT, 48)
|
||||
RELOC_NUMBER (R_XTENSA_SLOT14_ALT, 49)
|
||||
END_RELOC_NUMBERS (R_XTENSA_max)
|
||||
|
||||
/* Processor-specific flags for the ELF header e_flags field. */
|
||||
@ -78,11 +111,88 @@ END_RELOC_NUMBERS (R_XTENSA_max)
|
||||
|
||||
#define XTENSA_INSN_SEC_NAME ".xt.insn"
|
||||
#define XTENSA_LIT_SEC_NAME ".xt.lit"
|
||||
#define XTENSA_PROP_SEC_NAME ".xt.prop"
|
||||
|
||||
typedef struct property_table_entry_t
|
||||
{
|
||||
bfd_vma address;
|
||||
bfd_vma size;
|
||||
flagword flags;
|
||||
} property_table_entry;
|
||||
|
||||
/* Flags in the property tables to specify whether blocks of memory are
|
||||
literals, instructions, data, or unreachable. For instructions,
|
||||
blocks that begin loop targets and branch targets are designated.
|
||||
Blocks that do not allow density instructions, instruction reordering
|
||||
or transformation are also specified. Finally, for branch targets,
|
||||
branch target alignment priority is included. Alignment of the next
|
||||
block is specified in the current block and the size of the current
|
||||
block does not include any fill required to align to the next
|
||||
block. */
|
||||
|
||||
#define XTENSA_PROP_LITERAL 0x00000001
|
||||
#define XTENSA_PROP_INSN 0x00000002
|
||||
#define XTENSA_PROP_DATA 0x00000004
|
||||
#define XTENSA_PROP_UNREACHABLE 0x00000008
|
||||
/* Instruction-only properties at beginning of code. */
|
||||
#define XTENSA_PROP_INSN_LOOP_TARGET 0x00000010
|
||||
#define XTENSA_PROP_INSN_BRANCH_TARGET 0x00000020
|
||||
/* Instruction-only properties about code. */
|
||||
#define XTENSA_PROP_INSN_NO_DENSITY 0x00000040
|
||||
#define XTENSA_PROP_INSN_NO_REORDER 0x00000080
|
||||
#define XTENSA_PROP_INSN_NO_TRANSFORM 0x00000100
|
||||
|
||||
/* Branch target alignment information. This transmits information
|
||||
to the linker optimization about the priority of aligning a
|
||||
particular block for branch target alignment: None, low priority,
|
||||
high priority, or required. These only need to be checked in
|
||||
instruction blocks marked as XTENSA_PROP_INSN_BRANCH_TARGET.
|
||||
Common usage is:
|
||||
|
||||
switch (GET_XTENSA_PROP_BT_ALIGN(flags))
|
||||
case XTENSA_PROP_BT_ALIGN_NONE:
|
||||
case XTENSA_PROP_BT_ALIGN_LOW:
|
||||
case XTENSA_PROP_BT_ALIGN_HIGH:
|
||||
case XTENSA_PROP_BT_ALIGN_REQUIRE:
|
||||
*/
|
||||
#define XTENSA_PROP_BT_ALIGN_MASK 0x00000600
|
||||
|
||||
/* No branch target alignment. */
|
||||
#define XTENSA_PROP_BT_ALIGN_NONE 0x0
|
||||
/* Low priority branch target alignment. */
|
||||
#define XTENSA_PROP_BT_ALIGN_LOW 0x1
|
||||
/* High priority branch target alignment. */
|
||||
#define XTENSA_PROP_BT_ALIGN_HIGH 0x2
|
||||
/* Required branch target alignment. */
|
||||
#define XTENSA_PROP_BT_ALIGN_REQUIRE 0x3
|
||||
|
||||
#define GET_XTENSA_PROP_BT_ALIGN(flag) \
|
||||
(((unsigned)((flag) & (XTENSA_PROP_BT_ALIGN_MASK))) >> 9)
|
||||
#define SET_XTENSA_PROP_BT_ALIGN(flag, align) \
|
||||
(((flag) & (~XTENSA_PROP_BT_ALIGN_MASK)) | \
|
||||
(((align) << 9) & XTENSA_PROP_BT_ALIGN_MASK))
|
||||
|
||||
/* Alignment is specified in the block BEFORE the one that needs
|
||||
alignment. Up to 5 bits. Use GET_XTENSA_PROP_ALIGNMENT(flags) to
|
||||
get the required alignment specified as a power of 2. Use
|
||||
SET_XTENSA_PROP_ALIGNMENT(flags, pow2) to set the required
|
||||
alignment. Be careful of side effects since the SET will evaluate
|
||||
flags twice. Also, note that the SIZE of a block in the property
|
||||
table does not include the alignment size, so the alignment fill
|
||||
must be calculated to determine if two blocks are contiguous.
|
||||
TEXT_ALIGN is not currently implemented but is a placeholder for a
|
||||
possible future implementation. */
|
||||
|
||||
#define XTENSA_PROP_ALIGN 0x00000800
|
||||
|
||||
#define XTENSA_PROP_ALIGNMENT_MASK 0x0001f000
|
||||
|
||||
#define GET_XTENSA_PROP_ALIGNMENT(flag) \
|
||||
(((unsigned)((flag) & (XTENSA_PROP_ALIGNMENT_MASK))) >> 12)
|
||||
#define SET_XTENSA_PROP_ALIGNMENT(flag, align) \
|
||||
(((flag) & (~XTENSA_PROP_ALIGNMENT_MASK)) | \
|
||||
(((align) << 12) & XTENSA_PROP_ALIGNMENT_MASK))
|
||||
|
||||
#define XTENSA_PROP_INSN_ABSLIT 0x00020000
|
||||
|
||||
#endif /* _ELF_XTENSA_H */
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
/* Xtensa configuration settings.
|
||||
Copyright (C) 2001,2002,2003 Free Software Foundation, Inc.
|
||||
Copyright (C) 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
|
||||
Contributed by Bob Wilson (bwilson@tensilica.com) at Tensilica.
|
||||
|
||||
This program is free software; you can redistribute it and/or modify
|
||||
@ -42,6 +42,9 @@
|
||||
#undef XCHAL_HAVE_L32R
|
||||
#define XCHAL_HAVE_L32R 1
|
||||
|
||||
#undef XSHAL_USE_ABSOLUTE_LITERALS
|
||||
#define XSHAL_USE_ABSOLUTE_LITERALS 0
|
||||
|
||||
#undef XCHAL_HAVE_MAC16
|
||||
#define XCHAL_HAVE_MAC16 0
|
||||
|
||||
@ -87,6 +90,9 @@
|
||||
#undef XCHAL_HAVE_WINDOWED
|
||||
#define XCHAL_HAVE_WINDOWED 1
|
||||
|
||||
#undef XCHAL_HAVE_PREDICTED_BRANCHES
|
||||
#define XCHAL_HAVE_PREDICTED_BRANCHES 0
|
||||
|
||||
|
||||
#undef XCHAL_ICACHE_SIZE
|
||||
#define XCHAL_ICACHE_SIZE 8192
|
||||
@ -130,10 +136,7 @@
|
||||
#define XCHAL_DEBUGLEVEL 4
|
||||
|
||||
|
||||
#undef XCHAL_EXTRA_SA_SIZE
|
||||
#define XCHAL_EXTRA_SA_SIZE 0
|
||||
|
||||
#undef XCHAL_EXTRA_SA_ALIGN
|
||||
#define XCHAL_EXTRA_SA_ALIGN 1
|
||||
#undef XCHAL_INST_FETCH_WIDTH
|
||||
#define XCHAL_INST_FETCH_WIDTH 4
|
||||
|
||||
#endif /* !XTENSA_CONFIG_H */
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
/* Internal definitions for configurable Xtensa ISA support.
|
||||
Copyright 2003 Free Software Foundation, Inc.
|
||||
Copyright 2003, 2004 Free Software Foundation, Inc.
|
||||
|
||||
This file is part of BFD, the Binary File Descriptor library.
|
||||
|
||||
@ -17,98 +17,215 @@
|
||||
along with this program; if not, write to the Free Software
|
||||
Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
|
||||
|
||||
/* Use the statically-linked version for the GNU tools. */
|
||||
#define STATIC_LIBISA 1
|
||||
#ifndef XTENSA_ISA_INTERNAL_H
|
||||
#define XTENSA_ISA_INTERNAL_H
|
||||
|
||||
#define ISA_INTERFACE_VERSION 3
|
||||
/* Flags. */
|
||||
|
||||
struct config_struct
|
||||
{
|
||||
char *param_name;
|
||||
char *param_value;
|
||||
};
|
||||
#define XTENSA_OPERAND_IS_REGISTER 0x00000001
|
||||
#define XTENSA_OPERAND_IS_PCRELATIVE 0x00000002
|
||||
#define XTENSA_OPERAND_IS_INVISIBLE 0x00000004
|
||||
#define XTENSA_OPERAND_IS_UNKNOWN 0x00000008
|
||||
|
||||
/* Encode/decode function types for immediate operands. */
|
||||
typedef uint32 (*xtensa_immed_decode_fn) (uint32);
|
||||
typedef xtensa_encode_result (*xtensa_immed_encode_fn) (uint32 *);
|
||||
#define XTENSA_OPCODE_IS_BRANCH 0x00000001
|
||||
#define XTENSA_OPCODE_IS_JUMP 0x00000002
|
||||
#define XTENSA_OPCODE_IS_LOOP 0x00000004
|
||||
#define XTENSA_OPCODE_IS_CALL 0x00000008
|
||||
|
||||
/* Field accessor function types. */
|
||||
#define XTENSA_STATE_IS_EXPORTED 0x00000001
|
||||
|
||||
#define XTENSA_INTERFACE_HAS_SIDE_EFFECT 0x00000001
|
||||
|
||||
/* Function pointer typedefs */
|
||||
typedef void (*xtensa_format_encode_fn) (xtensa_insnbuf);
|
||||
typedef void (*xtensa_get_slot_fn) (const xtensa_insnbuf, xtensa_insnbuf);
|
||||
typedef void (*xtensa_set_slot_fn) (xtensa_insnbuf, const xtensa_insnbuf);
|
||||
typedef int (*xtensa_opcode_decode_fn) (const xtensa_insnbuf);
|
||||
typedef uint32 (*xtensa_get_field_fn) (const xtensa_insnbuf);
|
||||
typedef void (*xtensa_set_field_fn) (xtensa_insnbuf, uint32);
|
||||
typedef int (*xtensa_immed_decode_fn) (uint32 *);
|
||||
typedef int (*xtensa_immed_encode_fn) (uint32 *);
|
||||
typedef int (*xtensa_do_reloc_fn) (uint32 *, uint32);
|
||||
typedef int (*xtensa_undo_reloc_fn) (uint32 *, uint32);
|
||||
typedef void (*xtensa_opcode_encode_fn) (xtensa_insnbuf);
|
||||
typedef int (*xtensa_format_decode_fn) (const xtensa_insnbuf);
|
||||
typedef int (*xtensa_length_decode_fn) (const char *);
|
||||
|
||||
/* PC-relative relocation function types. */
|
||||
typedef uint32 (*xtensa_do_reloc_fn) (uint32, uint32);
|
||||
typedef uint32 (*xtensa_undo_reloc_fn) (uint32, uint32);
|
||||
|
||||
/* Instruction decode function type. */
|
||||
typedef int (*xtensa_insn_decode_fn) (const xtensa_insnbuf);
|
||||
|
||||
/* Instruction encoding template function type (each of these functions
|
||||
returns a constant template; they exist only to make it easier for the
|
||||
TIE compiler to generate endian-independent DLLs). */
|
||||
typedef xtensa_insnbuf (*xtensa_encoding_template_fn) (void);
|
||||
typedef struct xtensa_format_internal_struct
|
||||
{
|
||||
const char *name; /* Instruction format name. */
|
||||
int length; /* Instruction length in bytes. */
|
||||
xtensa_format_encode_fn encode_fn;
|
||||
int num_slots;
|
||||
int *slot_id; /* Array[num_slots] of slot IDs. */
|
||||
} xtensa_format_internal;
|
||||
|
||||
typedef struct xtensa_slot_internal_struct
|
||||
{
|
||||
const char *name; /* Not necessarily unique. */
|
||||
const char *format;
|
||||
int position;
|
||||
xtensa_get_slot_fn get_fn;
|
||||
xtensa_set_slot_fn set_fn;
|
||||
xtensa_get_field_fn *get_field_fns; /* Array[field_id]. */
|
||||
xtensa_set_field_fn *set_field_fns; /* Array[field_id]. */
|
||||
xtensa_opcode_decode_fn opcode_decode_fn;
|
||||
const char *nop_name;
|
||||
} xtensa_slot_internal;
|
||||
|
||||
typedef struct xtensa_operand_internal_struct
|
||||
{
|
||||
char *operand_kind; /* e.g., "a", "f", "i", "l".... */
|
||||
char inout; /* '<', '>', or '='. */
|
||||
char isPCRelative; /* Is this a PC-relative offset? */
|
||||
xtensa_get_field_fn get_field; /* Get encoded value of the field. */
|
||||
xtensa_set_field_fn set_field; /* Set field with an encoded value. */
|
||||
const char *name;
|
||||
int field_id;
|
||||
xtensa_regfile regfile; /* Register file. */
|
||||
int num_regs; /* Usually 1; 2 for reg pairs, etc. */
|
||||
uint32 flags; /* See XTENSA_OPERAND_* flags. */
|
||||
xtensa_immed_encode_fn encode; /* Encode the operand value. */
|
||||
xtensa_immed_decode_fn decode; /* Decode the value from the field. */
|
||||
xtensa_do_reloc_fn do_reloc; /* Perform a PC-relative relocation. */
|
||||
xtensa_do_reloc_fn do_reloc; /* Perform a PC-relative reloc. */
|
||||
xtensa_undo_reloc_fn undo_reloc; /* Undo a PC-relative relocation. */
|
||||
} xtensa_operand_internal;
|
||||
|
||||
typedef struct xtensa_arg_internal_struct
|
||||
{
|
||||
union {
|
||||
int operand_id; /* For normal operands. */
|
||||
xtensa_state state; /* For stateOperands. */
|
||||
} u;
|
||||
char inout; /* Direction: 'i', 'o', or 'm'. */
|
||||
} xtensa_arg_internal;
|
||||
|
||||
typedef struct xtensa_iclass_internal_struct
|
||||
{
|
||||
int num_operands; /* Size of "operands" array. */
|
||||
xtensa_operand_internal **operands; /* Array of operand structures. */
|
||||
} xtensa_iclass_internal;
|
||||
xtensa_arg_internal *operands; /* Array[num_operands]. */
|
||||
|
||||
int num_stateOperands; /* Size of "stateOperands" array. */
|
||||
xtensa_arg_internal *stateOperands; /* Array[num_stateOperands]. */
|
||||
|
||||
int num_interfaceOperands; /* Size of "interfaceOperands". */
|
||||
xtensa_interface *interfaceOperands; /* Array[num_interfaceOperands]. */
|
||||
} xtensa_iclass_internal;
|
||||
|
||||
typedef struct xtensa_opcode_internal_struct
|
||||
{
|
||||
const char *name; /* Opcode mnemonic. */
|
||||
int length; /* Length in bytes of the insn. */
|
||||
xtensa_encoding_template_fn template; /* Fn returning encoding template. */
|
||||
xtensa_iclass_internal *iclass; /* Iclass for this opcode. */
|
||||
int iclass_id; /* Iclass for this opcode. */
|
||||
uint32 flags; /* See XTENSA_OPCODE_* flags. */
|
||||
xtensa_opcode_encode_fn *encode_fns; /* Array[slot_id]. */
|
||||
int num_funcUnit_uses; /* Number of funcUnit_use entries. */
|
||||
xtensa_funcUnit_use *funcUnit_uses; /* Array[num_funcUnit_uses]. */
|
||||
} xtensa_opcode_internal;
|
||||
|
||||
|
||||
typedef struct opname_lookup_entry_struct
|
||||
typedef struct xtensa_regfile_internal_struct
|
||||
{
|
||||
const char *key; /* Opcode mnemonic. */
|
||||
xtensa_opcode opcode; /* Internal opcode number. */
|
||||
} opname_lookup_entry;
|
||||
const char *name; /* Full name of the regfile. */
|
||||
const char *shortname; /* Abbreviated name. */
|
||||
xtensa_regfile parent; /* View parent (or identity). */
|
||||
int num_bits; /* Width of the registers. */
|
||||
int num_entries; /* Number of registers. */
|
||||
} xtensa_regfile_internal;
|
||||
|
||||
typedef struct xtensa_interface_internal_struct
|
||||
{
|
||||
const char *name; /* Interface name. */
|
||||
int num_bits; /* Width of the interface. */
|
||||
uint32 flags; /* See XTENSA_INTERFACE_* flags. */
|
||||
char inout; /* "i" or "o". */
|
||||
} xtensa_interface_internal;
|
||||
|
||||
typedef struct xtensa_funcUnit_internal_struct
|
||||
{
|
||||
const char *name; /* Functional unit name. */
|
||||
int num_copies; /* Number of instances. */
|
||||
} xtensa_funcUnit_internal;
|
||||
|
||||
typedef struct xtensa_state_internal_struct
|
||||
{
|
||||
const char *name; /* State name. */
|
||||
int num_bits; /* Number of state bits. */
|
||||
uint32 flags; /* See XTENSA_STATE_* flags. */
|
||||
} xtensa_state_internal;
|
||||
|
||||
typedef struct xtensa_sysreg_internal_struct
|
||||
{
|
||||
const char *name; /* Register name. */
|
||||
int number; /* Register number. */
|
||||
int is_user; /* Non-zero if a "user register". */
|
||||
} xtensa_sysreg_internal;
|
||||
|
||||
typedef struct xtensa_lookup_entry_struct
|
||||
{
|
||||
const char *key;
|
||||
union
|
||||
{
|
||||
xtensa_opcode opcode; /* Internal opcode number. */
|
||||
xtensa_sysreg sysreg; /* Internal sysreg number. */
|
||||
xtensa_state state; /* Internal state number. */
|
||||
xtensa_interface intf; /* Internal interface number. */
|
||||
xtensa_funcUnit fun; /* Internal funcUnit number. */
|
||||
} u;
|
||||
} xtensa_lookup_entry;
|
||||
|
||||
typedef struct xtensa_isa_internal_struct
|
||||
{
|
||||
int is_big_endian; /* Endianness. */
|
||||
int insn_size; /* Maximum length in bytes. */
|
||||
int insnbuf_size; /* Number of insnbuf_words. */
|
||||
int num_opcodes; /* Total number for all modules. */
|
||||
xtensa_opcode_internal **opcode_table;/* Indexed by internal opcode #. */
|
||||
int num_modules; /* Number of modules (DLLs) loaded. */
|
||||
int *module_opcode_base; /* Starting opcode # for each module. */
|
||||
xtensa_insn_decode_fn *module_decode_fn; /* Decode fn for each module. */
|
||||
opname_lookup_entry *opname_lookup_table; /* Lookup table for each module. */
|
||||
struct config_struct *config; /* Table of configuration parameters. */
|
||||
int has_density; /* Is density option available? */
|
||||
|
||||
int num_formats;
|
||||
xtensa_format_internal *formats;
|
||||
xtensa_format_decode_fn format_decode_fn;
|
||||
xtensa_length_decode_fn length_decode_fn;
|
||||
|
||||
int num_slots;
|
||||
xtensa_slot_internal *slots;
|
||||
|
||||
int num_fields;
|
||||
|
||||
int num_operands;
|
||||
xtensa_operand_internal *operands;
|
||||
|
||||
int num_iclasses;
|
||||
xtensa_iclass_internal *iclasses;
|
||||
|
||||
int num_opcodes;
|
||||
xtensa_opcode_internal *opcodes;
|
||||
xtensa_lookup_entry *opname_lookup_table;
|
||||
|
||||
int num_regfiles;
|
||||
xtensa_regfile_internal *regfiles;
|
||||
|
||||
int num_states;
|
||||
xtensa_state_internal *states;
|
||||
xtensa_lookup_entry *state_lookup_table;
|
||||
|
||||
int num_sysregs;
|
||||
xtensa_sysreg_internal *sysregs;
|
||||
xtensa_lookup_entry *sysreg_lookup_table;
|
||||
|
||||
/* The current Xtensa ISA only supports 256 of each kind of sysreg so
|
||||
we can get away with implementing lookups with tables indexed by
|
||||
the register numbers. If we ever allow larger sysreg numbers, this
|
||||
may have to be reimplemented. The first entry in the following
|
||||
arrays corresponds to "special" registers and the second to "user"
|
||||
registers. */
|
||||
int max_sysreg_num[2];
|
||||
xtensa_sysreg *sysreg_table[2];
|
||||
|
||||
int num_interfaces;
|
||||
xtensa_interface_internal *interfaces;
|
||||
xtensa_lookup_entry *interface_lookup_table;
|
||||
|
||||
int num_funcUnits;
|
||||
xtensa_funcUnit_internal *funcUnits;
|
||||
xtensa_lookup_entry *funcUnit_lookup_table;
|
||||
|
||||
} xtensa_isa_internal;
|
||||
|
||||
extern int xtensa_isa_name_compare (const void *, const void *);
|
||||
|
||||
typedef struct xtensa_isa_module_struct
|
||||
{
|
||||
int (*get_num_opcodes_fn) (void);
|
||||
xtensa_opcode_internal **(*get_opcodes_fn) (void);
|
||||
int (*decode_insn_fn) (const xtensa_insnbuf);
|
||||
struct config_struct *(*get_config_table_fn) (void);
|
||||
} xtensa_isa_module;
|
||||
|
||||
extern xtensa_isa_module xtensa_isa_modules[];
|
||||
extern xtensa_isa_status xtisa_errno;
|
||||
extern char xtisa_error_msg[];
|
||||
|
||||
#endif /* !XTENSA_ISA_INTERNAL_H */
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
/* Interface definition for configurable Xtensa ISA support.
|
||||
Copyright 2003 Free Software Foundation, Inc.
|
||||
Copyright 2003, 2004 Free Software Foundation, Inc.
|
||||
|
||||
This file is part of BFD, the Binary File Descriptor library.
|
||||
|
||||
@ -20,209 +20,763 @@
|
||||
#ifndef XTENSA_LIBISA_H
|
||||
#define XTENSA_LIBISA_H
|
||||
|
||||
/* Use the statically-linked version for the GNU tools. */
|
||||
#define STATIC_LIBISA 1
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Use the statically-linked version for the GNU tools. */
|
||||
#define STATIC_LIBISA 1
|
||||
|
||||
/* Version number: This is intended to help support code that works with
|
||||
versions of this library from multiple Xtensa releases. */
|
||||
|
||||
#define XTENSA_ISA_VERSION 7000
|
||||
|
||||
#ifndef uint32
|
||||
#define uint32 unsigned int
|
||||
#endif
|
||||
|
||||
/* This file defines the interface to the Xtensa ISA library. This library
|
||||
contains most of the ISA-specific information for a particular Xtensa
|
||||
processor. For example, the set of valid instructions, their opcode
|
||||
encodings and operand fields are all included here. To support Xtensa's
|
||||
configurability and user-defined instruction extensions (i.e., TIE), the
|
||||
library is initialized by loading one or more dynamic libraries; only a
|
||||
small set of interface code is present in the statically-linked portion
|
||||
of the library.
|
||||
/* This file defines the interface to the Xtensa ISA library. This
|
||||
library contains most of the ISA-specific information for a
|
||||
particular Xtensa processor. For example, the set of valid
|
||||
instructions, their opcode encodings and operand fields are all
|
||||
included here.
|
||||
|
||||
This interface basically defines four abstract data types.
|
||||
This interface basically defines a number of abstract data types.
|
||||
|
||||
. an instruction buffer - for holding the raw instruction bits
|
||||
. ISA info - information about the ISA as a whole
|
||||
. opcode info - information about individual instructions
|
||||
. operand info - information about specific instruction operands
|
||||
. instruction formats - instruction size and slot structure
|
||||
. opcodes - information about individual instructions
|
||||
. operands - information about register and immediate instruction operands
|
||||
. stateOperands - information about processor state instruction operands
|
||||
. interfaceOperands - information about interface instruction operands
|
||||
. register files - register file information
|
||||
. processor states - internal processor state information
|
||||
. system registers - "special registers" and "user registers"
|
||||
. interfaces - TIE interfaces that are external to the processor
|
||||
. functional units - TIE shared functions
|
||||
|
||||
It would be nice to implement these as classes in C++, but the library is
|
||||
implemented in C to match the expectations of the GNU tools.
|
||||
Instead, the interface defines a set of functions to access each data
|
||||
type. With the exception of the instruction buffer, the internal
|
||||
representations of the data structures are hidden. All accesses must be
|
||||
made through the functions defined here. */
|
||||
The interface defines a set of functions to access each data type.
|
||||
With the exception of the instruction buffer, the internal
|
||||
representations of the data structures are hidden. All accesses must
|
||||
be made through the functions defined here. */
|
||||
|
||||
typedef void* xtensa_isa;
|
||||
typedef void* xtensa_operand;
|
||||
typedef struct xtensa_isa_opaque { int unused; } *xtensa_isa;
|
||||
|
||||
|
||||
/* Opcodes are represented here using sequential integers beginning with 0.
|
||||
The specific value used for a particular opcode is only fixed for a
|
||||
particular instantiation of an xtensa_isa structure, so these values
|
||||
should only be used internally. */
|
||||
/* Opcodes, formats, regfiles, states, sysregs, ctypes, and protos are
|
||||
represented here using sequential integers beginning with 0. The
|
||||
specific values are only fixed for a particular instantiation of an
|
||||
xtensa_isa structure, so these values should only be used
|
||||
internally. */
|
||||
|
||||
typedef int xtensa_opcode;
|
||||
typedef int xtensa_format;
|
||||
typedef int xtensa_regfile;
|
||||
typedef int xtensa_state;
|
||||
typedef int xtensa_sysreg;
|
||||
typedef int xtensa_interface;
|
||||
typedef int xtensa_funcUnit;
|
||||
|
||||
|
||||
/* Define a unique value for undefined items. */
|
||||
|
||||
/* Define a unique value for undefined opcodes ("static const int" doesn't
|
||||
seem to work for this because EGCS 1.0.3 on i686-Linux without -O won't
|
||||
allow it to be used as an initializer). */
|
||||
#define XTENSA_UNDEFINED -1
|
||||
|
||||
|
||||
typedef int libisa_module_specifier;
|
||||
/* Overview of using this interface to decode/encode instructions:
|
||||
|
||||
extern xtensa_isa xtensa_isa_init (void);
|
||||
Each Xtensa instruction is associated with a particular instruction
|
||||
format, where the format defines a fixed number of slots for
|
||||
operations. The formats for the core Xtensa ISA have only one slot,
|
||||
but FLIX instructions may have multiple slots. Within each slot,
|
||||
there is a single opcode and some number of associated operands.
|
||||
|
||||
The encoding and decoding functions operate on instruction buffers,
|
||||
not on the raw bytes of the instructions. The same instruction
|
||||
buffer data structure is used for both entire instructions and
|
||||
individual slots in those instructions -- the contents of a slot need
|
||||
to be extracted from or inserted into the buffer for the instruction
|
||||
as a whole.
|
||||
|
||||
Decoding an instruction involves first finding the format, which
|
||||
identifies the number of slots, and then decoding each slot
|
||||
separately. A slot is decoded by finding the opcode and then using
|
||||
the opcode to determine how many operands there are. For example:
|
||||
|
||||
xtensa_insnbuf_from_chars
|
||||
xtensa_format_decode
|
||||
for each slot {
|
||||
xtensa_format_get_slot
|
||||
xtensa_opcode_decode
|
||||
for each operand {
|
||||
xtensa_operand_get_field
|
||||
xtensa_operand_decode
|
||||
}
|
||||
}
|
||||
|
||||
Encoding an instruction is roughly the same procedure in reverse:
|
||||
|
||||
xtensa_format_encode
|
||||
for each slot {
|
||||
xtensa_opcode_encode
|
||||
for each operand {
|
||||
xtensa_operand_encode
|
||||
xtensa_operand_set_field
|
||||
}
|
||||
xtensa_format_set_slot
|
||||
}
|
||||
xtensa_insnbuf_to_chars
|
||||
*/
|
||||
|
||||
|
||||
/* Error handling. */
|
||||
|
||||
/* Error codes. The code for the most recent error condition can be
|
||||
retrieved with the "errno" function. For any result other than
|
||||
xtensa_isa_ok, an error message containing additional information
|
||||
about the problem can be retrieved using the "error_msg" function.
|
||||
The error messages are stored in an internal buffer, which should not
|
||||
should be freed and may be overwritten by subsequent operations. */
|
||||
|
||||
typedef enum xtensa_isa_status_enum
|
||||
{
|
||||
xtensa_isa_ok = 0,
|
||||
xtensa_isa_bad_format,
|
||||
xtensa_isa_bad_slot,
|
||||
xtensa_isa_bad_opcode,
|
||||
xtensa_isa_bad_operand,
|
||||
xtensa_isa_bad_field,
|
||||
xtensa_isa_bad_iclass,
|
||||
xtensa_isa_bad_regfile,
|
||||
xtensa_isa_bad_sysreg,
|
||||
xtensa_isa_bad_state,
|
||||
xtensa_isa_bad_interface,
|
||||
xtensa_isa_bad_funcUnit,
|
||||
xtensa_isa_wrong_slot,
|
||||
xtensa_isa_no_field,
|
||||
xtensa_isa_out_of_memory,
|
||||
xtensa_isa_buffer_overflow,
|
||||
xtensa_isa_internal_error,
|
||||
xtensa_isa_bad_value
|
||||
} xtensa_isa_status;
|
||||
|
||||
extern xtensa_isa_status
|
||||
xtensa_isa_errno (xtensa_isa isa);
|
||||
|
||||
extern char *
|
||||
xtensa_isa_error_msg (xtensa_isa isa);
|
||||
|
||||
|
||||
/* Instruction buffers. */
|
||||
|
||||
typedef uint32 xtensa_insnbuf_word;
|
||||
typedef xtensa_insnbuf_word *xtensa_insnbuf;
|
||||
|
||||
/* Get the size in words of the xtensa_insnbuf array. */
|
||||
extern int xtensa_insnbuf_size (xtensa_isa);
|
||||
|
||||
/* Allocate (with malloc) an xtensa_insnbuf of the right size. */
|
||||
extern xtensa_insnbuf xtensa_insnbuf_alloc (xtensa_isa);
|
||||
/* Get the size in "insnbuf_words" of the xtensa_insnbuf array. */
|
||||
|
||||
/* Release (with free) an xtensa_insnbuf of the right size. */
|
||||
extern void xtensa_insnbuf_free (xtensa_insnbuf);
|
||||
|
||||
/* Inward and outward conversion from memory images (byte streams) to our
|
||||
internal instruction representation. */
|
||||
extern void xtensa_insnbuf_to_chars (xtensa_isa, const xtensa_insnbuf,
|
||||
char *);
|
||||
|
||||
extern void xtensa_insnbuf_from_chars (xtensa_isa, xtensa_insnbuf,
|
||||
const char *);
|
||||
extern int
|
||||
xtensa_insnbuf_size (xtensa_isa isa);
|
||||
|
||||
|
||||
/* Allocate an xtensa_insnbuf of the right size. */
|
||||
|
||||
extern xtensa_insnbuf
|
||||
xtensa_insnbuf_alloc (xtensa_isa isa);
|
||||
|
||||
|
||||
/* Release an xtensa_insnbuf. */
|
||||
|
||||
extern void
|
||||
xtensa_insnbuf_free (xtensa_isa isa, xtensa_insnbuf buf);
|
||||
|
||||
|
||||
/* Conversion between raw memory (char arrays) and our internal
|
||||
instruction representation. This is complicated by the Xtensa ISA's
|
||||
variable instruction lengths. When converting to chars, the buffer
|
||||
must contain a valid instruction so we know how many bytes to copy;
|
||||
thus, the "to_chars" function returns the number of bytes copied or
|
||||
XTENSA_UNDEFINED on error. The "from_chars" function first reads the
|
||||
minimal number of bytes required to decode the instruction length and
|
||||
then proceeds to copy the entire instruction into the buffer; if the
|
||||
memory does not contain a valid instruction, it copies the maximum
|
||||
number of bytes required for the longest Xtensa instruction. The
|
||||
"num_chars" argument may be used to limit the number of bytes that
|
||||
can be read or written. Otherwise, if "num_chars" is zero, the
|
||||
functions may read or write past the end of the code. */
|
||||
|
||||
extern int
|
||||
xtensa_insnbuf_to_chars (xtensa_isa isa, const xtensa_insnbuf insn,
|
||||
char *cp, int num_chars);
|
||||
|
||||
extern void
|
||||
xtensa_insnbuf_from_chars (xtensa_isa isa, xtensa_insnbuf insn,
|
||||
const char *cp, int num_chars);
|
||||
|
||||
|
||||
/* ISA information. */
|
||||
|
||||
/* Load the ISA information from a shared library. If successful, this returns
|
||||
a value which identifies the ISA for use in subsequent calls to the ISA
|
||||
library; otherwise, it returns NULL. Multiple ISAs can be loaded to support
|
||||
heterogeneous multiprocessor systems. */
|
||||
extern xtensa_isa xtensa_load_isa (libisa_module_specifier);
|
||||
/* Initialize the ISA information. */
|
||||
|
||||
/* Extend an existing set of ISA information by loading an additional shared
|
||||
library of ISA information. This is primarily intended for loading TIE
|
||||
extensions. If successful, the return value is non-zero. */
|
||||
extern int xtensa_extend_isa (xtensa_isa, libisa_module_specifier);
|
||||
|
||||
/* The default ISA. This variable is set automatically to the ISA most
|
||||
recently loaded and is provided as a convenience. An exception is the GNU
|
||||
opcodes library, where there is a fixed interface that does not allow
|
||||
passing the ISA as a parameter and the ISA must be taken from this global
|
||||
variable. (Note: Since this variable is just a convenience, it is not
|
||||
exported when libisa is built as a DLL, due to the hassle of dealing with
|
||||
declspecs.) */
|
||||
extern xtensa_isa xtensa_default_isa;
|
||||
extern xtensa_isa
|
||||
xtensa_isa_init (xtensa_isa_status *errno_p, char **error_msg_p);
|
||||
|
||||
|
||||
/* Deallocate an xtensa_isa structure. */
|
||||
extern void xtensa_isa_free (xtensa_isa);
|
||||
|
||||
extern void
|
||||
xtensa_isa_free (xtensa_isa isa);
|
||||
|
||||
|
||||
/* Get the maximum instruction size in bytes. */
|
||||
extern int xtensa_insn_maxlength (xtensa_isa);
|
||||
|
||||
/* Get the total number of opcodes for this processor. */
|
||||
extern int xtensa_num_opcodes (xtensa_isa);
|
||||
extern int
|
||||
xtensa_isa_maxlength (xtensa_isa isa);
|
||||
|
||||
|
||||
/* Decode the length in bytes of an instruction in raw memory (not an
|
||||
insnbuf). This function reads only the minimal number of bytes
|
||||
required to decode the instruction length. Returns
|
||||
XTENSA_UNDEFINED on error. */
|
||||
|
||||
extern int
|
||||
xtensa_isa_length_from_chars (xtensa_isa isa, const char *cp);
|
||||
|
||||
|
||||
/* Get the number of stages in the processor's pipeline. The pipeline
|
||||
stage values returned by other functions in this library will range
|
||||
from 0 to N-1, where N is the value returned by this function.
|
||||
Note that the stage numbers used here may not correspond to the
|
||||
actual processor hardware, e.g., the hardware may have additional
|
||||
stages before stage 0. Returns XTENSA_UNDEFINED on error. */
|
||||
|
||||
extern int
|
||||
xtensa_isa_num_pipe_stages (xtensa_isa isa);
|
||||
|
||||
|
||||
/* Get the number of various entities that are defined for this processor. */
|
||||
|
||||
extern int
|
||||
xtensa_isa_num_formats (xtensa_isa isa);
|
||||
|
||||
extern int
|
||||
xtensa_isa_num_opcodes (xtensa_isa isa);
|
||||
|
||||
extern int
|
||||
xtensa_isa_num_regfiles (xtensa_isa isa);
|
||||
|
||||
extern int
|
||||
xtensa_isa_num_states (xtensa_isa isa);
|
||||
|
||||
extern int
|
||||
xtensa_isa_num_sysregs (xtensa_isa isa);
|
||||
|
||||
extern int
|
||||
xtensa_isa_num_interfaces (xtensa_isa isa);
|
||||
|
||||
extern int
|
||||
xtensa_isa_num_funcUnits (xtensa_isa isa);
|
||||
|
||||
|
||||
/* Instruction formats. */
|
||||
|
||||
/* Get the name of a format. Returns null on error. */
|
||||
|
||||
extern const char *
|
||||
xtensa_format_name (xtensa_isa isa, xtensa_format fmt);
|
||||
|
||||
|
||||
/* Given a format name, return the format number. Returns
|
||||
XTENSA_UNDEFINED if the name is not a valid format. */
|
||||
|
||||
extern xtensa_format
|
||||
xtensa_format_lookup (xtensa_isa isa, const char *fmtname);
|
||||
|
||||
|
||||
/* Decode the instruction format from a binary instruction buffer.
|
||||
Returns XTENSA_UNDEFINED if the format is not recognized. */
|
||||
|
||||
extern xtensa_format
|
||||
xtensa_format_decode (xtensa_isa isa, const xtensa_insnbuf insn);
|
||||
|
||||
|
||||
/* Set the instruction format field(s) in a binary instruction buffer.
|
||||
All the other fields are set to zero. Returns non-zero on error. */
|
||||
|
||||
extern int
|
||||
xtensa_format_encode (xtensa_isa isa, xtensa_format fmt, xtensa_insnbuf insn);
|
||||
|
||||
|
||||
/* Find the length (in bytes) of an instruction. Returns
|
||||
XTENSA_UNDEFINED on error. */
|
||||
|
||||
extern int
|
||||
xtensa_format_length (xtensa_isa isa, xtensa_format fmt);
|
||||
|
||||
|
||||
/* Get the number of slots in an instruction. Returns XTENSA_UNDEFINED
|
||||
on error. */
|
||||
|
||||
extern int
|
||||
xtensa_format_num_slots (xtensa_isa isa, xtensa_format fmt);
|
||||
|
||||
|
||||
/* Get the opcode for a no-op in a particular slot.
|
||||
Returns XTENSA_UNDEFINED on error. */
|
||||
|
||||
extern xtensa_opcode
|
||||
xtensa_format_slot_nop_opcode (xtensa_isa isa, xtensa_format fmt, int slot);
|
||||
|
||||
|
||||
/* Get the bits for a specified slot out of an insnbuf for the
|
||||
instruction as a whole and put them into an insnbuf for that one
|
||||
slot, and do the opposite to set a slot. Return non-zero on error. */
|
||||
|
||||
extern int
|
||||
xtensa_format_get_slot (xtensa_isa isa, xtensa_format fmt, int slot,
|
||||
const xtensa_insnbuf insn, xtensa_insnbuf slotbuf);
|
||||
|
||||
extern int
|
||||
xtensa_format_set_slot (xtensa_isa isa, xtensa_format fmt, int slot,
|
||||
xtensa_insnbuf insn, const xtensa_insnbuf slotbuf);
|
||||
|
||||
|
||||
/* Opcode information. */
|
||||
|
||||
/* Translate a mnemonic name to an opcode. Returns XTENSA_UNDEFINED if
|
||||
the name is not a valid opcode mnemonic. */
|
||||
extern xtensa_opcode xtensa_opcode_lookup (xtensa_isa, const char *);
|
||||
|
||||
/* Decode a binary instruction buffer. Returns the opcode or
|
||||
XTENSA_UNDEFINED if the instruction is illegal. */
|
||||
extern xtensa_opcode xtensa_decode_insn (xtensa_isa, const xtensa_insnbuf);
|
||||
extern xtensa_opcode
|
||||
xtensa_opcode_lookup (xtensa_isa isa, const char *opname);
|
||||
|
||||
|
||||
/* Opcode information. */
|
||||
/* Decode the opcode for one instruction slot from a binary instruction
|
||||
buffer. Returns the opcode or XTENSA_UNDEFINED if the opcode is
|
||||
illegal. */
|
||||
|
||||
/* Set the opcode field(s) in a binary instruction buffer. The operand
|
||||
fields are set to zero. */
|
||||
extern void xtensa_encode_insn (xtensa_isa, xtensa_opcode, xtensa_insnbuf);
|
||||
extern xtensa_opcode
|
||||
xtensa_opcode_decode (xtensa_isa isa, xtensa_format fmt, int slot,
|
||||
const xtensa_insnbuf slotbuf);
|
||||
|
||||
/* Get the mnemonic name for an opcode. */
|
||||
extern const char * xtensa_opcode_name (xtensa_isa, xtensa_opcode);
|
||||
|
||||
/* Find the length (in bytes) of an instruction. */
|
||||
extern int xtensa_insn_length (xtensa_isa, xtensa_opcode);
|
||||
/* Set the opcode field(s) for an instruction slot. All other fields
|
||||
in the slot are set to zero. Returns non-zero if the opcode cannot
|
||||
be encoded. */
|
||||
|
||||
/* Find the length of an instruction by looking only at the first byte. */
|
||||
extern int xtensa_insn_length_from_first_byte (xtensa_isa, char);
|
||||
extern int
|
||||
xtensa_opcode_encode (xtensa_isa isa, xtensa_format fmt, int slot,
|
||||
xtensa_insnbuf slotbuf, xtensa_opcode opc);
|
||||
|
||||
/* Find the number of operands for an instruction. */
|
||||
extern int xtensa_num_operands (xtensa_isa, xtensa_opcode);
|
||||
|
||||
/* Get the information about operand number "opnd" of a particular opcode. */
|
||||
extern xtensa_operand xtensa_get_operand (xtensa_isa, xtensa_opcode, int);
|
||||
/* Get the mnemonic name for an opcode. Returns null on error. */
|
||||
|
||||
extern const char *
|
||||
xtensa_opcode_name (xtensa_isa isa, xtensa_opcode opc);
|
||||
|
||||
|
||||
/* Check various properties of opcodes. These functions return 0 if
|
||||
the condition is false, 1 if the condition is true, and
|
||||
XTENSA_UNDEFINED on error. The instructions are classified as
|
||||
follows:
|
||||
|
||||
branch: conditional branch; may fall through to next instruction (B*)
|
||||
jump: unconditional branch (J, JX, RET*, RF*)
|
||||
loop: zero-overhead loop (LOOP*)
|
||||
call: unconditional call; control returns to next instruction (CALL*)
|
||||
|
||||
For the opcodes that affect control flow in some way, the branch
|
||||
target may be specified by an immediate operand or it may be an
|
||||
address stored in a register. You can distinguish these by
|
||||
checking if the instruction has a PC-relative immediate
|
||||
operand. */
|
||||
|
||||
extern int
|
||||
xtensa_opcode_is_branch (xtensa_isa isa, xtensa_opcode opc);
|
||||
|
||||
extern int
|
||||
xtensa_opcode_is_jump (xtensa_isa isa, xtensa_opcode opc);
|
||||
|
||||
extern int
|
||||
xtensa_opcode_is_loop (xtensa_isa isa, xtensa_opcode opc);
|
||||
|
||||
extern int
|
||||
xtensa_opcode_is_call (xtensa_isa isa, xtensa_opcode opc);
|
||||
|
||||
|
||||
/* Find the number of ordinary operands, state operands, and interface
|
||||
operands for an instruction. These return XTENSA_UNDEFINED on
|
||||
error. */
|
||||
|
||||
extern int
|
||||
xtensa_opcode_num_operands (xtensa_isa isa, xtensa_opcode opc);
|
||||
|
||||
|
||||
extern int
|
||||
xtensa_opcode_num_stateOperands (xtensa_isa isa, xtensa_opcode opc);
|
||||
|
||||
extern int
|
||||
xtensa_opcode_num_interfaceOperands (xtensa_isa isa, xtensa_opcode opc);
|
||||
|
||||
|
||||
/* Get functional unit usage requirements for an opcode. Each "use"
|
||||
is identified by a <functional unit, pipeline stage> pair. The
|
||||
"num_funcUnit_uses" function returns the number of these "uses" or
|
||||
XTENSA_UNDEFINED on error. The "funcUnit_use" function returns
|
||||
a pointer to a "use" pair or null on error. */
|
||||
|
||||
typedef struct xtensa_funcUnit_use_struct
|
||||
{
|
||||
xtensa_funcUnit unit;
|
||||
int stage;
|
||||
} xtensa_funcUnit_use;
|
||||
|
||||
extern int
|
||||
xtensa_opcode_num_funcUnit_uses (xtensa_isa isa, xtensa_opcode opc);
|
||||
|
||||
extern xtensa_funcUnit_use *
|
||||
xtensa_opcode_funcUnit_use (xtensa_isa isa, xtensa_opcode opc, int u);
|
||||
|
||||
|
||||
/* Operand information. */
|
||||
|
||||
/* Find the kind of operand. There are three possibilities:
|
||||
1) PC-relative immediates (e.g., "l", "L"). These can be identified with
|
||||
the xtensa_operand_isPCRelative function.
|
||||
2) non-PC-relative immediates ("i").
|
||||
3) register-file short names (e.g., "a", "b", "m" and others defined
|
||||
via TIE). */
|
||||
extern char * xtensa_operand_kind (xtensa_operand);
|
||||
/* Get the name of an operand. Returns null on error. */
|
||||
|
||||
/* Check if an operand is an input ('<'), output ('>'), or inout ('=')
|
||||
extern const char *
|
||||
xtensa_operand_name (xtensa_isa isa, xtensa_opcode opc, int opnd);
|
||||
|
||||
|
||||
/* Some operands are "invisible", i.e., not explicitly specified in
|
||||
assembly language. When assembling an instruction, you need not set
|
||||
the values of invisible operands, since they are either hardwired or
|
||||
derived from other field values. The values of invisible operands
|
||||
can be examined in the same way as other operands, but remember that
|
||||
an invisible operand may get its value from another visible one, so
|
||||
the entire instruction must be available before examining the
|
||||
invisible operand values. This function returns 1 if an operand is
|
||||
visible, 0 if it is invisible, or XTENSA_UNDEFINED on error. Note
|
||||
that whether an operand is visible is orthogonal to whether it is
|
||||
"implicit", i.e., whether it is encoded in a field in the
|
||||
instruction. */
|
||||
|
||||
extern int
|
||||
xtensa_operand_is_visible (xtensa_isa isa, xtensa_opcode opc, int opnd);
|
||||
|
||||
|
||||
/* Check if an operand is an input ('i'), output ('o'), or inout ('m')
|
||||
operand. Note: The output operand of a conditional assignment
|
||||
(e.g., movnez) appears here as an inout ('=') even if it is declared
|
||||
in the TIE code as an output ('>'); this allows the compiler to
|
||||
properly handle register allocation for conditional assignments. */
|
||||
extern char xtensa_operand_inout (xtensa_operand);
|
||||
(e.g., movnez) appears here as an inout ('m') even if it is declared
|
||||
in the TIE code as an output ('o'); this allows the compiler to
|
||||
properly handle register allocation for conditional assignments.
|
||||
Returns 0 on error. */
|
||||
|
||||
extern char
|
||||
xtensa_operand_inout (xtensa_isa isa, xtensa_opcode opc, int opnd);
|
||||
|
||||
|
||||
/* Get and set the raw (encoded) value of the field for the specified
|
||||
operand. The "set" function does not check if the value fits in the
|
||||
field; that is done by the "encode" function below. */
|
||||
extern uint32 xtensa_operand_get_field (xtensa_operand, const xtensa_insnbuf);
|
||||
field; that is done by the "encode" function below. Both of these
|
||||
functions return non-zero on error, e.g., if the field is not defined
|
||||
for the specified slot. */
|
||||
|
||||
extern void xtensa_operand_set_field (xtensa_operand, xtensa_insnbuf, uint32);
|
||||
extern int
|
||||
xtensa_operand_get_field (xtensa_isa isa, xtensa_opcode opc, int opnd,
|
||||
xtensa_format fmt, int slot,
|
||||
const xtensa_insnbuf slotbuf, uint32 *valp);
|
||||
|
||||
extern int
|
||||
xtensa_operand_set_field (xtensa_isa isa, xtensa_opcode opc, int opnd,
|
||||
xtensa_format fmt, int slot,
|
||||
xtensa_insnbuf slotbuf, uint32 val);
|
||||
|
||||
|
||||
/* Encode and decode operands. The raw bits in the operand field
|
||||
may be encoded in a variety of different ways. These functions hide the
|
||||
details of that encoding. The encode function has a special return type
|
||||
(xtensa_encode_result) to indicate success or the reason for failure; the
|
||||
encoded value is returned through the argument pointer. The decode function
|
||||
has no possibility of failure and returns the decoded value. */
|
||||
/* Encode and decode operands. The raw bits in the operand field may
|
||||
be encoded in a variety of different ways. These functions hide
|
||||
the details of that encoding. The result values are returned through
|
||||
the argument pointer. The return value is non-zero on error. */
|
||||
|
||||
typedef enum
|
||||
{
|
||||
xtensa_encode_result_ok,
|
||||
xtensa_encode_result_align,
|
||||
xtensa_encode_result_not_in_table,
|
||||
xtensa_encode_result_too_low,
|
||||
xtensa_encode_result_too_high,
|
||||
xtensa_encode_result_not_ok,
|
||||
xtensa_encode_result_max = xtensa_encode_result_not_ok
|
||||
} xtensa_encode_result;
|
||||
extern int
|
||||
xtensa_operand_encode (xtensa_isa isa, xtensa_opcode opc, int opnd,
|
||||
uint32 *valp);
|
||||
|
||||
extern xtensa_encode_result xtensa_operand_encode (xtensa_operand, uint32 *);
|
||||
|
||||
extern uint32 xtensa_operand_decode (xtensa_operand, uint32);
|
||||
extern int
|
||||
xtensa_operand_decode (xtensa_isa isa, xtensa_opcode opc, int opnd,
|
||||
uint32 *valp);
|
||||
|
||||
|
||||
/* For PC-relative offset operands, the interpretation of the offset may vary
|
||||
between opcodes, e.g., is it relative to the current PC or that of the next
|
||||
instruction? The following functions are defined to perform PC-relative
|
||||
relocations and to undo them (as in the disassembler). The first function
|
||||
takes the desired address and the PC of the current instruction and returns
|
||||
the unencoded value to be stored in the offset field. The second function
|
||||
takes the unencoded offset value and the current PC and returns the address.
|
||||
Note that these functions do not replace the encode/decode functions; the
|
||||
operands must be encoded/decoded separately. */
|
||||
/* An operand may be either a register operand or an immediate of some
|
||||
sort (e.g., PC-relative or not). The "is_register" function returns
|
||||
0 if the operand is an immediate, 1 if it is a register, and
|
||||
XTENSA_UNDEFINED on error. The "regfile" function returns the
|
||||
regfile for a register operand, or XTENSA_UNDEFINED on error. */
|
||||
|
||||
extern int xtensa_operand_isPCRelative (xtensa_operand);
|
||||
extern int
|
||||
xtensa_operand_is_register (xtensa_isa isa, xtensa_opcode opc, int opnd);
|
||||
|
||||
extern uint32 xtensa_operand_do_reloc (xtensa_operand, uint32, uint32);
|
||||
extern xtensa_regfile
|
||||
xtensa_operand_regfile (xtensa_isa isa, xtensa_opcode opc, int opnd);
|
||||
|
||||
|
||||
/* Register operands may span multiple consecutive registers, e.g., a
|
||||
64-bit data type may occupy two 32-bit registers. Only the first
|
||||
register is encoded in the operand field. This function specifies
|
||||
the number of consecutive registers occupied by this operand. For
|
||||
non-register operands, the return value is undefined. Returns
|
||||
XTENSA_UNDEFINED on error. */
|
||||
|
||||
extern int
|
||||
xtensa_operand_num_regs (xtensa_isa isa, xtensa_opcode opc, int opnd);
|
||||
|
||||
|
||||
/* Some register operands do not completely identify the register being
|
||||
accessed. For example, the operand value may be added to an internal
|
||||
state value. By definition, this implies that the corresponding
|
||||
regfile is not allocatable. Unknown registers should generally be
|
||||
treated with worst-case assumptions. The function returns 0 if the
|
||||
register value is unknown, 1 if known, and XTENSA_UNDEFINED on
|
||||
error. */
|
||||
|
||||
extern int
|
||||
xtensa_operand_is_known_reg (xtensa_isa isa, xtensa_opcode opc, int opnd);
|
||||
|
||||
|
||||
/* Check if an immediate operand is PC-relative. Returns 0 for register
|
||||
operands and non-PC-relative immediates, 1 for PC-relative
|
||||
immediates, and XTENSA_UNDEFINED on error. */
|
||||
|
||||
extern int
|
||||
xtensa_operand_is_PCrelative (xtensa_isa isa, xtensa_opcode opc, int opnd);
|
||||
|
||||
|
||||
/* For PC-relative offset operands, the interpretation of the offset may
|
||||
vary between opcodes, e.g., is it relative to the current PC or that
|
||||
of the next instruction? The following functions are defined to
|
||||
perform PC-relative relocations and to undo them (as in the
|
||||
disassembler). The "do_reloc" function takes the desired address
|
||||
value and the PC of the current instruction and sets the value to the
|
||||
corresponding PC-relative offset (which can then be encoded and
|
||||
stored into the operand field). The "undo_reloc" function takes the
|
||||
unencoded offset value and the current PC and sets the value to the
|
||||
appropriate address. The return values are non-zero on error. Note
|
||||
that these functions do not replace the encode/decode functions; the
|
||||
operands must be encoded/decoded separately and the encode functions
|
||||
are responsible for detecting invalid operand values. */
|
||||
|
||||
extern int
|
||||
xtensa_operand_do_reloc (xtensa_isa isa, xtensa_opcode opc, int opnd,
|
||||
uint32 *valp, uint32 pc);
|
||||
|
||||
extern int
|
||||
xtensa_operand_undo_reloc (xtensa_isa isa, xtensa_opcode opc, int opnd,
|
||||
uint32 *valp, uint32 pc);
|
||||
|
||||
|
||||
/* State Operands. */
|
||||
|
||||
/* Get the state accessed by a state operand. Returns XTENSA_UNDEFINED
|
||||
on error. */
|
||||
|
||||
extern xtensa_state
|
||||
xtensa_stateOperand_state (xtensa_isa isa, xtensa_opcode opc, int stOp);
|
||||
|
||||
|
||||
/* Check if a state operand is an input ('i'), output ('o'), or inout
|
||||
('m') operand. Returns 0 on error. */
|
||||
|
||||
extern char
|
||||
xtensa_stateOperand_inout (xtensa_isa isa, xtensa_opcode opc, int stOp);
|
||||
|
||||
|
||||
/* Interface Operands. */
|
||||
|
||||
/* Get the external interface accessed by an interface operand.
|
||||
Returns XTENSA_UNDEFINED on error. */
|
||||
|
||||
extern xtensa_interface
|
||||
xtensa_interfaceOperand_interface (xtensa_isa isa, xtensa_opcode opc,
|
||||
int ifOp);
|
||||
|
||||
|
||||
/* Register Files. */
|
||||
|
||||
/* Regfiles include both "real" regfiles and "views", where a view
|
||||
allows a group of adjacent registers in a real "parent" regfile to be
|
||||
viewed as a single register. A regfile view has all the same
|
||||
properties as its parent except for its (long) name, bit width, number
|
||||
of entries, and default ctype. You can use the parent function to
|
||||
distinguish these two classes. */
|
||||
|
||||
/* Look up a regfile by either its name or its abbreviated "short name".
|
||||
Returns XTENSA_UNDEFINED on error. The "lookup_shortname" function
|
||||
ignores "view" regfiles since they always have the same shortname as
|
||||
their parents. */
|
||||
|
||||
extern xtensa_regfile
|
||||
xtensa_regfile_lookup (xtensa_isa isa, const char *name);
|
||||
|
||||
extern xtensa_regfile
|
||||
xtensa_regfile_lookup_shortname (xtensa_isa isa, const char *shortname);
|
||||
|
||||
|
||||
/* Get the name or abbreviated "short name" of a regfile.
|
||||
Returns null on error. */
|
||||
|
||||
extern const char *
|
||||
xtensa_regfile_name (xtensa_isa isa, xtensa_regfile rf);
|
||||
|
||||
extern const char *
|
||||
xtensa_regfile_shortname (xtensa_isa isa, xtensa_regfile rf);
|
||||
|
||||
|
||||
/* Get the parent regfile of a "view" regfile. If the regfile is not a
|
||||
view, the result is the same as the input parameter. Returns
|
||||
XTENSA_UNDEFINED on error. */
|
||||
|
||||
extern xtensa_regfile
|
||||
xtensa_regfile_view_parent (xtensa_isa isa, xtensa_regfile rf);
|
||||
|
||||
|
||||
/* Get the bit width of a regfile or regfile view.
|
||||
Returns XTENSA_UNDEFINED on error. */
|
||||
|
||||
extern int
|
||||
xtensa_regfile_num_bits (xtensa_isa isa, xtensa_regfile rf);
|
||||
|
||||
|
||||
/* Get the number of regfile entries. Returns XTENSA_UNDEFINED on
|
||||
error. */
|
||||
|
||||
extern int
|
||||
xtensa_regfile_num_entries (xtensa_isa isa, xtensa_regfile rf);
|
||||
|
||||
|
||||
/* Processor States. */
|
||||
|
||||
/* Look up a state by name. Returns XTENSA_UNDEFINED on error. */
|
||||
|
||||
extern xtensa_state
|
||||
xtensa_state_lookup (xtensa_isa isa, const char *name);
|
||||
|
||||
|
||||
/* Get the name for a processor state. Returns null on error. */
|
||||
|
||||
extern const char *
|
||||
xtensa_state_name (xtensa_isa isa, xtensa_state st);
|
||||
|
||||
|
||||
/* Get the bit width for a processor state.
|
||||
Returns XTENSA_UNDEFINED on error. */
|
||||
|
||||
extern int
|
||||
xtensa_state_num_bits (xtensa_isa isa, xtensa_state st);
|
||||
|
||||
|
||||
/* Check if a state is exported from the processor core. Returns 0 if
|
||||
the condition is false, 1 if the condition is true, and
|
||||
XTENSA_UNDEFINED on error. */
|
||||
|
||||
extern int
|
||||
xtensa_state_is_exported (xtensa_isa isa, xtensa_state st);
|
||||
|
||||
|
||||
/* Sysregs ("special registers" and "user registers"). */
|
||||
|
||||
/* Look up a register by its number and whether it is a "user register"
|
||||
or a "special register". Returns XTENSA_UNDEFINED if the sysreg does
|
||||
not exist. */
|
||||
|
||||
extern xtensa_sysreg
|
||||
xtensa_sysreg_lookup (xtensa_isa isa, int num, int is_user);
|
||||
|
||||
|
||||
/* Check if there exists a sysreg with a given name.
|
||||
If not, this function returns XTENSA_UNDEFINED. */
|
||||
|
||||
extern xtensa_sysreg
|
||||
xtensa_sysreg_lookup_name (xtensa_isa isa, const char *name);
|
||||
|
||||
|
||||
/* Get the name of a sysreg. Returns null on error. */
|
||||
|
||||
extern const char *
|
||||
xtensa_sysreg_name (xtensa_isa isa, xtensa_sysreg sysreg);
|
||||
|
||||
|
||||
/* Get the register number. Returns XTENSA_UNDEFINED on error. */
|
||||
|
||||
extern int
|
||||
xtensa_sysreg_number (xtensa_isa isa, xtensa_sysreg sysreg);
|
||||
|
||||
|
||||
/* Check if a sysreg is a "special register" or a "user register".
|
||||
Returns 0 for special registers, 1 for user registers and
|
||||
XTENSA_UNDEFINED on error. */
|
||||
|
||||
extern int
|
||||
xtensa_sysreg_is_user (xtensa_isa isa, xtensa_sysreg sysreg);
|
||||
|
||||
|
||||
/* Interfaces. */
|
||||
|
||||
/* Find an interface by name. The return value is XTENSA_UNDEFINED if
|
||||
the specified interface is not found. */
|
||||
|
||||
extern xtensa_interface
|
||||
xtensa_interface_lookup (xtensa_isa isa, const char *ifname);
|
||||
|
||||
|
||||
/* Get the name of an interface. Returns null on error. */
|
||||
|
||||
extern const char *
|
||||
xtensa_interface_name (xtensa_isa isa, xtensa_interface intf);
|
||||
|
||||
|
||||
/* Get the bit width for an interface.
|
||||
Returns XTENSA_UNDEFINED on error. */
|
||||
|
||||
extern int
|
||||
xtensa_interface_num_bits (xtensa_isa isa, xtensa_interface intf);
|
||||
|
||||
|
||||
/* Check if an interface is an input ('i') or output ('o') with respect
|
||||
to the Xtensa processor core. Returns 0 on error. */
|
||||
|
||||
extern char
|
||||
xtensa_interface_inout (xtensa_isa isa, xtensa_interface intf);
|
||||
|
||||
|
||||
/* Check if accessing an interface has potential side effects.
|
||||
Currently "data" interfaces have side effects and "control"
|
||||
interfaces do not. Returns 1 if there are side effects, 0 if not,
|
||||
and XTENSA_UNDEFINED on error. */
|
||||
|
||||
extern int
|
||||
xtensa_interface_has_side_effect (xtensa_isa isa, xtensa_interface intf);
|
||||
|
||||
|
||||
/* Functional Units. */
|
||||
|
||||
/* Find a functional unit by name. The return value is XTENSA_UNDEFINED if
|
||||
the specified unit is not found. */
|
||||
|
||||
extern xtensa_funcUnit
|
||||
xtensa_funcUnit_lookup (xtensa_isa isa, const char *fname);
|
||||
|
||||
|
||||
/* Get the name of a functional unit. Returns null on error. */
|
||||
|
||||
extern const char *
|
||||
xtensa_funcUnit_name (xtensa_isa isa, xtensa_funcUnit fun);
|
||||
|
||||
|
||||
/* Functional units may be replicated. See how many instances of a
|
||||
particular function unit exist. Returns XTENSA_UNDEFINED on error. */
|
||||
|
||||
extern int
|
||||
xtensa_funcUnit_num_copies (xtensa_isa isa, xtensa_funcUnit fun);
|
||||
|
||||
extern uint32 xtensa_operand_undo_reloc (xtensa_operand, uint32, uint32);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
|
||||
21
ld/ChangeLog
21
ld/ChangeLog
@ -1,3 +1,24 @@
|
||||
2004-10-07 Bob Wilson <bob.wilson@acm.org>
|
||||
|
||||
* ld.texinfo (Xtensa): Describe new linker relaxation to optimize
|
||||
assembler-generated longcall sequences. Describe new --size-opt
|
||||
option.
|
||||
* emulparams/elf32xtensa.sh (OTHER_SECTIONS): Add .xt.prop section.
|
||||
* emultempl/xtensaelf.em (remove_section,
|
||||
replace_insn_sec_with_prop_sec, replace_instruction_table_sections,
|
||||
elf_xtensa_after_open): New.
|
||||
(OPTION_OPT_SIZEOPT, OPTION_LITERAL_MOVEMENT,
|
||||
OPTION_NO_LITERAL_MOVEMENT): Define.
|
||||
(elf32xtensa_size_opt, elf32xtensa_no_literal_movement): New globals.
|
||||
(PARSE_AND_LIST_LONGOPTS): Add size-opt and [no-]literal-movement.
|
||||
(PARSE_AND_LIST_OPTIONS): Add --size-opt.
|
||||
(PARSE_AND_LIST_ARGS_CASES): Handle OPTION_OPT_SIZEOPT,
|
||||
OPTION_LITERAL_MOVEMENT, and OPTION_NO_LITERAL_MOVEMENT.
|
||||
(LDEMUL_AFTER_OPEN): Set to elf_xtensa_after_open.
|
||||
* scripttempl/elfxtensa.sc: Update with changes from elf.sc.
|
||||
* Makefile.am (eelf32xtensa.c): Update dependencies.
|
||||
* Makefile.in: Regenerate.
|
||||
|
||||
2004-10-07 Jeff Baker <jbaker@qnx.com>
|
||||
|
||||
* lexsup.c: Handle --warn-shared-textrel option.
|
||||
|
||||
@ -609,8 +609,9 @@ eelf32vax.c: $(srcdir)/emulparams/elf32vax.sh \
|
||||
$(srcdir)/emultempl/elf32.em $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS}
|
||||
${GENSCRIPTS} elf32vax "$(tdir_elf32vax)"
|
||||
eelf32xtensa.c: $(srcdir)/emulparams/elf32xtensa.sh \
|
||||
$(srcdir)/emulparams/xtensa-config.sh \
|
||||
$(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/xtensaelf.em \
|
||||
$(srcdir)/emulparams/xtensa-config.sh $(srcdir)/emultempl/elf32.em \
|
||||
$(srcdir)/emultempl/xtensaelf.em $(INCDIR)/xtensa-config.h \
|
||||
$(BFDDIR)/elf-bfd.h $(BFDDIR)/libbfd.h $(INCDIR)/elf/xtensa.h \
|
||||
$(srcdir)/scripttempl/elfxtensa.sc ${GEN_DEPENDS}
|
||||
${GENSCRIPTS} elf32xtensa "$(tdir_elf32xtensa)"
|
||||
eelf32fr30.c: $(srcdir)/emulparams/elf32fr30.sh \
|
||||
|
||||
@ -1346,8 +1346,9 @@ eelf32vax.c: $(srcdir)/emulparams/elf32vax.sh \
|
||||
$(srcdir)/emultempl/elf32.em $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS}
|
||||
${GENSCRIPTS} elf32vax "$(tdir_elf32vax)"
|
||||
eelf32xtensa.c: $(srcdir)/emulparams/elf32xtensa.sh \
|
||||
$(srcdir)/emulparams/xtensa-config.sh \
|
||||
$(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/xtensaelf.em \
|
||||
$(srcdir)/emulparams/xtensa-config.sh $(srcdir)/emultempl/elf32.em \
|
||||
$(srcdir)/emultempl/xtensaelf.em $(INCDIR)/xtensa-config.h \
|
||||
$(BFDDIR)/elf-bfd.h $(BFDDIR)/libbfd.h $(INCDIR)/elf/xtensa.h \
|
||||
$(srcdir)/scripttempl/elfxtensa.sc ${GEN_DEPENDS}
|
||||
${GENSCRIPTS} elf32xtensa "$(tdir_elf32xtensa)"
|
||||
eelf32fr30.c: $(srcdir)/emulparams/elf32fr30.sh \
|
||||
|
||||
@ -29,4 +29,5 @@ OTHER_READWRITE_SECTIONS="
|
||||
OTHER_SECTIONS="
|
||||
.xt.lit 0 : { *(.xt.lit${RELOCATING+ .xt.lit.* .gnu.linkonce.p.*}) }
|
||||
.xt.insn 0 : { *(.xt.insn${RELOCATING+ .gnu.linkonce.x.*}) }
|
||||
.xt.prop 0 : { *(.xt.prop${RELOCATING+ .gnu.linkonce.prop.*}) }
|
||||
"
|
||||
|
||||
@ -25,9 +25,17 @@
|
||||
cat >>e${EMULATION_NAME}.c <<EOF
|
||||
|
||||
#include <xtensa-config.h>
|
||||
#include "../bfd/elf-bfd.h"
|
||||
#include "../bfd/libbfd.h"
|
||||
#include "elf/xtensa.h"
|
||||
#include "bfd.h"
|
||||
|
||||
static void xtensa_wild_group_interleave (lang_statement_union_type *);
|
||||
static void xtensa_colocate_output_literals (lang_statement_union_type *);
|
||||
static void remove_section (bfd *, asection *);
|
||||
static bfd_boolean replace_insn_sec_with_prop_sec (bfd *, const char *,
|
||||
const char *, char **);
|
||||
static void replace_instruction_table_sections (bfd *, asection *);
|
||||
|
||||
|
||||
/* Flag for the emulation-specific "--no-relax" option. */
|
||||
@ -37,7 +45,7 @@ static bfd_boolean disable_relaxation = FALSE;
|
||||
static bfd_vma xtensa_page_power = 12; /* 4K pages. */
|
||||
|
||||
/* To force a page break between literals and text, change
|
||||
xtensa_use_literal_pages to "true". */
|
||||
xtensa_use_literal_pages to "TRUE". */
|
||||
static bfd_boolean xtensa_use_literal_pages = FALSE;
|
||||
|
||||
#define EXTRA_VALIDATION 0
|
||||
@ -74,6 +82,266 @@ elf_xtensa_before_parse (void)
|
||||
}
|
||||
|
||||
|
||||
void
|
||||
remove_section (abfd, os)
|
||||
bfd *abfd;
|
||||
asection *os;
|
||||
{
|
||||
asection **spp;
|
||||
for (spp = &abfd->sections; *spp; spp = &(*spp)->next)
|
||||
if (*spp == os)
|
||||
{
|
||||
*spp = os->next;
|
||||
os->owner->section_count--;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
bfd_boolean
|
||||
replace_insn_sec_with_prop_sec (abfd, insn_sec_name, prop_sec_name,
|
||||
error_message)
|
||||
bfd *abfd;
|
||||
const char *insn_sec_name;
|
||||
const char *prop_sec_name;
|
||||
char **error_message;
|
||||
{
|
||||
asection *insn_sec;
|
||||
asection *prop_sec;
|
||||
bfd_byte *prop_contents = NULL;
|
||||
bfd_byte *insn_contents = NULL;
|
||||
unsigned entry_count;
|
||||
unsigned entry;
|
||||
Elf_Internal_Shdr *symtab_hdr;
|
||||
Elf_Internal_Rela *internal_relocs = NULL;
|
||||
unsigned reloc_count;
|
||||
|
||||
*error_message = "";
|
||||
insn_sec = bfd_get_section_by_name (abfd, insn_sec_name);
|
||||
if (insn_sec == NULL)
|
||||
return TRUE;
|
||||
entry_count = insn_sec->size / 8;
|
||||
|
||||
prop_sec = bfd_get_section_by_name (abfd, prop_sec_name);
|
||||
if (prop_sec != NULL && insn_sec != NULL)
|
||||
{
|
||||
*error_message = _("file already has property tables");
|
||||
return FALSE;
|
||||
}
|
||||
|
||||
if (insn_sec->size != 0)
|
||||
{
|
||||
insn_contents = (bfd_byte *) bfd_malloc (insn_sec->size);
|
||||
if (insn_contents == NULL)
|
||||
{
|
||||
*error_message = _("out of memory");
|
||||
goto cleanup;
|
||||
}
|
||||
if (! bfd_get_section_contents (abfd, insn_sec, insn_contents,
|
||||
(file_ptr) 0, insn_sec->size))
|
||||
{
|
||||
*error_message = _("failed to read section contents");
|
||||
goto cleanup;
|
||||
}
|
||||
}
|
||||
|
||||
/* Create a Property table section and relocation section for it. */
|
||||
prop_sec_name = strdup (prop_sec_name);
|
||||
prop_sec = bfd_make_section (abfd, prop_sec_name);
|
||||
if (prop_sec == NULL
|
||||
|| ! bfd_set_section_flags (abfd, prop_sec,
|
||||
bfd_get_section_flags (abfd, insn_sec))
|
||||
|| ! bfd_set_section_alignment (abfd, prop_sec, 2))
|
||||
{
|
||||
*error_message = _("could not create new section");
|
||||
goto cleanup;
|
||||
}
|
||||
|
||||
if (! bfd_set_section_flags (abfd, prop_sec,
|
||||
bfd_get_section_flags (abfd, insn_sec))
|
||||
|| ! bfd_set_section_alignment (abfd, prop_sec, 2))
|
||||
{
|
||||
*error_message = _("could not set new section properties");
|
||||
goto cleanup;
|
||||
}
|
||||
prop_sec->size = entry_count * 12;
|
||||
prop_contents = (bfd_byte *) bfd_zalloc (abfd, prop_sec->size);
|
||||
elf_section_data (prop_sec)->this_hdr.contents = prop_contents;
|
||||
|
||||
/* The entry size and size must be set to allow the linker to compute
|
||||
the number of relocations since it does not use reloc_count. */
|
||||
elf_section_data (prop_sec)->rel_hdr.sh_entsize =
|
||||
sizeof (Elf32_External_Rela);
|
||||
elf_section_data (prop_sec)->rel_hdr.sh_size =
|
||||
elf_section_data (insn_sec)->rel_hdr.sh_size;
|
||||
|
||||
if (prop_contents == NULL && prop_sec->size != 0)
|
||||
{
|
||||
*error_message = _("could not allocate section contents");
|
||||
goto cleanup;
|
||||
}
|
||||
|
||||
/* Read the relocations. */
|
||||
reloc_count = insn_sec->reloc_count;
|
||||
if (reloc_count != 0)
|
||||
{
|
||||
/* If there is already an internal_reloc, then save it so that the
|
||||
read_relocs function freshly allocates a copy. */
|
||||
Elf_Internal_Rela *saved_relocs = elf_section_data (insn_sec)->relocs;
|
||||
|
||||
elf_section_data (insn_sec)->relocs = NULL;
|
||||
internal_relocs =
|
||||
_bfd_elf_link_read_relocs (abfd, insn_sec, NULL, NULL, FALSE);
|
||||
elf_section_data (insn_sec)->relocs = saved_relocs;
|
||||
|
||||
if (internal_relocs == NULL)
|
||||
{
|
||||
*error_message = _("out of memory");
|
||||
goto cleanup;
|
||||
}
|
||||
}
|
||||
|
||||
/* Create a relocation section for the property section. */
|
||||
if (internal_relocs != NULL)
|
||||
{
|
||||
elf_section_data (prop_sec)->relocs = internal_relocs;
|
||||
prop_sec->reloc_count = reloc_count;
|
||||
}
|
||||
|
||||
/* Now copy each insn table entry to the prop table entry with
|
||||
appropriate flags. */
|
||||
for (entry = 0; entry < entry_count; ++entry)
|
||||
{
|
||||
unsigned value;
|
||||
unsigned flags = (XTENSA_PROP_INSN | XTENSA_PROP_INSN_NO_TRANSFORM
|
||||
| XTENSA_PROP_INSN_NO_REORDER);
|
||||
value = bfd_get_32 (abfd, insn_contents + entry * 8 + 0);
|
||||
bfd_put_32 (abfd, value, prop_contents + entry * 12 + 0);
|
||||
value = bfd_get_32 (abfd, insn_contents + entry * 8 + 4);
|
||||
bfd_put_32 (abfd, value, prop_contents + entry * 12 + 4);
|
||||
bfd_put_32 (abfd, flags, prop_contents + entry * 12 + 8);
|
||||
}
|
||||
|
||||
/* Now copy all of the relocations. Change offsets for the
|
||||
instruction table section to offsets in the property table
|
||||
section. */
|
||||
if (internal_relocs)
|
||||
{
|
||||
unsigned i;
|
||||
symtab_hdr = &elf_tdata (abfd)->symtab_hdr;
|
||||
|
||||
for (i = 0; i < reloc_count; i++)
|
||||
{
|
||||
Elf_Internal_Rela *rela;
|
||||
unsigned r_offset;
|
||||
|
||||
rela = &internal_relocs[i];
|
||||
|
||||
/* If this relocation is to the .xt.insn section,
|
||||
change the section number and the offset. */
|
||||
r_offset = rela->r_offset;
|
||||
r_offset += 4 * (r_offset / 8);
|
||||
rela->r_offset = r_offset;
|
||||
}
|
||||
}
|
||||
|
||||
remove_section (abfd, insn_sec);
|
||||
|
||||
if (insn_contents)
|
||||
free (insn_contents);
|
||||
|
||||
return TRUE;
|
||||
|
||||
cleanup:
|
||||
if (prop_sec && prop_sec->owner)
|
||||
remove_section (abfd, prop_sec);
|
||||
if (insn_contents)
|
||||
free (insn_contents);
|
||||
if (internal_relocs)
|
||||
free (internal_relocs);
|
||||
|
||||
return FALSE;
|
||||
}
|
||||
|
||||
|
||||
#define PROP_SEC_BASE_NAME ".xt.prop"
|
||||
#define INSN_SEC_BASE_NAME ".xt.insn"
|
||||
#define LINKONCE_SEC_OLD_TEXT_BASE_NAME ".gnu.linkonce.x."
|
||||
|
||||
|
||||
void
|
||||
replace_instruction_table_sections (abfd, sec)
|
||||
bfd *abfd;
|
||||
asection *sec;
|
||||
{
|
||||
char *message = "";
|
||||
const char *insn_sec_name = NULL;
|
||||
char *prop_sec_name = NULL;
|
||||
char *owned_prop_sec_name = NULL;
|
||||
const char *sec_name;
|
||||
|
||||
sec_name = bfd_get_section_name (abfd, sec);
|
||||
if (strcmp (sec_name, INSN_SEC_BASE_NAME) == 0)
|
||||
{
|
||||
insn_sec_name = INSN_SEC_BASE_NAME;
|
||||
prop_sec_name = PROP_SEC_BASE_NAME;
|
||||
}
|
||||
else if (strncmp (sec_name, LINKONCE_SEC_OLD_TEXT_BASE_NAME,
|
||||
strlen (LINKONCE_SEC_OLD_TEXT_BASE_NAME)) == 0)
|
||||
{
|
||||
insn_sec_name = sec_name;
|
||||
owned_prop_sec_name = (char *) xmalloc (strlen (sec_name) + 20);
|
||||
prop_sec_name = owned_prop_sec_name;
|
||||
strcpy (prop_sec_name, ".gnu.linkonce.prop.t.");
|
||||
strcat (prop_sec_name,
|
||||
sec_name + strlen (LINKONCE_SEC_OLD_TEXT_BASE_NAME));
|
||||
}
|
||||
if (insn_sec_name != NULL)
|
||||
{
|
||||
if (! replace_insn_sec_with_prop_sec (abfd, insn_sec_name, prop_sec_name,
|
||||
&message))
|
||||
{
|
||||
einfo (_("%P: warning: failed to convert %s table in %B (%s); subsequent disassembly may be incomplete\n"),
|
||||
insn_sec_name, abfd, message);
|
||||
}
|
||||
}
|
||||
if (owned_prop_sec_name)
|
||||
free (owned_prop_sec_name);
|
||||
}
|
||||
|
||||
|
||||
/* This is called after all input sections have been opened to convert
|
||||
instruction tables (.xt.insn, gnu.linkonce.x.*) tables into property
|
||||
tables (.xt.prop) before any section placement. */
|
||||
|
||||
static void
|
||||
elf_xtensa_after_open (void)
|
||||
{
|
||||
bfd *abfd;
|
||||
|
||||
/* First call the ELF version. */
|
||||
gld${EMULATION_NAME}_after_open ();
|
||||
|
||||
/* Now search the input files looking for instruction table sections. */
|
||||
for (abfd = link_info.input_bfds;
|
||||
abfd != NULL;
|
||||
abfd = abfd->link_next)
|
||||
{
|
||||
asection *sec = abfd->sections;
|
||||
asection *next_sec;
|
||||
|
||||
/* Do not use bfd_map_over_sections here since we are removing
|
||||
sections as we iterate. */
|
||||
while (sec != NULL)
|
||||
{
|
||||
next_sec = sec->next;
|
||||
replace_instruction_table_sections (abfd, sec);
|
||||
sec = next_sec;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/* This is called after the sections have been attached to output
|
||||
sections, but before any sizes or addresses have been set. */
|
||||
|
||||
@ -443,7 +711,7 @@ ld_xtensa_move_section_after (xtensa_ld_iter *to, xtensa_ld_iter *current)
|
||||
|
||||
|
||||
/* Can only be called with lang_statements that have lists. Returns
|
||||
false if the list is empty. */
|
||||
FALSE if the list is empty. */
|
||||
|
||||
static bfd_boolean
|
||||
iter_stack_empty (xtensa_ld_iter_stack **stack_p)
|
||||
@ -1443,30 +1711,49 @@ ld_xtensa_insert_page_offsets (bfd_vma dot,
|
||||
|
||||
EOF
|
||||
|
||||
# Define some shell vars to insert bits of code into the standard elf
|
||||
# Define some shell vars to insert bits of code into the standard ELF
|
||||
# parse_args and list_options functions.
|
||||
#
|
||||
PARSE_AND_LIST_PROLOGUE='
|
||||
#define OPTION_NO_RELAX 301
|
||||
#define OPTION_OPT_SIZEOPT (300)
|
||||
#define OPTION_NO_RELAX (OPTION_OPT_SIZEOPT + 1)
|
||||
#define OPTION_LITERAL_MOVEMENT (OPTION_NO_RELAX + 1)
|
||||
#define OPTION_NO_LITERAL_MOVEMENT (OPTION_LITERAL_MOVEMENT + 1)
|
||||
extern int elf32xtensa_size_opt;
|
||||
extern int elf32xtensa_no_literal_movement;
|
||||
'
|
||||
|
||||
PARSE_AND_LIST_LONGOPTS='
|
||||
{ "size-opt", no_argument, NULL, OPTION_OPT_SIZEOPT},
|
||||
{ "no-relax", no_argument, NULL, OPTION_NO_RELAX},
|
||||
{ "literal-movement", no_argument, NULL, OPTION_LITERAL_MOVEMENT},
|
||||
{ "no-literal-movement", no_argument, NULL, OPTION_NO_LITERAL_MOVEMENT},
|
||||
'
|
||||
|
||||
PARSE_AND_LIST_OPTIONS='
|
||||
fprintf (file, _(" --size-opt\t\tWhen relaxing longcalls, prefer size optimization\n\t\t\t over branch target alignment\n"));
|
||||
fprintf (file, _(" --no-relax\t\tDo not relax branches or coalesce literals\n"));
|
||||
'
|
||||
|
||||
PARSE_AND_LIST_ARGS_CASES='
|
||||
case OPTION_OPT_SIZEOPT:
|
||||
elf32xtensa_size_opt = 1;
|
||||
break;
|
||||
case OPTION_NO_RELAX:
|
||||
disable_relaxation = TRUE;
|
||||
break;
|
||||
case OPTION_LITERAL_MOVEMENT:
|
||||
elf32xtensa_no_literal_movement = 0;
|
||||
break;
|
||||
case OPTION_NO_LITERAL_MOVEMENT:
|
||||
elf32xtensa_no_literal_movement = 1;
|
||||
break;
|
||||
'
|
||||
|
||||
# Replace some of the standard ELF functions with our own versions.
|
||||
#
|
||||
LDEMUL_BEFORE_PARSE=elf_xtensa_before_parse
|
||||
LDEMUL_AFTER_OPEN=elf_xtensa_after_open
|
||||
LDEMUL_CHOOSE_TARGET=elf_xtensa_choose_target
|
||||
LDEMUL_PLACE_ORPHAN=elf_xtensa_place_orphan
|
||||
LDEMUL_BEFORE_ALLOCATION=elf_xtensa_before_allocation
|
||||
|
||||
@ -5552,34 +5552,53 @@ interleaving might place the @code{.literal} sections from an initial
|
||||
group of files followed by the @code{.text} sections of that group of
|
||||
files. Then, the @code{.literal} sections from the rest of the files
|
||||
and the @code{.text} sections from the rest of the files would follow.
|
||||
The non-interleaved order can still be specified as:
|
||||
|
||||
@smallexample
|
||||
SECTIONS
|
||||
@{
|
||||
.text : @{
|
||||
*(.literal) *(.text)
|
||||
@}
|
||||
@}
|
||||
@end smallexample
|
||||
|
||||
@cindex @code{--relax} on Xtensa
|
||||
@cindex @option{--relax} on Xtensa
|
||||
@cindex relaxing on Xtensa
|
||||
@kindex --no-relax
|
||||
The Xtensa version of @command{ld} enables the @option{--relax} option by
|
||||
default to attempt to reduce space in the output image by combining
|
||||
literals with identical values. It also provides the
|
||||
@option{--no-relax} option to disable this optimization. When enabled,
|
||||
the relaxation algorithm ensures that a literal will only be merged with
|
||||
another literal when the new merged literal location is within the
|
||||
offset range of all of its uses.
|
||||
Relaxation is enabled by default for the Xtensa version of @command{ld} and
|
||||
provides two important link-time optimizations. The first optimization
|
||||
is to combine identical literal values to reduce code size. A redundant
|
||||
literal will be removed and all the @code{L32R} instructions that use it
|
||||
will be changed to reference an identical literal, as long as the
|
||||
location of the replacement literal is within the offset range of all
|
||||
the @code{L32R} instructions. The second optimization is to remove
|
||||
unnecessary overhead from assembler-generated ``longcall'' sequences of
|
||||
@code{L32R}/@code{CALLX@var{n}} when the target functions are within
|
||||
range of direct @code{CALL@var{n}} instructions.
|
||||
|
||||
The relaxation mechanism will also attempt to optimize
|
||||
assembler-generated ``longcall'' sequences of
|
||||
@code{L32R}/@code{CALLX@var{n}} when the target is known to fit into a
|
||||
@code{CALL@var{n}} instruction encoding. The current optimization
|
||||
converts the sequence into @code{NOP}/@code{CALL@var{n}} and removes the
|
||||
literal referenced by the @code{L32R} instruction.
|
||||
For each of these cases where an indirect call sequence can be optimized
|
||||
to a direct call, the linker will change the @code{CALLX@var{n}}
|
||||
instruction to a @code{CALL@var{n}} instruction, remove the @code{L32R}
|
||||
instruction, and remove the literal referenced by the @code{L32R}
|
||||
instruction if it is not used for anything else. Removing the
|
||||
@code{L32R} instruction always reduces code size but can potentially
|
||||
hurt performance by changing the alignment of subsequent branch targets.
|
||||
By default, the linker will always preserve alignments, either by
|
||||
switching some instructions between 24-bit encodings and the equivalent
|
||||
density instructions or by inserting a no-op in place of the @code{L32R}
|
||||
instruction that was removed. If code size is more important than
|
||||
performance, the @option{--size-opt} option can be used to prevent the
|
||||
linker from widening density instructions or inserting no-ops, except in
|
||||
a few cases where no-ops are required for correctness.
|
||||
|
||||
The following Xtensa-specific command-line options can be used to
|
||||
control the linker:
|
||||
|
||||
@cindex Xtensa options
|
||||
@table @option
|
||||
@kindex --no-relax
|
||||
@item --no-relax
|
||||
Since the Xtensa version of @code{ld} enables the @option{--relax} option
|
||||
by default, the @option{--no-relax} option is provided to disable
|
||||
relaxation.
|
||||
|
||||
@item --size-opt
|
||||
When optimizing indirect calls to direct calls, optimize for code size
|
||||
more than performance. With this option, the linker will not insert
|
||||
no-ops or widen density instructions to preserve branch target
|
||||
alignment. There may still be some cases where no-ops are required to
|
||||
preserve the correctness of the code.
|
||||
@end table
|
||||
|
||||
@ifclear GENERIC
|
||||
@lowersections
|
||||
|
||||
@ -10,6 +10,8 @@
|
||||
# OTHER_TEXT_SECTIONS - these get put in .text when relocating
|
||||
# OTHER_READWRITE_SECTIONS - other than .data .bss .ctors .sdata ...
|
||||
# (e.g., .PARISC.global)
|
||||
# OTHER_RELRO_SECTIONS - other than .data.rel.ro ...
|
||||
# (e.g. PPC32 .fixup, .got[12])
|
||||
# OTHER_BSS_SECTIONS - other than .bss .sbss ...
|
||||
# OTHER_SECTIONS - at the end
|
||||
# EXECUTABLE_SYMBOLS - symbols that must be defined for an
|
||||
@ -67,17 +69,24 @@ test -z "$ENTRY" && ENTRY=_start
|
||||
test -z "${ELFSIZE}" && ELFSIZE=32
|
||||
test -z "${ALIGNMENT}" && ALIGNMENT="${ELFSIZE} / 8"
|
||||
test "$LD_FLAG" = "N" && DATA_ADDR=.
|
||||
test -n "$CREATE_SHLIB" && test -n "$SHLIB_DATA_ADDR" && COMMONPAGESIZE=""
|
||||
test -z "$CREATE_SHLIB" && test -n "$DATA_ADDR" && COMMONPAGESIZE=""
|
||||
test -n "$CREATE_SHLIB$CREATE_PIE" && test -n "$SHLIB_DATA_ADDR" && COMMONPAGESIZE=""
|
||||
test -z "$CREATE_SHLIB$CREATE_PIE" && test -n "$DATA_ADDR" && COMMONPAGESIZE=""
|
||||
DATA_SEGMENT_ALIGN="ALIGN(${SEGMENT_SIZE}) + (. & (${MAXPAGESIZE} - 1))"
|
||||
DATA_SEGMENT_RELRO_END=""
|
||||
DATA_SEGMENT_END=""
|
||||
if test -n "${COMMONPAGESIZE}"; then
|
||||
DATA_SEGMENT_ALIGN="ALIGN (${SEGMENT_SIZE}) - ((${MAXPAGESIZE} - .) & (${MAXPAGESIZE} - 1)); . = DATA_SEGMENT_ALIGN (${MAXPAGESIZE}, ${COMMONPAGESIZE})"
|
||||
DATA_SEGMENT_END=". = DATA_SEGMENT_END (.);"
|
||||
DATA_SEGMENT_RELRO_END=". = DATA_SEGMENT_RELRO_END (.);"
|
||||
fi
|
||||
INTERP=".interp ${RELOCATING-0} : { *(.interp) }"
|
||||
if test -z "$GOT"; then
|
||||
GOT=".got ${RELOCATING-0} : { *(.got) }"
|
||||
fi
|
||||
DYNAMIC=".dynamic ${RELOCATING-0} : { *(.dynamic) }"
|
||||
RODATA=".rodata ${RELOCATING-0} : { *(.rodata${RELOCATING+ .rodata.* .gnu.linkonce.r.*}) }"
|
||||
DATARELRO=".data.rel.ro : { *(.data.rel.ro.local) *(.data.rel.ro*) }"
|
||||
STACKNOTE="/DISCARD/ : { *(.note.GNU-stack) }"
|
||||
INIT_LIT=".init.literal 0 : { *(.init.literal) }"
|
||||
INIT=".init 0 : { *(.init) }"
|
||||
FINI_LIT=".fini.literal 0 : { *(.fini.literal) }"
|
||||
@ -111,6 +120,8 @@ if test -z "${NO_SMALL_DATA}"; then
|
||||
.rela.sdata2 ${RELOCATING-0} : { *(.rela.sdata2${RELOCATING+ .rela.sdata2.* .rela.gnu.linkonce.s2.*}) }"
|
||||
REL_SBSS2=".rel.sbss2 ${RELOCATING-0} : { *(.rel.sbss2${RELOCATING+ .rel.sbss2.* .rel.gnu.linkonce.sb2.*}) }
|
||||
.rela.sbss2 ${RELOCATING-0} : { *(.rela.sbss2${RELOCATING+ .rela.sbss2.* .rela.gnu.linkonce.sb2.*}) }"
|
||||
else
|
||||
NO_SMALL_DATA=" "
|
||||
fi
|
||||
CTOR=".ctors ${CONSTRUCTING-0} :
|
||||
{
|
||||
@ -175,8 +186,9 @@ ${RELOCATING- /* For some reason, the Solaris linker makes bad executables
|
||||
SECTIONS
|
||||
{
|
||||
/* Read-only sections, merged into text segment: */
|
||||
${CREATE_SHLIB-${RELOCATING+. = ${TEXT_BASE_ADDRESS};}}
|
||||
${CREATE_SHLIB-${CREATE_PIE-${RELOCATING+PROVIDE (__executable_start = ${TEXT_START_ADDR}); . = ${TEXT_BASE_ADDRESS};}}}
|
||||
${CREATE_SHLIB+${RELOCATING+. = ${SHLIB_TEXT_START_ADDR:-0} + SIZEOF_HEADERS;}}
|
||||
${CREATE_PIE+${RELOCATING+. = ${SHLIB_TEXT_START_ADDR:-0} + SIZEOF_HEADERS;}}
|
||||
${CREATE_SHLIB-${INTERP}}
|
||||
${INITIAL_READONLY_SECTIONS}
|
||||
${TEXT_DYNAMIC+${DYNAMIC}}
|
||||
@ -203,6 +215,8 @@ eval $COMBRELOCCAT <<EOF
|
||||
.rel.rodata ${RELOCATING-0} : { *(.rel.rodata${RELOCATING+ .rel.rodata.* .rel.gnu.linkonce.r.*}) }
|
||||
.rela.rodata ${RELOCATING-0} : { *(.rela.rodata${RELOCATING+ .rela.rodata.* .rela.gnu.linkonce.r.*}) }
|
||||
${OTHER_READONLY_RELOC_SECTIONS}
|
||||
.rel.data.rel.ro ${RELOCATING-0} : { *(.rel.data.rel.ro${RELOCATING+*}) }
|
||||
.rela.data.rel.ro ${RELOCATING-0} : { *(.rel.data.rel.ro${RELOCATING+*}) }
|
||||
.rel.data ${RELOCATING-0} : { *(.rel.data${RELOCATING+ .rel.data.* .rel.gnu.linkonce.d.*}) }
|
||||
.rela.data ${RELOCATING-0} : { *(.rela.data${RELOCATING+ .rela.data.* .rela.gnu.linkonce.d.*}) }
|
||||
.rel.tdata ${RELOCATING-0} : { *(.rel.tdata${RELOCATING+ .rel.tdata.* .rel.gnu.linkonce.td.*}) }
|
||||
@ -257,7 +271,8 @@ cat <<EOF
|
||||
${RELOCATING+${INIT_END}}
|
||||
|
||||
${RELOCATING+${TEXT_START_SYMBOLS}}
|
||||
*(.literal .text .stub${RELOCATING+ .text.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*})
|
||||
*(.literal .text .stub${RELOCATING+ .text.* .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*})
|
||||
KEEP (*(.text.*personality*))
|
||||
/* .gnu.warning sections are handled specially by elf32.em. */
|
||||
*(.gnu.warning)
|
||||
${RELOCATING+${OTHER_TEXT_SECTIONS}}
|
||||
@ -280,11 +295,22 @@ cat <<EOF
|
||||
${CREATE_SHLIB-${SBSS2}}
|
||||
${OTHER_READONLY_SECTIONS}
|
||||
.eh_frame_hdr : { *(.eh_frame_hdr) }
|
||||
.eh_frame ${RELOCATING-0} : ONLY_IF_RO { KEEP (*(.eh_frame)) }
|
||||
.gcc_except_table ${RELOCATING-0} : ONLY_IF_RO { KEEP (*(.gcc_except_table)) *(.gcc_except_table.*) }
|
||||
|
||||
/* Adjust the address for the data segment. We want to adjust up to
|
||||
the same address within the page on the next page up. */
|
||||
${CREATE_SHLIB-${RELOCATING+. = ${DATA_ADDR-${DATA_SEGMENT_ALIGN}};}}
|
||||
${CREATE_SHLIB-${CREATE_PIE-${RELOCATING+. = ${DATA_ADDR-${DATA_SEGMENT_ALIGN}};}}}
|
||||
${CREATE_SHLIB+${RELOCATING+. = ${SHLIB_DATA_ADDR-${DATA_SEGMENT_ALIGN}};}}
|
||||
${CREATE_PIE+${RELOCATING+. = ${SHLIB_DATA_ADDR-${DATA_SEGMENT_ALIGN}};}}
|
||||
|
||||
/* Exception handling */
|
||||
.eh_frame ${RELOCATING-0} : ONLY_IF_RW { KEEP (*(.eh_frame)) }
|
||||
.gcc_except_table ${RELOCATING-0} : ONLY_IF_RW { KEEP (*(.gcc_except_table)) *(.gcc_except_table.*) }
|
||||
|
||||
/* Thread Local Storage sections */
|
||||
.tdata ${RELOCATING-0} : { *(.tdata${RELOCATING+ .tdata.* .gnu.linkonce.td.*}) }
|
||||
.tbss ${RELOCATING-0} : { *(.tbss${RELOCATING+ .tbss.* .gnu.linkonce.tb.*})${RELOCATING+ *(.tcommon)} }
|
||||
|
||||
/* Ensure the __preinit_array_start label is properly aligned. We
|
||||
could instead move the label definition inside the section, but
|
||||
@ -292,36 +318,39 @@ cat <<EOF
|
||||
be empty, which isn't pretty. */
|
||||
${RELOCATING+. = ALIGN(${ALIGNMENT});}
|
||||
${RELOCATING+${CREATE_SHLIB-PROVIDE (__preinit_array_start = .);}}
|
||||
.preinit_array ${RELOCATING-0} : { *(.preinit_array) }
|
||||
.preinit_array ${RELOCATING-0} : { KEEP (*(.preinit_array)) }
|
||||
${RELOCATING+${CREATE_SHLIB-PROVIDE (__preinit_array_end = .);}}
|
||||
|
||||
${RELOCATING+${CREATE_SHLIB-PROVIDE (__init_array_start = .);}}
|
||||
.init_array ${RELOCATING-0} : { *(.init_array) }
|
||||
.init_array ${RELOCATING-0} : { KEEP (*(.init_array)) }
|
||||
${RELOCATING+${CREATE_SHLIB-PROVIDE (__init_array_end = .);}}
|
||||
|
||||
${RELOCATING+${CREATE_SHLIB-PROVIDE (__fini_array_start = .);}}
|
||||
.fini_array ${RELOCATING-0} : { *(.fini_array) }
|
||||
.fini_array ${RELOCATING-0} : { KEEP (*(.fini_array)) }
|
||||
${RELOCATING+${CREATE_SHLIB-PROVIDE (__fini_array_end = .);}}
|
||||
|
||||
${RELOCATING+${CTOR}}
|
||||
${RELOCATING+${DTOR}}
|
||||
.jcr ${RELOCATING-0} : { KEEP (*(.jcr)) }
|
||||
|
||||
${RELOCATING+${DATARELRO}}
|
||||
${OTHER_RELRO_SECTIONS}
|
||||
${TEXT_DYNAMIC-${DYNAMIC}}
|
||||
${NO_SMALL_DATA+${GOT}}
|
||||
${RELOCATING+${DATA_SEGMENT_RELRO_END}}
|
||||
|
||||
.data ${RELOCATING-0} :
|
||||
{
|
||||
${RELOCATING+${DATA_START_SYMBOLS}}
|
||||
*(.data${RELOCATING+ .data.* .gnu.linkonce.d.*})
|
||||
KEEP (*(.gnu.linkonce.d.*personality*))
|
||||
${CONSTRUCTING+SORT(CONSTRUCTORS)}
|
||||
}
|
||||
.data1 ${RELOCATING-0} : { *(.data1) }
|
||||
.tdata ${RELOCATING-0} : { *(.tdata${RELOCATING+ .tdata.* .gnu.linkonce.td.*}) }
|
||||
.tbss ${RELOCATING-0} : { *(.tbss${RELOCATING+ .tbss.* .gnu.linkonce.tb.*})${RELOCATING+ *(.tcommon)} }
|
||||
.eh_frame ${RELOCATING-0} : { KEEP (*(.eh_frame)) }
|
||||
.gcc_except_table ${RELOCATING-0} : { *(.gcc_except_table) }
|
||||
${WRITABLE_RODATA+${RODATA}}
|
||||
${OTHER_READWRITE_SECTIONS}
|
||||
${TEXT_DYNAMIC-${DYNAMIC}}
|
||||
${RELOCATING+${CTOR}}
|
||||
${RELOCATING+${DTOR}}
|
||||
.jcr ${RELOCATING-0} : { KEEP (*(.jcr)) }
|
||||
${RELOCATING+${OTHER_GOT_SYMBOLS}}
|
||||
.got ${RELOCATING-0} : { *(.got) }
|
||||
${NO_SMALL_DATA-${GOT}}
|
||||
${OTHER_GOT_SECTIONS}
|
||||
${CREATE_SHLIB+${SDATA2}}
|
||||
${CREATE_SHLIB+${SBSS2}}
|
||||
@ -393,5 +422,6 @@ cat <<EOF
|
||||
${STACK_ADDR+${STACK}}
|
||||
${OTHER_SECTIONS}
|
||||
${RELOCATING+${OTHER_END_SYMBOLS}}
|
||||
${RELOCATING+${STACKNOTE}}
|
||||
}
|
||||
EOF
|
||||
|
||||
@ -1,3 +1,9 @@
|
||||
2004-10-07 Bob Wilson <bob.wilson@acm.org>
|
||||
|
||||
* ld-xtensa/lcall1.s: Use .literal directive.
|
||||
* ld-xtensa/lcall2.s: Align function entry.
|
||||
* ld-xtensa/coalesce2.s: Likewise.
|
||||
|
||||
2004-10-04 H.J. Lu <hongjiu.lu@intel.com>
|
||||
|
||||
* ld-scripts/sort.exp: New file for section sorting tests.
|
||||
|
||||
@ -1,6 +1,7 @@
|
||||
.text
|
||||
.global foo
|
||||
.global g_name
|
||||
.align 4
|
||||
foo:
|
||||
entry a5,16
|
||||
movi a5,20000
|
||||
|
||||
@ -2,9 +2,7 @@
|
||||
.text
|
||||
.align 4
|
||||
label1:
|
||||
.begin literal
|
||||
.word 0xffffffff
|
||||
.end literal
|
||||
.literal .Lunused, 0xffffffff
|
||||
entry a5,16
|
||||
.begin longcalls
|
||||
call4 foo
|
||||
|
||||
@ -1,4 +1,5 @@
|
||||
.global foo
|
||||
.global foo
|
||||
.align 4
|
||||
foo:
|
||||
entry a5,16
|
||||
nop
|
||||
|
||||
@ -1,3 +1,12 @@
|
||||
2004-10-07 Bob Wilson <bob.wilson@acm.org>
|
||||
|
||||
* xtensa-dis.c (state_names): Delete.
|
||||
(fetch_data): Use xtensa_isa_maxlength.
|
||||
(print_xtensa_operand): Replace operand parameter with opcode/operand
|
||||
pair. Remove print_sr_name parameter. Use new xtensa-isa.h functions.
|
||||
(print_insn_xtensa): Use new xtensa-isa.h functions. Handle multislot
|
||||
instruction bundles. Use xmalloc instead of malloc.
|
||||
|
||||
2004-10-07 David Gibson <david@gibson.dropbear.id.au>
|
||||
|
||||
* ppc-opc.c: Replace literal "0"s with NULLs in pointer
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
/* xtensa-dis.c. Disassembly functions for Xtensa.
|
||||
Copyright 2003 Free Software Foundation, Inc.
|
||||
Copyright 2003, 2004 Free Software Foundation, Inc.
|
||||
Contributed by Bob Wilson at Tensilica, Inc. (bwilson@tensilica.com)
|
||||
|
||||
This file is part of GDB, GAS, and the GNU binutils.
|
||||
@ -25,328 +25,32 @@
|
||||
#include <string.h>
|
||||
#include "xtensa-isa.h"
|
||||
#include "ansidecl.h"
|
||||
#include "libiberty.h"
|
||||
#include "sysdep.h"
|
||||
#include "dis-asm.h"
|
||||
|
||||
#include <setjmp.h>
|
||||
|
||||
extern xtensa_isa xtensa_default_isa;
|
||||
|
||||
#ifndef MAX
|
||||
#define MAX(a,b) (a > b ? a : b)
|
||||
#endif
|
||||
|
||||
static char* state_names[256] =
|
||||
{
|
||||
"lbeg", /* 0 */
|
||||
"lend", /* 1 */
|
||||
"lcount", /* 2 */
|
||||
"sar", /* 3 */
|
||||
"br", /* 4 */
|
||||
|
||||
"reserved_5", /* 5 */
|
||||
"reserved_6", /* 6 */
|
||||
"reserved_7", /* 7 */
|
||||
|
||||
"av", /* 8 */
|
||||
"avh", /* 9 */
|
||||
"bv", /* 10 */
|
||||
"sav", /* 11 */
|
||||
"scompare1", /* 12 */
|
||||
|
||||
"reserved_13", /* 13 */
|
||||
"reserved_14", /* 14 */
|
||||
"reserved_15", /* 15 */
|
||||
|
||||
"acclo", /* 16 */
|
||||
"acchi", /* 17 */
|
||||
|
||||
"reserved_18", /* 18 */
|
||||
"reserved_19", /* 19 */
|
||||
"reserved_20", /* 20 */
|
||||
"reserved_21", /* 21 */
|
||||
"reserved_22", /* 22 */
|
||||
"reserved_23", /* 23 */
|
||||
"reserved_24", /* 24 */
|
||||
"reserved_25", /* 25 */
|
||||
"reserved_26", /* 26 */
|
||||
"reserved_27", /* 27 */
|
||||
"reserved_28", /* 28 */
|
||||
"reserved_29", /* 29 */
|
||||
"reserved_30", /* 30 */
|
||||
"reserved_31", /* 31 */
|
||||
|
||||
"mr0", /* 32 */
|
||||
"mr1", /* 33 */
|
||||
"mr2", /* 34 */
|
||||
"mr3", /* 35 */
|
||||
|
||||
"reserved_36", /* 36 */
|
||||
"reserved_37", /* 37 */
|
||||
"reserved_38", /* 38 */
|
||||
"reserved_39", /* 39 */
|
||||
"reserved_40", /* 40 */
|
||||
"reserved_41", /* 41 */
|
||||
"reserved_42", /* 42 */
|
||||
"reserved_43", /* 43 */
|
||||
"reserved_44", /* 44 */
|
||||
"reserved_45", /* 45 */
|
||||
"reserved_46", /* 46 */
|
||||
"reserved_47", /* 47 */
|
||||
"reserved_48", /* 48 */
|
||||
"reserved_49", /* 49 */
|
||||
"reserved_50", /* 50 */
|
||||
"reserved_51", /* 51 */
|
||||
"reserved_52", /* 52 */
|
||||
"reserved_53", /* 53 */
|
||||
"reserved_54", /* 54 */
|
||||
"reserved_55", /* 55 */
|
||||
"reserved_56", /* 56 */
|
||||
"reserved_57", /* 57 */
|
||||
"reserved_58", /* 58 */
|
||||
"reserved_59", /* 59 */
|
||||
"reserved_60", /* 60 */
|
||||
"reserved_61", /* 61 */
|
||||
"reserved_62", /* 62 */
|
||||
"reserved_63", /* 63 */
|
||||
|
||||
"reserved_64", /* 64 */
|
||||
"reserved_65", /* 65 */
|
||||
"reserved_66", /* 66 */
|
||||
"reserved_67", /* 67 */
|
||||
"reserved_68", /* 68 */
|
||||
"reserved_69", /* 69 */
|
||||
"reserved_70", /* 70 */
|
||||
"reserved_71", /* 71 */
|
||||
|
||||
"wb", /* 72 */
|
||||
"ws", /* 73 */
|
||||
|
||||
"reserved_74", /* 74 */
|
||||
"reserved_75", /* 75 */
|
||||
"reserved_76", /* 76 */
|
||||
"reserved_77", /* 77 */
|
||||
"reserved_78", /* 78 */
|
||||
"reserved_79", /* 79 */
|
||||
"reserved_80", /* 80 */
|
||||
"reserved_81", /* 81 */
|
||||
"reserved_82", /* 82 */
|
||||
|
||||
"ptevaddr", /* 83 */
|
||||
|
||||
"reserved_84", /* 84 */
|
||||
"reserved_85", /* 85 */
|
||||
"reserved_86", /* 86 */
|
||||
"reserved_87", /* 87 */
|
||||
"reserved_88", /* 88 */
|
||||
"reserved_89", /* 89 */
|
||||
|
||||
"rasid", /* 90 */
|
||||
"itlbcfg", /* 91 */
|
||||
"dtlbcfg", /* 92 */
|
||||
|
||||
"reserved_93", /* 93 */
|
||||
"reserved_94", /* 94 */
|
||||
"reserved_95", /* 95 */
|
||||
|
||||
"ibreakenable", /* 96 */
|
||||
|
||||
"reserved_97", /* 97 */
|
||||
|
||||
"cacheattr", /* 98 */
|
||||
|
||||
"reserved_99", /* 99 */
|
||||
"reserved_100", /* 100 */
|
||||
"reserved_101", /* 101 */
|
||||
"reserved_102", /* 102 */
|
||||
"reserved_103", /* 103 */
|
||||
|
||||
"ddr", /* 104 */
|
||||
|
||||
"reserved_105", /* 105 */
|
||||
"reserved_106", /* 106 */
|
||||
"reserved_107", /* 107 */
|
||||
"reserved_108", /* 108 */
|
||||
"reserved_109", /* 109 */
|
||||
"reserved_110", /* 110 */
|
||||
"reserved_111", /* 111 */
|
||||
"reserved_112", /* 112 */
|
||||
"reserved_113", /* 113 */
|
||||
"reserved_114", /* 114 */
|
||||
"reserved_115", /* 115 */
|
||||
"reserved_116", /* 116 */
|
||||
"reserved_117", /* 117 */
|
||||
"reserved_118", /* 118 */
|
||||
"reserved_119", /* 119 */
|
||||
"reserved_120", /* 120 */
|
||||
"reserved_121", /* 121 */
|
||||
"reserved_122", /* 122 */
|
||||
"reserved_123", /* 123 */
|
||||
"reserved_124", /* 124 */
|
||||
"reserved_125", /* 125 */
|
||||
"reserved_126", /* 126 */
|
||||
"reserved_127", /* 127 */
|
||||
|
||||
"ibreaka0", /* 128 */
|
||||
"ibreaka1", /* 129 */
|
||||
"ibreaka2", /* 130 */
|
||||
"ibreaka3", /* 131 */
|
||||
"ibreaka4", /* 132 */
|
||||
"ibreaka5", /* 133 */
|
||||
"ibreaka6", /* 134 */
|
||||
"ibreaka7", /* 135 */
|
||||
"ibreaka8", /* 136 */
|
||||
"ibreaka9", /* 137 */
|
||||
"ibreaka10", /* 138 */
|
||||
"ibreaka11", /* 139 */
|
||||
"ibreaka12", /* 140 */
|
||||
"ibreaka13", /* 141 */
|
||||
"ibreaka14", /* 142 */
|
||||
"ibreaka15", /* 143 */
|
||||
|
||||
"dbreaka0", /* 144 */
|
||||
"dbreaka1", /* 145 */
|
||||
"dbreaka2", /* 146 */
|
||||
"dbreaka3", /* 147 */
|
||||
"dbreaka4", /* 148 */
|
||||
"dbreaka5", /* 149 */
|
||||
"dbreaka6", /* 150 */
|
||||
"dbreaka7", /* 151 */
|
||||
"dbreaka8", /* 152 */
|
||||
"dbreaka9", /* 153 */
|
||||
"dbreaka10", /* 154 */
|
||||
"dbreaka11", /* 155 */
|
||||
"dbreaka12", /* 156 */
|
||||
"dbreaka13", /* 157 */
|
||||
"dbreaka14", /* 158 */
|
||||
"dbreaka15", /* 159 */
|
||||
|
||||
"dbreakc0", /* 160 */
|
||||
"dbreakc1", /* 161 */
|
||||
"dbreakc2", /* 162 */
|
||||
"dbreakc3", /* 163 */
|
||||
"dbreakc4", /* 164 */
|
||||
"dbreakc5", /* 165 */
|
||||
"dbreakc6", /* 166 */
|
||||
"dbreakc7", /* 167 */
|
||||
"dbreakc8", /* 168 */
|
||||
"dbreakc9", /* 169 */
|
||||
"dbreakc10", /* 170 */
|
||||
"dbreakc11", /* 171 */
|
||||
"dbreakc12", /* 172 */
|
||||
"dbreakc13", /* 173 */
|
||||
"dbreakc14", /* 174 */
|
||||
"dbreakc15", /* 175 */
|
||||
|
||||
"reserved_176", /* 176 */
|
||||
|
||||
"epc1", /* 177 */
|
||||
"epc2", /* 178 */
|
||||
"epc3", /* 179 */
|
||||
"epc4", /* 180 */
|
||||
"epc5", /* 181 */
|
||||
"epc6", /* 182 */
|
||||
"epc7", /* 183 */
|
||||
"epc8", /* 184 */
|
||||
"epc9", /* 185 */
|
||||
"epc10", /* 186 */
|
||||
"epc11", /* 187 */
|
||||
"epc12", /* 188 */
|
||||
"epc13", /* 189 */
|
||||
"epc14", /* 190 */
|
||||
"epc15", /* 191 */
|
||||
"depc", /* 192 */
|
||||
|
||||
"reserved_193", /* 193 */
|
||||
|
||||
"eps2", /* 194 */
|
||||
"eps3", /* 195 */
|
||||
"eps4", /* 196 */
|
||||
"eps5", /* 197 */
|
||||
"eps6", /* 198 */
|
||||
"eps7", /* 199 */
|
||||
"eps8", /* 200 */
|
||||
"eps9", /* 201 */
|
||||
"eps10", /* 202 */
|
||||
"eps11", /* 203 */
|
||||
"eps12", /* 204 */
|
||||
"eps13", /* 205 */
|
||||
"eps14", /* 206 */
|
||||
"eps15", /* 207 */
|
||||
|
||||
"reserved_208", /* 208 */
|
||||
|
||||
"excsave1", /* 209 */
|
||||
"excsave2", /* 210 */
|
||||
"excsave3", /* 211 */
|
||||
"excsave4", /* 212 */
|
||||
"excsave5", /* 213 */
|
||||
"excsave6", /* 214 */
|
||||
"excsave7", /* 215 */
|
||||
"excsave8", /* 216 */
|
||||
"excsave9", /* 217 */
|
||||
"excsave10", /* 218 */
|
||||
"excsave11", /* 219 */
|
||||
"excsave12", /* 220 */
|
||||
"excsave13", /* 221 */
|
||||
"excsave14", /* 222 */
|
||||
"excsave15", /* 223 */
|
||||
"cpenable", /* 224 */
|
||||
|
||||
"reserved_225", /* 225 */
|
||||
|
||||
"interrupt", /* 226 */
|
||||
"interrupt2", /* 227 */
|
||||
"intenable", /* 228 */
|
||||
|
||||
"reserved_229", /* 229 */
|
||||
|
||||
"ps", /* 230 */
|
||||
|
||||
"reserved_231", /* 231 */
|
||||
|
||||
"exccause", /* 232 */
|
||||
"debugcause", /* 233 */
|
||||
"ccount", /* 234 */
|
||||
"prid", /* 235 */
|
||||
"icount", /* 236 */
|
||||
"icountlvl", /* 237 */
|
||||
"excvaddr", /* 238 */
|
||||
|
||||
"reserved_239", /* 239 */
|
||||
|
||||
"ccompare0", /* 240 */
|
||||
"ccompare1", /* 241 */
|
||||
"ccompare2", /* 242 */
|
||||
"ccompare3", /* 243 */
|
||||
|
||||
"misc0", /* 244 */
|
||||
"misc1", /* 245 */
|
||||
"misc2", /* 246 */
|
||||
"misc3", /* 247 */
|
||||
|
||||
"reserved_248", /* 248 */
|
||||
"reserved_249", /* 249 */
|
||||
"reserved_250", /* 250 */
|
||||
"reserved_251", /* 251 */
|
||||
"reserved_252", /* 252 */
|
||||
"reserved_253", /* 253 */
|
||||
"reserved_254", /* 254 */
|
||||
"reserved_255", /* 255 */
|
||||
};
|
||||
|
||||
|
||||
int show_raw_fields;
|
||||
|
||||
static int fetch_data
|
||||
PARAMS ((struct disassemble_info *info, bfd_vma memaddr));
|
||||
PARAMS ((struct disassemble_info *, bfd_vma));
|
||||
static void print_xtensa_operand
|
||||
PARAMS ((bfd_vma, struct disassemble_info *, xtensa_operand,
|
||||
unsigned operand_val, int print_sr_name));
|
||||
PARAMS ((bfd_vma, struct disassemble_info *, xtensa_opcode, int, unsigned));
|
||||
|
||||
struct dis_private {
|
||||
struct dis_private
|
||||
{
|
||||
bfd_byte *byte_buf;
|
||||
jmp_buf bailout;
|
||||
};
|
||||
|
||||
|
||||
static int
|
||||
fetch_data (info, memaddr)
|
||||
struct disassemble_info *info;
|
||||
@ -354,7 +58,7 @@ fetch_data (info, memaddr)
|
||||
{
|
||||
int length, status = 0;
|
||||
struct dis_private *priv = (struct dis_private *) info->private_data;
|
||||
int insn_size = xtensa_insn_maxlength (xtensa_default_isa);
|
||||
int insn_size = xtensa_isa_maxlength (xtensa_default_isa);
|
||||
|
||||
/* Read the maximum instruction size, padding with zeros if we go past
|
||||
the end of the text section. This code will automatically adjust
|
||||
@ -375,14 +79,14 @@ fetch_data (info, memaddr)
|
||||
|
||||
|
||||
static void
|
||||
print_xtensa_operand (memaddr, info, opnd, operand_val, print_sr_name)
|
||||
print_xtensa_operand (memaddr, info, opc, opnd, operand_val)
|
||||
bfd_vma memaddr;
|
||||
struct disassemble_info *info;
|
||||
xtensa_operand opnd;
|
||||
xtensa_opcode opc;
|
||||
int opnd;
|
||||
unsigned operand_val;
|
||||
int print_sr_name;
|
||||
{
|
||||
char *kind = xtensa_operand_kind (opnd);
|
||||
xtensa_isa isa = xtensa_default_isa;
|
||||
int signed_operand_val;
|
||||
|
||||
if (show_raw_fields)
|
||||
@ -394,29 +98,42 @@ print_xtensa_operand (memaddr, info, opnd, operand_val, print_sr_name)
|
||||
return;
|
||||
}
|
||||
|
||||
operand_val = xtensa_operand_decode (opnd, operand_val);
|
||||
(void) xtensa_operand_decode (isa, opc, opnd, &operand_val);
|
||||
signed_operand_val = (int) operand_val;
|
||||
|
||||
if (xtensa_operand_isPCRelative (opnd))
|
||||
if (xtensa_operand_is_register (isa, opc, opnd) == 0)
|
||||
{
|
||||
operand_val = xtensa_operand_undo_reloc (opnd, operand_val, memaddr);
|
||||
info->target = operand_val;
|
||||
(*info->print_address_func) (info->target, info);
|
||||
}
|
||||
else if (!strcmp (kind, "i"))
|
||||
{
|
||||
if (print_sr_name
|
||||
&& signed_operand_val >= 0
|
||||
&& signed_operand_val <= 255)
|
||||
(*info->fprintf_func) (info->stream, "%s",
|
||||
state_names[signed_operand_val]);
|
||||
else if ((signed_operand_val > -256) && (signed_operand_val < 256))
|
||||
(*info->fprintf_func) (info->stream, "%d", signed_operand_val);
|
||||
if (xtensa_operand_is_PCrelative (isa, opc, opnd) == 1)
|
||||
{
|
||||
(void) xtensa_operand_undo_reloc (isa, opc, opnd,
|
||||
&operand_val, memaddr);
|
||||
info->target = operand_val;
|
||||
(*info->print_address_func) (info->target, info);
|
||||
}
|
||||
else
|
||||
(*info->fprintf_func) (info->stream, "0x%x",signed_operand_val);
|
||||
{
|
||||
if ((signed_operand_val > -256) && (signed_operand_val < 256))
|
||||
(*info->fprintf_func) (info->stream, "%d", signed_operand_val);
|
||||
else
|
||||
(*info->fprintf_func) (info->stream, "0x%x", signed_operand_val);
|
||||
}
|
||||
}
|
||||
else
|
||||
(*info->fprintf_func) (info->stream, "%s%u", kind, operand_val);
|
||||
{
|
||||
int i = 1;
|
||||
xtensa_regfile opnd_rf = xtensa_operand_regfile (isa, opc, opnd);
|
||||
(*info->fprintf_func) (info->stream, "%s%u",
|
||||
xtensa_regfile_shortname (isa, opnd_rf),
|
||||
operand_val);
|
||||
while (i < xtensa_operand_num_regs (isa, opc, opnd))
|
||||
{
|
||||
operand_val++;
|
||||
(*info->fprintf_func) (info->stream, ":%s%u",
|
||||
xtensa_regfile_shortname (isa, opnd_rf),
|
||||
operand_val);
|
||||
i++;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
@ -429,20 +146,21 @@ print_insn_xtensa (memaddr, info)
|
||||
struct disassemble_info *info;
|
||||
{
|
||||
unsigned operand_val;
|
||||
int bytes_fetched, size, maxsize, i, noperands;
|
||||
int bytes_fetched, size, maxsize, i, n, noperands, nslots;
|
||||
xtensa_isa isa;
|
||||
xtensa_opcode opc;
|
||||
char *op_name;
|
||||
int print_sr_name;
|
||||
xtensa_format fmt;
|
||||
struct dis_private priv;
|
||||
static bfd_byte *byte_buf = NULL;
|
||||
static xtensa_insnbuf insn_buffer = NULL;
|
||||
static xtensa_insnbuf slot_buffer = NULL;
|
||||
int first, first_slot, valid_insn;
|
||||
|
||||
if (!xtensa_default_isa)
|
||||
(void) xtensa_isa_init ();
|
||||
xtensa_default_isa = xtensa_isa_init (0, 0);
|
||||
|
||||
info->target = 0;
|
||||
maxsize = xtensa_insn_maxlength (xtensa_default_isa);
|
||||
maxsize = xtensa_isa_maxlength (xtensa_default_isa);
|
||||
|
||||
/* Set bytes_per_line to control the amount of whitespace between the hex
|
||||
values and the opcode. For Xtensa, we always print one "chunk" and we
|
||||
@ -458,9 +176,11 @@ print_insn_xtensa (memaddr, info)
|
||||
|
||||
/* Allocate buffers the first time through. */
|
||||
if (!insn_buffer)
|
||||
insn_buffer = xtensa_insnbuf_alloc (xtensa_default_isa);
|
||||
if (!byte_buf)
|
||||
byte_buf = (bfd_byte *) malloc (MAX (maxsize, 4));
|
||||
{
|
||||
insn_buffer = xtensa_insnbuf_alloc (xtensa_default_isa);
|
||||
slot_buffer = xtensa_insnbuf_alloc (xtensa_default_isa);
|
||||
byte_buf = (bfd_byte *) xmalloc (MAX (maxsize, 4));
|
||||
}
|
||||
|
||||
priv.byte_buf = byte_buf;
|
||||
|
||||
@ -471,6 +191,8 @@ print_insn_xtensa (memaddr, info)
|
||||
|
||||
/* Don't set "isa" before the setjmp to keep the compiler from griping. */
|
||||
isa = xtensa_default_isa;
|
||||
size = 0;
|
||||
nslots = 0;
|
||||
|
||||
/* Fetch the maximum size instruction. */
|
||||
bytes_fetched = fetch_data (info, memaddr);
|
||||
@ -478,44 +200,75 @@ print_insn_xtensa (memaddr, info)
|
||||
/* Copy the bytes into the decode buffer. */
|
||||
memset (insn_buffer, 0, (xtensa_insnbuf_size (isa) *
|
||||
sizeof (xtensa_insnbuf_word)));
|
||||
xtensa_insnbuf_from_chars (isa, insn_buffer, priv.byte_buf);
|
||||
xtensa_insnbuf_from_chars (isa, insn_buffer, priv.byte_buf, bytes_fetched);
|
||||
|
||||
opc = xtensa_decode_insn (isa, insn_buffer);
|
||||
if (opc == XTENSA_UNDEFINED
|
||||
|| ((size = xtensa_insn_length (isa, opc)) > bytes_fetched))
|
||||
fmt = xtensa_format_decode (isa, insn_buffer);
|
||||
if (fmt == XTENSA_UNDEFINED
|
||||
|| ((size = xtensa_format_length (isa, fmt)) > bytes_fetched))
|
||||
valid_insn = 0;
|
||||
else
|
||||
{
|
||||
/* Make sure all the opcodes are valid. */
|
||||
valid_insn = 1;
|
||||
nslots = xtensa_format_num_slots (isa, fmt);
|
||||
for (n = 0; n < nslots; n++)
|
||||
{
|
||||
xtensa_format_get_slot (isa, fmt, n, insn_buffer, slot_buffer);
|
||||
if (xtensa_opcode_decode (isa, fmt, n, slot_buffer)
|
||||
== XTENSA_UNDEFINED)
|
||||
{
|
||||
valid_insn = 0;
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
if (!valid_insn)
|
||||
{
|
||||
(*info->fprintf_func) (info->stream, ".byte %#02x", priv.byte_buf[0]);
|
||||
return 1;
|
||||
}
|
||||
|
||||
op_name = (char *) xtensa_opcode_name (isa, opc);
|
||||
(*info->fprintf_func) (info->stream, "%s", op_name);
|
||||
if (nslots > 1)
|
||||
(*info->fprintf_func) (info->stream, "{ ");
|
||||
|
||||
print_sr_name = (!strcasecmp (op_name, "wsr")
|
||||
|| !strcasecmp (op_name, "xsr")
|
||||
|| !strcasecmp (op_name, "rsr"));
|
||||
|
||||
/* Print the operands (if any). */
|
||||
noperands = xtensa_num_operands (isa, opc);
|
||||
if (noperands > 0)
|
||||
first_slot = 1;
|
||||
for (n = 0; n < nslots; n++)
|
||||
{
|
||||
int first = 1;
|
||||
if (first_slot)
|
||||
first_slot = 0;
|
||||
else
|
||||
(*info->fprintf_func) (info->stream, "; ");
|
||||
|
||||
(*info->fprintf_func) (info->stream, "\t");
|
||||
xtensa_format_get_slot (isa, fmt, n, insn_buffer, slot_buffer);
|
||||
opc = xtensa_opcode_decode (isa, fmt, n, slot_buffer);
|
||||
(*info->fprintf_func) (info->stream, "%s",
|
||||
xtensa_opcode_name (isa, opc));
|
||||
|
||||
/* Print the operands (if any). */
|
||||
noperands = xtensa_opcode_num_operands (isa, opc);
|
||||
first = 1;
|
||||
for (i = 0; i < noperands; i++)
|
||||
{
|
||||
xtensa_operand opnd = xtensa_get_operand (isa, opc, i);
|
||||
|
||||
if (xtensa_operand_is_visible (isa, opc, i) == 0)
|
||||
continue;
|
||||
if (first)
|
||||
first = 0;
|
||||
{
|
||||
(*info->fprintf_func) (info->stream, "\t");
|
||||
first = 0;
|
||||
}
|
||||
else
|
||||
(*info->fprintf_func) (info->stream, ", ");
|
||||
operand_val = xtensa_operand_get_field (opnd, insn_buffer);
|
||||
print_xtensa_operand (memaddr, info, opnd, operand_val,
|
||||
print_sr_name);
|
||||
}
|
||||
(void) xtensa_operand_get_field (isa, opc, i, fmt, n,
|
||||
slot_buffer, &operand_val);
|
||||
|
||||
print_xtensa_operand (memaddr, info, opc, i, operand_val);
|
||||
}
|
||||
}
|
||||
|
||||
if (nslots > 1)
|
||||
(*info->fprintf_func) (info->stream, " }");
|
||||
|
||||
info->bytes_per_chunk = size;
|
||||
info->display_endian = info->endian;
|
||||
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user