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Remove trailing spaces in opcodes

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This commit is contained in:
H.J. Lu 2015-08-12 04:45:07 -07:00
parent f3445b37b6
commit 43e65147c0
137 changed files with 4011 additions and 4011 deletions
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20
opcodes/ChangeLog-2006
View File

@ -193,11 +193,11 @@
2006-10-23 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
* i386-dis.c (dis386): Add support for the change in POPCNT opcode in
* i386-dis.c (dis386): Add support for the change in POPCNT opcode in
amdfam10 architecture.
(PREGRP37): NEW.
(print_insn): Disallow REP prefix for POPCNT.
2006-10-20 Andrew Stubbs <andrew.stubbs@st.com>
* sh-dis.c (print_insn_sh): Remove 0x from output to prevent GDB
@ -274,9 +274,9 @@
* i386-dis.c (MXC,EMC): Define.
(OP_MXC): New function to handle cvt* (convert instructions) between
%xmm and %mm register correctly.
(OP_EMC): ditto.
(prefix_user_table): Modified cvtpi2pd,cvtpd2pi and cvttpd2pi
instruction operands in PREGRP2,PREGRP3,PREGRP4 appropriately
(OP_EMC): ditto.
(prefix_user_table): Modified cvtpi2pd,cvtpd2pi and cvttpd2pi
instruction operands in PREGRP2,PREGRP3,PREGRP4 appropriately
with EMC/MXC.
2006-07-29 Richard Sandiford <richard@codesourcery.com>
@ -689,7 +689,7 @@
New cases '$' and '%' for read/write hyperprivileged register.
* sparc-opc.c (sparc_opcodes): Add new entries for UA2005
window handling and rdhpr/wrhpr instructions.
2006-02-24 DJ Delorie <dj@redhat.com>
* m32c-desc.c: Regenerate with linker relaxation attributes.
@ -742,13 +742,13 @@
* xc16x-desc.h: New file
* xc16x-desc.c: New file
* xc16x-opc.h: New file
* xc16x-opc.h: New file
* xc16x-opc.c: New file
* xc16x-ibld.c: New file
* xc16x-asm.c: New file
* xc16x-dis.c: New file
* Makefile.am: Entries for xc16x
* Makefile.in: Regenerate
* Makefile.am: Entries for xc16x
* Makefile.in: Regenerate
* cofigure.in: Add xc16x target information.
* configure: Regenerate.
* disassemble.c: Add xc16x target information.
@ -783,7 +783,7 @@
* z80-dis.c (struct buffer, prt_d, prt_d_n, arit_d, ld_r_d,
ld_d_r, pref_xd_cb): Use signed char to hold data to be
disassembled.
disassembled.
* z80-dis.c (TXTSIZ): Increase buffer size to 24, this fixes
buffer overflows when disassembling instructions like
ld (ix+123),0x23

4
opcodes/ChangeLog-2007
View File

@ -1071,7 +1071,7 @@
* s390-mkopc.c (struct s390_cond_ext_format): New global struct.
(s390_cond_ext_format): New global variable.
(expandConditionalJump): New function.
(main): Invoke expandConditionalJump for mnemonics containing '*'.
(main): Invoke expandConditionalJump for mnemonics containing '*'.
* s390-opc.txt: Replace mnemonics with conditional
mask extensions with instructions using the newly introduced '*' tag.
@ -1096,7 +1096,7 @@
* ia64-gen.c: (main): Add missing newline to copyright message.
* ia64-ic.tbl (fp-non-arith): Add xmpy.
* ia64-asmtab.c: Regenerate.
2007-08-01 Michael Snyder <msnyder@access-company.com>
* i386-dis.c (print_insn): Guard against NULL.

16
opcodes/Makefile.am
View File

@ -6,12 +6,12 @@
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 3 of the License, or
# (at your option) any later version.
#
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
#
# You should have received a copy of the GNU General Public License
# along with this program; see the file COPYING3. If not see
# <http://www.gnu.org/licenses/>.
@ -392,15 +392,15 @@ EPIPHANY_DEPS =
FR30_DEPS =
FRV_DEPS =
IP2K_DEPS =
IQ2000_DEPS =
LM32_DEPS =
IQ2000_DEPS =
LM32_DEPS =
M32C_DEPS =
M32R_DEPS =
MEP_DEPS =
MT_DEPS =
OR1K_DEPS =
XC16X_DEPS =
XSTORMY16_DEPS =
OR1K_DEPS =
XC16X_DEPS =
XSTORMY16_DEPS =
endif
run-cgen:
@ -546,7 +546,7 @@ i386-gen.o: i386-gen.c i386-opc.h $(srcdir)/../include/opcode/i386.h \
config.h i386-opc.h sysdep.h
$(COMPILE_FOR_BUILD) -c $(srcdir)/i386-gen.c
$(srcdir)/i386-tbl.h: $(srcdir)/i386-init.h
$(srcdir)/i386-tbl.h: $(srcdir)/i386-init.h
@echo $@
$(srcdir)/i386-init.h: @MAINT@ i386-gen$(EXEEXT_FOR_BUILD) i386-opc.tbl i386-reg.tbl

6
opcodes/Makefile.in
View File

@ -22,12 +22,12 @@
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 3 of the License, or
# (at your option) any later version.
#
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
#
# You should have received a copy of the GNU General Public License
# along with this program; see the file COPYING3. If not see
# <http://www.gnu.org/licenses/>.
@ -1416,7 +1416,7 @@ i386-gen.o: i386-gen.c i386-opc.h $(srcdir)/../include/opcode/i386.h \
config.h i386-opc.h sysdep.h
$(COMPILE_FOR_BUILD) -c $(srcdir)/i386-gen.c
$(srcdir)/i386-tbl.h: $(srcdir)/i386-init.h
$(srcdir)/i386-tbl.h: $(srcdir)/i386-init.h
@echo $@
$(srcdir)/i386-init.h: @MAINT@ i386-gen$(EXEEXT_FOR_BUILD) i386-opc.tbl i386-reg.tbl

2
opcodes/aarch64-gen.c
View File

@ -209,7 +209,7 @@ static int max_num_opcodes_at_leaf_node = 0;
is decided to be undividable and OPCODE will be assigned to BITTREE->LIST.
The function recursively call itself until OPCODE is undividable.
N.B. the nature of this algrithm determines that given any value in the
32-bit space, the computed decision tree will always be able to find one or
more opcodes entries for it, regardless whether there is a valid instruction

2
opcodes/alpha-opc.c
View File

@ -274,7 +274,7 @@ const struct alpha_operand alpha_operands[] =
/* The signed "23-bit" aligned displacement of Branch format insns. */
#define BDISP (MDISP + 1)
{ 21, 0, BFD_RELOC_23_PCREL_S2,
{ 21, 0, BFD_RELOC_23_PCREL_S2,
AXP_OPERAND_RELATIVE, insert_bdisp, extract_bdisp },
/* The 26-bit PALcode function */

6
opcodes/arc-dis.c
View File

@ -35,18 +35,18 @@
#define dbg (0)
#endif
/* Classification of the opcodes for the decoder to print
/* Classification of the opcodes for the decoder to print
the instructions. */
typedef enum
{
CLASS_A4_ARITH,
CLASS_A4_ARITH,
CLASS_A4_OP3_GENERAL,
CLASS_A4_FLAG,
/* All branches other than JC. */
CLASS_A4_BRANCH,
CLASS_A4_JC ,
/* All loads other than immediate
/* All loads other than immediate
indexed loads. */
CLASS_A4_LD0,
CLASS_A4_LD1,

8
opcodes/arc-dis.h
View File

@ -21,14 +21,14 @@
#ifndef ARCDIS_H
#define ARCDIS_H
enum
enum
{
BR_exec_when_no_jump,
BR_exec_always,
BR_exec_when_jump
};
enum Flow
enum Flow
{
noflow,
direct_jump,
@ -41,7 +41,7 @@ enum Flow
enum { no_reg = 99 };
enum { allOperandsSize = 256 };
struct arcDisState
struct arcDisState
{
void *_this;
int instructionLen;
@ -50,7 +50,7 @@ struct arcDisState
const char *(*auxRegName)(void*, int);
const char *(*condCodeName)(void*, int);
const char *(*instName)(void*, int, int, int*);
unsigned char* instruction;
unsigned index;
const char *comm[6]; /* instr name, cond, NOP, 3 operands */

10
opcodes/arc-ext.h
View File

@ -30,20 +30,20 @@ enum {NUM_EXT_INST = (0x1f-0x10+1) + (0x3f-0x09+1)};
enum {NUM_EXT_CORE = 59-32+1};
enum {NUM_EXT_COND = 0x1f-0x10+1};
struct ExtInstruction
struct ExtInstruction
{
char flags;
char *name;
};
};
struct ExtAuxRegister
struct ExtAuxRegister
{
long address;
char *name;
struct ExtAuxRegister *next;
struct ExtAuxRegister *next;
};
struct arcExtMap
struct arcExtMap
{
struct ExtAuxRegister *auxRegisters;
struct ExtInstruction *instructions[NUM_EXT_INST];

114
opcodes/arm-dis.c
View File

@ -125,7 +125,7 @@ struct opcode16
%<bitfield>'c print specified char iff bitfield is all ones
%<bitfield>`c print specified char iff bitfield is all zeroes
%<bitfield>?ab... select from array of values in big endian order
%L print as an iWMMXt N/M width field.
%Z print the Immediate of a WSHUFH instruction.
%l like 'A' except use byte offsets for 'B' & 'H'
@ -920,7 +920,7 @@ static const struct opcode32 coprocessor_opcodes[] =
%<bitfield>Sn print byte scaled width limited by n
%<bitfield>Tn print short scaled width limited by n
%<bitfield>Un print long scaled width limited by n
%<bitfield>'c print specified char iff bitfield is all ones
%<bitfield>`c print specified char iff bitfield is all zeroes
%<bitfield>?ab... select from array of values in big endian order. */
@ -1539,10 +1539,10 @@ static const struct opcode32 neon_opcodes[] =
%<bitfield>{r|R}u as %{r|R} but if matches the other %u field then is UNPREDICTABLE
%<bitfield>{r|R}U as %{r|R} but if matches the other %U field then is UNPREDICTABLE
%<bitfield>d print the bitfield in decimal
%<bitfield>W print the bitfield plus one in decimal
%<bitfield>W print the bitfield plus one in decimal
%<bitfield>x print the bitfield in hex
%<bitfield>X print the bitfield as 1 hex digit without leading "0x"
%<bitfield>'c print specified char iff bitfield is all ones
%<bitfield>`c print specified char iff bitfield is all zeroes
%<bitfield>?ab... select from array of values in big endian order
@ -3084,8 +3084,8 @@ arm_decode_bitfield (const char *ptr,
{
unsigned long value = 0;
int width = 0;
do
do
{
int start, end;
int bits;
@ -3310,7 +3310,7 @@ print_insn_coprocessor (bfd_vma pc,
func (stream, "\t; ");
/* For unaligned PCs, apply off-by-alignment
correction. */
info->print_address_func (offset + pc
info->print_address_func (offset + pc
+ info->bytes_per_chunk * 2
- (pc & 3),
info);
@ -3897,7 +3897,7 @@ print_insn_neon (struct disassemble_info *info, long given, bfd_boolean thumb)
else
return FALSE;
}
for (insn = neon_opcodes; insn->assembler; insn++)
{
if ((given & insn->mask) == insn->value)
@ -3928,7 +3928,7 @@ print_insn_neon (struct disassemble_info *info, long given, bfd_boolean thumb)
case 'A':
{
static const unsigned char enc[16] =
static const unsigned char enc[16] =
{
0x4, 0x14, /* st4 0,1 */
0x4, /* st1 2 */
@ -3950,7 +3950,7 @@ print_insn_neon (struct disassemble_info *info, long given, bfd_boolean thumb)
int n = enc[type] & 0xf;
int stride = (enc[type] >> 4) + 1;
int ix;
func (stream, "{");
if (stride > 1)
for (ix = 0; ix != n; ix++)
@ -3969,7 +3969,7 @@ print_insn_neon (struct disassemble_info *info, long given, bfd_boolean thumb)
func (stream, ", %s", arm_regnames[rm]);
}
break;
case 'B':
{
int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
@ -3985,7 +3985,7 @@ print_insn_neon (struct disassemble_info *info, long given, bfd_boolean thumb)
if (length > 1 && size > 0)
stride = (idx_align & (1 << size)) ? 2 : 1;
switch (length)
{
case 1:
@ -4002,19 +4002,19 @@ print_insn_neon (struct disassemble_info *info, long given, bfd_boolean thumb)
}
}
break;
case 2:
if (size == 2 && (idx_align & 2) != 0)
return FALSE;
align = (idx_align & 1) ? 16 << size : 0;
break;
case 3:
if ((size == 2 && (idx_align & 3) != 0)
|| (idx_align & 1) != 0)
return FALSE;
break;
case 4:
if (size == 2)
{
@ -4025,11 +4025,11 @@ print_insn_neon (struct disassemble_info *info, long given, bfd_boolean thumb)
else
align = (idx_align & 1) ? 32 << size : 0;
break;
default:
abort ();
}
func (stream, "{");
for (i = 0; i < length; i++)
func (stream, "%sd%d[%d]", (i == 0) ? "" : ",",
@ -4044,7 +4044,7 @@ print_insn_neon (struct disassemble_info *info, long given, bfd_boolean thumb)
func (stream, ", %s", arm_regnames[rm]);
}
break;
case 'C':
{
int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
@ -4056,12 +4056,12 @@ print_insn_neon (struct disassemble_info *info, long given, bfd_boolean thumb)
int n = type + 1;
int stride = ((given >> 5) & 0x1);
int ix;
if (stride && (n == 1))
n++;
else
stride++;
func (stream, "{");
if (stride > 1)
for (ix = 0; ix != n; ix++)
@ -4088,18 +4088,18 @@ print_insn_neon (struct disassemble_info *info, long given, bfd_boolean thumb)
func (stream, ", %s", arm_regnames[rm]);
}
break;
case 'D':
{
int raw_reg = (given & 0xf) | ((given >> 1) & 0x10);
int size = (given >> 20) & 3;
int reg = raw_reg & ((4 << size) - 1);
int ix = raw_reg >> size >> 2;
func (stream, "d%d[%d]", reg, ix);
}
break;
case 'E':
/* Neon encoded constant for mov, mvn, vorr, vbic. */
{
@ -4110,11 +4110,11 @@ print_insn_neon (struct disassemble_info *info, long given, bfd_boolean thumb)
unsigned shift;
int size = 0;
int isfloat = 0;
bits |= ((given >> 24) & 1) << 7;
bits |= ((given >> 16) & 7) << 4;
bits |= ((given >> 0) & 15) << 0;
if (cmode < 8)
{
shift = (cmode >> 1) & 3;
@ -4141,7 +4141,7 @@ print_insn_neon (struct disassemble_info *info, long given, bfd_boolean thumb)
/* Bit replication into bytes. */
int ix;
unsigned long mask;
value = 0;
hival = 0;
for (ix = 7; ix >= 0; ix--)
@ -4165,7 +4165,7 @@ print_insn_neon (struct disassemble_info *info, long given, bfd_boolean thumb)
{
/* Floating point encoding. */
int tmp;
value = (unsigned long) (bits & 0x7f) << 19;
value |= (unsigned long) (bits & 0x80) << 24;
tmp = bits & 0x40 ? 0x3c : 0x40;
@ -4185,7 +4185,7 @@ print_insn_neon (struct disassemble_info *info, long given, bfd_boolean thumb)
case 8:
func (stream, "#%ld\t; 0x%.2lx", value, value);
break;
case 16:
func (stream, "#%ld\t; 0x%.4lx", value, value);
break;
@ -4195,24 +4195,24 @@ print_insn_neon (struct disassemble_info *info, long given, bfd_boolean thumb)
{
unsigned char valbytes[4];
double fvalue;
/* Do this a byte at a time so we don't have to
worry about the host's endianness. */
valbytes[0] = value & 0xff;
valbytes[1] = (value >> 8) & 0xff;
valbytes[2] = (value >> 16) & 0xff;
valbytes[3] = (value >> 24) & 0xff;
floatformat_to_double
floatformat_to_double
(& floatformat_ieee_single_little, valbytes,
& fvalue);
func (stream, "#%.7g\t; 0x%.8lx", fvalue,
value);
}
else
func (stream, "#%ld\t; 0x%.8lx",
(long) (((value & 0x80000000L) != 0)
(long) (((value & 0x80000000L) != 0)
? value | ~0xffffffffL : value),
value);
break;
@ -4220,18 +4220,18 @@ print_insn_neon (struct disassemble_info *info, long given, bfd_boolean thumb)
case 64:
func (stream, "#0x%.8lx%.8lx", hival, value);
break;
default:
abort ();
}
}
break;
case 'F':
{
int regno = ((given >> 16) & 0xf) | ((given >> (7 - 4)) & 0x10);
int num = (given >> 8) & 0x3;
if (!num)
func (stream, "{d%d}", regno);
else if (num + regno >= 32)
@ -4249,7 +4249,7 @@ print_insn_neon (struct disassemble_info *info, long given, bfd_boolean thumb)
unsigned long value;
c = arm_decode_bitfield (c, given, &value, &width);
switch (*c)
{
case 'r':
@ -4262,7 +4262,7 @@ print_insn_neon (struct disassemble_info *info, long given, bfd_boolean thumb)
case 'e':
func (stream, "%ld", (1ul << width) - value);
break;
case 'S':
case 'T':
case 'U':
@ -4302,7 +4302,7 @@ print_insn_neon (struct disassemble_info *info, long given, bfd_boolean thumb)
else
func (stream, "q%ld", value >> 1);
break;
case '`':
c++;
if (value == 0)
@ -4345,20 +4345,20 @@ print_insn_neon (struct disassemble_info *info, long given, bfd_boolean thumb)
/* Return the name of a v7A special register. */
static const char *
static const char *
banked_regname (unsigned reg)
{
switch (reg)
{
case 15: return "CPSR";
case 32: return "R8_usr";
case 32: return "R8_usr";
case 33: return "R9_usr";
case 34: return "R10_usr";
case 35: return "R11_usr";
case 36: return "R12_usr";
case 37: return "SP_usr";
case 38: return "LR_usr";
case 40: return "R8_fiq";
case 40: return "R8_fiq";
case 41: return "R9_fiq";
case 42: return "R10_fiq";
case 43: return "R11_fiq";
@ -4739,7 +4739,7 @@ print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given)
}
else
{
func (stream, "%cPSR_",
func (stream, "%cPSR_",
(given & 0x00400000) ? 'S' : 'C');
if (given & 0x80000)
func (stream, "f");
@ -4753,7 +4753,7 @@ print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given)
break;
case 'U':
if ((given & 0xf0) == 0x60)
if ((given & 0xf0) == 0x60)
{
switch (given & 0xf)
{
@ -4762,8 +4762,8 @@ print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given)
func (stream, "#%d", (int) given & 0xf);
break;
}
}
else
}
else
{
const char * opt = data_barrier_option (given & 0xf);
if (opt != NULL)
@ -4780,7 +4780,7 @@ print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given)
unsigned long value;
c = arm_decode_bitfield (c, given, &value, &width);
switch (*c)
{
case 'R':
@ -5317,7 +5317,7 @@ print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given)
value_in_comment = imm;
}
break;
case 'J':
{
unsigned int imm = 0;
@ -5647,7 +5647,7 @@ print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given)
break;
case 'U':
if ((given & 0xf0) == 0x60)
if ((given & 0xf0) == 0x60)
{
switch (given & 0xf)
{
@ -5657,7 +5657,7 @@ print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given)
break;
}
}
else
else
{
const char * opt = data_barrier_option (given & 0xf);
if (opt != NULL)
@ -5688,7 +5688,7 @@ print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given)
sysm |= (given & 0x30);
sysm |= (given & 0x00100000) >> 14;
name = banked_regname (sysm);
if (name != NULL)
func (stream, "%s", name);
else
@ -5727,7 +5727,7 @@ print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given)
unsigned long val;
c = arm_decode_bitfield (c, given, &val, &width);
switch (*c)
{
case 'd':
@ -5766,7 +5766,7 @@ print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given)
if (val == ((1ul << width) - 1))
func (stream, "%c", *c);
break;
case '`':
c++;
if (val == 0)
@ -5777,7 +5777,7 @@ print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given)
func (stream, "%c", c[(1 << width) - (int) val]);
c += 1 << width;
break;
case 'x':
func (stream, "0x%lx", val & 0xffffffffUL);
break;
@ -5855,7 +5855,7 @@ arm_symbol_is_valid (asymbol * sym,
struct disassemble_info * info ATTRIBUTE_UNUSED)
{
const char * name;
if (sym == NULL)
return FALSE;
@ -5918,7 +5918,7 @@ parse_disassembler_options (char *options)
++ options;
/* Skip forward past seperators. */
while (ISSPACE (*options) || (*options == ','))
++ options;
++ options;
}
}
@ -6151,7 +6151,7 @@ print_insn (bfd_vma pc, struct disassemble_info *info, bfd_boolean little)
if ((info->flags & USER_SPECIFIED_MACHINE_TYPE) == 0)
/* If the user did not use the -m command line switch then default to
disassembling all types of ARM instruction.
The info->mach value has to be ignored as this will be based on
the default archictecture for the target and/or hints in the notes
section, but it will never be greater than the current largest arm

42
opcodes/avr-dis.c
View File

@ -62,7 +62,7 @@ avr_operand (unsigned int insn, unsigned int insn2, unsigned int pc, int constra
insn = (insn & 0xf) | ((insn & 0x0200) >> 5); /* Source register. */
else
insn = (insn & 0x01f0) >> 4; /* Destination register. */
sprintf (buf, "r%d", insn);
break;
@ -72,11 +72,11 @@ avr_operand (unsigned int insn, unsigned int insn2, unsigned int pc, int constra
else
sprintf (buf, "r%d", 16 + ((insn & 0xf0) >> 4));
break;
case 'w':
sprintf (buf, "r%d", 24 + ((insn & 0x30) >> 3));
break;
case 'a':
if (regs)
sprintf (buf, "r%d", 16 + (insn & 7));
@ -138,11 +138,11 @@ avr_operand (unsigned int insn, unsigned int insn2, unsigned int pc, int constra
case 'b':
{
unsigned int x;
x = (insn & 7);
x |= (insn >> 7) & (3 << 3);
x |= (insn >> 8) & (1 << 5);
if (insn & 0x8)
*buf++ = 'Y';
else
@ -151,17 +151,17 @@ avr_operand (unsigned int insn, unsigned int insn2, unsigned int pc, int constra
sprintf (comment, "0x%02x", x);
}
break;
case 'h':
*sym = 1;
*sym_addr = ((((insn & 1) | ((insn & 0x1f0) >> 3)) << 16) | insn2) * 2;
/* See PR binutils/2454. Ideally we would like to display the hex
value of the address only once, but this would mean recoding
objdump_print_address() which would affect many targets. */
sprintf (buf, "%#lx", (unsigned long) *sym_addr);
sprintf (buf, "%#lx", (unsigned long) *sym_addr);
strcpy (comment, comment_start);
break;
case 'L':
{
int rel_addr = (((insn & 0xfff) ^ 0x800) - 0x800) * 2;
@ -197,7 +197,7 @@ avr_operand (unsigned int insn, unsigned int insn2, unsigned int pc, int constra
sprintf (buf, "%d", val);
}
break;
case 'M':
sprintf (buf, "0x%02X", ((insn & 0xf00) >> 4) | (insn & 0xf));
sprintf (comment, "%d", ((insn & 0xf00) >> 4) | (insn & 0xf));
@ -208,7 +208,7 @@ avr_operand (unsigned int insn, unsigned int insn2, unsigned int pc, int constra
fprintf (stderr, _("Internal disassembler error"));
ok = 0;
break;
case 'K':
{
unsigned int x;
@ -218,15 +218,15 @@ avr_operand (unsigned int insn, unsigned int insn2, unsigned int pc, int constra
sprintf (comment, "%d", x);
}
break;
case 's':
sprintf (buf, "%d", insn & 7);
break;
case 'S':
sprintf (buf, "%d", (insn >> 4) & 7);
break;
case 'P':
{
unsigned int x;
@ -241,21 +241,21 @@ avr_operand (unsigned int insn, unsigned int insn2, unsigned int pc, int constra
case 'p':
{
unsigned int x;
x = (insn >> 3) & 0x1f;
sprintf (buf, "0x%02x", x);
sprintf (comment, "%d", x);
}
break;
case 'E':
sprintf (buf, "%d", (insn >> 4) & 15);
break;
case '?':
*buf = '\0';
break;
default:
sprintf (buf, "??");
fprintf (stderr, _("unknown constraint `%c'"), constraint);
@ -309,7 +309,7 @@ print_insn_avr (bfd_vma addr, disassemble_info *info)
comment_start = " ";
nopcodes = sizeof (avr_opcodes) / sizeof (struct avr_opcodes_s);
avr_bin_masks = xmalloc (nopcodes * sizeof (unsigned int));
for (opcode = avr_opcodes, maskptr = avr_bin_masks;
@ -319,7 +319,7 @@ print_insn_avr (bfd_vma addr, disassemble_info *info)
char * s;
unsigned int bin = 0;
unsigned int mask = 0;
for (s = opcode->opcode; *s; ++s)
{
bin <<= 1;
@ -336,7 +336,7 @@ print_insn_avr (bfd_vma addr, disassemble_info *info)
}
insn = avrdis_opcode (addr, info);
for (opcode = avr_opcodes, maskptr = avr_bin_masks;
opcode->name;
opcode++, maskptr++)
@ -346,7 +346,7 @@ print_insn_avr (bfd_vma addr, disassemble_info *info)
if ((insn & *maskptr) == opcode->bin_opcode)
break;
}
/* Special case: disassemble `ldd r,b+0' as `ld r,b', and
`std b+0,r' as `st b,r' (next entry in the table). */

2
opcodes/cgen-asm.c
View File

@ -212,7 +212,7 @@ cgen_parse_keyword (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
character of the suffix ('.') is special. */
if (*p)
++p;
/* Allow letters, digits, and any special characters. */
while (((p - start) < (int) sizeof (buf))
&& *p

36
opcodes/cgen-asm.in
View File

@ -60,9 +60,9 @@ static const char * parse_insn_normal
Returns NULL for success, an error message for failure. */
char *
char *
@arch@_cgen_build_insn_regex (CGEN_INSN *insn)
{
{
CGEN_OPCODE *opc = (CGEN_OPCODE *) CGEN_INSN_OPCODE (insn);
const char *mnem = CGEN_INSN_MNEMONIC (insn);
char rxbuf[CGEN_MAX_RX_ELEMENTS];
@ -101,18 +101,18 @@ char *
/* Copy any remaining literals from the syntax string into the rx. */
for(; * syn != 0 && rx <= rxbuf + (CGEN_MAX_RX_ELEMENTS - 7 - 4); ++syn)
{
if (CGEN_SYNTAX_CHAR_P (* syn))
if (CGEN_SYNTAX_CHAR_P (* syn))
{
char c = CGEN_SYNTAX_CHAR (* syn);
switch (c)
switch (c)
{
/* Escape any regex metacharacters in the syntax. */
case '.': case '[': case '\\':
case '*': case '^': case '$':
case '.': case '[': case '\\':
case '*': case '^': case '$':
#ifdef CGEN_ESCAPE_EXTENDED_REGEX
case '?': case '{': case '}':
case '?': case '{': case '}':
case '(': case ')': case '*':
case '|': case '+': case ']':
#endif
@ -142,20 +142,20 @@ char *
}
/* Trailing whitespace ok. */
* rx++ = '[';
* rx++ = ' ';
* rx++ = '\t';
* rx++ = ']';
* rx++ = '*';
* rx++ = '[';
* rx++ = ' ';
* rx++ = '\t';
* rx++ = ']';
* rx++ = '*';
/* But anchor it after that. */
* rx++ = '$';
* rx++ = '$';
* rx = '\0';
CGEN_INSN_RX (insn) = xmalloc (sizeof (regex_t));
reg_err = regcomp ((regex_t *) CGEN_INSN_RX (insn), rxbuf, REG_NOSUB);
if (reg_err == 0)
if (reg_err == 0)
return NULL;
else
{
@ -354,7 +354,7 @@ const CGEN_INSN *
const CGEN_INSN *insn = ilist->insn;
recognized_mnemonic = 1;
#ifdef CGEN_VALIDATE_INSN_SUPPORTED
#ifdef CGEN_VALIDATE_INSN_SUPPORTED
/* Not usually needed as unsupported opcodes
shouldn't be in the hash lists. */
/* Is this insn supported by the selected cpu? */
@ -414,7 +414,7 @@ const CGEN_INSN *
if (strlen (start) > 50)
/* xgettext:c-format */
sprintf (errbuf, "%s `%.50s...'", tmp_errmsg, start);
else
else
/* xgettext:c-format */
sprintf (errbuf, "%s `%.50s'", tmp_errmsg, start);
}
@ -423,11 +423,11 @@ const CGEN_INSN *
if (strlen (start) > 50)
/* xgettext:c-format */
sprintf (errbuf, _("bad instruction `%.50s...'"), start);
else
else
/* xgettext:c-format */
sprintf (errbuf, _("bad instruction `%.50s'"), start);
}
*errmsg = errbuf;
return NULL;
}

2
opcodes/cgen-dis.c
View File

@ -49,7 +49,7 @@ count_decodable_bits (const CGEN_INSN *insn)
return bits;
}
/* Add an instruction to the hash chain. */
/* Add an instruction to the hash chain. */
static void
add_insn_to_hash_chain (CGEN_INSN_LIST *hentbuf,
const CGEN_INSN *insn,

8
opcodes/cgen-dis.in
View File

@ -231,7 +231,7 @@ print_insn (CGEN_CPU_DESC cd,
int length;
unsigned long insn_value_cropped;
#ifdef CGEN_VALIDATE_INSN_SUPPORTED
#ifdef CGEN_VALIDATE_INSN_SUPPORTED
/* Not needed as insn shouldn't be in hash lists if not supported. */
/* Supported by this cpu? */
if (! @arch@_cgen_insn_supported (cd, insn))
@ -249,7 +249,7 @@ print_insn (CGEN_CPU_DESC cd,
relevant part from the buffer. */
if ((unsigned) (CGEN_INSN_BITSIZE (insn) / 8) < buflen &&
(unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long))
insn_value_cropped = bfd_get_bits (buf, CGEN_INSN_BITSIZE (insn),
insn_value_cropped = bfd_get_bits (buf, CGEN_INSN_BITSIZE (insn),
info->endian == BFD_ENDIAN_BIG);
else
insn_value_cropped = insn_value;
@ -368,7 +368,7 @@ print_insn_@arch@ (bfd_vma pc, disassemble_info *info)
arch = info->arch;
if (arch == bfd_arch_unknown)
arch = CGEN_BFD_ARCH;
/* There's no standard way to compute the machine or isa number
so we leave it to the target. */
#ifdef CGEN_COMPUTE_MACH
@ -409,7 +409,7 @@ print_insn_@arch@ (bfd_vma pc, disassemble_info *info)
break;
}
}
}
}
/* If we haven't initialized yet, initialize the opcode table. */
if (! cd)

4
opcodes/cgen-ibld.in
View File

@ -154,7 +154,7 @@ insert_normal (CGEN_CPU_DESC cd,
{
long minval = - (1L << (length - 1));
unsigned long maxval = mask;
if ((value > 0 && (unsigned long) value > maxval)
|| value < minval)
{
@ -192,7 +192,7 @@ insert_normal (CGEN_CPU_DESC cd,
{
long minval = - (1L << (length - 1));
long maxval = (1L << (length - 1)) - 1;
if (value < minval || value > maxval)
{
sprintf

6
opcodes/cgen-opc.c
View File

@ -127,7 +127,7 @@ cgen_keyword_add (CGEN_KEYWORD *kt, CGEN_KEYWORD_ENTRY *ke)
&& ! strchr (kt->nonalpha_chars, ke->name[i]))
{
size_t idx = strlen (kt->nonalpha_chars);
/* If you hit this limit, please don't just
increase the size of the field, instead
look for a better algorithm. */
@ -369,7 +369,7 @@ cgen_get_insn_value (CGEN_CPU_DESC cd, unsigned char *buf, int length)
segments, and endian-convert them, one at a time. */
int i;
/* Enforce divisibility. */
/* Enforce divisibility. */
if ((length % insn_chunk_bitsize) != 0)
abort ();
@ -408,7 +408,7 @@ cgen_put_insn_value (CGEN_CPU_DESC cd,
segments, and endian-convert them, one at a time. */
int i;
/* Enforce divisibility. */
/* Enforce divisibility. */
if ((length % insn_chunk_bitsize) != 0)
abort ();

2
opcodes/cgen.sh
View File

@ -26,7 +26,7 @@
# cgen.sh action srcdir cgen cgendir cgenflags arch prefix \
# arch-file opc-file options [extrafiles]
#
# ACTION is currently always "opcodes". It exists to be consistent with the
# ACTION is currently always "opcodes". It exists to be consistent with the
# simulator.
# ARCH is the name of the architecture.
# It is substituted into @arch@ and @ARCH@ in the generated files.

6
opcodes/configure.ac
View File

@ -6,12 +6,12 @@ dnl This file is free software; you can redistribute it and/or modify
dnl it under the terms of the GNU General Public License as published by
dnl the Free Software Foundation; either version 3 of the License, or
dnl (at your option) any later version.
dnl
dnl
dnl This program is distributed in the hope that it will be useful,
dnl but WITHOUT ANY WARRANTY; without even the implied warranty of
dnl MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
dnl GNU General Public License for more details.
dnl
dnl
dnl You should have received a copy of the GNU General Public License
dnl along with this program; see the file COPYING3. If not see
dnl <http://www.gnu.org/licenses/>.
@ -234,7 +234,7 @@ do
. $srcdir/../bfd/config.bfd
selarchs="$selarchs $targ_archs"
fi
done
done
# Utility var, documents generic cgen support files.

4
opcodes/configure.com
View File

@ -12,12 +12,12 @@ $! This file is free software; you can redistribute it and/or modify
$! it under the terms of the GNU General Public License as published by
$! the Free Software Foundation; either version 3 of the License, or
$! (at your option) any later version.
$!
$!
$! This program is distributed in the hope that it will be useful,
$! but WITHOUT ANY WARRANTY; without even the implied warranty of
$! MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
$! GNU General Public License for more details.
$!
$!
$! You should have received a copy of the GNU General Public License
$! along with this program; see the file COPYING3. If not see
$! <http://www.gnu.org/licenses/>.

8
opcodes/cr16-dis.c
View File

@ -358,7 +358,7 @@ make_argument (argument * a, int start_bits)
switch (a->type)
{
case arg_r:
p = makelongparameter (cr16_allWords,
p = makelongparameter (cr16_allWords,
inst_bit_size - (start_bits + a->size),
inst_bit_size - start_bits);
a->r = p.val;
@ -386,7 +386,7 @@ make_argument (argument * a, int start_bits)
break;
case arg_ic:
p = makelongparameter (cr16_allWords,
p = makelongparameter (cr16_allWords,
inst_bit_size - (start_bits + a->size),
inst_bit_size - start_bits);
a->constant = p.val;
@ -466,7 +466,7 @@ make_argument (argument * a, int start_bits)
}
else if (instruction->size == 2)
{
p = makelongparameter (cr16_allWords, inst_bit_size - 16,
p = makelongparameter (cr16_allWords, inst_bit_size - 16,
inst_bit_size);
a->constant = p.val;
}
@ -795,7 +795,7 @@ get_words_at_PC (bfd_vma memaddr, struct disassemble_info *info)
for (i = 0, mem = memaddr; i < 3; i++, mem += 2)
cr16_words[i] = get_word_at_PC (mem, info);
cr16_allWords = ((ULONGLONG) cr16_words[0] << 32)
cr16_allWords = ((ULONGLONG) cr16_words[0] << 32)
+ ((unsigned long) cr16_words[1] << 16) + cr16_words[2];
}

2
opcodes/cris-dis.c
View File

@ -813,7 +813,7 @@ print_with_operands (const struct cris_opcode *opcodep,
*tp++ = 'c';
*tp++ = 'r';
break;
case '[':
case ']':
case ',':

12
opcodes/crx-dis.c
View File

@ -60,9 +60,9 @@ cinv_entry;
/* CRX 'cinv' options. */
const cinv_entry crx_cinvs[] =
{
{"[i]", 2}, {"[i,u]", 3}, {"[d]", 4}, {"[d,u]", 5},
{"[d,i]", 6}, {"[d,i,u]", 7}, {"[b]", 8},
{"[b,i]", 10}, {"[b,i,u]", 11}, {"[b,d]", 12},
{"[i]", 2}, {"[i,u]", 3}, {"[d]", 4}, {"[d,u]", 5},
{"[d,i]", 6}, {"[d,i,u]", 7}, {"[b]", 8},
{"[b,i]", 10}, {"[b,i,u]", 11}, {"[b,d]", 12},
{"[b,d,u]", 13}, {"[b,d,i]", 14}, {"[b,d,i,u]", 15}
};
@ -76,7 +76,7 @@ typedef enum REG_ARG_TYPE
/* CO-Processor register (c<N>). */
COP_ARG,
/* CO-Processor special register (cs<N>). */
COPS_ARG
COPS_ARG
}
REG_ARG_TYPE;
@ -534,8 +534,8 @@ print_arg (argument *a, bfd_vma memaddr, struct disassemble_info *info)
else if (INST_HAS_REG_LIST)
{
REG_ARG_TYPE reg_arg_type = IS_INSN_TYPE (COP_REG_INS) ?
COP_ARG : IS_INSN_TYPE (COPS_REG_INS) ?
REG_ARG_TYPE reg_arg_type = IS_INSN_TYPE (COP_REG_INS) ?
COP_ARG : IS_INSN_TYPE (COPS_REG_INS) ?
COPS_ARG : (instruction->flags & USER_REG) ?
USER_REG_ARG : REG_ARG;

2
opcodes/d10v-opc.c
View File

@ -89,7 +89,7 @@ const struct pd_reg d10v_predefined_registers[] =
{ "sp", NULL, OPERAND_SP|(OPERAND_GPR+15) },
};
int
int
d10v_reg_name_cnt (void)
{
return (sizeof(d10v_predefined_registers) / sizeof(struct pd_reg));

2
opcodes/d30v-opc.c
View File

@ -194,7 +194,7 @@ const struct pd_reg pre_defined_registers[] =
{ "va", NULL, OPERAND_FLAG + 6 },
};
int
int
reg_name_cnt (void)
{
return sizeof (pre_defined_registers) / sizeof (struct pd_reg);

2
opcodes/dis-buf.c
View File

@ -33,7 +33,7 @@ buffer_read_memory (bfd_vma memaddr,
{
unsigned int opb = info->octets_per_byte;
unsigned int end_addr_offset = length / opb;
unsigned int max_addr_offset = info->buffer_length / opb;
unsigned int max_addr_offset = info->buffer_length / opb;
unsigned int octets = (memaddr - info->buffer_vma) * opb;
if (memaddr < info->buffer_vma

2
opcodes/dlx-dis.c
View File

@ -295,7 +295,7 @@ dlx_aluI_type (struct disassemble_info* info)
{ OPC(SGTUIOP), "sgtui" }, /* Store word. */
{ OPC(SLEUIOP), "sleui" }, /* Store word. */
{ OPC(SGEUIOP), "sgeui" }, /* Store word. */
#if 0
#if 0
{ OPC(MVTSOP), "mvts" }, /* Store word. */
{ OPC(MVFSOP), "mvfs" }, /* Store word. */
#endif

38
opcodes/epiphany-asm.c
View File

@ -458,7 +458,7 @@ epiphany_cgen_parse_operand (CGEN_CPU_DESC cd,
return errmsg;
}
cgen_parse_fn * const epiphany_cgen_parse_handlers[] =
cgen_parse_fn * const epiphany_cgen_parse_handlers[] =
{
parse_insn_normal,
};
@ -488,9 +488,9 @@ CGEN_ASM_INIT_HOOK
Returns NULL for success, an error message for failure. */
char *
char *
epiphany_cgen_build_insn_regex (CGEN_INSN *insn)
{
{
CGEN_OPCODE *opc = (CGEN_OPCODE *) CGEN_INSN_OPCODE (insn);
const char *mnem = CGEN_INSN_MNEMONIC (insn);
char rxbuf[CGEN_MAX_RX_ELEMENTS];
@ -529,18 +529,18 @@ epiphany_cgen_build_insn_regex (CGEN_INSN *insn)
/* Copy any remaining literals from the syntax string into the rx. */
for(; * syn != 0 && rx <= rxbuf + (CGEN_MAX_RX_ELEMENTS - 7 - 4); ++syn)
{
if (CGEN_SYNTAX_CHAR_P (* syn))
if (CGEN_SYNTAX_CHAR_P (* syn))
{
char c = CGEN_SYNTAX_CHAR (* syn);
switch (c)
switch (c)
{
/* Escape any regex metacharacters in the syntax. */
case '.': case '[': case '\\':
case '*': case '^': case '$':
case '.': case '[': case '\\':
case '*': case '^': case '$':
#ifdef CGEN_ESCAPE_EXTENDED_REGEX
case '?': case '{': case '}':
case '?': case '{': case '}':
case '(': case ')': case '*':
case '|': case '+': case ']':
#endif
@ -570,20 +570,20 @@ epiphany_cgen_build_insn_regex (CGEN_INSN *insn)
}
/* Trailing whitespace ok. */
* rx++ = '[';
* rx++ = ' ';
* rx++ = '\t';
* rx++ = ']';
* rx++ = '*';
* rx++ = '[';
* rx++ = ' ';
* rx++ = '\t';
* rx++ = ']';
* rx++ = '*';
/* But anchor it after that. */
* rx++ = '$';
* rx++ = '$';
* rx = '\0';
CGEN_INSN_RX (insn) = xmalloc (sizeof (regex_t));
reg_err = regcomp ((regex_t *) CGEN_INSN_RX (insn), rxbuf, REG_NOSUB);
if (reg_err == 0)
if (reg_err == 0)
return NULL;
else
{
@ -782,7 +782,7 @@ epiphany_cgen_assemble_insn (CGEN_CPU_DESC cd,
const CGEN_INSN *insn = ilist->insn;
recognized_mnemonic = 1;
#ifdef CGEN_VALIDATE_INSN_SUPPORTED
#ifdef CGEN_VALIDATE_INSN_SUPPORTED
/* Not usually needed as unsupported opcodes
shouldn't be in the hash lists. */
/* Is this insn supported by the selected cpu? */
@ -842,7 +842,7 @@ epiphany_cgen_assemble_insn (CGEN_CPU_DESC cd,
if (strlen (start) > 50)
/* xgettext:c-format */
sprintf (errbuf, "%s `%.50s...'", tmp_errmsg, start);
else
else
/* xgettext:c-format */
sprintf (errbuf, "%s `%.50s'", tmp_errmsg, start);
}
@ -851,11 +851,11 @@ epiphany_cgen_assemble_insn (CGEN_CPU_DESC cd,
if (strlen (start) > 50)
/* xgettext:c-format */
sprintf (errbuf, _("bad instruction `%.50s...'"), start);
else
else
/* xgettext:c-format */
sprintf (errbuf, _("bad instruction `%.50s'"), start);
}
*errmsg = errbuf;
return NULL;
}

186
opcodes/epiphany-desc.c
View File

@ -534,367 +534,367 @@ const CGEN_OPERAND epiphany_cgen_operand_table[] =
{
/* pc: program counter */
{ "pc", EPIPHANY_OPERAND_PC, HW_H_PC, 0, 0,
{ 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_NIL] } },
{ 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_NIL] } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* zbit: integer zero bit */
{ "zbit", EPIPHANY_OPERAND_ZBIT, HW_H_ZBIT, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* nbit: integer neg bit */
{ "nbit", EPIPHANY_OPERAND_NBIT, HW_H_NBIT, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* cbit: integer carry bit */
{ "cbit", EPIPHANY_OPERAND_CBIT, HW_H_CBIT, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* vbit: integer overflow bit */
{ "vbit", EPIPHANY_OPERAND_VBIT, HW_H_VBIT, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* bzbit: floating point zero bit */
{ "bzbit", EPIPHANY_OPERAND_BZBIT, HW_H_BZBIT, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* bnbit: floating point neg bit */
{ "bnbit", EPIPHANY_OPERAND_BNBIT, HW_H_BNBIT, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* bvbit: floating point ovfl bit */
{ "bvbit", EPIPHANY_OPERAND_BVBIT, HW_H_BVBIT, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* bcbit: floating point carry bit */
{ "bcbit", EPIPHANY_OPERAND_BCBIT, HW_H_BCBIT, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* bubit: floating point underfl bit */
{ "bubit", EPIPHANY_OPERAND_BUBIT, HW_H_BUBIT, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* bibit: floating point invalid bit */
{ "bibit", EPIPHANY_OPERAND_BIBIT, HW_H_BIBIT, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* vsbit: integer overflow sticky */
{ "vsbit", EPIPHANY_OPERAND_VSBIT, HW_H_VSBIT, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* bvsbit: floating point overflow sticky */
{ "bvsbit", EPIPHANY_OPERAND_BVSBIT, HW_H_BVSBIT, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* bisbit: floating point invalid sticky */
{ "bisbit", EPIPHANY_OPERAND_BISBIT, HW_H_BISBIT, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* busbit: floating point underflow sticky */
{ "busbit", EPIPHANY_OPERAND_BUSBIT, HW_H_BUSBIT, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* expcause0bit: exceprion cause bit0 */
{ "expcause0bit", EPIPHANY_OPERAND_EXPCAUSE0BIT, HW_H_EXPCAUSE0BIT, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* expcause1bit: exceprion cause bit1 */
{ "expcause1bit", EPIPHANY_OPERAND_EXPCAUSE1BIT, HW_H_EXPCAUSE1BIT, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* expcause2bit: external load stalled bit */
{ "expcause2bit", EPIPHANY_OPERAND_EXPCAUSE2BIT, HW_H_EXPCAUSE2BIT, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* extFstallbit: external fetch stalled bit */
{ "extFstallbit", EPIPHANY_OPERAND_EXTFSTALLBIT, HW_H_EXTFSTALLBIT, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* trmbit: 0=round to nearest, 1=trunacte selct bit */
{ "trmbit", EPIPHANY_OPERAND_TRMBIT, HW_H_TRMBIT, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* invExcEnbit: invalid exception enable bit */
{ "invExcEnbit", EPIPHANY_OPERAND_INVEXCENBIT, HW_H_INVEXCENBIT, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* ovfExcEnbit: overflow exception enable bit */
{ "ovfExcEnbit", EPIPHANY_OPERAND_OVFEXCENBIT, HW_H_OVFEXCENBIT, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* unExcEnbit: underflow exception enable bit */
{ "unExcEnbit", EPIPHANY_OPERAND_UNEXCENBIT, HW_H_UNEXCENBIT, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* timer0bit0: timer 0 mode selection 0 */
{ "timer0bit0", EPIPHANY_OPERAND_TIMER0BIT0, HW_H_TIMER0BIT0, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* timer0bit1: timer 0 mode selection 1 */
{ "timer0bit1", EPIPHANY_OPERAND_TIMER0BIT1, HW_H_TIMER0BIT1, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* timer0bit2: timer 0 mode selection 2 */
{ "timer0bit2", EPIPHANY_OPERAND_TIMER0BIT2, HW_H_TIMER0BIT2, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* timer0bit3: timer 0 mode selection 3 */
{ "timer0bit3", EPIPHANY_OPERAND_TIMER0BIT3, HW_H_TIMER0BIT3, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* timer1bit0: timer 1 mode selection 0 */
{ "timer1bit0", EPIPHANY_OPERAND_TIMER1BIT0, HW_H_TIMER1BIT0, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* timer1bit1: timer 1 mode selection 1 */
{ "timer1bit1", EPIPHANY_OPERAND_TIMER1BIT1, HW_H_TIMER1BIT1, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* timer1bit2: timer 1 mode selection 2 */
{ "timer1bit2", EPIPHANY_OPERAND_TIMER1BIT2, HW_H_TIMER1BIT2, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* timer1bit3: timer 1 mode selection 3 */
{ "timer1bit3", EPIPHANY_OPERAND_TIMER1BIT3, HW_H_TIMER1BIT3, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* mbkptEnbit: multicore bkpt enable */
{ "mbkptEnbit", EPIPHANY_OPERAND_MBKPTENBIT, HW_H_MBKPTENBIT, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* clockGateEnbit: clock gate enable enable */
{ "clockGateEnbit", EPIPHANY_OPERAND_CLOCKGATEENBIT, HW_H_CLOCKGATEENBIT, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* arithmetic-modebit0: arithmetic mode bit0 */
{ "arithmetic-modebit0", EPIPHANY_OPERAND_ARITHMETIC_MODEBIT0, HW_H_ARITHMETIC_MODEBIT0, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* arithmetic-modebit1: arithmetic mode bit1 */
{ "arithmetic-modebit1", EPIPHANY_OPERAND_ARITHMETIC_MODEBIT1, HW_H_ARITHMETIC_MODEBIT1, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* arithmetic-modebit2: arithmetic mode bit2 */
{ "arithmetic-modebit2", EPIPHANY_OPERAND_ARITHMETIC_MODEBIT2, HW_H_ARITHMETIC_MODEBIT2, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* coreCfgResBit12: core config bit 12 */
{ "coreCfgResBit12", EPIPHANY_OPERAND_CORECFGRESBIT12, HW_H_CORECFGRESBIT12, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* coreCfgResBit13: core config bit 13 */
{ "coreCfgResBit13", EPIPHANY_OPERAND_CORECFGRESBIT13, HW_H_CORECFGRESBIT13, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* coreCfgResBit14: core config bit 14 */
{ "coreCfgResBit14", EPIPHANY_OPERAND_CORECFGRESBIT14, HW_H_CORECFGRESBIT14, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* coreCfgResBit15: core config bit 15 */
{ "coreCfgResBit15", EPIPHANY_OPERAND_CORECFGRESBIT15, HW_H_CORECFGRESBIT15, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* coreCfgResBit16: core config bit 16 */
{ "coreCfgResBit16", EPIPHANY_OPERAND_CORECFGRESBIT16, HW_H_CORECFGRESBIT16, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* coreCfgResBit20: core config bit 20 */
{ "coreCfgResBit20", EPIPHANY_OPERAND_CORECFGRESBIT20, HW_H_CORECFGRESBIT20, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* coreCfgResBit21: core config bit 21 */
{ "coreCfgResBit21", EPIPHANY_OPERAND_CORECFGRESBIT21, HW_H_CORECFGRESBIT21, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* coreCfgResBit24: core config bit 24 */
{ "coreCfgResBit24", EPIPHANY_OPERAND_CORECFGRESBIT24, HW_H_CORECFGRESBIT24, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* coreCfgResBit25: core config bit 25 */
{ "coreCfgResBit25", EPIPHANY_OPERAND_CORECFGRESBIT25, HW_H_CORECFGRESBIT25, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* coreCfgResBit26: core config bit 26 */
{ "coreCfgResBit26", EPIPHANY_OPERAND_CORECFGRESBIT26, HW_H_CORECFGRESBIT26, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* coreCfgResBit27: core config bit 27 */
{ "coreCfgResBit27", EPIPHANY_OPERAND_CORECFGRESBIT27, HW_H_CORECFGRESBIT27, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* coreCfgResBit28: core config bit 28 */
{ "coreCfgResBit28", EPIPHANY_OPERAND_CORECFGRESBIT28, HW_H_CORECFGRESBIT28, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* coreCfgResBit29: core config bit 29 */
{ "coreCfgResBit29", EPIPHANY_OPERAND_CORECFGRESBIT29, HW_H_CORECFGRESBIT29, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* coreCfgResBit30: core config bit 30 */
{ "coreCfgResBit30", EPIPHANY_OPERAND_CORECFGRESBIT30, HW_H_CORECFGRESBIT30, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* coreCfgResBit31: core config bit 31 */
{ "coreCfgResBit31", EPIPHANY_OPERAND_CORECFGRESBIT31, HW_H_CORECFGRESBIT31, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* gidisablebit: global interrupt disable bit */
{ "gidisablebit", EPIPHANY_OPERAND_GIDISABLEBIT, HW_H_GIDISABLEBIT, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* kmbit: kernel mode bit */
{ "kmbit", EPIPHANY_OPERAND_KMBIT, HW_H_KMBIT, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* caibit: core actibe indicator bit */
{ "caibit", EPIPHANY_OPERAND_CAIBIT, HW_H_CAIBIT, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* sflagbit: sflag bit */
{ "sflagbit", EPIPHANY_OPERAND_SFLAGBIT, HW_H_SFLAGBIT, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* memaddr: memory effective address */
{ "memaddr", EPIPHANY_OPERAND_MEMADDR, HW_H_MEMADDR, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* simm24: branch address pc-relative */
{ "simm24", EPIPHANY_OPERAND_SIMM24, HW_H_IADDR, 31, 24,
{ 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_SIMM24] } },
{ 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_SIMM24] } },
{ 0|A(RELAX)|A(RELOC)|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } } },
/* simm8: branch address pc-relative */
{ "simm8", EPIPHANY_OPERAND_SIMM8, HW_H_IADDR, 15, 8,
{ 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_SIMM8] } },
{ 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_SIMM8] } },
{ 0|A(RELAX)|A(RELOC)|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } } },
/* rd: destination register */
{ "rd", EPIPHANY_OPERAND_RD, HW_H_REGISTERS, 15, 3,
{ 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_RD] } },
{ 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_RD] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* rn: source register */
{ "rn", EPIPHANY_OPERAND_RN, HW_H_REGISTERS, 12, 3,
{ 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_RN] } },
{ 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_RN] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* rm: source register */
{ "rm", EPIPHANY_OPERAND_RM, HW_H_REGISTERS, 9, 3,
{ 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_RM] } },
{ 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_RM] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* frd: fp destination register */
{ "frd", EPIPHANY_OPERAND_FRD, HW_H_FPREGISTERS, 15, 3,
{ 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_RD] } },
{ 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_RD] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* frn: fp source register */
{ "frn", EPIPHANY_OPERAND_FRN, HW_H_FPREGISTERS, 12, 3,
{ 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_RN] } },
{ 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_RN] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* frm: fp source register */
{ "frm", EPIPHANY_OPERAND_FRM, HW_H_FPREGISTERS, 9, 3,
{ 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_RM] } },
{ 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_RM] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* rd6: destination register */
{ "rd6", EPIPHANY_OPERAND_RD6, HW_H_REGISTERS, 15, 6,
{ 2, { (const PTR) &EPIPHANY_F_RD6_MULTI_IFIELD[0] } },
{ 2, { (const PTR) &EPIPHANY_F_RD6_MULTI_IFIELD[0] } },
{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
/* rn6: source register */
{ "rn6", EPIPHANY_OPERAND_RN6, HW_H_REGISTERS, 12, 6,
{ 2, { (const PTR) &EPIPHANY_F_RN6_MULTI_IFIELD[0] } },
{ 2, { (const PTR) &EPIPHANY_F_RN6_MULTI_IFIELD[0] } },
{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
/* rm6: source register */
{ "rm6", EPIPHANY_OPERAND_RM6, HW_H_REGISTERS, 9, 6,
{ 2, { (const PTR) &EPIPHANY_F_RM6_MULTI_IFIELD[0] } },
{ 2, { (const PTR) &EPIPHANY_F_RM6_MULTI_IFIELD[0] } },
{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
/* frd6: fp destination register */
{ "frd6", EPIPHANY_OPERAND_FRD6, HW_H_FPREGISTERS, 15, 6,
{ 2, { (const PTR) &EPIPHANY_F_RD6_MULTI_IFIELD[0] } },
{ 2, { (const PTR) &EPIPHANY_F_RD6_MULTI_IFIELD[0] } },
{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
/* frn6: fp source register */
{ "frn6", EPIPHANY_OPERAND_FRN6, HW_H_FPREGISTERS, 12, 6,
{ 2, { (const PTR) &EPIPHANY_F_RN6_MULTI_IFIELD[0] } },
{ 2, { (const PTR) &EPIPHANY_F_RN6_MULTI_IFIELD[0] } },
{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
/* frm6: fp source register */
{ "frm6", EPIPHANY_OPERAND_FRM6, HW_H_FPREGISTERS, 9, 6,
{ 2, { (const PTR) &EPIPHANY_F_RM6_MULTI_IFIELD[0] } },
{ 2, { (const PTR) &EPIPHANY_F_RM6_MULTI_IFIELD[0] } },
{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
/* sd: special destination */
{ "sd", EPIPHANY_OPERAND_SD, HW_H_CORE_REGISTERS, 15, 3,
{ 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_SD] } },
{ 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_SD] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* sn: special source */
{ "sn", EPIPHANY_OPERAND_SN, HW_H_CORE_REGISTERS, 12, 3,
{ 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_SN] } },
{ 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_SN] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* sd6: special destination register */
{ "sd6", EPIPHANY_OPERAND_SD6, HW_H_CORE_REGISTERS, 15, 6,
{ 2, { (const PTR) &EPIPHANY_F_SD6_MULTI_IFIELD[0] } },
{ 2, { (const PTR) &EPIPHANY_F_SD6_MULTI_IFIELD[0] } },
{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
/* sn6: special source register */
{ "sn6", EPIPHANY_OPERAND_SN6, HW_H_CORE_REGISTERS, 12, 6,
{ 2, { (const PTR) &EPIPHANY_F_SN6_MULTI_IFIELD[0] } },
{ 2, { (const PTR) &EPIPHANY_F_SN6_MULTI_IFIELD[0] } },
{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
/* sddma: dma register */
{ "sddma", EPIPHANY_OPERAND_SDDMA, HW_H_COREDMA_REGISTERS, 15, 6,
{ 2, { (const PTR) &EPIPHANY_F_SD6_MULTI_IFIELD[0] } },
{ 2, { (const PTR) &EPIPHANY_F_SD6_MULTI_IFIELD[0] } },
{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
/* sndma: dma register */
{ "sndma", EPIPHANY_OPERAND_SNDMA, HW_H_COREDMA_REGISTERS, 12, 6,
{ 2, { (const PTR) &EPIPHANY_F_SN6_MULTI_IFIELD[0] } },
{ 2, { (const PTR) &EPIPHANY_F_SN6_MULTI_IFIELD[0] } },
{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
/* sdmem: mem register */
{ "sdmem", EPIPHANY_OPERAND_SDMEM, HW_H_COREMEM_REGISTERS, 15, 6,
{ 2, { (const PTR) &EPIPHANY_F_SD6_MULTI_IFIELD[0] } },
{ 2, { (const PTR) &EPIPHANY_F_SD6_MULTI_IFIELD[0] } },
{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
/* snmem: mem register */
{ "snmem", EPIPHANY_OPERAND_SNMEM, HW_H_COREMEM_REGISTERS, 12, 6,
{ 2, { (const PTR) &EPIPHANY_F_SN6_MULTI_IFIELD[0] } },
{ 2, { (const PTR) &EPIPHANY_F_SN6_MULTI_IFIELD[0] } },
{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
/* sdmesh: mesh register */
{ "sdmesh", EPIPHANY_OPERAND_SDMESH, HW_H_COREMESH_REGISTERS, 15, 6,
{ 2, { (const PTR) &EPIPHANY_F_SD6_MULTI_IFIELD[0] } },
{ 2, { (const PTR) &EPIPHANY_F_SD6_MULTI_IFIELD[0] } },
{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
/* snmesh: mesh register */
{ "snmesh", EPIPHANY_OPERAND_SNMESH, HW_H_COREMESH_REGISTERS, 12, 6,
{ 2, { (const PTR) &EPIPHANY_F_SN6_MULTI_IFIELD[0] } },
{ 2, { (const PTR) &EPIPHANY_F_SN6_MULTI_IFIELD[0] } },
{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
/* simm3: signed 3-bit literal */
{ "simm3", EPIPHANY_OPERAND_SIMM3, HW_H_SINT, 9, 3,
{ 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_SDISP3] } },
{ 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_SDISP3] } },
{ 0|A(RELAX), { { { (1<<MACH_BASE), 0 } } } } },
/* simm11: signed 11-bit literal */
{ "simm11", EPIPHANY_OPERAND_SIMM11, HW_H_SINT, 9, 11,
{ 2, { (const PTR) &EPIPHANY_F_SDISP11_MULTI_IFIELD[0] } },
{ 2, { (const PTR) &EPIPHANY_F_SDISP11_MULTI_IFIELD[0] } },
{ 0|A(RELAX)|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
/* disp3: short data displacement */
{ "disp3", EPIPHANY_OPERAND_DISP3, HW_H_UINT, 9, 3,
{ 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_DISP3] } },
{ 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_DISP3] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* trapnum6: parameter for swi or trap */
{ "trapnum6", EPIPHANY_OPERAND_TRAPNUM6, HW_H_UINT, 15, 6,
{ 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_TRAP_NUM] } },
{ 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_TRAP_NUM] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* swi_num: unsigned 6-bit swi# */
{ "swi_num", EPIPHANY_OPERAND_SWI_NUM, HW_H_UINT, 15, 6,
{ 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_TRAP_NUM] } },
{ 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_TRAP_NUM] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* disp11: sign-magnitude data displacement */
{ "disp11", EPIPHANY_OPERAND_DISP11, HW_H_UINT, 9, 11,
{ 2, { (const PTR) &EPIPHANY_F_DISP11_MULTI_IFIELD[0] } },
{ 2, { (const PTR) &EPIPHANY_F_DISP11_MULTI_IFIELD[0] } },
{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
/* shift: immediate shift amount */
{ "shift", EPIPHANY_OPERAND_SHIFT, HW_H_UINT, 9, 5,
{ 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_SHIFT] } },
{ 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_SHIFT] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* imm16: 16-bit unsigned literal */
{ "imm16", EPIPHANY_OPERAND_IMM16, HW_H_ADDR, 12, 16,
{ 2, { (const PTR) &EPIPHANY_F_IMM16_MULTI_IFIELD[0] } },
{ 2, { (const PTR) &EPIPHANY_F_IMM16_MULTI_IFIELD[0] } },
{ 0|A(RELAX)|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
/* imm8: 8-bit unsigned literal */
{ "imm8", EPIPHANY_OPERAND_IMM8, HW_H_ADDR, 12, 8,
{ 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_IMM8] } },
{ 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_IMM8] } },
{ 0|A(RELAX), { { { (1<<MACH_BASE), 0 } } } } },
/* direction: +/- indexing */
{ "direction", EPIPHANY_OPERAND_DIRECTION, HW_H_UINT, 20, 1,
{ 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_ADDSUBX] } },
{ 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_ADDSUBX] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* dpmi: +/- magnitude immediate displacement */
{ "dpmi", EPIPHANY_OPERAND_DPMI, HW_H_UINT, 24, 1,
{ 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_SUBD] } },
{ 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_SUBD] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* sentinel */
{ 0, 0, 0, 0, 0,
@ -2212,7 +2212,7 @@ epiphany_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...)
/* Default to not allowing signed overflow. */
cd->signed_overflow_ok_p = 0;
return (CGEN_CPU_DESC) cd;
}
@ -2252,7 +2252,7 @@ epiphany_cgen_cpu_close (CGEN_CPU_DESC cd)
for (i = 0; i < cd->insn_table.num_init_entries; ++i, ++insns)
if (CGEN_INSN_RX (insns))
regfree (CGEN_INSN_RX (insns));
}
}
if (cd->macro_insn_table.init_entries)
free ((CGEN_INSN *) cd->macro_insn_table.init_entries);

10
opcodes/epiphany-dis.c
View File

@ -279,7 +279,7 @@ epiphany_cgen_print_operand (CGEN_CPU_DESC cd,
}
}
cgen_print_fn * const epiphany_cgen_print_handlers[] =
cgen_print_fn * const epiphany_cgen_print_handlers[] =
{
print_insn_normal,
};
@ -469,7 +469,7 @@ print_insn (CGEN_CPU_DESC cd,
int length;
unsigned long insn_value_cropped;
#ifdef CGEN_VALIDATE_INSN_SUPPORTED
#ifdef CGEN_VALIDATE_INSN_SUPPORTED
/* Not needed as insn shouldn't be in hash lists if not supported. */
/* Supported by this cpu? */
if (! epiphany_cgen_insn_supported (cd, insn))
@ -487,7 +487,7 @@ print_insn (CGEN_CPU_DESC cd,
relevant part from the buffer. */
if ((unsigned) (CGEN_INSN_BITSIZE (insn) / 8) < buflen &&
(unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long))
insn_value_cropped = bfd_get_bits (buf, CGEN_INSN_BITSIZE (insn),
insn_value_cropped = bfd_get_bits (buf, CGEN_INSN_BITSIZE (insn),
info->endian == BFD_ENDIAN_BIG);
else
insn_value_cropped = insn_value;
@ -606,7 +606,7 @@ print_insn_epiphany (bfd_vma pc, disassemble_info *info)
arch = info->arch;
if (arch == bfd_arch_unknown)
arch = CGEN_BFD_ARCH;
/* There's no standard way to compute the machine or isa number
so we leave it to the target. */
#ifdef CGEN_COMPUTE_MACH
@ -647,7 +647,7 @@ print_insn_epiphany (bfd_vma pc, disassemble_info *info)
break;
}
}
}
}
/* If we haven't initialized yet, initialize the opcode table. */
if (! cd)

8
opcodes/epiphany-ibld.c
View File

@ -154,7 +154,7 @@ insert_normal (CGEN_CPU_DESC cd,
{
long minval = - (1L << (length - 1));
unsigned long maxval = mask;
if ((value > 0 && (unsigned long) value > maxval)
|| value < minval)
{
@ -192,7 +192,7 @@ insert_normal (CGEN_CPU_DESC cd,
{
long minval = - (1L << (length - 1));
long maxval = (1L << (length - 1)) - 1;
if (value < minval || value > maxval)
{
sprintf
@ -1170,12 +1170,12 @@ epiphany_cgen_extract_operand (CGEN_CPU_DESC cd,
return length;
}
cgen_insert_fn * const epiphany_cgen_insert_handlers[] =
cgen_insert_fn * const epiphany_cgen_insert_handlers[] =
{
insert_insn_normal,
};
cgen_extract_fn * const epiphany_cgen_extract_handlers[] =
cgen_extract_fn * const epiphany_cgen_extract_handlers[] =
{
extract_insn_normal,
};

38
opcodes/fr30-asm.c
View File

@ -313,7 +313,7 @@ fr30_cgen_parse_operand (CGEN_CPU_DESC cd,
return errmsg;
}
cgen_parse_fn * const fr30_cgen_parse_handlers[] =
cgen_parse_fn * const fr30_cgen_parse_handlers[] =
{
parse_insn_normal,
};
@ -343,9 +343,9 @@ CGEN_ASM_INIT_HOOK
Returns NULL for success, an error message for failure. */
char *
char *
fr30_cgen_build_insn_regex (CGEN_INSN *insn)
{
{
CGEN_OPCODE *opc = (CGEN_OPCODE *) CGEN_INSN_OPCODE (insn);
const char *mnem = CGEN_INSN_MNEMONIC (insn);
char rxbuf[CGEN_MAX_RX_ELEMENTS];
@ -384,18 +384,18 @@ fr30_cgen_build_insn_regex (CGEN_INSN *insn)
/* Copy any remaining literals from the syntax string into the rx. */
for(; * syn != 0 && rx <= rxbuf + (CGEN_MAX_RX_ELEMENTS - 7 - 4); ++syn)
{
if (CGEN_SYNTAX_CHAR_P (* syn))
if (CGEN_SYNTAX_CHAR_P (* syn))
{
char c = CGEN_SYNTAX_CHAR (* syn);
switch (c)
switch (c)
{
/* Escape any regex metacharacters in the syntax. */
case '.': case '[': case '\\':
case '*': case '^': case '$':
case '.': case '[': case '\\':
case '*': case '^': case '$':
#ifdef CGEN_ESCAPE_EXTENDED_REGEX
case '?': case '{': case '}':
case '?': case '{': case '}':
case '(': case ')': case '*':
case '|': case '+': case ']':
#endif
@ -425,20 +425,20 @@ fr30_cgen_build_insn_regex (CGEN_INSN *insn)
}
/* Trailing whitespace ok. */
* rx++ = '[';
* rx++ = ' ';
* rx++ = '\t';
* rx++ = ']';
* rx++ = '*';
* rx++ = '[';
* rx++ = ' ';
* rx++ = '\t';
* rx++ = ']';
* rx++ = '*';
/* But anchor it after that. */
* rx++ = '$';
* rx++ = '$';
* rx = '\0';
CGEN_INSN_RX (insn) = xmalloc (sizeof (regex_t));
reg_err = regcomp ((regex_t *) CGEN_INSN_RX (insn), rxbuf, REG_NOSUB);
if (reg_err == 0)
if (reg_err == 0)
return NULL;
else
{
@ -637,7 +637,7 @@ fr30_cgen_assemble_insn (CGEN_CPU_DESC cd,
const CGEN_INSN *insn = ilist->insn;
recognized_mnemonic = 1;
#ifdef CGEN_VALIDATE_INSN_SUPPORTED
#ifdef CGEN_VALIDATE_INSN_SUPPORTED
/* Not usually needed as unsupported opcodes
shouldn't be in the hash lists. */
/* Is this insn supported by the selected cpu? */
@ -697,7 +697,7 @@ fr30_cgen_assemble_insn (CGEN_CPU_DESC cd,
if (strlen (start) > 50)
/* xgettext:c-format */
sprintf (errbuf, "%s `%.50s...'", tmp_errmsg, start);
else
else
/* xgettext:c-format */
sprintf (errbuf, "%s `%.50s'", tmp_errmsg, start);
}
@ -706,11 +706,11 @@ fr30_cgen_assemble_insn (CGEN_CPU_DESC cd,
if (strlen (start) > 50)
/* xgettext:c-format */
sprintf (errbuf, _("bad instruction `%.50s...'"), start);
else
else
/* xgettext:c-format */
sprintf (errbuf, _("bad instruction `%.50s'"), start);
}
*errmsg = errbuf;
return NULL;
}

102
opcodes/fr30-desc.c
View File

@ -364,199 +364,199 @@ const CGEN_OPERAND fr30_cgen_operand_table[] =
{
/* pc: program counter */
{ "pc", FR30_OPERAND_PC, HW_H_PC, 0, 0,
{ 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_NIL] } },
{ 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_NIL] } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* Ri: destination register */
{ "Ri", FR30_OPERAND_RI, HW_H_GR, 12, 4,
{ 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_RI] } },
{ 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_RI] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* Rj: source register */
{ "Rj", FR30_OPERAND_RJ, HW_H_GR, 8, 4,
{ 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_RJ] } },
{ 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_RJ] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* Ric: target register coproc insn */
{ "Ric", FR30_OPERAND_RIC, HW_H_GR, 12, 4,
{ 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_RIC] } },
{ 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_RIC] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* Rjc: source register coproc insn */
{ "Rjc", FR30_OPERAND_RJC, HW_H_GR, 8, 4,
{ 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_RJC] } },
{ 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_RJC] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* CRi: coprocessor register */
{ "CRi", FR30_OPERAND_CRI, HW_H_CR, 12, 4,
{ 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_CRI] } },
{ 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_CRI] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* CRj: coprocessor register */
{ "CRj", FR30_OPERAND_CRJ, HW_H_CR, 8, 4,
{ 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_CRJ] } },
{ 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_CRJ] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* Rs1: dedicated register */
{ "Rs1", FR30_OPERAND_RS1, HW_H_DR, 8, 4,
{ 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_RS1] } },
{ 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_RS1] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* Rs2: dedicated register */
{ "Rs2", FR30_OPERAND_RS2, HW_H_DR, 12, 4,
{ 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_RS2] } },
{ 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_RS2] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* R13: General Register 13 */
{ "R13", FR30_OPERAND_R13, HW_H_R13, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { (const PTR) 0 } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* R14: General Register 14 */
{ "R14", FR30_OPERAND_R14, HW_H_R14, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { (const PTR) 0 } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* R15: General Register 15 */
{ "R15", FR30_OPERAND_R15, HW_H_R15, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { (const PTR) 0 } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* ps: Program Status register */
{ "ps", FR30_OPERAND_PS, HW_H_PS, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { (const PTR) 0 } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* u4: 4 bit unsigned immediate */
{ "u4", FR30_OPERAND_U4, HW_H_UINT, 8, 4,
{ 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_U4] } },
{ 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_U4] } },
{ 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } },
/* u4c: 4 bit unsigned immediate */
{ "u4c", FR30_OPERAND_U4C, HW_H_UINT, 12, 4,
{ 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_U4C] } },
{ 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_U4C] } },
{ 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } },
/* u8: 8 bit unsigned immediate */
{ "u8", FR30_OPERAND_U8, HW_H_UINT, 8, 8,
{ 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_U8] } },
{ 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_U8] } },
{ 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } },
/* i8: 8 bit unsigned immediate */
{ "i8", FR30_OPERAND_I8, HW_H_UINT, 4, 8,
{ 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_I8] } },
{ 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_I8] } },
{ 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } },
/* udisp6: 6 bit unsigned immediate */
{ "udisp6", FR30_OPERAND_UDISP6, HW_H_UINT, 8, 4,
{ 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_UDISP6] } },
{ 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_UDISP6] } },
{ 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } },
/* disp8: 8 bit signed immediate */
{ "disp8", FR30_OPERAND_DISP8, HW_H_SINT, 4, 8,
{ 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_DISP8] } },
{ 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_DISP8] } },
{ 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } },
/* disp9: 9 bit signed immediate */
{ "disp9", FR30_OPERAND_DISP9, HW_H_SINT, 4, 8,
{ 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_DISP9] } },
{ 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_DISP9] } },
{ 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } },
/* disp10: 10 bit signed immediate */
{ "disp10", FR30_OPERAND_DISP10, HW_H_SINT, 4, 8,
{ 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_DISP10] } },
{ 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_DISP10] } },
{ 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } },
/* s10: 10 bit signed immediate */
{ "s10", FR30_OPERAND_S10, HW_H_SINT, 8, 8,
{ 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_S10] } },
{ 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_S10] } },
{ 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } },
/* u10: 10 bit unsigned immediate */
{ "u10", FR30_OPERAND_U10, HW_H_UINT, 8, 8,
{ 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_U10] } },
{ 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_U10] } },
{ 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } },
/* i32: 32 bit immediate */
{ "i32", FR30_OPERAND_I32, HW_H_UINT, 0, 32,
{ 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_I32] } },
{ 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_I32] } },
{ 0|A(HASH_PREFIX)|A(SIGN_OPT), { { { (1<<MACH_BASE), 0 } } } } },
/* m4: 4 bit negative immediate */
{ "m4", FR30_OPERAND_M4, HW_H_SINT, 8, 4,
{ 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_M4] } },
{ 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_M4] } },
{ 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } },
/* i20: 20 bit immediate */
{ "i20", FR30_OPERAND_I20, HW_H_UINT, 0, 20,
{ 2, { (const PTR) &FR30_F_I20_MULTI_IFIELD[0] } },
{ 2, { (const PTR) &FR30_F_I20_MULTI_IFIELD[0] } },
{ 0|A(HASH_PREFIX)|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
/* dir8: 8 bit direct address */
{ "dir8", FR30_OPERAND_DIR8, HW_H_UINT, 8, 8,
{ 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_DIR8] } },
{ 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_DIR8] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* dir9: 9 bit direct address */
{ "dir9", FR30_OPERAND_DIR9, HW_H_UINT, 8, 8,
{ 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_DIR9] } },
{ 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_DIR9] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* dir10: 10 bit direct address */
{ "dir10", FR30_OPERAND_DIR10, HW_H_UINT, 8, 8,
{ 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_DIR10] } },
{ 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_DIR10] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* label9: 9 bit pc relative address */
{ "label9", FR30_OPERAND_LABEL9, HW_H_IADDR, 8, 8,
{ 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_REL9] } },
{ 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_REL9] } },
{ 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } } },
/* label12: 12 bit pc relative address */
{ "label12", FR30_OPERAND_LABEL12, HW_H_IADDR, 5, 11,
{ 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_REL12] } },
{ 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_REL12] } },
{ 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } } },
/* reglist_low_ld: 8 bit low register mask for ldm */
{ "reglist_low_ld", FR30_OPERAND_REGLIST_LOW_LD, HW_H_UINT, 8, 8,
{ 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_REGLIST_LOW_LD] } },
{ 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_REGLIST_LOW_LD] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* reglist_hi_ld: 8 bit high register mask for ldm */
{ "reglist_hi_ld", FR30_OPERAND_REGLIST_HI_LD, HW_H_UINT, 8, 8,
{ 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_REGLIST_HI_LD] } },
{ 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_REGLIST_HI_LD] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* reglist_low_st: 8 bit low register mask for stm */
{ "reglist_low_st", FR30_OPERAND_REGLIST_LOW_ST, HW_H_UINT, 8, 8,
{ 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_REGLIST_LOW_ST] } },
{ 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_REGLIST_LOW_ST] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* reglist_hi_st: 8 bit high register mask for stm */
{ "reglist_hi_st", FR30_OPERAND_REGLIST_HI_ST, HW_H_UINT, 8, 8,
{ 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_REGLIST_HI_ST] } },
{ 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_REGLIST_HI_ST] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* cc: condition codes */
{ "cc", FR30_OPERAND_CC, HW_H_UINT, 4, 4,
{ 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_CC] } },
{ 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_CC] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* ccc: coprocessor calc */
{ "ccc", FR30_OPERAND_CCC, HW_H_UINT, 0, 8,
{ 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_CCC] } },
{ 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_CCC] } },
{ 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } },
/* nbit: negative bit */
{ "nbit", FR30_OPERAND_NBIT, HW_H_NBIT, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* vbit: overflow bit */
{ "vbit", FR30_OPERAND_VBIT, HW_H_VBIT, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* zbit: zero bit */
{ "zbit", FR30_OPERAND_ZBIT, HW_H_ZBIT, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* cbit: carry bit */
{ "cbit", FR30_OPERAND_CBIT, HW_H_CBIT, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* ibit: interrupt bit */
{ "ibit", FR30_OPERAND_IBIT, HW_H_IBIT, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* sbit: stack bit */
{ "sbit", FR30_OPERAND_SBIT, HW_H_SBIT, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* tbit: trace trap bit */
{ "tbit", FR30_OPERAND_TBIT, HW_H_TBIT, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* d0bit: division 0 bit */
{ "d0bit", FR30_OPERAND_D0BIT, HW_H_D0BIT, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* d1bit: division 1 bit */
{ "d1bit", FR30_OPERAND_D1BIT, HW_H_D1BIT, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* ccr: condition code bits */
{ "ccr", FR30_OPERAND_CCR, HW_H_CCR, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* scr: system condition bits */
{ "scr", FR30_OPERAND_SCR, HW_H_SCR, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* ilm: interrupt level mask */
{ "ilm", FR30_OPERAND_ILM, HW_H_ILM, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* sentinel */
{ 0, 0, 0, 0, 0,
@ -1689,7 +1689,7 @@ fr30_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...)
/* Default to not allowing signed overflow. */
cd->signed_overflow_ok_p = 0;
return (CGEN_CPU_DESC) cd;
}
@ -1729,7 +1729,7 @@ fr30_cgen_cpu_close (CGEN_CPU_DESC cd)
for (i = 0; i < cd->insn_table.num_init_entries; ++i, ++insns)
if (CGEN_INSN_RX (insns))
regfree (CGEN_INSN_RX (insns));
}
}
if (cd->macro_insn_table.init_entries)
free ((CGEN_INSN *) cd->macro_insn_table.init_entries);

12
opcodes/fr30-dis.c
View File

@ -79,7 +79,7 @@ print_register_list (void * dis_info,
(*info->fprintf_func) (info->stream, "r%li", reg_index + offset);
comma = ",";
}
for (reg_index = 1; reg_index <= 7; ++reg_index)
{
if (load_store)
@ -301,7 +301,7 @@ fr30_cgen_print_operand (CGEN_CPU_DESC cd,
}
}
cgen_print_fn * const fr30_cgen_print_handlers[] =
cgen_print_fn * const fr30_cgen_print_handlers[] =
{
print_insn_normal,
};
@ -491,7 +491,7 @@ print_insn (CGEN_CPU_DESC cd,
int length;
unsigned long insn_value_cropped;
#ifdef CGEN_VALIDATE_INSN_SUPPORTED
#ifdef CGEN_VALIDATE_INSN_SUPPORTED
/* Not needed as insn shouldn't be in hash lists if not supported. */
/* Supported by this cpu? */
if (! fr30_cgen_insn_supported (cd, insn))
@ -509,7 +509,7 @@ print_insn (CGEN_CPU_DESC cd,
relevant part from the buffer. */
if ((unsigned) (CGEN_INSN_BITSIZE (insn) / 8) < buflen &&
(unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long))
insn_value_cropped = bfd_get_bits (buf, CGEN_INSN_BITSIZE (insn),
insn_value_cropped = bfd_get_bits (buf, CGEN_INSN_BITSIZE (insn),
info->endian == BFD_ENDIAN_BIG);
else
insn_value_cropped = insn_value;
@ -628,7 +628,7 @@ print_insn_fr30 (bfd_vma pc, disassemble_info *info)
arch = info->arch;
if (arch == bfd_arch_unknown)
arch = CGEN_BFD_ARCH;
/* There's no standard way to compute the machine or isa number
so we leave it to the target. */
#ifdef CGEN_COMPUTE_MACH
@ -669,7 +669,7 @@ print_insn_fr30 (bfd_vma pc, disassemble_info *info)
break;
}
}
}
}
/* If we haven't initialized yet, initialize the opcode table. */
if (! cd)

8
opcodes/fr30-ibld.c
View File

@ -154,7 +154,7 @@ insert_normal (CGEN_CPU_DESC cd,
{
long minval = - (1L << (length - 1));
unsigned long maxval = mask;
if ((value > 0 && (unsigned long) value > maxval)
|| value < minval)
{
@ -192,7 +192,7 @@ insert_normal (CGEN_CPU_DESC cd,
{
long minval = - (1L << (length - 1));
long maxval = (1L << (length - 1)) - 1;
if (value < minval || value > maxval)
{
sprintf
@ -936,12 +936,12 @@ fr30_cgen_extract_operand (CGEN_CPU_DESC cd,
return length;
}
cgen_insert_fn * const fr30_cgen_insert_handlers[] =
cgen_insert_fn * const fr30_cgen_insert_handlers[] =
{
insert_insn_normal,
};
cgen_extract_fn * const fr30_cgen_extract_handlers[] =
cgen_extract_fn * const fr30_cgen_extract_handlers[] =
{
extract_insn_normal,
};

66
opcodes/frv-asm.c
View File

@ -99,10 +99,10 @@ parse_ldd_annotation (CGEN_CPU_DESC cd,
return errmsg;
}
}
while (**strp == ' ' || **strp == '\t')
++*strp;
if (**strp != '@')
return "missing `@'";
@ -138,10 +138,10 @@ parse_call_annotation (CGEN_CPU_DESC cd,
return errmsg;
}
}
while (**strp == ' ' || **strp == '\t')
++*strp;
if (**strp != '@')
return "missing `@'";
@ -177,10 +177,10 @@ parse_ld_annotation (CGEN_CPU_DESC cd,
return errmsg;
}
}
while (**strp == ' ' || **strp == '\t')
++*strp;
if (**strp != '@')
return "missing `@'";
@ -198,7 +198,7 @@ parse_ulo16 (CGEN_CPU_DESC cd,
const char *errmsg;
enum cgen_parse_operand_result result_type;
bfd_vma value;
if (**strp == '#' || **strp == '%')
{
if (strncasecmp (*strp + 1, "lo(", 3) == 0)
@ -324,7 +324,7 @@ parse_uslo16 (CGEN_CPU_DESC cd,
const char *errmsg;
enum cgen_parse_operand_result result_type;
bfd_vma value;
if (**strp == '#' || **strp == '%')
{
if (strncasecmp (*strp + 1, "lo(", 3) == 0)
@ -450,7 +450,7 @@ parse_uhi16 (CGEN_CPU_DESC cd,
const char *errmsg;
enum cgen_parse_operand_result result_type;
bfd_vma value;
if (**strp == '#' || **strp == '%')
{
if (strncasecmp (*strp + 1, "hi(", 3) == 0)
@ -635,7 +635,7 @@ parse_d12 (CGEN_CPU_DESC cd,
const char *errmsg;
enum cgen_parse_operand_result result_type;
bfd_vma value;
/* Check for small data reference. */
if (**strp == '#' || **strp == '%')
{
@ -748,7 +748,7 @@ parse_s12 (CGEN_CPU_DESC cd,
const char *errmsg;
enum cgen_parse_operand_result result_type;
bfd_vma value;
/* Check for small data reference. */
if (**strp == '#' || **strp == '%')
{
@ -864,7 +864,7 @@ parse_u12 (CGEN_CPU_DESC cd,
const char *errmsg;
enum cgen_parse_operand_result result_type;
bfd_vma value;
/* Check for small data reference. */
if ((**strp == '#' || **strp == '%')
&& strncasecmp (*strp + 1, "gprel12(", 8) == 0)
@ -895,7 +895,7 @@ parse_A (CGEN_CPU_DESC cd,
unsigned long A)
{
const char *errmsg;
if (**strp == '#')
++*strp;
@ -957,7 +957,7 @@ parse_call_label (CGEN_CPU_DESC cd,
{
const char *errmsg;
bfd_vma value;
/* Check for small data reference. */
if (opinfo == 0 && (**strp == '#' || **strp == '%'))
{
@ -1266,7 +1266,7 @@ frv_cgen_parse_operand (CGEN_CPU_DESC cd,
return errmsg;
}
cgen_parse_fn * const frv_cgen_parse_handlers[] =
cgen_parse_fn * const frv_cgen_parse_handlers[] =
{
parse_insn_normal,
};
@ -1296,9 +1296,9 @@ CGEN_ASM_INIT_HOOK
Returns NULL for success, an error message for failure. */
char *
char *
frv_cgen_build_insn_regex (CGEN_INSN *insn)
{
{
CGEN_OPCODE *opc = (CGEN_OPCODE *) CGEN_INSN_OPCODE (insn);
const char *mnem = CGEN_INSN_MNEMONIC (insn);
char rxbuf[CGEN_MAX_RX_ELEMENTS];
@ -1337,18 +1337,18 @@ frv_cgen_build_insn_regex (CGEN_INSN *insn)
/* Copy any remaining literals from the syntax string into the rx. */
for(; * syn != 0 && rx <= rxbuf + (CGEN_MAX_RX_ELEMENTS - 7 - 4); ++syn)
{
if (CGEN_SYNTAX_CHAR_P (* syn))
if (CGEN_SYNTAX_CHAR_P (* syn))
{
char c = CGEN_SYNTAX_CHAR (* syn);
switch (c)
switch (c)
{
/* Escape any regex metacharacters in the syntax. */
case '.': case '[': case '\\':
case '*': case '^': case '$':
case '.': case '[': case '\\':
case '*': case '^': case '$':
#ifdef CGEN_ESCAPE_EXTENDED_REGEX
case '?': case '{': case '}':
case '?': case '{': case '}':
case '(': case ')': case '*':
case '|': case '+': case ']':
#endif
@ -1378,20 +1378,20 @@ frv_cgen_build_insn_regex (CGEN_INSN *insn)
}
/* Trailing whitespace ok. */
* rx++ = '[';
* rx++ = ' ';
* rx++ = '\t';
* rx++ = ']';
* rx++ = '*';
* rx++ = '[';
* rx++ = ' ';
* rx++ = '\t';
* rx++ = ']';
* rx++ = '*';
/* But anchor it after that. */
* rx++ = '$';
* rx++ = '$';
* rx = '\0';
CGEN_INSN_RX (insn) = xmalloc (sizeof (regex_t));
reg_err = regcomp ((regex_t *) CGEN_INSN_RX (insn), rxbuf, REG_NOSUB);
if (reg_err == 0)
if (reg_err == 0)
return NULL;
else
{
@ -1590,7 +1590,7 @@ frv_cgen_assemble_insn (CGEN_CPU_DESC cd,
const CGEN_INSN *insn = ilist->insn;
recognized_mnemonic = 1;
#ifdef CGEN_VALIDATE_INSN_SUPPORTED
#ifdef CGEN_VALIDATE_INSN_SUPPORTED
/* Not usually needed as unsupported opcodes
shouldn't be in the hash lists. */
/* Is this insn supported by the selected cpu? */
@ -1650,7 +1650,7 @@ frv_cgen_assemble_insn (CGEN_CPU_DESC cd,
if (strlen (start) > 50)
/* xgettext:c-format */
sprintf (errbuf, "%s `%.50s...'", tmp_errmsg, start);
else
else
/* xgettext:c-format */
sprintf (errbuf, "%s `%.50s'", tmp_errmsg, start);
}
@ -1659,11 +1659,11 @@ frv_cgen_assemble_insn (CGEN_CPU_DESC cd,
if (strlen (start) > 50)
/* xgettext:c-format */
sprintf (errbuf, _("bad instruction `%.50s...'"), start);
else
else
/* xgettext:c-format */
sprintf (errbuf, _("bad instruction `%.50s'"), start);
}
*errmsg = errbuf;
return NULL;
}

182
opcodes/frv-desc.c
View File

@ -2054,359 +2054,359 @@ const CGEN_OPERAND frv_cgen_operand_table[] =
{
/* pc: program counter */
{ "pc", FRV_OPERAND_PC, HW_H_PC, 0, 0,
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_NIL] } },
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_NIL] } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* pack: packing bit */
{ "pack", FRV_OPERAND_PACK, HW_H_PACK, 31, 1,
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_PACK] } },
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_PACK] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* GRi: source register 1 */
{ "GRi", FRV_OPERAND_GRI, HW_H_GR, 17, 6,
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_GRI] } },
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_GRI] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* GRj: source register 2 */
{ "GRj", FRV_OPERAND_GRJ, HW_H_GR, 5, 6,
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_GRJ] } },
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_GRJ] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* GRk: destination register */
{ "GRk", FRV_OPERAND_GRK, HW_H_GR, 30, 6,
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_GRK] } },
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_GRK] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* GRkhi: destination register */
{ "GRkhi", FRV_OPERAND_GRKHI, HW_H_GR_HI, 30, 6,
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_GRK] } },
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_GRK] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* GRklo: destination register */
{ "GRklo", FRV_OPERAND_GRKLO, HW_H_GR_LO, 30, 6,
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_GRK] } },
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_GRK] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* GRdoublek: destination register */
{ "GRdoublek", FRV_OPERAND_GRDOUBLEK, HW_H_GR_DOUBLE, 30, 6,
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_GRK] } },
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_GRK] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* ACC40Si: signed accumulator */
{ "ACC40Si", FRV_OPERAND_ACC40SI, HW_H_ACC40S, 17, 6,
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_ACC40SI] } },
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_ACC40SI] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* ACC40Ui: unsigned accumulator */
{ "ACC40Ui", FRV_OPERAND_ACC40UI, HW_H_ACC40U, 17, 6,
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_ACC40UI] } },
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_ACC40UI] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* ACC40Sk: target accumulator */
{ "ACC40Sk", FRV_OPERAND_ACC40SK, HW_H_ACC40S, 30, 6,
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_ACC40SK] } },
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_ACC40SK] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* ACC40Uk: target accumulator */
{ "ACC40Uk", FRV_OPERAND_ACC40UK, HW_H_ACC40U, 30, 6,
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_ACC40UK] } },
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_ACC40UK] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* ACCGi: source register */
{ "ACCGi", FRV_OPERAND_ACCGI, HW_H_ACCG, 17, 6,
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_ACCGI] } },
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_ACCGI] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* ACCGk: target register */
{ "ACCGk", FRV_OPERAND_ACCGK, HW_H_ACCG, 30, 6,
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_ACCGK] } },
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_ACCGK] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* CPRi: source register */
{ "CPRi", FRV_OPERAND_CPRI, HW_H_CPR, 17, 6,
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_CPRI] } },
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_CPRI] } },
{ 0, { { { (1<<MACH_FRV), 0 } } } } },
/* CPRj: source register */
{ "CPRj", FRV_OPERAND_CPRJ, HW_H_CPR, 5, 6,
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_CPRJ] } },
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_CPRJ] } },
{ 0, { { { (1<<MACH_FRV), 0 } } } } },
/* CPRk: destination register */
{ "CPRk", FRV_OPERAND_CPRK, HW_H_CPR, 30, 6,
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_CPRK] } },
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_CPRK] } },
{ 0, { { { (1<<MACH_FRV), 0 } } } } },
/* CPRdoublek: destination register */
{ "CPRdoublek", FRV_OPERAND_CPRDOUBLEK, HW_H_CPR_DOUBLE, 30, 6,
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_CPRK] } },
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_CPRK] } },
{ 0, { { { (1<<MACH_FRV), 0 } } } } },
/* FRinti: source register 1 */
{ "FRinti", FRV_OPERAND_FRINTI, HW_H_FR_INT, 17, 6,
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FRI] } },
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FRI] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* FRintj: source register 2 */
{ "FRintj", FRV_OPERAND_FRINTJ, HW_H_FR_INT, 5, 6,
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FRJ] } },
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FRJ] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* FRintk: target register */
{ "FRintk", FRV_OPERAND_FRINTK, HW_H_FR_INT, 30, 6,
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FRK] } },
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FRK] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* FRi: source register 1 */
{ "FRi", FRV_OPERAND_FRI, HW_H_FR, 17, 6,
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FRI] } },
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FRI] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* FRj: source register 2 */
{ "FRj", FRV_OPERAND_FRJ, HW_H_FR, 5, 6,
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FRJ] } },
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FRJ] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* FRk: destination register */
{ "FRk", FRV_OPERAND_FRK, HW_H_FR, 30, 6,
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FRK] } },
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FRK] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* FRkhi: destination register */
{ "FRkhi", FRV_OPERAND_FRKHI, HW_H_FR_HI, 30, 6,
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FRK] } },
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FRK] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* FRklo: destination register */
{ "FRklo", FRV_OPERAND_FRKLO, HW_H_FR_LO, 30, 6,
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FRK] } },
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FRK] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* FRdoublei: source register 1 */
{ "FRdoublei", FRV_OPERAND_FRDOUBLEI, HW_H_FR_DOUBLE, 17, 6,
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FRI] } },
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FRI] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* FRdoublej: source register 2 */
{ "FRdoublej", FRV_OPERAND_FRDOUBLEJ, HW_H_FR_DOUBLE, 5, 6,
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FRJ] } },
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FRJ] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* FRdoublek: target register */
{ "FRdoublek", FRV_OPERAND_FRDOUBLEK, HW_H_FR_DOUBLE, 30, 6,
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FRK] } },
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FRK] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* CRi: source register 1 */
{ "CRi", FRV_OPERAND_CRI, HW_H_CCCR, 14, 3,
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_CRI] } },
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_CRI] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* CRj: source register 2 */
{ "CRj", FRV_OPERAND_CRJ, HW_H_CCCR, 2, 3,
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_CRJ] } },
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_CRJ] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* CRj_int: destination register */
{ "CRj_int", FRV_OPERAND_CRJ_INT, HW_H_CCCR, 26, 2,
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_CRJ_INT] } },
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_CRJ_INT] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* CRj_float: destination register */
{ "CRj_float", FRV_OPERAND_CRJ_FLOAT, HW_H_CCCR, 26, 2,
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_CRJ_FLOAT] } },
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_CRJ_FLOAT] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* CRk: destination register */
{ "CRk", FRV_OPERAND_CRK, HW_H_CCCR, 27, 3,
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_CRK] } },
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_CRK] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* CCi: condition register */
{ "CCi", FRV_OPERAND_CCI, HW_H_CCCR, 11, 3,
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_CCI] } },
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_CCI] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* ICCi_1: condition register */
{ "ICCi_1", FRV_OPERAND_ICCI_1, HW_H_ICCR, 11, 2,
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_ICCI_1] } },
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_ICCI_1] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* ICCi_2: condition register */
{ "ICCi_2", FRV_OPERAND_ICCI_2, HW_H_ICCR, 26, 2,
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_ICCI_2] } },
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_ICCI_2] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* ICCi_3: condition register */
{ "ICCi_3", FRV_OPERAND_ICCI_3, HW_H_ICCR, 1, 2,
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_ICCI_3] } },
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_ICCI_3] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* FCCi_1: condition register */
{ "FCCi_1", FRV_OPERAND_FCCI_1, HW_H_FCCR, 11, 2,
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FCCI_1] } },
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FCCI_1] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* FCCi_2: condition register */
{ "FCCi_2", FRV_OPERAND_FCCI_2, HW_H_FCCR, 26, 2,
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FCCI_2] } },
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FCCI_2] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* FCCi_3: condition register */
{ "FCCi_3", FRV_OPERAND_FCCI_3, HW_H_FCCR, 1, 2,
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FCCI_3] } },
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FCCI_3] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* FCCk: condition register */
{ "FCCk", FRV_OPERAND_FCCK, HW_H_FCCR, 26, 2,
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FCCK] } },
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FCCK] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* eir: exception insn reg */
{ "eir", FRV_OPERAND_EIR, HW_H_UINT, 17, 6,
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_EIR] } },
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_EIR] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* s10: 10 bit signed immediate */
{ "s10", FRV_OPERAND_S10, HW_H_SINT, 9, 10,
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_S10] } },
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_S10] } },
{ 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } },
/* u16: 16 bit unsigned immediate */
{ "u16", FRV_OPERAND_U16, HW_H_UINT, 15, 16,
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_U16] } },
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_U16] } },
{ 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } },
/* s16: 16 bit signed immediate */
{ "s16", FRV_OPERAND_S16, HW_H_SINT, 15, 16,
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_S16] } },
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_S16] } },
{ 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } },
/* s6: 6 bit signed immediate */
{ "s6", FRV_OPERAND_S6, HW_H_SINT, 5, 6,
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_S6] } },
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_S6] } },
{ 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } },
/* s6_1: 6 bit signed immediate */
{ "s6_1", FRV_OPERAND_S6_1, HW_H_SINT, 11, 6,
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_S6_1] } },
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_S6_1] } },
{ 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } },
/* u6: 6 bit unsigned immediate */
{ "u6", FRV_OPERAND_U6, HW_H_UINT, 5, 6,
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_U6] } },
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_U6] } },
{ 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } },
/* s5: 5 bit signed immediate */
{ "s5", FRV_OPERAND_S5, HW_H_SINT, 4, 5,
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_S5] } },
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_S5] } },
{ 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } },
/* cond: conditional arithmetic */
{ "cond", FRV_OPERAND_COND, HW_H_UINT, 8, 1,
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_COND] } },
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_COND] } },
{ 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } },
/* ccond: lr branch condition */
{ "ccond", FRV_OPERAND_CCOND, HW_H_UINT, 12, 1,
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_CCOND] } },
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_CCOND] } },
{ 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } },
/* hint: 2 bit branch predictor */
{ "hint", FRV_OPERAND_HINT, HW_H_UINT, 17, 2,
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_HINT] } },
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_HINT] } },
{ 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } },
/* hint_taken: 2 bit branch predictor */
{ "hint_taken", FRV_OPERAND_HINT_TAKEN, HW_H_HINT_TAKEN, 17, 2,
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_HINT] } },
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_HINT] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* hint_not_taken: 2 bit branch predictor */
{ "hint_not_taken", FRV_OPERAND_HINT_NOT_TAKEN, HW_H_HINT_NOT_TAKEN, 17, 2,
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_HINT] } },
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_HINT] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* LI: link indicator */
{ "LI", FRV_OPERAND_LI, HW_H_UINT, 25, 1,
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_LI] } },
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_LI] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* lock: cache lock indicator */
{ "lock", FRV_OPERAND_LOCK, HW_H_UINT, 25, 1,
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_LOCK] } },
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_LOCK] } },
{ 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } },
/* debug: debug mode indicator */
{ "debug", FRV_OPERAND_DEBUG, HW_H_UINT, 25, 1,
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_DEBUG] } },
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_DEBUG] } },
{ 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } },
/* ae: all entries indicator */
{ "ae", FRV_OPERAND_AE, HW_H_UINT, 25, 1,
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_AE] } },
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_AE] } },
{ 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } },
/* label16: 18 bit pc relative address */
{ "label16", FRV_OPERAND_LABEL16, HW_H_IADDR, 15, 16,
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_LABEL16] } },
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_LABEL16] } },
{ 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } } },
/* LRAE: Load Real Address E flag */
{ "LRAE", FRV_OPERAND_LRAE, HW_H_UINT, 5, 1,
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_LRAE] } },
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_LRAE] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* LRAD: Load Real Address D flag */
{ "LRAD", FRV_OPERAND_LRAD, HW_H_UINT, 4, 1,
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_LRAD] } },
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_LRAD] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* LRAS: Load Real Address S flag */
{ "LRAS", FRV_OPERAND_LRAS, HW_H_UINT, 3, 1,
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_LRAS] } },
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_LRAS] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* TLBPRopx: TLB Probe operation number */
{ "TLBPRopx", FRV_OPERAND_TLBPROPX, HW_H_UINT, 28, 3,
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_TLBPROPX] } },
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_TLBPROPX] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* TLBPRL: TLB Probe L flag */
{ "TLBPRL", FRV_OPERAND_TLBPRL, HW_H_UINT, 25, 1,
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_TLBPRL] } },
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_TLBPRL] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* A0: A==0 operand of mclracc */
{ "A0", FRV_OPERAND_A0, HW_H_UINT, 17, 1,
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_A] } },
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_A] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* A1: A==1 operand of mclracc */
{ "A1", FRV_OPERAND_A1, HW_H_UINT, 17, 1,
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_A] } },
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_A] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* FRintieven: (even) source register 1 */
{ "FRintieven", FRV_OPERAND_FRINTIEVEN, HW_H_FR_INT, 17, 6,
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FRI] } },
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FRI] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* FRintjeven: (even) source register 2 */
{ "FRintjeven", FRV_OPERAND_FRINTJEVEN, HW_H_FR_INT, 5, 6,
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FRJ] } },
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FRJ] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* FRintkeven: (even) target register */
{ "FRintkeven", FRV_OPERAND_FRINTKEVEN, HW_H_FR_INT, 30, 6,
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FRK] } },
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FRK] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* d12: 12 bit signed immediate */
{ "d12", FRV_OPERAND_D12, HW_H_SINT, 11, 12,
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_D12] } },
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_D12] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* s12: 12 bit signed immediate */
{ "s12", FRV_OPERAND_S12, HW_H_SINT, 11, 12,
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_D12] } },
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_D12] } },
{ 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } },
/* u12: 12 bit signed immediate */
{ "u12", FRV_OPERAND_U12, HW_H_SINT, 5, 12,
{ 2, { (const PTR) &FRV_F_U12_MULTI_IFIELD[0] } },
{ 2, { (const PTR) &FRV_F_U12_MULTI_IFIELD[0] } },
{ 0|A(HASH_PREFIX)|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
/* spr: special purpose register */
{ "spr", FRV_OPERAND_SPR, HW_H_SPR, 17, 12,
{ 2, { (const PTR) &FRV_F_SPR_MULTI_IFIELD[0] } },
{ 2, { (const PTR) &FRV_F_SPR_MULTI_IFIELD[0] } },
{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
/* ulo16: 16 bit unsigned immediate, for #lo() */
{ "ulo16", FRV_OPERAND_ULO16, HW_H_UINT, 15, 16,
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_U16] } },
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_U16] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* slo16: 16 bit unsigned immediate, for #lo() */
{ "slo16", FRV_OPERAND_SLO16, HW_H_SINT, 15, 16,
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_S16] } },
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_S16] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* uhi16: 16 bit unsigned immediate, for #hi() */
{ "uhi16", FRV_OPERAND_UHI16, HW_H_UINT, 15, 16,
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_U16] } },
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_U16] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* label24: 26 bit pc relative address */
{ "label24", FRV_OPERAND_LABEL24, HW_H_IADDR, 17, 24,
{ 2, { (const PTR) &FRV_F_LABEL24_MULTI_IFIELD[0] } },
{ 2, { (const PTR) &FRV_F_LABEL24_MULTI_IFIELD[0] } },
{ 0|A(PCREL_ADDR)|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
/* psr_esr: PSR.ESR bit */
{ "psr_esr", FRV_OPERAND_PSR_ESR, HW_H_PSR_ESR, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* psr_s: PSR.S bit */
{ "psr_s", FRV_OPERAND_PSR_S, HW_H_PSR_S, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* psr_ps: PSR.PS bit */
{ "psr_ps", FRV_OPERAND_PSR_PS, HW_H_PSR_PS, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* psr_et: PSR.ET bit */
{ "psr_et", FRV_OPERAND_PSR_ET, HW_H_PSR_ET, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* bpsr_bs: BPSR.BS bit */
{ "bpsr_bs", FRV_OPERAND_BPSR_BS, HW_H_BPSR_BS, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* bpsr_bet: BPSR.BET bit */
{ "bpsr_bet", FRV_OPERAND_BPSR_BET, HW_H_BPSR_BET, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* tbr_tba: TBR.TBA */
{ "tbr_tba", FRV_OPERAND_TBR_TBA, HW_H_TBR_TBA, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* tbr_tt: TBR.TT */
{ "tbr_tt", FRV_OPERAND_TBR_TT, HW_H_TBR_TT, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* ldann: ld annotation */
{ "ldann", FRV_OPERAND_LDANN, HW_H_RELOC_ANN, 0, 0,
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_RELOC_ANN] } },
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_RELOC_ANN] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* lddann: ldd annotation */
{ "lddann", FRV_OPERAND_LDDANN, HW_H_RELOC_ANN, 0, 0,
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_RELOC_ANN] } },
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_RELOC_ANN] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* callann: call annotation */
{ "callann", FRV_OPERAND_CALLANN, HW_H_RELOC_ANN, 0, 0,
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_RELOC_ANN] } },
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_RELOC_ANN] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* sentinel */
{ 0, 0, 0, 0, 0,
@ -6429,7 +6429,7 @@ frv_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...)
/* Default to not allowing signed overflow. */
cd->signed_overflow_ok_p = 0;
return (CGEN_CPU_DESC) cd;
}
@ -6469,7 +6469,7 @@ frv_cgen_cpu_close (CGEN_CPU_DESC cd)
for (i = 0; i < cd->insn_table.num_init_entries; ++i, ++insns)
if (CGEN_INSN_RX (insns))
regfree (CGEN_INSN_RX (insns));
}
}
if (cd->macro_insn_table.init_entries)
free ((CGEN_INSN *) cd->macro_insn_table.init_entries);

12
opcodes/frv-dis.c
View File

@ -69,7 +69,7 @@ print_at (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
disassemble_info *info = (disassemble_info *) dis_info;
(*info->fprintf_func) (info->stream, "@");
}
}
static void
print_spr (CGEN_CPU_DESC cd,
@ -398,7 +398,7 @@ frv_cgen_print_operand (CGEN_CPU_DESC cd,
}
}
cgen_print_fn * const frv_cgen_print_handlers[] =
cgen_print_fn * const frv_cgen_print_handlers[] =
{
print_insn_normal,
};
@ -588,7 +588,7 @@ print_insn (CGEN_CPU_DESC cd,
int length;
unsigned long insn_value_cropped;
#ifdef CGEN_VALIDATE_INSN_SUPPORTED
#ifdef CGEN_VALIDATE_INSN_SUPPORTED
/* Not needed as insn shouldn't be in hash lists if not supported. */
/* Supported by this cpu? */
if (! frv_cgen_insn_supported (cd, insn))
@ -606,7 +606,7 @@ print_insn (CGEN_CPU_DESC cd,
relevant part from the buffer. */
if ((unsigned) (CGEN_INSN_BITSIZE (insn) / 8) < buflen &&
(unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long))
insn_value_cropped = bfd_get_bits (buf, CGEN_INSN_BITSIZE (insn),
insn_value_cropped = bfd_get_bits (buf, CGEN_INSN_BITSIZE (insn),
info->endian == BFD_ENDIAN_BIG);
else
insn_value_cropped = insn_value;
@ -725,7 +725,7 @@ print_insn_frv (bfd_vma pc, disassemble_info *info)
arch = info->arch;
if (arch == bfd_arch_unknown)
arch = CGEN_BFD_ARCH;
/* There's no standard way to compute the machine or isa number
so we leave it to the target. */
#ifdef CGEN_COMPUTE_MACH
@ -766,7 +766,7 @@ print_insn_frv (bfd_vma pc, disassemble_info *info)
break;
}
}
}
}
/* If we haven't initialized yet, initialize the opcode table. */
if (! cd)

8
opcodes/frv-ibld.c
View File

@ -154,7 +154,7 @@ insert_normal (CGEN_CPU_DESC cd,
{
long minval = - (1L << (length - 1));
unsigned long maxval = mask;
if ((value > 0 && (unsigned long) value > maxval)
|| value < minval)
{
@ -192,7 +192,7 @@ insert_normal (CGEN_CPU_DESC cd,
{
long minval = - (1L << (length - 1));
long maxval = (1L << (length - 1)) - 1;
if (value < minval || value > maxval)
{
sprintf
@ -1174,12 +1174,12 @@ frv_cgen_extract_operand (CGEN_CPU_DESC cd,
return length;
}
cgen_insert_fn * const frv_cgen_insert_handlers[] =
cgen_insert_fn * const frv_cgen_insert_handlers[] =
{
insert_insn_normal,
};
cgen_extract_fn * const frv_cgen_extract_handlers[] =
cgen_extract_fn * const frv_cgen_extract_handlers[] =
{
extract_insn_normal,
};

10
opcodes/frv-opc.c
View File

@ -234,7 +234,7 @@ static CGEN_ATTR_VALUE_ENUM_TYPE fr400_unit_mapping[] =
/* NIL */ UNIT_NIL,
/* I0 */ UNIT_I0,
/* I1 */ UNIT_I1,
/* I01 */ UNIT_I01,
/* I01 */ UNIT_I01,
/* I2 */ UNIT_NIL, /* no I2 or I3 unit */
/* I3 */ UNIT_NIL,
/* IALL */ UNIT_I01, /* only I0 and I1 units */
@ -269,7 +269,7 @@ static CGEN_ATTR_VALUE_ENUM_TYPE fr450_unit_mapping[] =
/* NIL */ UNIT_NIL,
/* I0 */ UNIT_I0,
/* I1 */ UNIT_I1,
/* I01 */ UNIT_I01,
/* I01 */ UNIT_I01,
/* I2 */ UNIT_NIL, /* no I2 or I3 unit */
/* I3 */ UNIT_NIL,
/* IALL */ UNIT_I01, /* only I0 and I1 units */
@ -301,7 +301,7 @@ static CGEN_ATTR_VALUE_ENUM_TYPE fr500_unit_mapping[] =
/* NIL */ UNIT_NIL,
/* I0 */ UNIT_I0,
/* I1 */ UNIT_I1,
/* I01 */ UNIT_I01,
/* I01 */ UNIT_I01,
/* I2 */ UNIT_NIL, /* no I2 or I3 unit */
/* I3 */ UNIT_NIL,
/* IALL */ UNIT_I01, /* only I0 and I1 units */
@ -333,10 +333,10 @@ static CGEN_ATTR_VALUE_ENUM_TYPE fr550_unit_mapping[] =
/* NIL */ UNIT_NIL,
/* I0 */ UNIT_I0,
/* I1 */ UNIT_I1,
/* I01 */ UNIT_I01,
/* I01 */ UNIT_I01,
/* I2 */ UNIT_I2,
/* I3 */ UNIT_I3,
/* IALL */ UNIT_IALL,
/* IALL */ UNIT_IALL,
/* FM0 */ UNIT_FM0,
/* FM1 */ UNIT_FM1,
/* FM01 */ UNIT_FM01,

32
opcodes/h8300-dis.c
View File

@ -269,14 +269,14 @@ print_one_arg (disassemble_info *info,
{
outfn (stream, ".%s%d (0x%lx)",
(short) cst > 0 ? "+" : "",
(short) cst,
(short) cst,
(long)(addr + (short) cst + len));
}
else
{
outfn (stream, ".%s%d (0x%lx)",
(char) cst > 0 ? "+" : "",
(char) cst,
(char) cst,
(long)(addr + (char) cst + len));
}
}
@ -285,12 +285,12 @@ print_one_arg (disassemble_info *info,
else if ((x & MODE) == INDEXB)
/* Always take low half of reg. */
outfn (stream, "@(0x%x:%d,%s.b)", cst, cstlen,
outfn (stream, "@(0x%x:%d,%s.b)", cst, cstlen,
regnames[rdisp_n < 8 ? rdisp_n + 8 : rdisp_n]);
else if ((x & MODE) == INDEXW)
/* Always take low half of reg. */
outfn (stream, "@(0x%x:%d,%s.w)", cst, cstlen,
outfn (stream, "@(0x%x:%d,%s.w)", cst, cstlen,
wregnames[rdisp_n < 8 ? rdisp_n : rdisp_n - 8]);
else if ((x & MODE) == INDEXL)
@ -460,8 +460,8 @@ bfd_h8_disassemble (bfd_vma addr, disassemble_info *info, int mach)
|| (looking_for & MODE) == INDEXW
|| (looking_for & MODE) == INDEXL)
{
extract_immediate (stream, looking_for, thisnib,
data + len / 2, cst + opnr,
extract_immediate (stream, looking_for, thisnib,
data + len / 2, cst + opnr,
cstlen + opnr, q);
/* Even address == bra, odd == bra/s. */
if (q->how == O (O_BRAS, SB))
@ -529,8 +529,8 @@ bfd_h8_disassemble (bfd_vma addr, disassemble_info *info, int mach)
{
int i = len / 2;
cst[opnr] = ((data[i] << 24)
| (data[i + 1] << 16)
cst[opnr] = ((data[i] << 24)
| (data[i + 1] << 16)
| (data[i + 2] << 8)
| (data[i + 3]));
@ -540,7 +540,7 @@ bfd_h8_disassemble (bfd_vma addr, disassemble_info *info, int mach)
{
int i = len / 2;
cst[opnr] =
cst[opnr] =
(data[i] << 16) | (data[i + 1] << 8) | (data[i + 2]);
cstlen[opnr] = 24;
}
@ -633,21 +633,21 @@ bfd_h8_disassemble (bfd_vma addr, disassemble_info *info, int mach)
if (args[1] == (op_type) E)
{
/* Short form. */
print_one_arg (info, addr, args[0], cst[0],
cstlen[0], dispregno[0], regno[0],
print_one_arg (info, addr, args[0], cst[0],
cstlen[0], dispregno[0], regno[0],
pregnames, qi->length);
outfn (stream, ",er%d", dispregno[0]);
}
else
{
outfn (stream, "@(0x%x:%d,", cst[0], cstlen[0]);
print_one_arg (info, addr, args[1], cst[1],
cstlen[1], dispregno[1], regno[1],
print_one_arg (info, addr, args[1], cst[1],
cstlen[1], dispregno[1], regno[1],
pregnames, qi->length);
outfn (stream, ".%c),",
(args[0] & MODE) == INDEXB ? 'b' : 'w');
print_one_arg (info, addr, args[2], cst[2],
cstlen[2], dispregno[2], regno[2],
print_one_arg (info, addr, args[2], cst[2],
cstlen[2], dispregno[2], regno[2],
pregnames, qi->length);
}
return qi->length;
@ -669,7 +669,7 @@ bfd_h8_disassemble (bfd_vma addr, disassemble_info *info, int mach)
return qi->length;
}
for (nargs = 0;
for (nargs = 0;
nargs < 3 && args[nargs] != (op_type) E;
nargs++)
{

2
opcodes/i370-opc.c
View File

@ -257,7 +257,7 @@ const struct i370_operand i370_operands[] =
#define SS_D2 (SS_B2 + 1)
#define SS_D2_MASK (0xfff)
{ 12, 0, insert_ss_d2, extract_ss_d2, I370_OPERAND_RELATIVE, "SS D2" },
};

2
opcodes/i386-opc.h
View File

@ -196,7 +196,7 @@ enum
CpuAVX512VBMI,
/* mwaitx instruction required */
CpuMWAITX,
/* Clzero instruction required */
/* Clzero instruction required */
CpuCLZERO,
/* 64bit support required */
Cpu64,

12
opcodes/i860-dis.c
View File

@ -28,14 +28,14 @@
#define I860_REG_PREFIX "%"
/* Integer register names (encoded as 0..31 in the instruction). */
static const char *const grnames[] =
static const char *const grnames[] =
{"r0", "r1", "sp", "fp", "r4", "r5", "r6", "r7",
"r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
"r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
"r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"};
/* FP register names (encoded as 0..31 in the instruction). */
static const char *const frnames[] =
static const char *const frnames[] =
{"f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
"f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
"f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
@ -43,7 +43,7 @@ static const char *const frnames[] =
/* Control/status register names (encoded as 0..11 in the instruction).
Registers bear, ccr, p0, p1, p2 and p3 are XP only. */
static const char *const crnames[] =
static const char *const crnames[] =
{"fir", "psr", "dirbase", "db", "fsr", "epsr", "bear", "ccr",
"p0", "p1", "p2", "p3", "--", "--", "--", "--" };
@ -78,9 +78,9 @@ print_br_address (disassemble_info *info, bfd_vma memaddr, long val)
long adj = (long)memaddr + 4 + (val << 2);
(*info->fprintf_func) (info->stream, "0x%08lx", adj);
/* Attempt to obtain a symbol for the target address. */
if (info->print_address_func && adj != 0)
{
(*info->fprintf_func) (info->stream, "\t// ");
@ -134,7 +134,7 @@ print_insn_i860 (bfd_vma memaddr, disassemble_info *info)
int val;
/* If this a flop (or a shrd) and its dual bit is set,
prefix with 'd.'. */
prefix with 'd.'. */
if (((insn & 0xfc000000) == 0x48000000
|| (insn & 0xfc000000) == 0xb0000000)
&& (insn & 0x200))

2778
opcodes/ia64-asmtab.c
View File

File diff suppressed because it is too large Load Diff

12
opcodes/ia64-asmtab.h
View File

@ -31,7 +31,7 @@ struct ia64_main_table
opcode. */
unsigned short name_index;
/* The type of opcode; corresponds to the TYPE field in
/* The type of opcode; corresponds to the TYPE field in
struct ia64_opcode. */
unsigned char opcode_type;
@ -64,7 +64,7 @@ struct ia64_main_table
The completer entries modify certain bits in the instruction opcode.
Which bits are to be modified are marked by the BITS, MASK and
OFFSET fields. The completer entry may also note dependencies for the
opcode.
opcode.
These completers are arranged in a DAG; the pointers are indexes
into the completer_table array. The completer DAG is searched by
@ -81,7 +81,7 @@ struct ia64_main_table
not contain an empty entry.
Terminal completers (those completers that validly complete an
instruction) are marked by having the TERMINAL_COMPLETER flag set.
instruction) are marked by having the TERMINAL_COMPLETER flag set.
Only dependencies listed in the terminal completer for an opcode are
considered to apply to that opcode instance. */
@ -91,7 +91,7 @@ struct ia64_completer_table
/* The bit value that this completer sets. */
unsigned int bits;
/* And its mask. 1s are bits that are to be modified in the
/* And its mask. 1s are bits that are to be modified in the
instruction. */
unsigned int mask;
@ -118,11 +118,11 @@ struct ia64_completer_table
/* This contains sufficient information for the disassembler to resolve
the complete name of the original instruction. */
struct ia64_dis_names
struct ia64_dis_names
{
/* COMPLETER_INDEX represents the tree of completers that make up
the instruction. The LSB represents the top of the tree for the
specified instruction.
specified instruction.
A 0 bit indicates to go to the next alternate completer via the
alternative field; a 1 bit indicates that the current completer

2
opcodes/ia64-dis.c
View File

@ -303,7 +303,7 @@ print_insn_ia64 (bfd_vma memaddr, struct disassemble_info *info)
need_comma = 0;
}
}
if (slotnum + 1 == ia64_templ_desc[template_val].group_boundary
if (slotnum + 1 == ia64_templ_desc[template_val].group_boundary
|| ((slotnum == 2) && s_bit))
(*info->fprintf_func) (info->stream, ";;");

136
opcodes/ia64-gen.c
View File

@ -22,15 +22,15 @@
/* While the ia64-opc-* set of opcode tables are easy to maintain,
they waste a tremendous amount of space. ia64-gen rearranges the
instructions into a directed acyclic graph (DAG) of instruction opcodes and
their possible completers, as well as compacting the set of strings used.
instructions into a directed acyclic graph (DAG) of instruction opcodes and
their possible completers, as well as compacting the set of strings used.
The disassembler table consists of a state machine that does
branching based on the bits of the opcode being disassembled. The
state encodings have been chosen to minimize the amount of space
required.
required.
The resource table is constructed based on some text dependency tables,
The resource table is constructed based on some text dependency tables,
which are also easier to maintain than the final representation. */
#include "sysdep.h"
@ -172,7 +172,7 @@ struct bittree
alphabetical order. */
/* One entry in the string table. */
struct string_entry
struct string_entry
{
/* The index in the ia64_strings[] array for this entry. */
int num;
@ -188,11 +188,11 @@ int strtabtotlen = 0;
struct rdep
{
char *name; /* Resource name. */
unsigned
unsigned
mode:2, /* RAW, WAW, or WAR. */
semantics:3; /* Dependency semantics. */
char *extra; /* Additional semantics info. */
int nchks;
int nchks;
int total_chks; /* Total #of terminal insns. */
int *chks; /* Insn classes which read (RAW), write
(WAW), or write (WAR) this rsrc. */
@ -211,12 +211,12 @@ static int rdepstotlen = 0;
/* Array of all instruction classes. */
struct iclass
{
{
char *name; /* Instruction class name. */
int is_class; /* Is a class, not a terminal. */
int nsubs;
int nsubs;
int *subs; /* Other classes within this class. */
int nxsubs;
int nxsubs;
int xsubs[4]; /* Exclusions. */
char *comment; /* Optional comment. */
int note; /* Optional note. */
@ -301,7 +301,7 @@ static void
fail (const char *message, ...)
{
va_list args;
va_start (args, message);
fprintf (stderr, _("%s: Error: "), program_name);
vfprintf (stderr, message, args);
@ -336,7 +336,7 @@ insert_resource (const char *name, enum ia64_dependency_mode type)
rdeps[rdepslen]->name = xstrdup (name);
rdeps[rdepslen]->mode = type;
rdeps[rdepslen]->waw_special = 0;
return rdeps[rdepslen++];
}
@ -405,7 +405,7 @@ insert_deplist (int count, unsigned short *deps)
/* Add the given pair of dependency lists to the opcode dependency list. */
static short
insert_dependencies (int nchks, unsigned short *chks,
insert_dependencies (int nchks, unsigned short *chks,
int nregs, unsigned short *regs)
{
struct opdep *pair;
@ -419,14 +419,14 @@ insert_dependencies (int nchks, unsigned short *chks,
chkind = insert_deplist (nchks, chks);
for (i = 0; i < opdeplen; i++)
if (opdeps[i]->chk == chkind
if (opdeps[i]->chk == chkind
&& opdeps[i]->reg == regind)
return i;
pair = tmalloc (struct opdep);
pair->chk = chkind;
pair->reg = regind;
if (opdeplen == opdeptotlen)
{
opdeptotlen += 20;
@ -438,7 +438,7 @@ insert_dependencies (int nchks, unsigned short *chks,
return opdeplen++;
}
static void
static void
mark_used (struct iclass *ic, int clear_terminals)
{
int i;
@ -521,7 +521,7 @@ fetch_insn_class (const char *full_name, int create)
if (strcmp (name, ics[i]->name) == 0
&& ((comment == NULL && ics[i]->comment == NULL)
|| (comment != NULL && ics[i]->comment != NULL
&& strncmp (ics[i]->comment, comment,
&& strncmp (ics[i]->comment, comment,
strlen (ics[i]->comment)) == 0))
&& note == ics[i]->note)
return i;
@ -623,10 +623,10 @@ load_insn_classes (void)
int iclass;
char *name;
char *tmp;
if (fgets (buf, sizeof (buf), fp) == NULL)
break;
while (ISSPACE (buf[strlen (buf) - 1]))
buf[strlen (buf) - 1] = '\0';
@ -670,9 +670,9 @@ load_insn_classes (void)
}
if (*tmp == ',')
*tmp++ = '\0';
ics[iclass]->subs = (int *)
xrealloc ((void *)ics[iclass]->subs,
xrealloc ((void *)ics[iclass]->subs,
(ics[iclass]->nsubs + 1) * sizeof (int));
sub = fetch_insn_class (subname, 1);
@ -682,7 +682,7 @@ load_insn_classes (void)
}
/* Make sure classes come before terminals. */
qsort ((void *)ics[iclass]->subs,
qsort ((void *)ics[iclass]->subs,
ics[iclass]->nsubs, sizeof(int), sub_compare);
}
fclose (fp);
@ -712,7 +712,7 @@ parse_resource_users (const char *ref, int **usersp, int *nusersp,
int iclass;
int create = 0;
char *name;
while (ISSPACE (*tmp))
++tmp;
name = tmp;
@ -720,7 +720,7 @@ parse_resource_users (const char *ref, int **usersp, int *nusersp,
++tmp;
c = *tmp;
*tmp++ = '\0';
xsect = strchr (name, '\\');
if ((notestr = strstr (name, "+")) != NULL)
{
@ -738,7 +738,7 @@ parse_resource_users (const char *ref, int **usersp, int *nusersp,
if (!xsect)
*notestr = '\0';
}
else
else
note = 0;
/* All classes are created when the insn class table is parsed;
@ -748,7 +748,7 @@ parse_resource_users (const char *ref, int **usersp, int *nusersp,
table). */
if (! CONST_STRNEQ (name, "IC:") || xsect != NULL)
create = 1;
iclass = fetch_insn_class (name, create);
if (iclass != -1)
{
@ -788,7 +788,7 @@ parse_semantics (char *sem)
return IA64_DVS_SPECIFIC;
else if (strcmp (sem, "stop") == 0)
return IA64_DVS_STOP;
else
else
return IA64_DVS_OTHER;
}
@ -835,7 +835,7 @@ load_depfile (const char *filename, enum ia64_dependency_mode mode)
while (*tmp != ';')
++tmp;
*tmp++ = '\0';
while (ISSPACE (*tmp))
++tmp;
regp = tmp;
@ -883,7 +883,7 @@ load_dependencies (void)
}
/* Is the given operand an indirect register file operand? */
static int
static int
irf_operand (int op, const char *field)
{
if (!field)
@ -910,7 +910,7 @@ irf_operand (int op, const char *field)
/* Handle mov_ar, mov_br, mov_cr, move_dahr, mov_indirect, mov_ip, mov_pr,
* mov_psr, and mov_um insn classes. */
static int
in_iclass_mov_x (struct ia64_opcode *idesc, struct iclass *ic,
in_iclass_mov_x (struct ia64_opcode *idesc, struct iclass *ic,
const char *format, const char *field)
{
int plain_mov = strcmp (idesc->name, "mov") == 0;
@ -1031,7 +1031,7 @@ in_iclass_mov_x (struct ia64_opcode *idesc, struct iclass *ic,
/* Is the given opcode in the given insn class? */
static int
in_iclass (struct ia64_opcode *idesc, struct iclass *ic,
in_iclass (struct ia64_opcode *idesc, struct iclass *ic,
const char *format, const char *field, int *notep)
{
int i;
@ -1049,7 +1049,7 @@ in_iclass (struct ia64_opcode *idesc, struct iclass *ic,
{
warn (_("most recent format '%s'\nappears more restrictive than '%s'\n"),
ic->comment, format);
format = ic->comment;
format = ic->comment;
}
}
else
@ -1074,7 +1074,7 @@ in_iclass (struct ia64_opcode *idesc, struct iclass *ic,
int len = strlen(ic->name);
resolved = ((strncmp (ic->name, idesc->name, len) == 0)
&& (idesc->name[len] == '\0'
&& (idesc->name[len] == '\0'
|| idesc->name[len] == '.'));
/* All break, nop, and hint variations must match exactly. */
@ -1162,7 +1162,7 @@ in_iclass (struct ia64_opcode *idesc, struct iclass *ic,
resolved = 0;
}
/* Misc brl variations ('.cond' is optional);
/* Misc brl variations ('.cond' is optional);
plain brl matches brl.cond. */
if (!resolved
&& (strcmp (idesc->name, "brl") == 0
@ -1173,7 +1173,7 @@ in_iclass (struct ia64_opcode *idesc, struct iclass *ic,
}
/* Misc br variations ('.cond' is optional). */
if (!resolved
if (!resolved
&& (strcmp (idesc->name, "br") == 0
|| CONST_STRNEQ (idesc->name, "br."))
&& strcmp (ic->name, "br.cond") == 0)
@ -1190,8 +1190,8 @@ in_iclass (struct ia64_opcode *idesc, struct iclass *ic,
/* probe variations. */
if (!resolved && CONST_STRNEQ (idesc->name, "probe"))
{
resolved = strcmp (ic->name, "probe") == 0
&& !((strstr (idesc->name, "fault") != NULL)
resolved = strcmp (ic->name, "probe") == 0
&& !((strstr (idesc->name, "fault") != NULL)
^ (format && strstr (format, "M40") != NULL));
}
@ -1226,7 +1226,7 @@ in_iclass (struct ia64_opcode *idesc, struct iclass *ic,
resolved = in_iclass_mov_x (idesc, ic, format, field);
}
/* Keep track of this so we can flag any insn classes which aren't
/* Keep track of this so we can flag any insn classes which aren't
mapped onto at least one real insn. */
if (resolved)
ic->terminal_resolved = 1;
@ -1248,7 +1248,7 @@ in_iclass (struct ia64_opcode *idesc, struct iclass *ic,
break;
}
}
/* If it's in this IC, add the IC note (if any) to the insn. */
if (resolved)
{
@ -1483,7 +1483,7 @@ lookup_specifier (const char *name)
return IA64_RS_PMD;
if (strstr (name, "RR#") != NULL)
return IA64_RS_RR;
warn (_("Don't know how to specify # dependency %s\n"),
name);
}
@ -1514,7 +1514,7 @@ print_dependency_table (void)
{
int i, j;
if (debug)
if (debug)
{
for (i=0;i < iclen;i++)
{
@ -1530,7 +1530,7 @@ print_dependency_table (void)
ics[i]->name);
}
}
else
else
{
if (!ics[i]->terminal_resolved && !ics[i]->orphan)
{
@ -1556,16 +1556,16 @@ print_dependency_table (void)
if (debug > 1)
for (i = 0; i < rdepslen; i++)
{
{
static const char *mode_str[] = { "RAW", "WAW", "WAR" };
if (rdeps[i]->total_chks == 0)
{
if (rdeps[i]->total_regs)
warn (_("Warning: rsrc %s (%s) has no chks\n"),
warn (_("Warning: rsrc %s (%s) has no chks\n"),
rdeps[i]->name, mode_str[rdeps[i]->mode]);
else
warn (_("Warning: rsrc %s (%s) has no chks or regs\n"),
warn (_("Warning: rsrc %s (%s) has no chks or regs\n"),
rdeps[i]->name, mode_str[rdeps[i]->mode]);
}
else if (rdeps[i]->total_regs == 0)
@ -1579,7 +1579,7 @@ print_dependency_table (void)
for (i = 0; i < rdepslen; i++)
{
/* '%', '#', AR[], CR[], or PSR. indicates we need to specify the actual
resource used. */
resource used. */
int specifier = lookup_specifier (rdeps[i]->name);
int regindex = lookup_regindex (rdeps[i]->name, specifier);
@ -1633,11 +1633,11 @@ print_dependency_table (void)
printf (" { ");
if (opdeps[i]->chk == -1)
printf ("0, NULL, ");
else
else
printf ("NELS(dep%d), dep%d, ", opdeps[i]->chk, opdeps[i]->chk);
if (opdeps[i]->reg == -1)
printf ("0, NULL, ");
else
else
printf ("NELS(dep%d), dep%d, ", opdeps[i]->reg, opdeps[i]->reg);
printf ("},\n");
}
@ -1656,7 +1656,7 @@ insert_string (char *str)
{
strtabtotlen += 20;
string_table = (struct string_entry **)
xrealloc (string_table,
xrealloc (string_table,
sizeof (struct string_entry **) * strtabtotlen);
}
@ -1729,7 +1729,7 @@ make_bittree_entry (void)
res->bits_to_skip = 0;
return res;
}
static struct disent *
add_dis_table_ent (struct disent *which, int insn, int order,
@ -1794,7 +1794,7 @@ insert_bit_table_ent (struct bittree *curr_ent, int bit, ia64_insn opcode,
if (bit == -1)
{
struct disent *nent = add_dis_table_ent (curr_ent->disent,
struct disent *nent = add_dis_table_ent (curr_ent->disent,
opcodenum, order,
completer_index);
curr_ent->disent = nent;
@ -1833,8 +1833,8 @@ add_dis_entry (struct bittree *first, ia64_insn opcode, ia64_insn mask,
if (ent->is_terminal)
{
insert_bit_table_ent (bittree, 40, newopcode, mask,
opcodenum, opcode_count - ent->order - 1,
insert_bit_table_ent (bittree, 40, newopcode, mask,
opcodenum, opcode_count - ent->order - 1,
(completer_index << 1) | 1);
}
completer_index <<= 1;
@ -2013,7 +2013,7 @@ gen_dis_table (struct bittree *ent)
else
idest = ent->disent->ournum;
/* If the destination offset for the if (bit is 1) test is less
/* If the destination offset for the if (bit is 1) test is less
than 256 bytes away, we can store it as 8-bits instead of 16;
the instruction has bit 5 set for the 16-bit address, and bit
4 for the 8-bit address. Since we've already allocated 16
@ -2108,7 +2108,7 @@ gen_dis_table (struct bittree *ent)
{
if (ent->skip_flag)
printf ("%d: skipping %d\n", our_offset, ent->bits_to_skip);
if (ent->bits[0] != NULL)
printf ("%d: if (0:%d) goto %d\n", our_offset, zero_count + 1,
zero_dest);
@ -2164,7 +2164,7 @@ generate_disassembler (void)
if (ptr->opcode->type != IA64_TYPE_DYN)
add_dis_entry (bittree,
ptr->opcode->opcode, ptr->opcode->mask,
ptr->opcode->opcode, ptr->opcode->mask,
ptr->main_index,
ptr->completers, 1);
}
@ -2189,7 +2189,7 @@ print_string_table (void)
for (x = 0; x < strtablen; x++)
{
int len;
if (strlen (string_table[x]->s) > 75)
abort ();
@ -2291,7 +2291,7 @@ insert_gclist (struct completer_entry *ent)
end = i - 1;
else if (c == 0)
{
while (i > 0
while (i > 0
&& ent->name->num == glist[i - 1]->name->num)
i--;
@ -2368,7 +2368,7 @@ compute_completer_bits (struct main_entry *ment, struct completer_entry *ent)
while (p != NULL && ! p->is_terminal)
p = p->parent;
if (p != NULL)
p_bits = p->bits;
else
@ -2421,7 +2421,7 @@ collapse_redundant_completers (void)
/* Attach two lists of dependencies to each opcode.
1) all resources which, when already marked in use, conflict with this
opcode (chks)
opcode (chks)
2) all resources which must be marked in use when this opcode is used
(regs). */
static int
@ -2432,7 +2432,7 @@ insert_opcode_dependencies (struct ia64_opcode *opc,
(79) and cmpxchng has the most regs (54) so 100 here should be enough. */
int i;
int nregs = 0;
unsigned short regs[256];
unsigned short regs[256];
int nchks = 0;
unsigned short chks[256];
/* Flag insns for which no class matched; there should be none. */
@ -2504,7 +2504,7 @@ insert_opcode_dependencies (struct ia64_opcode *opc,
if (no_class_found)
warn (_("opcode %s has no class (ops %d %d %d)\n"),
opc->name,
opc->name,
opc->operands[0], opc->operands[1], opc->operands[2]);
return insert_dependencies (nchks, chks, nregs, regs);
@ -2600,7 +2600,7 @@ print_completer_entry (struct completer_entry *ent)
if (bits & 0xffffffff00000000LL)
abort ();
}
printf (" { 0x%x, 0x%x, %d, %d, %d, %d, %d, %d },\n",
(int)bits,
(int)mask,
@ -2629,7 +2629,7 @@ opcodes_eq (struct ia64_opcode *opc1, struct ia64_opcode *opc2)
int x;
int plen1, plen2;
if ((opc1->mask != opc2->mask) || (opc1->type != opc2->type)
if ((opc1->mask != opc2->mask) || (opc1->type != opc2->type)
|| (opc1->num_outputs != opc2->num_outputs)
|| (opc1->flags != opc2->flags))
return 0;
@ -2664,7 +2664,7 @@ add_opcode_entry (struct ia64_opcode *opc)
name = insert_string (prefix);
/* Walk the list of opcode table entries. If it's a new
instruction, allocate and fill in a new entry. Note
instruction, allocate and fill in a new entry. Note
the main table is alphabetical by opcode name. */
while (*place != NULL)
@ -2766,7 +2766,7 @@ shrink (struct ia64_opcode *table)
/* Program options. */
#define OPTION_SRCDIR 200
struct option long_options[] =
struct option long_options[] =
{
{"srcdir", required_argument, NULL, OPTION_SRCDIR},
{"debug", no_argument, NULL, 'd'},
@ -2796,7 +2796,7 @@ main (int argc, char **argv)
extern int chdir (char *);
char *srcdir = NULL;
int c;
program_name = *argv;
xmalloc_set_program_name (program_name);
@ -2824,7 +2824,7 @@ main (int argc, char **argv)
if (optind != argc)
usage (stdout, 1);
if (srcdir != NULL)
if (srcdir != NULL)
if (chdir (srcdir) != 0)
fail (_("unable to change directory to \"%s\", errno = %s\n"),
srcdir, strerror (errno));

8
opcodes/ia64-opc-m.c
View File

@ -190,7 +190,7 @@ struct ia64_opcode ia64_opcodes_m[] =
{"ptc.e", M0, OpX3X6b (1, 0, 0x34), {R3}, PRIV, 0, NULL},
#if 0
// old pre-psn variant with 2-bit hints;
// old pre-psn variant with 2-bit hints;
// saved for reference
/* integer load */
{"ld1", M, OpMXX6aHint (4, 0, 0, 0x00, 0), {R1, MR3}, EMPTY},
@ -893,7 +893,7 @@ struct ia64_opcode ia64_opcodes_m[] =
#undef LDINCREG
#if 0
// old pre-psn variant with 2-bit hints;
// old pre-psn variant with 2-bit hints;
// saved for reference
{"st1", M, OpMXX6aHint (4, 0, 0, 0x30, 0), {MR3, R2}, EMPTY},
@ -1281,7 +1281,7 @@ struct ia64_opcode ia64_opcodes_m[] =
#undef STINCIMMED
#if 0
// old pre-psn variant with 2-bit hints;
// old pre-psn variant with 2-bit hints;
// saved for reference
/* Floating-point load. */
{"ldfs", M, OpMXX6aHint (6, 0, 0, 0x02, 0), {F1, MR3}, EMPTY},
@ -1718,7 +1718,7 @@ struct ia64_opcode ia64_opcodes_m[] =
#undef FLDINCREG
#if 0
// old pre-psn variant with 2-bit hints;
// old pre-psn variant with 2-bit hints;
// saved for reference
/* Floating-point store. */
{"stfs", M, OpMXX6aHint (6, 0, 0, 0x32, 0), {MR3, F2}, EMPTY},

58
opcodes/ip2k-asm.c
View File

@ -58,7 +58,7 @@ parse_fr (CGEN_CPU_DESC cd,
{
const char *errmsg;
const char *old_strp;
char *afteroffset;
char *afteroffset;
enum cgen_parse_operand_result result_type;
bfd_vma value;
extern CGEN_KEYWORD ip2k_cgen_opval_register_names;
@ -107,7 +107,7 @@ parse_fr (CGEN_CPU_DESC cd,
}
else
{
*strp += 4;
*strp += 4;
*valuep = 0;
errmsg = NULL;
return errmsg;
@ -241,7 +241,7 @@ parse_addr16 (CGEN_CPU_DESC cd,
errmsg = _("parse_addr16: invalid opindex.");
return errmsg;
}
errmsg = cgen_parse_address (cd, strp, opindex, code,
& result_type, & value);
if (errmsg == NULL)
@ -255,7 +255,7 @@ parse_addr16 (CGEN_CPU_DESC cd,
else
/* code = BFD_RELOC_IP2K_LOW8DATA. */
value &= 0x00FF;
}
}
*valuep = value;
}
@ -272,7 +272,7 @@ parse_addr16_cjp (CGEN_CPU_DESC cd,
enum cgen_parse_operand_result result_type;
bfd_reloc_code_real_type code = BFD_RELOC_NONE;
bfd_vma value;
if (opindex == (CGEN_OPERAND_TYPE) IP2K_OPERAND_ADDR16CJP)
code = BFD_RELOC_IP2K_ADDR16CJP;
else if (opindex == (CGEN_OPERAND_TYPE) IP2K_OPERAND_ADDR16P)
@ -300,10 +300,10 @@ parse_addr16_cjp (CGEN_CPU_DESC cd,
are labels. */
*valuep = value;
}
else
else
errmsg = _("cgen_parse_address returned a symbol. Literal required.");
}
return errmsg;
return errmsg;
}
static const char *
@ -352,7 +352,7 @@ parse_lit8 (CGEN_CPU_DESC cd,
/* Parse %op operand. */
if (code != BFD_RELOC_NONE)
{
errmsg = cgen_parse_address (cd, strp, opindex, code,
errmsg = cgen_parse_address (cd, strp, opindex, code,
& result_type, & value);
if ((errmsg == NULL) &&
(result_type != CGEN_PARSE_OPERAND_RESULT_QUEUED))
@ -412,7 +412,7 @@ parse_bit3 (CGEN_CPU_DESC cd,
errmsg = _("Attempt to find bit index of 0");
return errmsg;
}
if (mode == 1)
{
count = 31;
@ -431,7 +431,7 @@ parse_bit3 (CGEN_CPU_DESC cd,
value >>= 1;
}
}
*valuep = count;
}
@ -514,7 +514,7 @@ ip2k_cgen_parse_operand (CGEN_CPU_DESC cd,
return errmsg;
}
cgen_parse_fn * const ip2k_cgen_parse_handlers[] =
cgen_parse_fn * const ip2k_cgen_parse_handlers[] =
{
parse_insn_normal,
};
@ -544,9 +544,9 @@ CGEN_ASM_INIT_HOOK
Returns NULL for success, an error message for failure. */
char *
char *
ip2k_cgen_build_insn_regex (CGEN_INSN *insn)
{
{
CGEN_OPCODE *opc = (CGEN_OPCODE *) CGEN_INSN_OPCODE (insn);
const char *mnem = CGEN_INSN_MNEMONIC (insn);
char rxbuf[CGEN_MAX_RX_ELEMENTS];
@ -585,18 +585,18 @@ ip2k_cgen_build_insn_regex (CGEN_INSN *insn)
/* Copy any remaining literals from the syntax string into the rx. */
for(; * syn != 0 && rx <= rxbuf + (CGEN_MAX_RX_ELEMENTS - 7 - 4); ++syn)
{
if (CGEN_SYNTAX_CHAR_P (* syn))
if (CGEN_SYNTAX_CHAR_P (* syn))
{
char c = CGEN_SYNTAX_CHAR (* syn);
switch (c)
switch (c)
{
/* Escape any regex metacharacters in the syntax. */
case '.': case '[': case '\\':
case '*': case '^': case '$':
case '.': case '[': case '\\':
case '*': case '^': case '$':
#ifdef CGEN_ESCAPE_EXTENDED_REGEX
case '?': case '{': case '}':
case '?': case '{': case '}':
case '(': case ')': case '*':
case '|': case '+': case ']':
#endif
@ -626,20 +626,20 @@ ip2k_cgen_build_insn_regex (CGEN_INSN *insn)
}
/* Trailing whitespace ok. */
* rx++ = '[';
* rx++ = ' ';
* rx++ = '\t';
* rx++ = ']';
* rx++ = '*';
* rx++ = '[';
* rx++ = ' ';
* rx++ = '\t';
* rx++ = ']';
* rx++ = '*';
/* But anchor it after that. */
* rx++ = '$';
* rx++ = '$';
* rx = '\0';
CGEN_INSN_RX (insn) = xmalloc (sizeof (regex_t));
reg_err = regcomp ((regex_t *) CGEN_INSN_RX (insn), rxbuf, REG_NOSUB);
if (reg_err == 0)
if (reg_err == 0)
return NULL;
else
{
@ -838,7 +838,7 @@ ip2k_cgen_assemble_insn (CGEN_CPU_DESC cd,
const CGEN_INSN *insn = ilist->insn;
recognized_mnemonic = 1;
#ifdef CGEN_VALIDATE_INSN_SUPPORTED
#ifdef CGEN_VALIDATE_INSN_SUPPORTED
/* Not usually needed as unsupported opcodes
shouldn't be in the hash lists. */
/* Is this insn supported by the selected cpu? */
@ -898,7 +898,7 @@ ip2k_cgen_assemble_insn (CGEN_CPU_DESC cd,
if (strlen (start) > 50)
/* xgettext:c-format */
sprintf (errbuf, "%s `%.50s...'", tmp_errmsg, start);
else
else
/* xgettext:c-format */
sprintf (errbuf, "%s `%.50s'", tmp_errmsg, start);
}
@ -907,11 +907,11 @@ ip2k_cgen_assemble_insn (CGEN_CPU_DESC cd,
if (strlen (start) > 50)
/* xgettext:c-format */
sprintf (errbuf, _("bad instruction `%.50s...'"), start);
else
else
/* xgettext:c-format */
sprintf (errbuf, _("bad instruction `%.50s'"), start);
}
*errmsg = errbuf;
return NULL;
}

30
opcodes/ip2k-desc.c
View File

@ -332,55 +332,55 @@ const CGEN_OPERAND ip2k_cgen_operand_table[] =
{
/* pc: program counter */
{ "pc", IP2K_OPERAND_PC, HW_H_PC, 0, 0,
{ 0, { (const PTR) &ip2k_cgen_ifld_table[IP2K_F_NIL] } },
{ 0, { (const PTR) &ip2k_cgen_ifld_table[IP2K_F_NIL] } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* addr16cjp: 13-bit address */
{ "addr16cjp", IP2K_OPERAND_ADDR16CJP, HW_H_UINT, 12, 13,
{ 0, { (const PTR) &ip2k_cgen_ifld_table[IP2K_F_ADDR16CJP] } },
{ 0, { (const PTR) &ip2k_cgen_ifld_table[IP2K_F_ADDR16CJP] } },
{ 0|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } } },
/* fr: register */
{ "fr", IP2K_OPERAND_FR, HW_H_REGISTERS, 8, 9,
{ 0, { (const PTR) &ip2k_cgen_ifld_table[IP2K_F_REG] } },
{ 0, { (const PTR) &ip2k_cgen_ifld_table[IP2K_F_REG] } },
{ 0|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } } },
/* lit8: 8-bit signed literal */
{ "lit8", IP2K_OPERAND_LIT8, HW_H_SINT, 7, 8,
{ 0, { (const PTR) &ip2k_cgen_ifld_table[IP2K_F_IMM8] } },
{ 0, { (const PTR) &ip2k_cgen_ifld_table[IP2K_F_IMM8] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* bitno: bit number */
{ "bitno", IP2K_OPERAND_BITNO, HW_H_UINT, 11, 3,
{ 0, { (const PTR) &ip2k_cgen_ifld_table[IP2K_F_BITNO] } },
{ 0, { (const PTR) &ip2k_cgen_ifld_table[IP2K_F_BITNO] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* addr16p: page number */
{ "addr16p", IP2K_OPERAND_ADDR16P, HW_H_UINT, 2, 3,
{ 0, { (const PTR) &ip2k_cgen_ifld_table[IP2K_F_PAGE3] } },
{ 0, { (const PTR) &ip2k_cgen_ifld_table[IP2K_F_PAGE3] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* addr16h: high 8 bits of address */
{ "addr16h", IP2K_OPERAND_ADDR16H, HW_H_UINT, 7, 8,
{ 0, { (const PTR) &ip2k_cgen_ifld_table[IP2K_F_IMM8] } },
{ 0, { (const PTR) &ip2k_cgen_ifld_table[IP2K_F_IMM8] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* addr16l: low 8 bits of address */
{ "addr16l", IP2K_OPERAND_ADDR16L, HW_H_UINT, 7, 8,
{ 0, { (const PTR) &ip2k_cgen_ifld_table[IP2K_F_IMM8] } },
{ 0, { (const PTR) &ip2k_cgen_ifld_table[IP2K_F_IMM8] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* reti3: reti flags */
{ "reti3", IP2K_OPERAND_RETI3, HW_H_UINT, 2, 3,
{ 0, { (const PTR) &ip2k_cgen_ifld_table[IP2K_F_RETI3] } },
{ 0, { (const PTR) &ip2k_cgen_ifld_table[IP2K_F_RETI3] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* pabits: page bits */
{ "pabits", IP2K_OPERAND_PABITS, HW_H_PABITS, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { (const PTR) 0 } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* zbit: zero bit */
{ "zbit", IP2K_OPERAND_ZBIT, HW_H_ZBIT, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { (const PTR) 0 } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* cbit: carry bit */
{ "cbit", IP2K_OPERAND_CBIT, HW_H_CBIT, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { (const PTR) 0 } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* dcbit: digit carry bit */
{ "dcbit", IP2K_OPERAND_DCBIT, HW_H_DCBIT, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { (const PTR) 0 } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* sentinel */
{ 0, 0, 0, 0, 0,
@ -1118,7 +1118,7 @@ ip2k_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...)
/* Default to not allowing signed overflow. */
cd->signed_overflow_ok_p = 0;
return (CGEN_CPU_DESC) cd;
}
@ -1158,7 +1158,7 @@ ip2k_cgen_cpu_close (CGEN_CPU_DESC cd)
for (i = 0; i < cd->insn_table.num_init_entries; ++i, ++insns)
if (CGEN_INSN_RX (insns))
regfree (CGEN_INSN_RX (insns));
}
}
if (cd->macro_insn_table.init_entries)
free ((CGEN_INSN *) cd->macro_insn_table.init_entries);

10
opcodes/ip2k-dis.c
View File

@ -290,7 +290,7 @@ ip2k_cgen_print_operand (CGEN_CPU_DESC cd,
}
}
cgen_print_fn * const ip2k_cgen_print_handlers[] =
cgen_print_fn * const ip2k_cgen_print_handlers[] =
{
print_insn_normal,
};
@ -480,7 +480,7 @@ print_insn (CGEN_CPU_DESC cd,
int length;
unsigned long insn_value_cropped;
#ifdef CGEN_VALIDATE_INSN_SUPPORTED
#ifdef CGEN_VALIDATE_INSN_SUPPORTED
/* Not needed as insn shouldn't be in hash lists if not supported. */
/* Supported by this cpu? */
if (! ip2k_cgen_insn_supported (cd, insn))
@ -498,7 +498,7 @@ print_insn (CGEN_CPU_DESC cd,
relevant part from the buffer. */
if ((unsigned) (CGEN_INSN_BITSIZE (insn) / 8) < buflen &&
(unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long))
insn_value_cropped = bfd_get_bits (buf, CGEN_INSN_BITSIZE (insn),
insn_value_cropped = bfd_get_bits (buf, CGEN_INSN_BITSIZE (insn),
info->endian == BFD_ENDIAN_BIG);
else
insn_value_cropped = insn_value;
@ -617,7 +617,7 @@ print_insn_ip2k (bfd_vma pc, disassemble_info *info)
arch = info->arch;
if (arch == bfd_arch_unknown)
arch = CGEN_BFD_ARCH;
/* There's no standard way to compute the machine or isa number
so we leave it to the target. */
#ifdef CGEN_COMPUTE_MACH
@ -658,7 +658,7 @@ print_insn_ip2k (bfd_vma pc, disassemble_info *info)
break;
}
}
}
}
/* If we haven't initialized yet, initialize the opcode table. */
if (! cd)

8
opcodes/ip2k-ibld.c
View File

@ -154,7 +154,7 @@ insert_normal (CGEN_CPU_DESC cd,
{
long minval = - (1L << (length - 1));
unsigned long maxval = mask;
if ((value > 0 && (unsigned long) value > maxval)
|| value < minval)
{
@ -192,7 +192,7 @@ insert_normal (CGEN_CPU_DESC cd,
{
long minval = - (1L << (length - 1));
long maxval = (1L << (length - 1)) - 1;
if (value < minval || value > maxval)
{
sprintf
@ -683,12 +683,12 @@ ip2k_cgen_extract_operand (CGEN_CPU_DESC cd,
return length;
}
cgen_insert_fn * const ip2k_cgen_insert_handlers[] =
cgen_insert_fn * const ip2k_cgen_insert_handlers[] =
{
insert_insn_normal,
};
cgen_extract_fn * const ip2k_cgen_extract_handlers[] =
cgen_extract_fn * const ip2k_cgen_extract_handlers[] =
{
extract_insn_normal,
};

2
opcodes/ip2k-opc.c
View File

@ -60,7 +60,7 @@ ip2k_cgen_insn_supported (CGEN_CPU_DESC cd, const CGEN_INSN *insn)
/* No mach attribute? Assume it's supported for all machs. */
if (machs == 0)
return 1;
return (machs & cd->machs) != 0;
}

48
opcodes/iq2000-asm.c
View File

@ -70,16 +70,16 @@ iq2000_cgen_isa_register (const char **strp)
int len;
int ch1, ch2;
if (**strp == 'r' || **strp == 'R')
if (**strp == 'r' || **strp == 'R')
{
len = strlen (*strp);
if (len == 2)
if (len == 2)
{
ch1 = (*strp)[1];
if ('0' <= ch1 && ch1 <= '9')
return 1;
}
else if (len == 3)
}
else if (len == 3)
{
ch1 = (*strp)[1];
ch2 = (*strp)[2];
@ -112,7 +112,7 @@ parse_mimm (CGEN_CPU_DESC cd,
else
{
long value;
errmsg = cgen_parse_signed_integer (cd, strp, opindex, & value);
if (errmsg == NULL)
{
@ -462,7 +462,7 @@ iq2000_cgen_parse_operand (CGEN_CPU_DESC cd,
return errmsg;
}
cgen_parse_fn * const iq2000_cgen_parse_handlers[] =
cgen_parse_fn * const iq2000_cgen_parse_handlers[] =
{
parse_insn_normal,
};
@ -492,9 +492,9 @@ CGEN_ASM_INIT_HOOK
Returns NULL for success, an error message for failure. */
char *
char *
iq2000_cgen_build_insn_regex (CGEN_INSN *insn)
{
{
CGEN_OPCODE *opc = (CGEN_OPCODE *) CGEN_INSN_OPCODE (insn);
const char *mnem = CGEN_INSN_MNEMONIC (insn);
char rxbuf[CGEN_MAX_RX_ELEMENTS];
@ -533,18 +533,18 @@ iq2000_cgen_build_insn_regex (CGEN_INSN *insn)
/* Copy any remaining literals from the syntax string into the rx. */
for(; * syn != 0 && rx <= rxbuf + (CGEN_MAX_RX_ELEMENTS - 7 - 4); ++syn)
{
if (CGEN_SYNTAX_CHAR_P (* syn))
if (CGEN_SYNTAX_CHAR_P (* syn))
{
char c = CGEN_SYNTAX_CHAR (* syn);
switch (c)
switch (c)
{
/* Escape any regex metacharacters in the syntax. */
case '.': case '[': case '\\':
case '*': case '^': case '$':
case '.': case '[': case '\\':
case '*': case '^': case '$':
#ifdef CGEN_ESCAPE_EXTENDED_REGEX
case '?': case '{': case '}':
case '?': case '{': case '}':
case '(': case ')': case '*':
case '|': case '+': case ']':
#endif
@ -574,20 +574,20 @@ iq2000_cgen_build_insn_regex (CGEN_INSN *insn)
}
/* Trailing whitespace ok. */
* rx++ = '[';
* rx++ = ' ';
* rx++ = '\t';
* rx++ = ']';
* rx++ = '*';
* rx++ = '[';
* rx++ = ' ';
* rx++ = '\t';
* rx++ = ']';
* rx++ = '*';
/* But anchor it after that. */
* rx++ = '$';
* rx++ = '$';
* rx = '\0';
CGEN_INSN_RX (insn) = xmalloc (sizeof (regex_t));
reg_err = regcomp ((regex_t *) CGEN_INSN_RX (insn), rxbuf, REG_NOSUB);
if (reg_err == 0)
if (reg_err == 0)
return NULL;
else
{
@ -786,7 +786,7 @@ iq2000_cgen_assemble_insn (CGEN_CPU_DESC cd,
const CGEN_INSN *insn = ilist->insn;
recognized_mnemonic = 1;
#ifdef CGEN_VALIDATE_INSN_SUPPORTED
#ifdef CGEN_VALIDATE_INSN_SUPPORTED
/* Not usually needed as unsupported opcodes
shouldn't be in the hash lists. */
/* Is this insn supported by the selected cpu? */
@ -846,7 +846,7 @@ iq2000_cgen_assemble_insn (CGEN_CPU_DESC cd,
if (strlen (start) > 50)
/* xgettext:c-format */
sprintf (errbuf, "%s `%.50s...'", tmp_errmsg, start);
else
else
/* xgettext:c-format */
sprintf (errbuf, "%s `%.50s'", tmp_errmsg, start);
}
@ -855,11 +855,11 @@ iq2000_cgen_assemble_insn (CGEN_CPU_DESC cd,
if (strlen (start) > 50)
/* xgettext:c-format */
sprintf (errbuf, _("bad instruction `%.50s...'"), start);
else
else
/* xgettext:c-format */
sprintf (errbuf, _("bad instruction `%.50s'"), start);
}
*errmsg = errbuf;
return NULL;
}

68
opcodes/iq2000-desc.c
View File

@ -316,131 +316,131 @@ const CGEN_OPERAND iq2000_cgen_operand_table[] =
{
/* pc: program counter */
{ "pc", IQ2000_OPERAND_PC, HW_H_PC, 0, 0,
{ 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_NIL] } },
{ 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_NIL] } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* rs: register Rs */
{ "rs", IQ2000_OPERAND_RS, HW_H_GR, 25, 5,
{ 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_RS] } },
{ 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_RS] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* rt: register Rt */
{ "rt", IQ2000_OPERAND_RT, HW_H_GR, 20, 5,
{ 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_RT] } },
{ 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_RT] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* rd: register Rd */
{ "rd", IQ2000_OPERAND_RD, HW_H_GR, 15, 5,
{ 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_RD] } },
{ 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_RD] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* rd-rs: register Rd from Rs */
{ "rd-rs", IQ2000_OPERAND_RD_RS, HW_H_GR, 15, 10,
{ 2, { (const PTR) &IQ2000_F_RD_RS_MULTI_IFIELD[0] } },
{ 2, { (const PTR) &IQ2000_F_RD_RS_MULTI_IFIELD[0] } },
{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
/* rd-rt: register Rd from Rt */
{ "rd-rt", IQ2000_OPERAND_RD_RT, HW_H_GR, 15, 10,
{ 2, { (const PTR) &IQ2000_F_RD_RT_MULTI_IFIELD[0] } },
{ 2, { (const PTR) &IQ2000_F_RD_RT_MULTI_IFIELD[0] } },
{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
/* rt-rs: register Rt from Rs */
{ "rt-rs", IQ2000_OPERAND_RT_RS, HW_H_GR, 20, 10,
{ 2, { (const PTR) &IQ2000_F_RT_RS_MULTI_IFIELD[0] } },
{ 2, { (const PTR) &IQ2000_F_RT_RS_MULTI_IFIELD[0] } },
{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
/* shamt: shift amount */
{ "shamt", IQ2000_OPERAND_SHAMT, HW_H_UINT, 10, 5,
{ 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_SHAMT] } },
{ 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_SHAMT] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* imm: immediate */
{ "imm", IQ2000_OPERAND_IMM, HW_H_UINT, 15, 16,
{ 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_IMM] } },
{ 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_IMM] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* offset: pc-relative offset */
{ "offset", IQ2000_OPERAND_OFFSET, HW_H_IADDR, 15, 16,
{ 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_OFFSET] } },
{ 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_OFFSET] } },
{ 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } } },
/* baseoff: base register offset */
{ "baseoff", IQ2000_OPERAND_BASEOFF, HW_H_IADDR, 15, 16,
{ 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_IMM] } },
{ 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_IMM] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* jmptarg: jump target */
{ "jmptarg", IQ2000_OPERAND_JMPTARG, HW_H_IADDR, 15, 16,
{ 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_JTARG] } },
{ 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_JTARG] } },
{ 0|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } } },
/* mask: mask */
{ "mask", IQ2000_OPERAND_MASK, HW_H_UINT, 9, 4,
{ 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_MASK] } },
{ 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_MASK] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* maskq10: iq10 mask */
{ "maskq10", IQ2000_OPERAND_MASKQ10, HW_H_UINT, 10, 5,
{ 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_MASKQ10] } },
{ 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_MASKQ10] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* maskl: mask left */
{ "maskl", IQ2000_OPERAND_MASKL, HW_H_UINT, 4, 5,
{ 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_MASKL] } },
{ 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_MASKL] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* count: count */
{ "count", IQ2000_OPERAND_COUNT, HW_H_UINT, 15, 7,
{ 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_COUNT] } },
{ 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_COUNT] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* _index: index */
{ "_index", IQ2000_OPERAND__INDEX, HW_H_UINT, 8, 9,
{ 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_INDEX] } },
{ 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_INDEX] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* execode: execcode */
{ "execode", IQ2000_OPERAND_EXECODE, HW_H_UINT, 25, 20,
{ 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_EXCODE] } },
{ 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_EXCODE] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* bytecount: byte count */
{ "bytecount", IQ2000_OPERAND_BYTECOUNT, HW_H_UINT, 7, 8,
{ 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_BYTECOUNT] } },
{ 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_BYTECOUNT] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* cam-y: cam global opn y */
{ "cam-y", IQ2000_OPERAND_CAM_Y, HW_H_UINT, 2, 3,
{ 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_CAM_Y] } },
{ 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_CAM_Y] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* cam-z: cam global mask z */
{ "cam-z", IQ2000_OPERAND_CAM_Z, HW_H_UINT, 5, 3,
{ 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_CAM_Z] } },
{ 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_CAM_Z] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* cm-3func: CM 3 bit fn field */
{ "cm-3func", IQ2000_OPERAND_CM_3FUNC, HW_H_UINT, 5, 3,
{ 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_CM_3FUNC] } },
{ 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_CM_3FUNC] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* cm-4func: CM 4 bit fn field */
{ "cm-4func", IQ2000_OPERAND_CM_4FUNC, HW_H_UINT, 5, 4,
{ 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_CM_4FUNC] } },
{ 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_CM_4FUNC] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* cm-3z: CM 3 bit Z field */
{ "cm-3z", IQ2000_OPERAND_CM_3Z, HW_H_UINT, 1, 2,
{ 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_CM_3Z] } },
{ 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_CM_3Z] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* cm-4z: CM 4 bit Z field */
{ "cm-4z", IQ2000_OPERAND_CM_4Z, HW_H_UINT, 2, 3,
{ 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_CM_4Z] } },
{ 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_CM_4Z] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* base: base register */
{ "base", IQ2000_OPERAND_BASE, HW_H_GR, 25, 5,
{ 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_RS] } },
{ 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_RS] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* maskr: mask right */
{ "maskr", IQ2000_OPERAND_MASKR, HW_H_UINT, 25, 5,
{ 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_RS] } },
{ 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_RS] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* bitnum: bit number */
{ "bitnum", IQ2000_OPERAND_BITNUM, HW_H_UINT, 20, 5,
{ 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_RT] } },
{ 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_RT] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* hi16: high 16 bit immediate */
{ "hi16", IQ2000_OPERAND_HI16, HW_H_UINT, 15, 16,
{ 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_IMM] } },
{ 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_IMM] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* lo16: 16 bit signed immediate, for low */
{ "lo16", IQ2000_OPERAND_LO16, HW_H_UINT, 15, 16,
{ 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_IMM] } },
{ 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_IMM] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* mlo16: negated 16 bit signed immediate */
{ "mlo16", IQ2000_OPERAND_MLO16, HW_H_UINT, 15, 16,
{ 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_IMM] } },
{ 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_IMM] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* jmptargq10: iq10 21-bit jump offset */
{ "jmptargq10", IQ2000_OPERAND_JMPTARGQ10, HW_H_IADDR, 20, 21,
{ 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_JTARGQ10] } },
{ 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_JTARGQ10] } },
{ 0|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } } },
/* sentinel */
{ 0, 0, 0, 0, 0,
@ -2123,7 +2123,7 @@ iq2000_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...)
/* Default to not allowing signed overflow. */
cd->signed_overflow_ok_p = 0;
return (CGEN_CPU_DESC) cd;
}
@ -2163,7 +2163,7 @@ iq2000_cgen_cpu_close (CGEN_CPU_DESC cd)
for (i = 0; i < cd->insn_table.num_init_entries; ++i, ++insns)
if (CGEN_INSN_RX (insns))
regfree (CGEN_INSN_RX (insns));
}
}
if (cd->macro_insn_table.init_entries)
free ((CGEN_INSN *) cd->macro_insn_table.init_entries);

10
opcodes/iq2000-dis.c
View File

@ -191,7 +191,7 @@ iq2000_cgen_print_operand (CGEN_CPU_DESC cd,
}
}
cgen_print_fn * const iq2000_cgen_print_handlers[] =
cgen_print_fn * const iq2000_cgen_print_handlers[] =
{
print_insn_normal,
};
@ -381,7 +381,7 @@ print_insn (CGEN_CPU_DESC cd,
int length;
unsigned long insn_value_cropped;
#ifdef CGEN_VALIDATE_INSN_SUPPORTED
#ifdef CGEN_VALIDATE_INSN_SUPPORTED
/* Not needed as insn shouldn't be in hash lists if not supported. */
/* Supported by this cpu? */
if (! iq2000_cgen_insn_supported (cd, insn))
@ -399,7 +399,7 @@ print_insn (CGEN_CPU_DESC cd,
relevant part from the buffer. */
if ((unsigned) (CGEN_INSN_BITSIZE (insn) / 8) < buflen &&
(unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long))
insn_value_cropped = bfd_get_bits (buf, CGEN_INSN_BITSIZE (insn),
insn_value_cropped = bfd_get_bits (buf, CGEN_INSN_BITSIZE (insn),
info->endian == BFD_ENDIAN_BIG);
else
insn_value_cropped = insn_value;
@ -518,7 +518,7 @@ print_insn_iq2000 (bfd_vma pc, disassemble_info *info)
arch = info->arch;
if (arch == bfd_arch_unknown)
arch = CGEN_BFD_ARCH;
/* There's no standard way to compute the machine or isa number
so we leave it to the target. */
#ifdef CGEN_COMPUTE_MACH
@ -559,7 +559,7 @@ print_insn_iq2000 (bfd_vma pc, disassemble_info *info)
break;
}
}
}
}
/* If we haven't initialized yet, initialize the opcode table. */
if (! cd)

8
opcodes/iq2000-ibld.c
View File

@ -154,7 +154,7 @@ insert_normal (CGEN_CPU_DESC cd,
{
long minval = - (1L << (length - 1));
unsigned long maxval = mask;
if ((value > 0 && (unsigned long) value > maxval)
|| value < minval)
{
@ -192,7 +192,7 @@ insert_normal (CGEN_CPU_DESC cd,
{
long minval = - (1L << (length - 1));
long maxval = (1L << (length - 1)) - 1;
if (value < minval || value > maxval)
{
sprintf
@ -889,12 +889,12 @@ iq2000_cgen_extract_operand (CGEN_CPU_DESC cd,
return length;
}
cgen_insert_fn * const iq2000_cgen_insert_handlers[] =
cgen_insert_fn * const iq2000_cgen_insert_handlers[] =
{
insert_insn_normal,
};
cgen_extract_fn * const iq2000_cgen_extract_handlers[] =
cgen_extract_fn * const iq2000_cgen_extract_handlers[] =
{
extract_insn_normal,
};

38
opcodes/lm32-asm.c
View File

@ -352,7 +352,7 @@ lm32_cgen_parse_operand (CGEN_CPU_DESC cd,
return errmsg;
}
cgen_parse_fn * const lm32_cgen_parse_handlers[] =
cgen_parse_fn * const lm32_cgen_parse_handlers[] =
{
parse_insn_normal,
};
@ -382,9 +382,9 @@ CGEN_ASM_INIT_HOOK
Returns NULL for success, an error message for failure. */
char *
char *
lm32_cgen_build_insn_regex (CGEN_INSN *insn)
{
{
CGEN_OPCODE *opc = (CGEN_OPCODE *) CGEN_INSN_OPCODE (insn);
const char *mnem = CGEN_INSN_MNEMONIC (insn);
char rxbuf[CGEN_MAX_RX_ELEMENTS];
@ -423,18 +423,18 @@ lm32_cgen_build_insn_regex (CGEN_INSN *insn)
/* Copy any remaining literals from the syntax string into the rx. */
for(; * syn != 0 && rx <= rxbuf + (CGEN_MAX_RX_ELEMENTS - 7 - 4); ++syn)
{
if (CGEN_SYNTAX_CHAR_P (* syn))
if (CGEN_SYNTAX_CHAR_P (* syn))
{
char c = CGEN_SYNTAX_CHAR (* syn);
switch (c)
switch (c)
{
/* Escape any regex metacharacters in the syntax. */
case '.': case '[': case '\\':
case '*': case '^': case '$':
case '.': case '[': case '\\':
case '*': case '^': case '$':
#ifdef CGEN_ESCAPE_EXTENDED_REGEX
case '?': case '{': case '}':
case '?': case '{': case '}':
case '(': case ')': case '*':
case '|': case '+': case ']':
#endif
@ -464,20 +464,20 @@ lm32_cgen_build_insn_regex (CGEN_INSN *insn)
}
/* Trailing whitespace ok. */
* rx++ = '[';
* rx++ = ' ';
* rx++ = '\t';
* rx++ = ']';
* rx++ = '*';
* rx++ = '[';
* rx++ = ' ';
* rx++ = '\t';
* rx++ = ']';
* rx++ = '*';
/* But anchor it after that. */
* rx++ = '$';
* rx++ = '$';
* rx = '\0';
CGEN_INSN_RX (insn) = xmalloc (sizeof (regex_t));
reg_err = regcomp ((regex_t *) CGEN_INSN_RX (insn), rxbuf, REG_NOSUB);
if (reg_err == 0)
if (reg_err == 0)
return NULL;
else
{
@ -676,7 +676,7 @@ lm32_cgen_assemble_insn (CGEN_CPU_DESC cd,
const CGEN_INSN *insn = ilist->insn;
recognized_mnemonic = 1;
#ifdef CGEN_VALIDATE_INSN_SUPPORTED
#ifdef CGEN_VALIDATE_INSN_SUPPORTED
/* Not usually needed as unsupported opcodes
shouldn't be in the hash lists. */
/* Is this insn supported by the selected cpu? */
@ -736,7 +736,7 @@ lm32_cgen_assemble_insn (CGEN_CPU_DESC cd,
if (strlen (start) > 50)
/* xgettext:c-format */
sprintf (errbuf, "%s `%.50s...'", tmp_errmsg, start);
else
else
/* xgettext:c-format */
sprintf (errbuf, "%s `%.50s'", tmp_errmsg, start);
}
@ -745,11 +745,11 @@ lm32_cgen_assemble_insn (CGEN_CPU_DESC cd,
if (strlen (start) > 50)
/* xgettext:c-format */
sprintf (errbuf, _("bad instruction `%.50s...'"), start);
else
else
/* xgettext:c-format */
sprintf (errbuf, _("bad instruction `%.50s'"), start);
}
*errmsg = errbuf;
return NULL;
}

40
opcodes/lm32-desc.c
View File

@ -274,75 +274,75 @@ const CGEN_OPERAND lm32_cgen_operand_table[] =
{
/* pc: program counter */
{ "pc", LM32_OPERAND_PC, HW_H_PC, 0, 0,
{ 0, { (const PTR) &lm32_cgen_ifld_table[LM32_F_NIL] } },
{ 0, { (const PTR) &lm32_cgen_ifld_table[LM32_F_NIL] } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* r0: register 0 */
{ "r0", LM32_OPERAND_R0, HW_H_GR, 25, 5,
{ 0, { (const PTR) &lm32_cgen_ifld_table[LM32_F_R0] } },
{ 0, { (const PTR) &lm32_cgen_ifld_table[LM32_F_R0] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* r1: register 1 */
{ "r1", LM32_OPERAND_R1, HW_H_GR, 20, 5,
{ 0, { (const PTR) &lm32_cgen_ifld_table[LM32_F_R1] } },
{ 0, { (const PTR) &lm32_cgen_ifld_table[LM32_F_R1] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* r2: register 2 */
{ "r2", LM32_OPERAND_R2, HW_H_GR, 15, 5,
{ 0, { (const PTR) &lm32_cgen_ifld_table[LM32_F_R2] } },
{ 0, { (const PTR) &lm32_cgen_ifld_table[LM32_F_R2] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* shift: shift amout */
{ "shift", LM32_OPERAND_SHIFT, HW_H_UINT, 4, 5,
{ 0, { (const PTR) &lm32_cgen_ifld_table[LM32_F_SHIFT] } },
{ 0, { (const PTR) &lm32_cgen_ifld_table[LM32_F_SHIFT] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* imm: signed immediate */
{ "imm", LM32_OPERAND_IMM, HW_H_SINT, 15, 16,
{ 0, { (const PTR) &lm32_cgen_ifld_table[LM32_F_IMM] } },
{ 0, { (const PTR) &lm32_cgen_ifld_table[LM32_F_IMM] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* uimm: unsigned immediate */
{ "uimm", LM32_OPERAND_UIMM, HW_H_UINT, 15, 16,
{ 0, { (const PTR) &lm32_cgen_ifld_table[LM32_F_UIMM] } },
{ 0, { (const PTR) &lm32_cgen_ifld_table[LM32_F_UIMM] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* branch: branch offset */
{ "branch", LM32_OPERAND_BRANCH, HW_H_IADDR, 15, 16,
{ 0, { (const PTR) &lm32_cgen_ifld_table[LM32_F_BRANCH] } },
{ 0, { (const PTR) &lm32_cgen_ifld_table[LM32_F_BRANCH] } },
{ 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } } },
/* call: call offset */
{ "call", LM32_OPERAND_CALL, HW_H_IADDR, 25, 26,
{ 0, { (const PTR) &lm32_cgen_ifld_table[LM32_F_CALL] } },
{ 0, { (const PTR) &lm32_cgen_ifld_table[LM32_F_CALL] } },
{ 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } } },
/* csr: csr */
{ "csr", LM32_OPERAND_CSR, HW_H_CSR, 25, 5,
{ 0, { (const PTR) &lm32_cgen_ifld_table[LM32_F_CSR] } },
{ 0, { (const PTR) &lm32_cgen_ifld_table[LM32_F_CSR] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* user: user */
{ "user", LM32_OPERAND_USER, HW_H_UINT, 10, 11,
{ 0, { (const PTR) &lm32_cgen_ifld_table[LM32_F_USER] } },
{ 0, { (const PTR) &lm32_cgen_ifld_table[LM32_F_USER] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* exception: exception */
{ "exception", LM32_OPERAND_EXCEPTION, HW_H_UINT, 25, 26,
{ 0, { (const PTR) &lm32_cgen_ifld_table[LM32_F_EXCEPTION] } },
{ 0, { (const PTR) &lm32_cgen_ifld_table[LM32_F_EXCEPTION] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* hi16: high 16-bit immediate */
{ "hi16", LM32_OPERAND_HI16, HW_H_UINT, 15, 16,
{ 0, { (const PTR) &lm32_cgen_ifld_table[LM32_F_UIMM] } },
{ 0, { (const PTR) &lm32_cgen_ifld_table[LM32_F_UIMM] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* lo16: low 16-bit immediate */
{ "lo16", LM32_OPERAND_LO16, HW_H_UINT, 15, 16,
{ 0, { (const PTR) &lm32_cgen_ifld_table[LM32_F_UIMM] } },
{ 0, { (const PTR) &lm32_cgen_ifld_table[LM32_F_UIMM] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* gp16: gp relative 16-bit immediate */
{ "gp16", LM32_OPERAND_GP16, HW_H_SINT, 15, 16,
{ 0, { (const PTR) &lm32_cgen_ifld_table[LM32_F_IMM] } },
{ 0, { (const PTR) &lm32_cgen_ifld_table[LM32_F_IMM] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* got16: got 16-bit immediate */
{ "got16", LM32_OPERAND_GOT16, HW_H_SINT, 15, 16,
{ 0, { (const PTR) &lm32_cgen_ifld_table[LM32_F_IMM] } },
{ 0, { (const PTR) &lm32_cgen_ifld_table[LM32_F_IMM] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* gotoffhi16: got offset high 16-bit immediate */
{ "gotoffhi16", LM32_OPERAND_GOTOFFHI16, HW_H_SINT, 15, 16,
{ 0, { (const PTR) &lm32_cgen_ifld_table[LM32_F_IMM] } },
{ 0, { (const PTR) &lm32_cgen_ifld_table[LM32_F_IMM] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* gotofflo16: got offset low 16-bit immediate */
{ "gotofflo16", LM32_OPERAND_GOTOFFLO16, HW_H_SINT, 15, 16,
{ 0, { (const PTR) &lm32_cgen_ifld_table[LM32_F_IMM] } },
{ 0, { (const PTR) &lm32_cgen_ifld_table[LM32_F_IMM] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* sentinel */
{ 0, 0, 0, 0, 0,
@ -1105,7 +1105,7 @@ lm32_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...)
/* Default to not allowing signed overflow. */
cd->signed_overflow_ok_p = 0;
return (CGEN_CPU_DESC) cd;
}
@ -1145,7 +1145,7 @@ lm32_cgen_cpu_close (CGEN_CPU_DESC cd)
for (i = 0; i < cd->insn_table.num_init_entries; ++i, ++insns)
if (CGEN_INSN_RX (insns))
regfree (CGEN_INSN_RX (insns));
}
}
if (cd->macro_insn_table.init_entries)
free ((CGEN_INSN *) cd->macro_insn_table.init_entries);

10
opcodes/lm32-dis.c
View File

@ -149,7 +149,7 @@ lm32_cgen_print_operand (CGEN_CPU_DESC cd,
}
}
cgen_print_fn * const lm32_cgen_print_handlers[] =
cgen_print_fn * const lm32_cgen_print_handlers[] =
{
print_insn_normal,
};
@ -339,7 +339,7 @@ print_insn (CGEN_CPU_DESC cd,
int length;
unsigned long insn_value_cropped;
#ifdef CGEN_VALIDATE_INSN_SUPPORTED
#ifdef CGEN_VALIDATE_INSN_SUPPORTED
/* Not needed as insn shouldn't be in hash lists if not supported. */
/* Supported by this cpu? */
if (! lm32_cgen_insn_supported (cd, insn))
@ -357,7 +357,7 @@ print_insn (CGEN_CPU_DESC cd,
relevant part from the buffer. */
if ((unsigned) (CGEN_INSN_BITSIZE (insn) / 8) < buflen &&
(unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long))
insn_value_cropped = bfd_get_bits (buf, CGEN_INSN_BITSIZE (insn),
insn_value_cropped = bfd_get_bits (buf, CGEN_INSN_BITSIZE (insn),
info->endian == BFD_ENDIAN_BIG);
else
insn_value_cropped = insn_value;
@ -476,7 +476,7 @@ print_insn_lm32 (bfd_vma pc, disassemble_info *info)
arch = info->arch;
if (arch == bfd_arch_unknown)
arch = CGEN_BFD_ARCH;
/* There's no standard way to compute the machine or isa number
so we leave it to the target. */
#ifdef CGEN_COMPUTE_MACH
@ -517,7 +517,7 @@ print_insn_lm32 (bfd_vma pc, disassemble_info *info)
break;
}
}
}
}
/* If we haven't initialized yet, initialize the opcode table. */
if (! cd)

8
opcodes/lm32-ibld.c
View File

@ -154,7 +154,7 @@ insert_normal (CGEN_CPU_DESC cd,
{
long minval = - (1L << (length - 1));
unsigned long maxval = mask;
if ((value > 0 && (unsigned long) value > maxval)
|| value < minval)
{
@ -192,7 +192,7 @@ insert_normal (CGEN_CPU_DESC cd,
{
long minval = - (1L << (length - 1));
long maxval = (1L << (length - 1)) - 1;
if (value < minval || value > maxval)
{
sprintf
@ -739,12 +739,12 @@ lm32_cgen_extract_operand (CGEN_CPU_DESC cd,
return length;
}
cgen_insert_fn * const lm32_cgen_insert_handlers[] =
cgen_insert_fn * const lm32_cgen_insert_handlers[] =
{
insert_insn_normal,
};
cgen_extract_fn * const lm32_cgen_extract_handlers[] =
cgen_extract_fn * const lm32_cgen_extract_handlers[] =
{
extract_insn_normal,
};

2
opcodes/lm32-opc.h
View File

@ -31,7 +31,7 @@ This file is part of the GNU Binutils and/or GDB, the GNU debugger.
#define CGEN_VERBOSE_ASSEMBLER_ERRORS
#define CGEN_DIS_HASH_SIZE 64
#define CGEN_DIS_HASH(buf,value) ((value >> 26) & 0x3f)
#define CGEN_DIS_HASH(buf,value) ((value >> 26) & 0x3f)
/* -- asm.c */
/* Enum declaration for lm32 instruction types. */

12
opcodes/m10200-dis.c
View File

@ -20,7 +20,7 @@
#include "sysdep.h"
#include <stdio.h>
#include "opcode/mn10200.h"
#include "opcode/mn10200.h"
#include "dis-asm.h"
#include "opintl.h"
@ -54,7 +54,7 @@ disassemble (bfd_vma memaddr,
mysize = 5;
else
abort ();
if (op->format == FMT_2 || op->format == FMT_5)
extra_shift = 8;
else if (op->format == FMT_3
@ -70,7 +70,7 @@ disassemble (bfd_vma memaddr,
const unsigned char *opindex_ptr;
unsigned int nocomma;
int paren = 0;
match = 1;
(*info->fprintf_func) (info->stream, "%s\t", op->name);
@ -104,7 +104,7 @@ disassemble (bfd_vma memaddr,
(*info->fprintf_func) (info->stream, ",");
nocomma = 0;
if ((operand->flags & MN10200_OPERAND_DREG) != 0)
{
value = ((insn >> (operand->shift + extra_shift))
@ -144,7 +144,7 @@ disassemble (bfd_vma memaddr,
else if ((operand->flags & MN10200_OPERAND_MEMADDR) != 0)
(*info->print_address_func) (value, info);
else
else
(*info->fprintf_func) (info->stream, "%ld", value);
}
/* All done. */
@ -157,7 +157,7 @@ disassemble (bfd_vma memaddr,
(*info->fprintf_func) (info->stream, _("unknown\t0x%04lx"), insn);
}
int
int
print_insn_mn10200 (bfd_vma memaddr, struct disassemble_info *info)
{
int status;

10
opcodes/m10200-opc.c
View File

@ -24,7 +24,7 @@
const struct mn10200_operand mn10200_operands[] = {
#define UNUSED 0
{0, 0, 0},
{0, 0, 0},
/* dn register in the first register operand position. */
#define DN0 (UNUSED+1)
@ -130,7 +130,7 @@ const struct mn10200_operand mn10200_operands[] = {
/* Either an open paren or close paren. */
#define PAREN (SIMM16N+1)
{0, 0, MN10200_OPERAND_PAREN},
{0, 0, MN10200_OPERAND_PAREN},
/* dn register that appears in the first and second register positions. */
#define DN01 (PAREN+1)
@ -139,10 +139,10 @@ const struct mn10200_operand mn10200_operands[] = {
/* an register that appears in the first and second register positions. */
#define AN01 (DN01+1)
{2, 0, MN10200_OPERAND_AREG | MN10200_OPERAND_REPEATED},
} ;
} ;
#define MEM(ADDR) PAREN, ADDR, PAREN
#define MEM2(ADDR1,ADDR2) PAREN, ADDR1, ADDR2, PAREN
#define MEM(ADDR) PAREN, ADDR, PAREN
#define MEM2(ADDR1,ADDR2) PAREN, ADDR1, ADDR2, PAREN
/* The opcode table.

24
opcodes/m10300-opc.c
View File

@ -26,7 +26,7 @@
const struct mn10300_operand mn10300_operands[] = {
#define UNUSED 0
{0, 0, 0},
{0, 0, 0},
/* dn register in the first register operand position. */
#define DN0 (UNUSED+1)
@ -97,7 +97,7 @@ const struct mn10300_operand mn10300_operands[] = {
{16, 0, MN10300_OPERAND_PROMOTE | MN10300_OPERAND_MEMADDR},
/* 32bit immediate, high 16 bits in the main instruction
word, 16bits in the extension word.
word, 16bits in the extension word.
The "bits" field indicates how many bits are in the
main instruction word for MN10300_OPERAND_SPLIT! */
@ -114,7 +114,7 @@ const struct mn10300_operand mn10300_operands[] = {
/* 32bit immediate, high 16 bits in the main instruction
word, 16bits in the extension word, low 16bits are left
shifted 8 places.
shifted 8 places.
The "bits" field indicates how many bits are in the
main instruction word for MN10300_OPERAND_SPLIT! */
@ -131,7 +131,7 @@ const struct mn10300_operand mn10300_operands[] = {
/* 32bit immediate, high 24 bits in the main instruction
word, 8 in the extension word, low 8 bits are left
shifted 16 places.
shifted 16 places.
The "bits" field indicates how many bits are in the
main instruction word for MN10300_OPERAND_SPLIT! */
@ -184,7 +184,7 @@ const struct mn10300_operand mn10300_operands[] = {
/* Either an open paren or close paren. */
#define PAREN (SIMM16+1)
{0, 0, MN10300_OPERAND_PAREN},
{0, 0, MN10300_OPERAND_PAREN},
/* dn register that appears in the first and second register positions. */
#define DN01 (PAREN+1)
@ -270,7 +270,7 @@ const struct mn10300_operand mn10300_operands[] = {
/* + for autoincrement */
#define PLUS (XRM2+1)
{0, 0, MN10300_OPERAND_PLUS},
{0, 0, MN10300_OPERAND_PLUS},
#define XRN02 (PLUS+1)
{4, 0, MN10300_OPERAND_XRREG | MN10300_OPERAND_REPEATED},
@ -420,12 +420,12 @@ const struct mn10300_operand mn10300_operands[] = {
#define FDN3 (FDN2+1)
{5, -12, MN10300_OPERAND_FDREG },
} ;
} ;
#define MEM(ADDR) PAREN, ADDR, PAREN
#define MEMINC(ADDR) PAREN, ADDR, PLUS, PAREN
#define MEMINC2(ADDR,INC) PAREN, ADDR, PLUS, INC, PAREN
#define MEM2(ADDR1,ADDR2) PAREN, ADDR1, ADDR2, PAREN
#define MEM(ADDR) PAREN, ADDR, PAREN
#define MEMINC(ADDR) PAREN, ADDR, PLUS, PAREN
#define MEMINC2(ADDR,INC) PAREN, ADDR, PLUS, INC, PAREN
#define MEM2(ADDR1,ADDR2) PAREN, ADDR1, ADDR2, PAREN
/* The opcode table.
@ -1666,7 +1666,7 @@ const struct mn10300_opcode mn10300_opcodes[] = {
{ "leq_mov", 0xf7e00008, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}},
{ "lne_mov", 0xf7e00009, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}},
{ "lra_mov", 0xf7e0000a, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}},
{ 0, 0, 0, 0, 0, 0, {0}},
} ;

78
opcodes/m32c-asm.c
View File

@ -58,14 +58,14 @@ m32c_cgen_isa_register (const char **strp)
{
int u;
const char *s = *strp;
static char * m32c_register_names [] =
static char * m32c_register_names [] =
{
"r0", "r1", "r2", "r3", "r0l", "r0h", "r1l", "r1h",
"a0", "a1", "r2r0", "r3r1", "sp", "fb", "dct0", "dct1", "flg", "svf",
"drc0", "drc1", "dmd0", "dmd1", "intb", "svp", "vct", "isp", "dma0",
"dma1", "dra0", "dra1", "dsa0", "dsa1", 0
};
for (u = 0; m32c_register_names[u]; u++)
{
int len = strlen (m32c_register_names[u]);
@ -148,7 +148,7 @@ parse_unsigned8 (CGEN_CPU_DESC cd, const char **strp,
return errmsg;
}
if (strncmp (*strp, "0x0", 3) == 0
if (strncmp (*strp, "0x0", 3) == 0
|| (**strp == '0' && *(*strp + 1) != 'x'))
have_zero = 1;
@ -173,7 +173,7 @@ parse_signed4 (CGEN_CPU_DESC cd, const char **strp,
signed long value;
long have_zero = 0;
if (strncmp (*strp, "0x0", 3) == 0
if (strncmp (*strp, "0x0", 3) == 0
|| (**strp == '0' && *(*strp + 1) != 'x'))
have_zero = 1;
@ -198,7 +198,7 @@ parse_signed4n (CGEN_CPU_DESC cd, const char **strp,
signed long value;
long have_zero = 0;
if (strncmp (*strp, "0x0", 3) == 0
if (strncmp (*strp, "0x0", 3) == 0
|| (**strp == '0' && *(*strp + 1) != 'x'))
have_zero = 1;
@ -292,10 +292,10 @@ parse_unsigned16 (CGEN_CPU_DESC cd, const char **strp,
if (m32c_cgen_isa_register (strp))
return "Invalid literal"; /* Anything -- will not be seen. */
if (strncmp (*strp, "0x0", 3) == 0
if (strncmp (*strp, "0x0", 3) == 0
|| (**strp == '0' && *(*strp + 1) != 'x'))
have_zero = 1;
errmsg = cgen_parse_unsigned_integer (cd, strp, opindex, & value);
if (errmsg)
return errmsg;
@ -381,7 +381,7 @@ parse_unsigned20 (CGEN_CPU_DESC cd, const char **strp,
{
const char *errmsg = 0;
unsigned long value;
/* Don't successfully parse literals beginning with '['. */
if (**strp == '[')
return "Invalid literal"; /* Anything -- will not be seen. */
@ -407,7 +407,7 @@ parse_unsigned24 (CGEN_CPU_DESC cd, const char **strp,
{
const char *errmsg = 0;
unsigned long value;
/* Don't successfully parse literals beginning with '['. */
if (**strp == '[')
return "Invalid literal"; /* Anything -- will not be seen. */
@ -453,7 +453,7 @@ parse_signed32 (CGEN_CPU_DESC cd, const char **strp,
{
const char *errmsg = 0;
signed long value;
errmsg = cgen_parse_signed_integer (cd, strp, opindex, & value);
if (errmsg)
return errmsg;
@ -486,7 +486,7 @@ parse_imm3_S (CGEN_CPU_DESC cd, const char **strp,
{
const char *errmsg = 0;
signed long value;
errmsg = cgen_parse_signed_integer (cd, strp, opindex, & value);
if (errmsg)
return errmsg;
@ -504,7 +504,7 @@ parse_bit3_S (CGEN_CPU_DESC cd, const char **strp,
{
const char *errmsg = 0;
signed long value;
errmsg = cgen_parse_signed_integer (cd, strp, opindex, & value);
if (errmsg)
return errmsg;
@ -591,7 +591,7 @@ parse_unsigned_bitbase (CGEN_CPU_DESC cd, const char **strp,
++newp;
if (strncmp (newp, "0x0", 3) == 0
if (strncmp (newp, "0x0", 3) == 0
|| (newp[0] == '0' && newp[1] != 'x'))
have_zero = 1;
@ -646,7 +646,7 @@ parse_signed_bitbase (CGEN_CPU_DESC cd, const char **strp,
++newp;
if (strncmp (newp, "0x0", 3) == 0
if (strncmp (newp, "0x0", 3) == 0
|| (newp[0] == '0' && newp[1] != 'x'))
have_zero = 1;
@ -731,7 +731,7 @@ static const char *
parse_suffix (const char **strp, char suffix)
{
const char *newp = *strp;
if (**strp == ':' && TOLOWER (*(*strp + 1)) == suffix)
newp = *strp + 2;
@ -740,7 +740,7 @@ parse_suffix (const char **strp, char suffix)
*strp = newp;
return 0;
}
return "Invalid suffix"; /* Anything -- will not be seen. */
}
@ -859,7 +859,7 @@ parse_regset (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
{
const char *errmsg = 0;
int regno = 0;
*valuep = 0;
while (**strp && **strp != ')')
{
@ -878,19 +878,19 @@ parse_regset (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
errmsg = _("Register number is not valid");
regno = **strp - '0' + 4;
}
else if (strncasecmp (*strp, "sb", 2) == 0 || strncasecmp (*strp, "SB", 2) == 0)
{
regno = 6;
++*strp;
}
else if (strncasecmp (*strp, "fb", 2) == 0 || strncasecmp (*strp, "FB", 2) == 0)
{
regno = 7;
++*strp;
}
if (push) /* Mask is reversed for push. */
*valuep |= 0x80 >> regno;
else
@ -1587,7 +1587,7 @@ m32c_cgen_parse_operand (CGEN_CPU_DESC cd,
return errmsg;
}
cgen_parse_fn * const m32c_cgen_parse_handlers[] =
cgen_parse_fn * const m32c_cgen_parse_handlers[] =
{
parse_insn_normal,
};
@ -1617,9 +1617,9 @@ CGEN_ASM_INIT_HOOK
Returns NULL for success, an error message for failure. */
char *
char *
m32c_cgen_build_insn_regex (CGEN_INSN *insn)
{
{
CGEN_OPCODE *opc = (CGEN_OPCODE *) CGEN_INSN_OPCODE (insn);
const char *mnem = CGEN_INSN_MNEMONIC (insn);
char rxbuf[CGEN_MAX_RX_ELEMENTS];
@ -1658,18 +1658,18 @@ m32c_cgen_build_insn_regex (CGEN_INSN *insn)
/* Copy any remaining literals from the syntax string into the rx. */
for(; * syn != 0 && rx <= rxbuf + (CGEN_MAX_RX_ELEMENTS - 7 - 4); ++syn)
{
if (CGEN_SYNTAX_CHAR_P (* syn))
if (CGEN_SYNTAX_CHAR_P (* syn))
{
char c = CGEN_SYNTAX_CHAR (* syn);
switch (c)
switch (c)
{
/* Escape any regex metacharacters in the syntax. */
case '.': case '[': case '\\':
case '*': case '^': case '$':
case '.': case '[': case '\\':
case '*': case '^': case '$':
#ifdef CGEN_ESCAPE_EXTENDED_REGEX
case '?': case '{': case '}':
case '?': case '{': case '}':
case '(': case ')': case '*':
case '|': case '+': case ']':
#endif
@ -1699,20 +1699,20 @@ m32c_cgen_build_insn_regex (CGEN_INSN *insn)
}
/* Trailing whitespace ok. */
* rx++ = '[';
* rx++ = ' ';
* rx++ = '\t';
* rx++ = ']';
* rx++ = '*';
* rx++ = '[';
* rx++ = ' ';
* rx++ = '\t';
* rx++ = ']';
* rx++ = '*';
/* But anchor it after that. */
* rx++ = '$';
* rx++ = '$';
* rx = '\0';
CGEN_INSN_RX (insn) = xmalloc (sizeof (regex_t));
reg_err = regcomp ((regex_t *) CGEN_INSN_RX (insn), rxbuf, REG_NOSUB);
if (reg_err == 0)
if (reg_err == 0)
return NULL;
else
{
@ -1911,7 +1911,7 @@ m32c_cgen_assemble_insn (CGEN_CPU_DESC cd,
const CGEN_INSN *insn = ilist->insn;
recognized_mnemonic = 1;
#ifdef CGEN_VALIDATE_INSN_SUPPORTED
#ifdef CGEN_VALIDATE_INSN_SUPPORTED
/* Not usually needed as unsupported opcodes
shouldn't be in the hash lists. */
/* Is this insn supported by the selected cpu? */
@ -1971,7 +1971,7 @@ m32c_cgen_assemble_insn (CGEN_CPU_DESC cd,
if (strlen (start) > 50)
/* xgettext:c-format */
sprintf (errbuf, "%s `%.50s...'", tmp_errmsg, start);
else
else
/* xgettext:c-format */
sprintf (errbuf, "%s `%.50s'", tmp_errmsg, start);
}
@ -1980,11 +1980,11 @@ m32c_cgen_assemble_insn (CGEN_CPU_DESC cd,
if (strlen (start) > 50)
/* xgettext:c-format */
sprintf (errbuf, _("bad instruction `%.50s...'"), start);
else
else
/* xgettext:c-format */
sprintf (errbuf, _("bad instruction `%.50s'"), start);
}
*errmsg = errbuf;
return NULL;
}

422
opcodes/m32c-desc.c
View File

File diff suppressed because it is too large Load Diff

14
opcodes/m32c-dis.c
View File

@ -203,7 +203,7 @@ print_regset (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
int length ATTRIBUTE_UNUSED,
int push)
{
static char * m16c_register_names [] =
static char * m16c_register_names [] =
{
"r0", "r1", "r2", "r3", "a0", "a1", "sb", "fb"
};
@ -216,7 +216,7 @@ print_regset (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
mask = 0x80;
else
mask = 1;
if (value & mask)
{
(*info->fprintf_func) (info->stream, "%s", m16c_register_names [0]);
@ -893,7 +893,7 @@ m32c_cgen_print_operand (CGEN_CPU_DESC cd,
}
}
cgen_print_fn * const m32c_cgen_print_handlers[] =
cgen_print_fn * const m32c_cgen_print_handlers[] =
{
print_insn_normal,
};
@ -1083,7 +1083,7 @@ print_insn (CGEN_CPU_DESC cd,
int length;
unsigned long insn_value_cropped;
#ifdef CGEN_VALIDATE_INSN_SUPPORTED
#ifdef CGEN_VALIDATE_INSN_SUPPORTED
/* Not needed as insn shouldn't be in hash lists if not supported. */
/* Supported by this cpu? */
if (! m32c_cgen_insn_supported (cd, insn))
@ -1101,7 +1101,7 @@ print_insn (CGEN_CPU_DESC cd,
relevant part from the buffer. */
if ((unsigned) (CGEN_INSN_BITSIZE (insn) / 8) < buflen &&
(unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long))
insn_value_cropped = bfd_get_bits (buf, CGEN_INSN_BITSIZE (insn),
insn_value_cropped = bfd_get_bits (buf, CGEN_INSN_BITSIZE (insn),
info->endian == BFD_ENDIAN_BIG);
else
insn_value_cropped = insn_value;
@ -1220,7 +1220,7 @@ print_insn_m32c (bfd_vma pc, disassemble_info *info)
arch = info->arch;
if (arch == bfd_arch_unknown)
arch = CGEN_BFD_ARCH;
/* There's no standard way to compute the machine or isa number
so we leave it to the target. */
#ifdef CGEN_COMPUTE_MACH
@ -1261,7 +1261,7 @@ print_insn_m32c (bfd_vma pc, disassemble_info *info)
break;
}
}
}
}
/* If we haven't initialized yet, initialize the opcode table. */
if (! cd)

8
opcodes/m32c-ibld.c
View File

@ -154,7 +154,7 @@ insert_normal (CGEN_CPU_DESC cd,
{
long minval = - (1L << (length - 1));
unsigned long maxval = mask;
if ((value > 0 && (unsigned long) value > maxval)
|| value < minval)
{
@ -192,7 +192,7 @@ insert_normal (CGEN_CPU_DESC cd,
{
long minval = - (1L << (length - 1));
long maxval = (1L << (length - 1)) - 1;
if (value < minval || value > maxval)
{
sprintf
@ -2893,12 +2893,12 @@ m32c_cgen_extract_operand (CGEN_CPU_DESC cd,
return length;
}
cgen_insert_fn * const m32c_cgen_insert_handlers[] =
cgen_insert_fn * const m32c_cgen_insert_handlers[] =
{
insert_insn_normal,
};
cgen_extract_fn * const m32c_cgen_extract_handlers[] =
cgen_extract_fn * const m32c_cgen_extract_handlers[] =
{
extract_insn_normal,
};

8
opcodes/m32c-opc.c
View File

@ -35,19 +35,19 @@ static unsigned int
m32c_asm_hash (const char *mnem)
{
unsigned int h;
/* The length of the mnemonic for the Jcnd insns is 1. Hash jsri. */
if (mnem[0] == 'j' && mnem[1] != 's')
return 'j';
/* Don't hash scCND */
if (mnem[0] == 's' && mnem[1] == 'c')
return 's';
/* Don't hash bmCND */
if (mnem[0] == 'b' && mnem[1] == 'm')
return 'b';
for (h = 0; *mnem && *mnem != ' ' && *mnem != ':'; ++mnem)
h += *mnem;
return h % CGEN_ASM_HASH_SIZE;

38
opcodes/m32r-asm.c
View File

@ -331,7 +331,7 @@ m32r_cgen_parse_operand (CGEN_CPU_DESC cd,
return errmsg;
}
cgen_parse_fn * const m32r_cgen_parse_handlers[] =
cgen_parse_fn * const m32r_cgen_parse_handlers[] =
{
parse_insn_normal,
};
@ -361,9 +361,9 @@ CGEN_ASM_INIT_HOOK
Returns NULL for success, an error message for failure. */
char *
char *
m32r_cgen_build_insn_regex (CGEN_INSN *insn)
{
{
CGEN_OPCODE *opc = (CGEN_OPCODE *) CGEN_INSN_OPCODE (insn);
const char *mnem = CGEN_INSN_MNEMONIC (insn);
char rxbuf[CGEN_MAX_RX_ELEMENTS];
@ -402,18 +402,18 @@ m32r_cgen_build_insn_regex (CGEN_INSN *insn)
/* Copy any remaining literals from the syntax string into the rx. */
for(; * syn != 0 && rx <= rxbuf + (CGEN_MAX_RX_ELEMENTS - 7 - 4); ++syn)
{
if (CGEN_SYNTAX_CHAR_P (* syn))
if (CGEN_SYNTAX_CHAR_P (* syn))
{
char c = CGEN_SYNTAX_CHAR (* syn);
switch (c)
switch (c)
{
/* Escape any regex metacharacters in the syntax. */
case '.': case '[': case '\\':
case '*': case '^': case '$':
case '.': case '[': case '\\':
case '*': case '^': case '$':
#ifdef CGEN_ESCAPE_EXTENDED_REGEX
case '?': case '{': case '}':
case '?': case '{': case '}':
case '(': case ')': case '*':
case '|': case '+': case ']':
#endif
@ -443,20 +443,20 @@ m32r_cgen_build_insn_regex (CGEN_INSN *insn)
}
/* Trailing whitespace ok. */
* rx++ = '[';
* rx++ = ' ';
* rx++ = '\t';
* rx++ = ']';
* rx++ = '*';
* rx++ = '[';
* rx++ = ' ';
* rx++ = '\t';
* rx++ = ']';
* rx++ = '*';
/* But anchor it after that. */
* rx++ = '$';
* rx++ = '$';
* rx = '\0';
CGEN_INSN_RX (insn) = xmalloc (sizeof (regex_t));
reg_err = regcomp ((regex_t *) CGEN_INSN_RX (insn), rxbuf, REG_NOSUB);
if (reg_err == 0)
if (reg_err == 0)
return NULL;
else
{
@ -655,7 +655,7 @@ m32r_cgen_assemble_insn (CGEN_CPU_DESC cd,
const CGEN_INSN *insn = ilist->insn;
recognized_mnemonic = 1;
#ifdef CGEN_VALIDATE_INSN_SUPPORTED
#ifdef CGEN_VALIDATE_INSN_SUPPORTED
/* Not usually needed as unsupported opcodes
shouldn't be in the hash lists. */
/* Is this insn supported by the selected cpu? */
@ -715,7 +715,7 @@ m32r_cgen_assemble_insn (CGEN_CPU_DESC cd,
if (strlen (start) > 50)
/* xgettext:c-format */
sprintf (errbuf, "%s `%.50s...'", tmp_errmsg, start);
else
else
/* xgettext:c-format */
sprintf (errbuf, "%s `%.50s'", tmp_errmsg, start);
}
@ -724,11 +724,11 @@ m32r_cgen_assemble_insn (CGEN_CPU_DESC cd,
if (strlen (start) > 50)
/* xgettext:c-format */
sprintf (errbuf, _("bad instruction `%.50s...'"), start);
else
else
/* xgettext:c-format */
sprintf (errbuf, _("bad instruction `%.50s'"), start);
}
*errmsg = errbuf;
return NULL;
}

60
opcodes/m32r-desc.c
View File

@ -312,115 +312,115 @@ const CGEN_OPERAND m32r_cgen_operand_table[] =
{
/* pc: program counter */
{ "pc", M32R_OPERAND_PC, HW_H_PC, 0, 0,
{ 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_NIL] } },
{ 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_NIL] } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* sr: source register */
{ "sr", M32R_OPERAND_SR, HW_H_GR, 12, 4,
{ 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_R2] } },
{ 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_R2] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* dr: destination register */
{ "dr", M32R_OPERAND_DR, HW_H_GR, 4, 4,
{ 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_R1] } },
{ 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_R1] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* src1: source register 1 */
{ "src1", M32R_OPERAND_SRC1, HW_H_GR, 4, 4,
{ 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_R1] } },
{ 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_R1] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* src2: source register 2 */
{ "src2", M32R_OPERAND_SRC2, HW_H_GR, 12, 4,
{ 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_R2] } },
{ 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_R2] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* scr: source control register */
{ "scr", M32R_OPERAND_SCR, HW_H_CR, 12, 4,
{ 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_R2] } },
{ 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_R2] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* dcr: destination control register */
{ "dcr", M32R_OPERAND_DCR, HW_H_CR, 4, 4,
{ 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_R1] } },
{ 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_R1] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* simm8: 8 bit signed immediate */
{ "simm8", M32R_OPERAND_SIMM8, HW_H_SINT, 8, 8,
{ 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_SIMM8] } },
{ 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_SIMM8] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* simm16: 16 bit signed immediate */
{ "simm16", M32R_OPERAND_SIMM16, HW_H_SINT, 16, 16,
{ 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_SIMM16] } },
{ 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_SIMM16] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* uimm3: 3 bit unsigned number */
{ "uimm3", M32R_OPERAND_UIMM3, HW_H_UINT, 5, 3,
{ 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_UIMM3] } },
{ 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_UIMM3] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* uimm4: 4 bit trap number */
{ "uimm4", M32R_OPERAND_UIMM4, HW_H_UINT, 12, 4,
{ 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_UIMM4] } },
{ 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_UIMM4] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* uimm5: 5 bit shift count */
{ "uimm5", M32R_OPERAND_UIMM5, HW_H_UINT, 11, 5,
{ 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_UIMM5] } },
{ 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_UIMM5] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* uimm8: 8 bit unsigned immediate */
{ "uimm8", M32R_OPERAND_UIMM8, HW_H_UINT, 8, 8,
{ 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_UIMM8] } },
{ 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_UIMM8] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* uimm16: 16 bit unsigned immediate */
{ "uimm16", M32R_OPERAND_UIMM16, HW_H_UINT, 16, 16,
{ 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_UIMM16] } },
{ 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_UIMM16] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* imm1: 1 bit immediate */
{ "imm1", M32R_OPERAND_IMM1, HW_H_UINT, 15, 1,
{ 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_IMM1] } },
{ 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_IMM1] } },
{ 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } } } } },
/* accd: accumulator destination register */
{ "accd", M32R_OPERAND_ACCD, HW_H_ACCUMS, 4, 2,
{ 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_ACCD] } },
{ 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_ACCD] } },
{ 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } } } } },
/* accs: accumulator source register */
{ "accs", M32R_OPERAND_ACCS, HW_H_ACCUMS, 12, 2,
{ 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_ACCS] } },
{ 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_ACCS] } },
{ 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } } } } },
/* acc: accumulator reg (d) */
{ "acc", M32R_OPERAND_ACC, HW_H_ACCUMS, 8, 1,
{ 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_ACC] } },
{ 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_ACC] } },
{ 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } } } } },
/* hash: # prefix */
{ "hash", M32R_OPERAND_HASH, HW_H_SINT, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { (const PTR) 0 } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* hi16: high 16 bit immediate, sign optional */
{ "hi16", M32R_OPERAND_HI16, HW_H_HI16, 16, 16,
{ 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_HI16] } },
{ 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_HI16] } },
{ 0|A(SIGN_OPT), { { { (1<<MACH_BASE), 0 } } } } },
/* slo16: 16 bit signed immediate, for low() */
{ "slo16", M32R_OPERAND_SLO16, HW_H_SLO16, 16, 16,
{ 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_SIMM16] } },
{ 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_SIMM16] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* ulo16: 16 bit unsigned immediate, for low() */
{ "ulo16", M32R_OPERAND_ULO16, HW_H_ULO16, 16, 16,
{ 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_UIMM16] } },
{ 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_UIMM16] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* uimm24: 24 bit address */
{ "uimm24", M32R_OPERAND_UIMM24, HW_H_ADDR, 8, 24,
{ 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_UIMM24] } },
{ 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_UIMM24] } },
{ 0|A(RELOC)|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } } },
/* disp8: 8 bit displacement */
{ "disp8", M32R_OPERAND_DISP8, HW_H_IADDR, 8, 8,
{ 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_DISP8] } },
{ 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_DISP8] } },
{ 0|A(RELAX)|A(RELOC)|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } } },
/* disp16: 16 bit displacement */
{ "disp16", M32R_OPERAND_DISP16, HW_H_IADDR, 16, 16,
{ 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_DISP16] } },
{ 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_DISP16] } },
{ 0|A(RELOC)|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } } },
/* disp24: 24 bit displacement */
{ "disp24", M32R_OPERAND_DISP24, HW_H_IADDR, 8, 24,
{ 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_DISP24] } },
{ 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_DISP24] } },
{ 0|A(RELAX)|A(RELOC)|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } } },
/* condbit: condition bit */
{ "condbit", M32R_OPERAND_CONDBIT, HW_H_COND, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* accum: accumulator */
{ "accum", M32R_OPERAND_ACCUM, HW_H_ACCUM, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* sentinel */
{ 0, 0, 0, 0, 0,
@ -1468,7 +1468,7 @@ m32r_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...)
/* Default to not allowing signed overflow. */
cd->signed_overflow_ok_p = 0;
return (CGEN_CPU_DESC) cd;
}
@ -1508,7 +1508,7 @@ m32r_cgen_cpu_close (CGEN_CPU_DESC cd)
for (i = 0; i < cd->insn_table.num_init_entries; ++i, ++insns)
if (CGEN_INSN_RX (insns))
regfree (CGEN_INSN_RX (insns));
}
}
if (cd->macro_insn_table.init_entries)
free ((CGEN_INSN *) cd->macro_insn_table.init_entries);

10
opcodes/m32r-dis.c
View File

@ -281,7 +281,7 @@ m32r_cgen_print_operand (CGEN_CPU_DESC cd,
}
}
cgen_print_fn * const m32r_cgen_print_handlers[] =
cgen_print_fn * const m32r_cgen_print_handlers[] =
{
print_insn_normal,
};
@ -471,7 +471,7 @@ print_insn (CGEN_CPU_DESC cd,
int length;
unsigned long insn_value_cropped;
#ifdef CGEN_VALIDATE_INSN_SUPPORTED
#ifdef CGEN_VALIDATE_INSN_SUPPORTED
/* Not needed as insn shouldn't be in hash lists if not supported. */
/* Supported by this cpu? */
if (! m32r_cgen_insn_supported (cd, insn))
@ -489,7 +489,7 @@ print_insn (CGEN_CPU_DESC cd,
relevant part from the buffer. */
if ((unsigned) (CGEN_INSN_BITSIZE (insn) / 8) < buflen &&
(unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long))
insn_value_cropped = bfd_get_bits (buf, CGEN_INSN_BITSIZE (insn),
insn_value_cropped = bfd_get_bits (buf, CGEN_INSN_BITSIZE (insn),
info->endian == BFD_ENDIAN_BIG);
else
insn_value_cropped = insn_value;
@ -608,7 +608,7 @@ print_insn_m32r (bfd_vma pc, disassemble_info *info)
arch = info->arch;
if (arch == bfd_arch_unknown)
arch = CGEN_BFD_ARCH;
/* There's no standard way to compute the machine or isa number
so we leave it to the target. */
#ifdef CGEN_COMPUTE_MACH
@ -649,7 +649,7 @@ print_insn_m32r (bfd_vma pc, disassemble_info *info)
break;
}
}
}
}
/* If we haven't initialized yet, initialize the opcode table. */
if (! cd)

8
opcodes/m32r-ibld.c
View File

@ -154,7 +154,7 @@ insert_normal (CGEN_CPU_DESC cd,
{
long minval = - (1L << (length - 1));
unsigned long maxval = mask;
if ((value > 0 && (unsigned long) value > maxval)
|| value < minval)
{
@ -192,7 +192,7 @@ insert_normal (CGEN_CPU_DESC cd,
{
long minval = - (1L << (length - 1));
long maxval = (1L << (length - 1)) - 1;
if (value < minval || value > maxval)
{
sprintf
@ -803,12 +803,12 @@ m32r_cgen_extract_operand (CGEN_CPU_DESC cd,
return length;
}
cgen_insert_fn * const m32r_cgen_insert_handlers[] =
cgen_insert_fn * const m32r_cgen_insert_handlers[] =
{
insert_insn_normal,
};
cgen_extract_fn * const m32r_cgen_extract_handlers[] =
cgen_extract_fn * const m32r_cgen_extract_handlers[] =
{
extract_insn_normal,
};

4
opcodes/m68hc11-dis.c
View File

@ -697,7 +697,7 @@ print_insn (bfd_vma memaddr, struct disassemble_info* info, int arch)
{
int cur_page;
bfd_vma vaddr;
if (memaddr >= M68HC12_BANK_VIRT)
cur_page = ((memaddr - M68HC12_BANK_VIRT)
>> M68HC12_BANK_SHIFT);
@ -827,7 +827,7 @@ print_insn (bfd_vma memaddr, struct disassemble_info* info, int arch)
val = buffer[0] & 0x0ff;
(*info->fprintf_func) (info->stream, ", 0x%x", val);
}
#ifdef DEBUG
/* Consistency check. 'format' must be 0, so that we have handled
all formats; and the computed size of the insn must match the

2
opcodes/m68hc11-opc.c
View File

@ -328,7 +328,7 @@ const struct m68hc11_opcode m68hc11_opcodes[] = {
{ "bgt", OP_JUMP_REL, 2, 0x2e, 1, 3, CHG_NONE, cpu6811 | cpu6812|cpu9s12x, 0 },
{ "bhi", OP_JUMP_REL, 2, 0x22, 1, 3, CHG_NONE, cpu6811 | cpu6812|cpu9s12x, 0 },
{ "bhs", OP_JUMP_REL, 2, 0x24, 1, 3, CHG_NONE, cpu6811 | cpu6812|cpu9s12x, 0 },
{ "bita", OP_IMM8, 2, 0x85, 1, 1, CLR_V_CHG_NZ, cpu6811|cpu6812|cpu9s12x, 0 },
{ "bita", OP_DIRECT, 2, 0x95, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812|cpu9s12x, 0 },
{ "bita", OP_IND16, 3, 0xb5, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812|cpu9s12x, 0 },

6
opcodes/m68k-dis.c
View File

@ -79,7 +79,7 @@ static char *const reg_half_names[] =
return ret_val; \
val = COERCE16 ((p[-2] << 8) + p[-1]); \
} \
while (0)
while (0)
/* Get a 4 byte signed integer. */
#define COERCE32(x) ((bfd_signed_vma) ((x) ^ 0x80000000) - 0x80000000)
@ -1336,7 +1336,7 @@ match_insn_m68k (bfd_vma memaddr,
if (*args == '.')
args++;
/* Point at first word of argument data,
and at descriptor for first argument. */
p = buffer + 2;
@ -1583,7 +1583,7 @@ m68k_scan_mask (bfd_vma memaddr, disassemble_info *info,
}
}
return 0;
}
}
/* Print the m68k instruction at address MEMADDR in debugged memory,
on INFO->STREAM. Returns length of the instruction, in bytes. */

18
opcodes/m68k-opc.c
View File

@ -292,7 +292,7 @@ const struct m68k_opcode m68k_opcodes[] =
{"cmpl", 6, one(0006200), one(0177700), "#lDs", mcfisa_a },
{"cmpl", 2, one(0130610), one(0170770), "+s+d", m68000up },
{"cmpl", 2, one(0130200), one(0170700), "*lDd", m68000up | mcfisa_a },
{"cp0bcbusy",2, one (0176300), one (01777770), "BW", mcfisa_a},
{"cp1bcbusy",2, one (0177300), one (01777770), "BW", mcfisa_a},
{"cp0nop", 4, two (0176000,0), two (01777477,0170777), "jE", mcfisa_a},
@ -316,7 +316,7 @@ const struct m68k_opcode m68k_opcodes[] =
{"cp1stl", 6, one (0177600), one (01777700), ".R1pwjEK3", mcfisa_a},
{"cp0st", 6, one (0176600), one (01777700), ".R1pwjEK3", mcfisa_a},
{"cp1st", 6, one (0177600), one (01777700), ".R1pwjEK3", mcfisa_a},
{"dbcc", 2, one(0052310), one(0177770), "DsBw", m68000up },
{"dbcs", 2, one(0052710), one(0177770), "DsBw", m68000up },
{"dbeq", 2, one(0053710), one(0177770), "DsBw", m68000up },
@ -376,7 +376,7 @@ const struct m68k_opcode m68k_opcodes[] =
{"eor", 4, one(0005174), one(0177777), "#wSs", m68000up },
{"eor", 4, one(0005100), one(0177700), "#w$s", m68000up },
{"eor", 2, one(0130500), one(0170700), "Dd$s", m68000up },
{"exg", 2, one(0140500), one(0170770), "DdDs", m68000up },
{"exg", 2, one(0140510), one(0170770), "AdAs", m68000up },
{"exg", 2, one(0140610), one(0170770), "DdAs", m68000up },
@ -2005,22 +2005,22 @@ const struct m68k_opcode m68k_opcodes[] =
{"roxrl", 2, one(0160260), one(0170770), "DdDs", m68000up },
{"rtd", 4, one(0047164), one(0177777), "#w", m68010up },
{"rte", 2, one(0047163), one(0177777), "", m68000up | mcfisa_a },
{"rtm", 2, one(0003300), one(0177760), "Rs", m68020 },
{"rtr", 2, one(0047167), one(0177777), "", m68000up },
{"rts", 2, one(0047165), one(0177777), "", m68000up | mcfisa_a },
{"satsl", 2, one(0046200), one(0177770), "Ds", mcfisa_b | mcfisa_c },
{"sbcd", 2, one(0100400), one(0170770), "DsDd", m68000up },
{"sbcd", 2, one(0100410), one(0170770), "-s-d", m68000up },
{"stldsr", 6, two(0x40e7, 0x46fc), two(0xffff, 0xffff), "#w", mcfisa_aa | mcfisa_c },
/* Traps have to come before conditional sets, as they have a more
specific opcode. */
{"trapcc", 2, one(0052374), one(0177777), "", m68020up | cpu32 | fido_a },

14
opcodes/m88k-dis.c
View File

@ -522,7 +522,7 @@ HASHTAB *hashtable[HASHVAL] = {0};
/* Initialize the disassembler instruction table.
Initialize the hash table and instruction table for the
disassembler. This should be called once before the first call to
disasm(). */
@ -549,14 +549,14 @@ init_disasm (void)
hashtable[hashvalue] = &hashentries[i];
}
}
/* Decode an Operand of an instruction.
This function formats and writes an operand of an instruction to
info based on the operand specification. When the `first' flag is
set this is the first operand of an instruction. Undefined operand
types cause a <dis error> message.
Parameters:
disassemble_info where the operand may be printed
OPSPEC *opptr pointer to an operand specification
@ -564,7 +564,7 @@ init_disasm (void)
UINT pc pc of instruction; used for pc-relative disp.
int first flag which if nonzero indicates the first
operand of an instruction
The operand specified is extracted from the instruction and is
written to buf in the format specified. The operand is preceded by
a comma if it is not the first operand of an instruction and it is
@ -654,7 +654,7 @@ printop (struct disassemble_info *info,
else
(*info->fprintf_func) (info->stream, "%x", extracted_field);
break;
case PCREL:
(*info->print_address_func)
(pc + (4 * (SEXT (inst, opptr->offset, opptr->width))),
@ -683,7 +683,7 @@ printop (struct disassemble_info *info,
`pc' should be the address of this instruction, it will be used to
print the target address if this is a relative jump or call the
disassembled instruction is written to `info'.
The function returns the length of this instruction in bytes. */
static int

4
opcodes/makefile.vms
View File

@ -11,12 +11,12 @@
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 3 of the License, or
# (at your option) any later version.
#
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
#
# You should have received a copy of the GNU General Public License
# along with this program; see the file COPYING3. If not see
# <http://www.gnu.org/licenses/>.

4
opcodes/mcore-opc.h
View File

@ -128,14 +128,14 @@ const mcore_opcode_info mcore_table[] =
{ "cmpnei", OB, 0, 0x2A00 },
{ "bmaski", OMa, 0, 0x2C00 },
{ "divu", O1R1, 0, 0x2C10 },
/* SPACE: 0x2c20 - 0x2c7f */
/* SPACE: 0x2c20 - 0x2c7f */
{ "bmaski", OMb, 0, 0x2C80 },
{ "bmaski", OMc, 0, 0x2D00 },
{ "andi", OB, 0, 0x2E00 },
{ "bclri", OB, 0, 0x3000 },
/* SPACE: 0x3200 - 0x320f */
{ "divs", O1R1, 0, 0x3210 },
/* SPACE: 0x3220 - 0x326f */
/* SPACE: 0x3220 - 0x326f */
{ "bgeni", OBRa, 0, 0x3270 },
{ "bgeni", OBRb, 0, 0x3280 },
{ "bgeni", OBRc, 0, 0x3300 },

74
opcodes/mep-asm.c
View File

@ -488,7 +488,7 @@ parse_unsigned7 (CGEN_CPU_DESC cd, const char **strp,
break;
default:
/* Safe assumption? */
abort ();
abort ();
}
errmsg = cgen_parse_address (cd, strp, opindex, reloc,
NULL, &value);
@ -534,7 +534,7 @@ parse_cdisp10 (CGEN_CPU_DESC cd,
if ((MEP_CPU & EF_MEP_CPU_MASK) == EF_MEP_CPU_C5)
wide = 1;
if (strncmp (*strp, "0x0", 3) == 0
if (strncmp (*strp, "0x0", 3) == 0
|| (**strp == '0' && *(*strp + 1) != 'x'))
have_zero = 1;
@ -601,7 +601,7 @@ mep_cgen_expand_macros_and_parse_operand
static char *
str_append (char *dest, const char *input, int len)
{
{
char *new_dest;
int oldlen;
@ -637,8 +637,8 @@ expand_macro (arg *args, int narg, macro *mac)
/* printf("expanding macro %s with %d args\n", mac->name, narg + 1); */
while (*e)
{
if (*e == '`' &&
(*e+1) &&
if (*e == '`' &&
(*e+1) &&
((*(e + 1) - '1') <= MAXARGS) &&
((*(e + 1) - '1') <= narg))
{
@ -661,7 +661,7 @@ expand_macro (arg *args, int narg, macro *mac)
free (result);
return rescanned_result;
}
else
else
return result;
}
@ -686,8 +686,8 @@ expand_string (const char *in, int first_only)
switch (state)
{
case IN_TEXT:
if (*in == '%' && *(in + 1) && (!first_only || num_expansions == 0))
{
if (*in == '%' && *(in + 1) && (!first_only || num_expansions == 0))
{
pmacro = lookup_macro (in + 1);
if (pmacro)
{
@ -698,7 +698,7 @@ expand_string (const char *in, int first_only)
while (*in == ' ') ++in;
if (*in != '(')
{
state = IN_TEXT;
state = IN_TEXT;
pmacro = NULL;
}
else
@ -707,7 +707,7 @@ expand_string (const char *in, int first_only)
narg = 0;
args[narg].start = in + 1;
args[narg].len = 0;
mark = in + 1;
mark = in + 1;
}
}
}
@ -747,9 +747,9 @@ expand_string (const char *in, int first_only)
depth++;
default:
args[narg].len++;
break;
break;
}
}
}
else
{
if (*in == ')')
@ -757,14 +757,14 @@ expand_string (const char *in, int first_only)
if (narg > -1)
args[narg].len++;
}
}
++in;
}
if (mark != in)
result = str_append (result, mark, in - mark);
return result;
}
@ -803,10 +803,10 @@ mep_cgen_expand_macros_and_parse_operand (CGEN_CPU_DESC cd, int opindex,
{
if (strstr (*strp_in, str))
/* A macro-expansion was pulled off the front. */
*strp_in = strstr (*strp_in, str);
*strp_in = strstr (*strp_in, str);
else
/* A non-macro-expansion was pulled off the front. */
*strp_in += (str - hold);
*strp_in += (str - hold);
}
if (hold)
@ -815,7 +815,7 @@ mep_cgen_expand_macros_and_parse_operand (CGEN_CPU_DESC cd, int opindex,
return errmsg;
}
#define CGEN_ASM_INIT_HOOK (cd->parse_operand = mep_cgen_expand_macros_and_parse_operand);
#define CGEN_ASM_INIT_HOOK (cd->parse_operand = mep_cgen_expand_macros_and_parse_operand);
/* -- dis.c */
@ -1289,7 +1289,7 @@ mep_cgen_parse_operand (CGEN_CPU_DESC cd,
return errmsg;
}
cgen_parse_fn * const mep_cgen_parse_handlers[] =
cgen_parse_fn * const mep_cgen_parse_handlers[] =
{
parse_insn_normal,
};
@ -1319,9 +1319,9 @@ CGEN_ASM_INIT_HOOK
Returns NULL for success, an error message for failure. */
char *
char *
mep_cgen_build_insn_regex (CGEN_INSN *insn)
{
{
CGEN_OPCODE *opc = (CGEN_OPCODE *) CGEN_INSN_OPCODE (insn);
const char *mnem = CGEN_INSN_MNEMONIC (insn);
char rxbuf[CGEN_MAX_RX_ELEMENTS];
@ -1360,18 +1360,18 @@ mep_cgen_build_insn_regex (CGEN_INSN *insn)
/* Copy any remaining literals from the syntax string into the rx. */
for(; * syn != 0 && rx <= rxbuf + (CGEN_MAX_RX_ELEMENTS - 7 - 4); ++syn)
{
if (CGEN_SYNTAX_CHAR_P (* syn))
if (CGEN_SYNTAX_CHAR_P (* syn))
{
char c = CGEN_SYNTAX_CHAR (* syn);
switch (c)
switch (c)
{
/* Escape any regex metacharacters in the syntax. */
case '.': case '[': case '\\':
case '*': case '^': case '$':
case '.': case '[': case '\\':
case '*': case '^': case '$':
#ifdef CGEN_ESCAPE_EXTENDED_REGEX
case '?': case '{': case '}':
case '?': case '{': case '}':
case '(': case ')': case '*':
case '|': case '+': case ']':
#endif
@ -1401,20 +1401,20 @@ mep_cgen_build_insn_regex (CGEN_INSN *insn)
}
/* Trailing whitespace ok. */
* rx++ = '[';
* rx++ = ' ';
* rx++ = '\t';
* rx++ = ']';
* rx++ = '*';
* rx++ = '[';
* rx++ = ' ';
* rx++ = '\t';
* rx++ = ']';
* rx++ = '*';
/* But anchor it after that. */
* rx++ = '$';
* rx++ = '$';
* rx = '\0';
CGEN_INSN_RX (insn) = xmalloc (sizeof (regex_t));
reg_err = regcomp ((regex_t *) CGEN_INSN_RX (insn), rxbuf, REG_NOSUB);
if (reg_err == 0)
if (reg_err == 0)
return NULL;
else
{
@ -1613,7 +1613,7 @@ mep_cgen_assemble_insn (CGEN_CPU_DESC cd,
const CGEN_INSN *insn = ilist->insn;
recognized_mnemonic = 1;
#ifdef CGEN_VALIDATE_INSN_SUPPORTED
#ifdef CGEN_VALIDATE_INSN_SUPPORTED
/* Not usually needed as unsupported opcodes
shouldn't be in the hash lists. */
/* Is this insn supported by the selected cpu? */
@ -1673,7 +1673,7 @@ mep_cgen_assemble_insn (CGEN_CPU_DESC cd,
if (strlen (start) > 50)
/* xgettext:c-format */
sprintf (errbuf, "%s `%.50s...'", tmp_errmsg, start);
else
else
/* xgettext:c-format */
sprintf (errbuf, "%s `%.50s'", tmp_errmsg, start);
}
@ -1682,11 +1682,11 @@ mep_cgen_assemble_insn (CGEN_CPU_DESC cd,
if (strlen (start) > 50)
/* xgettext:c-format */
sprintf (errbuf, _("bad instruction `%.50s...'"), start);
else
else
/* xgettext:c-format */
sprintf (errbuf, _("bad instruction `%.50s'"), start);
}
*errmsg = errbuf;
return NULL;
}

298
opcodes/mep-desc.c
View File

@ -103,13 +103,13 @@ static const CGEN_ATTR_ENTRY CRET_attr[] ATTRIBUTE_UNUSED =
{ 0, 0 }
};
static const CGEN_ATTR_ENTRY ALIGN_attr [] ATTRIBUTE_UNUSED =
static const CGEN_ATTR_ENTRY ALIGN_attr [] ATTRIBUTE_UNUSED =
{
{"integer", 1},
{ 0, 0 }
};
static const CGEN_ATTR_ENTRY LATENCY_attr [] ATTRIBUTE_UNUSED =
static const CGEN_ATTR_ENTRY LATENCY_attr [] ATTRIBUTE_UNUSED =
{
{"integer", 0},
{ 0, 0 }
@ -880,583 +880,583 @@ const CGEN_OPERAND mep_cgen_operand_table[] =
{
/* pc: program counter */
{ "pc", MEP_OPERAND_PC, HW_H_PC, 0, 0,
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_NIL] } },
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_NIL] } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* r0: register 0 */
{ "r0", MEP_OPERAND_R0, HW_H_GPR, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { (const PTR) 0 } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* rn: register Rn */
{ "rn", MEP_OPERAND_RN, HW_H_GPR, 4, 4,
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RN] } },
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RN] } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* rm: register Rm */
{ "rm", MEP_OPERAND_RM, HW_H_GPR, 8, 4,
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RM] } },
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RM] } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* rl: register Rl */
{ "rl", MEP_OPERAND_RL, HW_H_GPR, 12, 4,
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RL] } },
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RL] } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* rn3: register 0-7 */
{ "rn3", MEP_OPERAND_RN3, HW_H_GPR, 5, 3,
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RN3] } },
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RN3] } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* rma: register Rm holding pointer */
{ "rma", MEP_OPERAND_RMA, HW_H_GPR, 8, 4,
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RM] } },
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RM] } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_POINTER, 0 } }, { { 1, 0 } } } } },
/* rnc: register Rn holding char */
{ "rnc", MEP_OPERAND_RNC, HW_H_GPR, 4, 4,
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RN] } },
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RN] } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* rnuc: register Rn holding unsigned char */
{ "rnuc", MEP_OPERAND_RNUC, HW_H_GPR, 4, 4,
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RN] } },
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RN] } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* rns: register Rn holding short */
{ "rns", MEP_OPERAND_RNS, HW_H_GPR, 4, 4,
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RN] } },
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RN] } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* rnus: register Rn holding unsigned short */
{ "rnus", MEP_OPERAND_RNUS, HW_H_GPR, 4, 4,
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RN] } },
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RN] } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* rnl: register Rn holding long */
{ "rnl", MEP_OPERAND_RNL, HW_H_GPR, 4, 4,
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RN] } },
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RN] } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* rnul: register Rn holding unsigned long */
{ "rnul", MEP_OPERAND_RNUL, HW_H_GPR, 4, 4,
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RN] } },
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RN] } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_ULONG, 0 } }, { { 1, 0 } } } } },
/* rn3c: register 0-7 holding unsigned char */
{ "rn3c", MEP_OPERAND_RN3C, HW_H_GPR, 5, 3,
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RN3] } },
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RN3] } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* rn3uc: register 0-7 holding byte */
{ "rn3uc", MEP_OPERAND_RN3UC, HW_H_GPR, 5, 3,
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RN3] } },
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RN3] } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* rn3s: register 0-7 holding unsigned short */
{ "rn3s", MEP_OPERAND_RN3S, HW_H_GPR, 5, 3,
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RN3] } },
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RN3] } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* rn3us: register 0-7 holding short */
{ "rn3us", MEP_OPERAND_RN3US, HW_H_GPR, 5, 3,
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RN3] } },
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RN3] } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* rn3l: register 0-7 holding unsigned long */
{ "rn3l", MEP_OPERAND_RN3L, HW_H_GPR, 5, 3,
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RN3] } },
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RN3] } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* rn3ul: register 0-7 holding long */
{ "rn3ul", MEP_OPERAND_RN3UL, HW_H_GPR, 5, 3,
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RN3] } },
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RN3] } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_ULONG, 0 } }, { { 1, 0 } } } } },
/* lp: link pointer */
{ "lp", MEP_OPERAND_LP, HW_H_CSR, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { (const PTR) 0 } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* sar: shift amount register */
{ "sar", MEP_OPERAND_SAR, HW_H_CSR, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { (const PTR) 0 } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* hi: high result */
{ "hi", MEP_OPERAND_HI, HW_H_CSR, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { (const PTR) 0 } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* lo: low result */
{ "lo", MEP_OPERAND_LO, HW_H_CSR, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { (const PTR) 0 } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* mb0: modulo begin register 0 */
{ "mb0", MEP_OPERAND_MB0, HW_H_CSR, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { (const PTR) 0 } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* me0: modulo end register 0 */
{ "me0", MEP_OPERAND_ME0, HW_H_CSR, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { (const PTR) 0 } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* mb1: modulo begin register 1 */
{ "mb1", MEP_OPERAND_MB1, HW_H_CSR, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { (const PTR) 0 } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* me1: modulo end register 1 */
{ "me1", MEP_OPERAND_ME1, HW_H_CSR, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { (const PTR) 0 } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* psw: program status word */
{ "psw", MEP_OPERAND_PSW, HW_H_CSR, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { (const PTR) 0 } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* epc: exception prog counter */
{ "epc", MEP_OPERAND_EPC, HW_H_CSR, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { (const PTR) 0 } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* exc: exception cause */
{ "exc", MEP_OPERAND_EXC, HW_H_CSR, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { (const PTR) 0 } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* npc: nmi program counter */
{ "npc", MEP_OPERAND_NPC, HW_H_CSR, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { (const PTR) 0 } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* dbg: debug register */
{ "dbg", MEP_OPERAND_DBG, HW_H_CSR, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { (const PTR) 0 } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* depc: debug exception pc */
{ "depc", MEP_OPERAND_DEPC, HW_H_CSR, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { (const PTR) 0 } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* opt: option register */
{ "opt", MEP_OPERAND_OPT, HW_H_CSR, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { (const PTR) 0 } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* r1: register 1 */
{ "r1", MEP_OPERAND_R1, HW_H_GPR, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { (const PTR) 0 } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* tp: tiny data area pointer */
{ "tp", MEP_OPERAND_TP, HW_H_GPR, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { (const PTR) 0 } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* sp: stack pointer */
{ "sp", MEP_OPERAND_SP, HW_H_GPR, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { (const PTR) 0 } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* tpr: comment */
{ "tpr", MEP_OPERAND_TPR, HW_H_GPR, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { (const PTR) 0 } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* spr: comment */
{ "spr", MEP_OPERAND_SPR, HW_H_GPR, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { (const PTR) 0 } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* csrn: control/special register */
{ "csrn", MEP_OPERAND_CSRN, HW_H_CSR, 8, 5,
{ 2, { (const PTR) &MEP_F_CSRN_MULTI_IFIELD[0] } },
{ 2, { (const PTR) &MEP_F_CSRN_MULTI_IFIELD[0] } },
{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_REGNUM, 0 } }, { { 1, 0 } } } } },
/* csrn-idx: control/special reg idx */
{ "csrn-idx", MEP_OPERAND_CSRN_IDX, HW_H_UINT, 8, 5,
{ 2, { (const PTR) &MEP_F_CSRN_MULTI_IFIELD[0] } },
{ 2, { (const PTR) &MEP_F_CSRN_MULTI_IFIELD[0] } },
{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* crn64: copro Rn (64-bit) */
{ "crn64", MEP_OPERAND_CRN64, HW_H_CR64, 4, 4,
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_CRN] } },
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_CRN] } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_CP_DATA_BUS_INT, 0 } }, { { 1, 0 } } } } },
/* crn: copro Rn (32-bit) */
{ "crn", MEP_OPERAND_CRN, HW_H_CR, 4, 4,
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_CRN] } },
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_CRN] } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_CP_DATA_BUS_INT, 0 } }, { { 1, 0 } } } } },
/* crnx64: copro Rn (0-31, 64-bit) */
{ "crnx64", MEP_OPERAND_CRNX64, HW_H_CR64, 4, 5,
{ 2, { (const PTR) &MEP_F_CRNX_MULTI_IFIELD[0] } },
{ 2, { (const PTR) &MEP_F_CRNX_MULTI_IFIELD[0] } },
{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_CP_DATA_BUS_INT, 0 } }, { { 1, 0 } } } } },
/* crnx: copro Rn (0-31, 32-bit) */
{ "crnx", MEP_OPERAND_CRNX, HW_H_CR, 4, 5,
{ 2, { (const PTR) &MEP_F_CRNX_MULTI_IFIELD[0] } },
{ 2, { (const PTR) &MEP_F_CRNX_MULTI_IFIELD[0] } },
{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_CP_DATA_BUS_INT, 0 } }, { { 1, 0 } } } } },
/* ccrn: copro control reg CCRn */
{ "ccrn", MEP_OPERAND_CCRN, HW_H_CCR, 4, 6,
{ 2, { (const PTR) &MEP_F_CCRN_MULTI_IFIELD[0] } },
{ 2, { (const PTR) &MEP_F_CCRN_MULTI_IFIELD[0] } },
{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_REGNUM, 0 } }, { { 1, 0 } } } } },
/* cccc: copro flags */
{ "cccc", MEP_OPERAND_CCCC, HW_H_UINT, 8, 4,
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RM] } },
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RM] } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* pcrel8a2: comment */
{ "pcrel8a2", MEP_OPERAND_PCREL8A2, HW_H_SINT, 8, 7,
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_8S8A2] } },
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_8S8A2] } },
{ 0|A(RELAX)|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LABEL, 0 } }, { { 1, 0 } } } } },
/* pcrel12a2: comment */
{ "pcrel12a2", MEP_OPERAND_PCREL12A2, HW_H_SINT, 4, 11,
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_12S4A2] } },
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_12S4A2] } },
{ 0|A(RELAX)|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LABEL, 0 } }, { { 1, 0 } } } } },
/* pcrel17a2: comment */
{ "pcrel17a2", MEP_OPERAND_PCREL17A2, HW_H_SINT, 16, 16,
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_17S16A2] } },
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_17S16A2] } },
{ 0|A(RELAX)|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LABEL, 0 } }, { { 1, 0 } } } } },
/* pcrel24a2: comment */
{ "pcrel24a2", MEP_OPERAND_PCREL24A2, HW_H_SINT, 5, 23,
{ 2, { (const PTR) &MEP_F_24S5A2N_MULTI_IFIELD[0] } },
{ 2, { (const PTR) &MEP_F_24S5A2N_MULTI_IFIELD[0] } },
{ 0|A(PCREL_ADDR)|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LABEL, 0 } }, { { 1, 0 } } } } },
/* pcabs24a2: comment */
{ "pcabs24a2", MEP_OPERAND_PCABS24A2, HW_H_UINT, 5, 23,
{ 2, { (const PTR) &MEP_F_24U5A2N_MULTI_IFIELD[0] } },
{ 2, { (const PTR) &MEP_F_24U5A2N_MULTI_IFIELD[0] } },
{ 0|A(ABS_ADDR)|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LABEL, 0 } }, { { 1, 0 } } } } },
/* sdisp16: comment */
{ "sdisp16", MEP_OPERAND_SDISP16, HW_H_SINT, 16, 16,
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_16S16] } },
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_16S16] } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* simm16: comment */
{ "simm16", MEP_OPERAND_SIMM16, HW_H_SINT, 16, 16,
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_16S16] } },
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_16S16] } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* uimm16: comment */
{ "uimm16", MEP_OPERAND_UIMM16, HW_H_UINT, 16, 16,
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_16U16] } },
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_16U16] } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* code16: uci/dsp code (16 bits) */
{ "code16", MEP_OPERAND_CODE16, HW_H_UINT, 16, 16,
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_16U16] } },
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_16U16] } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* udisp2: SSARB addend (2 bits) */
{ "udisp2", MEP_OPERAND_UDISP2, HW_H_SINT, 6, 2,
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_2U6] } },
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_2U6] } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* uimm2: interrupt (2 bits) */
{ "uimm2", MEP_OPERAND_UIMM2, HW_H_UINT, 10, 2,
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_2U10] } },
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_2U10] } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* simm6: add const (6 bits) */
{ "simm6", MEP_OPERAND_SIMM6, HW_H_SINT, 8, 6,
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_6S8] } },
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_6S8] } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* simm8: mov const (8 bits) */
{ "simm8", MEP_OPERAND_SIMM8, HW_H_SINT, 8, 8,
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_8S8] } },
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_8S8] } },
{ 0|A(RELOC_IMPLIES_OVERFLOW), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* addr24a4: comment */
{ "addr24a4", MEP_OPERAND_ADDR24A4, HW_H_UINT, 8, 22,
{ 2, { (const PTR) &MEP_F_24U8A4N_MULTI_IFIELD[0] } },
{ 2, { (const PTR) &MEP_F_24U8A4N_MULTI_IFIELD[0] } },
{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 4, 0 } } } } },
/* code24: coprocessor code */
{ "code24", MEP_OPERAND_CODE24, HW_H_UINT, 4, 24,
{ 2, { (const PTR) &MEP_F_24U4N_MULTI_IFIELD[0] } },
{ 2, { (const PTR) &MEP_F_24U4N_MULTI_IFIELD[0] } },
{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* callnum: system call number */
{ "callnum", MEP_OPERAND_CALLNUM, HW_H_UINT, 5, 4,
{ 4, { (const PTR) &MEP_F_CALLNUM_MULTI_IFIELD[0] } },
{ 4, { (const PTR) &MEP_F_CALLNUM_MULTI_IFIELD[0] } },
{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* uimm3: bit immediate (3 bits) */
{ "uimm3", MEP_OPERAND_UIMM3, HW_H_UINT, 5, 3,
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_3U5] } },
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_3U5] } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* uimm4: bCC const (4 bits) */
{ "uimm4", MEP_OPERAND_UIMM4, HW_H_UINT, 8, 4,
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_4U8] } },
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_4U8] } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* uimm5: bit/shift val (5 bits) */
{ "uimm5", MEP_OPERAND_UIMM5, HW_H_UINT, 8, 5,
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_5U8] } },
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_5U8] } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* udisp7: comment */
{ "udisp7", MEP_OPERAND_UDISP7, HW_H_UINT, 9, 7,
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_7U9] } },
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_7U9] } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* udisp7a2: comment */
{ "udisp7a2", MEP_OPERAND_UDISP7A2, HW_H_UINT, 9, 6,
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_7U9A2] } },
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_7U9A2] } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 2, 0 } } } } },
/* udisp7a4: comment */
{ "udisp7a4", MEP_OPERAND_UDISP7A4, HW_H_UINT, 9, 5,
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_7U9A4] } },
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_7U9A4] } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 4, 0 } } } } },
/* uimm7a4: comment */
{ "uimm7a4", MEP_OPERAND_UIMM7A4, HW_H_UINT, 9, 5,
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_7U9A4] } },
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_7U9A4] } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 4, 0 } } } } },
/* uimm24: immediate (24 bits) */
{ "uimm24", MEP_OPERAND_UIMM24, HW_H_UINT, 8, 24,
{ 2, { (const PTR) &MEP_F_24U8N_MULTI_IFIELD[0] } },
{ 2, { (const PTR) &MEP_F_24U8N_MULTI_IFIELD[0] } },
{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* cimm4: cache immed'te (4 bits) */
{ "cimm4", MEP_OPERAND_CIMM4, HW_H_UINT, 4, 4,
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RN] } },
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RN] } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* cimm5: clip immediate (5 bits) */
{ "cimm5", MEP_OPERAND_CIMM5, HW_H_UINT, 24, 5,
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_5U24] } },
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_5U24] } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* cdisp10: comment */
{ "cdisp10", MEP_OPERAND_CDISP10, HW_H_SINT, 22, 10,
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_CDISP10] } },
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_CDISP10] } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* cdisp10a2: comment */
{ "cdisp10a2", MEP_OPERAND_CDISP10A2, HW_H_SINT, 22, 10,
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_CDISP10] } },
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_CDISP10] } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* cdisp10a4: comment */
{ "cdisp10a4", MEP_OPERAND_CDISP10A4, HW_H_SINT, 22, 10,
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_CDISP10] } },
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_CDISP10] } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* cdisp10a8: comment */
{ "cdisp10a8", MEP_OPERAND_CDISP10A8, HW_H_SINT, 22, 10,
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_CDISP10] } },
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_CDISP10] } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* zero: Zero operand */
{ "zero", MEP_OPERAND_ZERO, HW_H_SINT, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { (const PTR) 0 } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* rl5: register Rl c5 */
{ "rl5", MEP_OPERAND_RL5, HW_H_GPR, 20, 4,
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RL5] } },
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RL5] } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* cdisp12: copro addend (12 bits) */
{ "cdisp12", MEP_OPERAND_CDISP12, HW_H_SINT, 20, 12,
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_12S20] } },
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_12S20] } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* c5rmuimm20: 20-bit immediate in rm and imm16 */
{ "c5rmuimm20", MEP_OPERAND_C5RMUIMM20, HW_H_UINT, 8, 20,
{ 2, { (const PTR) &MEP_F_C5_RMUIMM20_MULTI_IFIELD[0] } },
{ 2, { (const PTR) &MEP_F_C5_RMUIMM20_MULTI_IFIELD[0] } },
{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* c5rnmuimm24: 24-bit immediate in rn, rm, and imm16 */
{ "c5rnmuimm24", MEP_OPERAND_C5RNMUIMM24, HW_H_UINT, 4, 24,
{ 2, { (const PTR) &MEP_F_C5_RNMUIMM24_MULTI_IFIELD[0] } },
{ 2, { (const PTR) &MEP_F_C5_RNMUIMM24_MULTI_IFIELD[0] } },
{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* cp_flag: branch condition register */
{ "cp_flag", MEP_OPERAND_CP_FLAG, HW_H_CCR, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { (const PTR) 0 } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* ivc2_csar0: ivc2_csar0 */
{ "ivc2_csar0", MEP_OPERAND_IVC2_CSAR0, HW_H_CCR_IVC2, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { (const PTR) 0 } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x7c" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* ivc2_cc: ivc2_cc */
{ "ivc2_cc", MEP_OPERAND_IVC2_CC, HW_H_CCR_IVC2, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { (const PTR) 0 } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x7c" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* ivc2_cofr0: ivc2_cofr0 */
{ "ivc2_cofr0", MEP_OPERAND_IVC2_COFR0, HW_H_CCR_IVC2, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { (const PTR) 0 } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x7c" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* ivc2_cofr1: ivc2_cofr1 */
{ "ivc2_cofr1", MEP_OPERAND_IVC2_COFR1, HW_H_CCR_IVC2, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { (const PTR) 0 } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x7c" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* ivc2_cofa0: ivc2_cofa0 */
{ "ivc2_cofa0", MEP_OPERAND_IVC2_COFA0, HW_H_CCR_IVC2, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { (const PTR) 0 } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x7c" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* ivc2_cofa1: ivc2_cofa1 */
{ "ivc2_cofa1", MEP_OPERAND_IVC2_COFA1, HW_H_CCR_IVC2, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { (const PTR) 0 } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x7c" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* ivc2_csar1: ivc2_csar1 */
{ "ivc2_csar1", MEP_OPERAND_IVC2_CSAR1, HW_H_CCR_IVC2, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { (const PTR) 0 } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x7c" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* ivc2_acc0_0: acc0_0 */
{ "ivc2_acc0_0", MEP_OPERAND_IVC2_ACC0_0, HW_H_CCR_IVC2, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { (const PTR) 0 } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x7c" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* ivc2_acc0_1: acc0_1 */
{ "ivc2_acc0_1", MEP_OPERAND_IVC2_ACC0_1, HW_H_CCR_IVC2, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { (const PTR) 0 } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x7c" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* ivc2_acc0_2: acc0_2 */
{ "ivc2_acc0_2", MEP_OPERAND_IVC2_ACC0_2, HW_H_CCR_IVC2, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { (const PTR) 0 } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x7c" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* ivc2_acc0_3: acc0_3 */
{ "ivc2_acc0_3", MEP_OPERAND_IVC2_ACC0_3, HW_H_CCR_IVC2, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { (const PTR) 0 } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x7c" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* ivc2_acc0_4: acc0_4 */
{ "ivc2_acc0_4", MEP_OPERAND_IVC2_ACC0_4, HW_H_CCR_IVC2, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { (const PTR) 0 } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x7c" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* ivc2_acc0_5: acc0_5 */
{ "ivc2_acc0_5", MEP_OPERAND_IVC2_ACC0_5, HW_H_CCR_IVC2, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { (const PTR) 0 } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x7c" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* ivc2_acc0_6: acc0_6 */
{ "ivc2_acc0_6", MEP_OPERAND_IVC2_ACC0_6, HW_H_CCR_IVC2, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { (const PTR) 0 } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x7c" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* ivc2_acc0_7: acc0_7 */
{ "ivc2_acc0_7", MEP_OPERAND_IVC2_ACC0_7, HW_H_CCR_IVC2, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { (const PTR) 0 } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x7c" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* ivc2_acc1_0: acc1_0 */
{ "ivc2_acc1_0", MEP_OPERAND_IVC2_ACC1_0, HW_H_CCR_IVC2, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { (const PTR) 0 } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x7c" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* ivc2_acc1_1: acc1_1 */
{ "ivc2_acc1_1", MEP_OPERAND_IVC2_ACC1_1, HW_H_CCR_IVC2, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { (const PTR) 0 } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x7c" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* ivc2_acc1_2: acc1_2 */
{ "ivc2_acc1_2", MEP_OPERAND_IVC2_ACC1_2, HW_H_CCR_IVC2, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { (const PTR) 0 } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x7c" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* ivc2_acc1_3: acc1_3 */
{ "ivc2_acc1_3", MEP_OPERAND_IVC2_ACC1_3, HW_H_CCR_IVC2, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { (const PTR) 0 } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x7c" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* ivc2_acc1_4: acc1_4 */
{ "ivc2_acc1_4", MEP_OPERAND_IVC2_ACC1_4, HW_H_CCR_IVC2, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { (const PTR) 0 } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x7c" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* ivc2_acc1_5: acc1_5 */
{ "ivc2_acc1_5", MEP_OPERAND_IVC2_ACC1_5, HW_H_CCR_IVC2, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { (const PTR) 0 } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x7c" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* ivc2_acc1_6: acc1_6 */
{ "ivc2_acc1_6", MEP_OPERAND_IVC2_ACC1_6, HW_H_CCR_IVC2, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { (const PTR) 0 } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x7c" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* ivc2_acc1_7: acc1_7 */
{ "ivc2_acc1_7", MEP_OPERAND_IVC2_ACC1_7, HW_H_CCR_IVC2, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { (const PTR) 0 } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x7c" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* croc: $CRo C3 */
{ "croc", MEP_OPERAND_CROC, HW_H_CR64, 7, 5,
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_5U7] } },
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_5U7] } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_CP_DATA_BUS_INT, 0 } }, { { 1, 0 } } } } },
/* crqc: $CRq C3 */
{ "crqc", MEP_OPERAND_CRQC, HW_H_CR64, 21, 5,
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_5U21] } },
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_5U21] } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_CP_DATA_BUS_INT, 0 } }, { { 1, 0 } } } } },
/* crpc: $CRp C3 */
{ "crpc", MEP_OPERAND_CRPC, HW_H_CR64, 26, 5,
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_5U26] } },
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_5U26] } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_CP_DATA_BUS_INT, 0 } }, { { 1, 0 } } } } },
/* ivc-x-6-1: filler */
{ "ivc-x-6-1", MEP_OPERAND_IVC_X_6_1, HW_H_UINT, 6, 1,
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_1U6] } },
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_1U6] } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* ivc-x-6-2: filler */
{ "ivc-x-6-2", MEP_OPERAND_IVC_X_6_2, HW_H_UINT, 6, 2,
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_2U6] } },
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_2U6] } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* ivc-x-6-3: filler */
{ "ivc-x-6-3", MEP_OPERAND_IVC_X_6_3, HW_H_UINT, 6, 3,
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_3U6] } },
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_3U6] } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* imm3p4: Imm3p4 */
{ "imm3p4", MEP_OPERAND_IMM3P4, HW_H_UINT, 4, 3,
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_3U4] } },
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_3U4] } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* imm3p9: Imm3p9 */
{ "imm3p9", MEP_OPERAND_IMM3P9, HW_H_UINT, 9, 3,
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_3U9] } },
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_3U9] } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* imm4p8: Imm4p8 */
{ "imm4p8", MEP_OPERAND_IMM4P8, HW_H_UINT, 8, 4,
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_4U8] } },
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_4U8] } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* imm5p7: Imm5p7 */
{ "imm5p7", MEP_OPERAND_IMM5P7, HW_H_UINT, 7, 5,
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_5U7] } },
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_5U7] } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* imm6p6: Imm6p6 */
{ "imm6p6", MEP_OPERAND_IMM6P6, HW_H_UINT, 6, 6,
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_6U6] } },
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_6U6] } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* imm8p4: Imm8p4 */
{ "imm8p4", MEP_OPERAND_IMM8P4, HW_H_UINT, 4, 8,
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_8U4] } },
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_8U4] } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* simm8p4: sImm8p4 */
{ "simm8p4", MEP_OPERAND_SIMM8P4, HW_H_SINT, 4, 8,
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_8S4] } },
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_8S4] } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* imm3p5: Imm3p5 */
{ "imm3p5", MEP_OPERAND_IMM3P5, HW_H_UINT, 5, 3,
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_3U5] } },
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_3U5] } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* imm3p12: Imm3p12 */
{ "imm3p12", MEP_OPERAND_IMM3P12, HW_H_UINT, 12, 3,
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_3U12] } },
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_3U12] } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* imm4p4: Imm4p4 */
{ "imm4p4", MEP_OPERAND_IMM4P4, HW_H_UINT, 4, 4,
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_4U4] } },
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_4U4] } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* imm4p10: Imm4p10 */
{ "imm4p10", MEP_OPERAND_IMM4P10, HW_H_UINT, 10, 4,
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_4U10] } },
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_4U10] } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* imm5p8: Imm5p8 */
{ "imm5p8", MEP_OPERAND_IMM5P8, HW_H_UINT, 8, 5,
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_5U8] } },
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_5U8] } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* imm5p3: Imm5p3 */
{ "imm5p3", MEP_OPERAND_IMM5P3, HW_H_UINT, 3, 5,
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_5U3] } },
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_5U3] } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* imm6p2: Imm6p2 */
{ "imm6p2", MEP_OPERAND_IMM6P2, HW_H_UINT, 2, 6,
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_6U2] } },
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_6U2] } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* imm5p23: Imm5p23 */
{ "imm5p23", MEP_OPERAND_IMM5P23, HW_H_UINT, 23, 5,
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_5U23] } },
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_5U23] } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* imm3p25: Imm3p25 */
{ "imm3p25", MEP_OPERAND_IMM3P25, HW_H_UINT, 25, 3,
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_3U25] } },
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_3U25] } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* imm8p0: Imm8p0 */
{ "imm8p0", MEP_OPERAND_IMM8P0, HW_H_UINT, 0, 8,
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_8U0] } },
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_8U0] } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* simm8p0: sImm8p0 */
{ "simm8p0", MEP_OPERAND_SIMM8P0, HW_H_SINT, 0, 8,
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_8S0] } },
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_8S0] } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* simm8p20: sImm8p20 */
{ "simm8p20", MEP_OPERAND_SIMM8P20, HW_H_SINT, 20, 8,
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_8S20] } },
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_8S20] } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* imm8p20: Imm8p20 */
{ "imm8p20", MEP_OPERAND_IMM8P20, HW_H_UINT, 20, 8,
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_8U20] } },
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_8U20] } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* crop: $CRo Pn */
{ "crop", MEP_OPERAND_CROP, HW_H_CR64, 23, 5,
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_5U23] } },
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_5U23] } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_CP_DATA_BUS_INT, 0 } }, { { 1, 0 } } } } },
/* crqp: $CRq Pn */
{ "crqp", MEP_OPERAND_CRQP, HW_H_CR64, 13, 5,
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_5U13] } },
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_5U13] } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_CP_DATA_BUS_INT, 0 } }, { { 1, 0 } } } } },
/* crpp: $CRp Pn */
{ "crpp", MEP_OPERAND_CRPP, HW_H_CR64, 18, 5,
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_5U18] } },
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_5U18] } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_CP_DATA_BUS_INT, 0 } }, { { 1, 0 } } } } },
/* ivc-x-0-2: filler */
{ "ivc-x-0-2", MEP_OPERAND_IVC_X_0_2, HW_H_UINT, 0, 2,
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_2U0] } },
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_2U0] } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* ivc-x-0-3: filler */
{ "ivc-x-0-3", MEP_OPERAND_IVC_X_0_3, HW_H_UINT, 0, 3,
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_3U0] } },
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_3U0] } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* ivc-x-0-4: filler */
{ "ivc-x-0-4", MEP_OPERAND_IVC_X_0_4, HW_H_UINT, 0, 4,
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_4U0] } },
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_4U0] } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* ivc-x-0-5: filler */
{ "ivc-x-0-5", MEP_OPERAND_IVC_X_0_5, HW_H_UINT, 0, 5,
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_5U0] } },
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_5U0] } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* imm16p0: comment */
{ "imm16p0", MEP_OPERAND_IMM16P0, HW_H_UINT, 0, 16,
{ 2, { (const PTR) &MEP_F_IVC2_IMM16P0_MULTI_IFIELD[0] } },
{ 2, { (const PTR) &MEP_F_IVC2_IMM16P0_MULTI_IFIELD[0] } },
{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* simm16p0: comment */
{ "simm16p0", MEP_OPERAND_SIMM16P0, HW_H_SINT, 0, 16,
{ 2, { (const PTR) &MEP_F_IVC2_SIMM16P0_MULTI_IFIELD[0] } },
{ 2, { (const PTR) &MEP_F_IVC2_SIMM16P0_MULTI_IFIELD[0] } },
{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* ivc2rm: reg Rm */
{ "ivc2rm", MEP_OPERAND_IVC2RM, HW_H_GPR, 4, 4,
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_CRM] } },
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_CRM] } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* ivc2crn: copro Rn (0-31, 64-bit */
{ "ivc2crn", MEP_OPERAND_IVC2CRN, HW_H_CR64, 0, 5,
{ 2, { (const PTR) &MEP_F_IVC2_CRNX_MULTI_IFIELD[0] } },
{ 2, { (const PTR) &MEP_F_IVC2_CRNX_MULTI_IFIELD[0] } },
{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_CP_DATA_BUS_INT, 0 } }, { { 1, 0 } } } } },
/* ivc2ccrn: copro control reg CCRn */
{ "ivc2ccrn", MEP_OPERAND_IVC2CCRN, HW_H_CCR_IVC2, 0, 6,
{ 2, { (const PTR) &MEP_F_IVC2_CCRN_MULTI_IFIELD[0] } },
{ 2, { (const PTR) &MEP_F_IVC2_CCRN_MULTI_IFIELD[0] } },
{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_REGNUM, 0 } }, { { 1, 0 } } } } },
/* ivc2c3ccrn: copro control reg CCRn */
{ "ivc2c3ccrn", MEP_OPERAND_IVC2C3CCRN, HW_H_CCR_IVC2, 4, 6,
{ 2, { (const PTR) &MEP_F_IVC2_CCRN_C3_MULTI_IFIELD[0] } },
{ 2, { (const PTR) &MEP_F_IVC2_CCRN_C3_MULTI_IFIELD[0] } },
{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_REGNUM, 0 } }, { { 1, 0 } } } } },
/* sentinel */
{ 0, 0, 0, 0, 0,
@ -6329,7 +6329,7 @@ mep_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...)
/* Default to not allowing signed overflow. */
cd->signed_overflow_ok_p = 0;
return (CGEN_CPU_DESC) cd;
}
@ -6369,7 +6369,7 @@ mep_cgen_cpu_close (CGEN_CPU_DESC cd)
for (i = 0; i < cd->insn_table.num_init_entries; ++i, ++insns)
if (CGEN_INSN_RX (insns))
regfree (CGEN_INSN_RX (insns));
}
}
if (cd->macro_insn_table.init_entries)
free ((CGEN_INSN *) cd->macro_insn_table.init_entries);

50
opcodes/mep-dis.c
View File

@ -78,7 +78,7 @@ print_tpreg (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, PTR dis_info,
}
static void
print_spreg (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, PTR dis_info,
print_spreg (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, PTR dis_info,
CGEN_KEYWORD *table ATTRIBUTE_UNUSED, long val ATTRIBUTE_UNUSED,
unsigned int flags ATTRIBUTE_UNUSED)
{
@ -143,11 +143,11 @@ mep_print_vliw_insns (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info,
if (corelength > 0)
{
int my_status = 0;
for (i = 0; i < corelength; i++ )
insnbuf[i] = buf[i];
cd->isas = & MEP_CORE_ISA;
my_status = print_insn (cd, pc, info, insnbuf, corelength);
if (my_status != corelength)
{
@ -159,7 +159,7 @@ mep_print_vliw_insns (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info,
/* Print the + to indicate that the following copro insn is */
/* part of a vliw group. */
if (copro1length > 0)
(*info->fprintf_func) (info->stream, " + ");
(*info->fprintf_func) (info->stream, " + ");
}
/* Now all that is left to be processed is the coprocessor insns
@ -171,7 +171,7 @@ mep_print_vliw_insns (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info,
if (copro1length > 0)
{
int my_status = 0;
for (i = corelength; i < corelength + copro1length; i++ )
insnbuf[i - corelength] = buf[i];
@ -190,7 +190,7 @@ mep_print_vliw_insns (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info,
break;
case 8:
cd->isas = & MEP_COP64_ISA;
break;
break;
default:
/* Shouldn't be anything but 16,32,48,64. */
break;
@ -223,7 +223,7 @@ mep_print_vliw_insns (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info,
for (i = corelength + copro1length; i < 64; i++)
insnbuf[i - (corelength + copro1length)] = buf[i];
switch (copro2length)
{
case 2:
@ -236,7 +236,7 @@ mep_print_vliw_insns (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info,
cd->isas = 1 << ISA_EXT_COP1_48;
break;
case 8:
cd->isas = 1 << ISA_EXT_COP1_64;
cd->isas = 1 << ISA_EXT_COP1_64;
break;
default:
/* Shouldn't be anything but 16,32,48,64. */
@ -264,29 +264,29 @@ mep_print_vliw_insns (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info,
return status;
}
/* The two functions mep_examine_vliw[32,64]_insns are used find out
which vliw combinaion (16 bit core with 48 bit copro, 32 bit core
with 32 bit copro, etc.) is present. Later on, when internally
parallel coprocessors are handled, only these functions should
need to be changed.
/* The two functions mep_examine_vliw[32,64]_insns are used find out
which vliw combinaion (16 bit core with 48 bit copro, 32 bit core
with 32 bit copro, etc.) is present. Later on, when internally
parallel coprocessors are handled, only these functions should
need to be changed.
At this time only the following combinations are supported:
At this time only the following combinations are supported:
VLIW32 Mode:
16 bit core insn (core) and 16 bit coprocessor insn (cop1)
32 bit core insn (core)
32 bit coprocessor insn (cop1)
Note: As of this time, I do not believe we have enough information
to distinguish a 32 bit core insn from a 32 bit cop insn. Also,
no 16 bit coprocessor insns have been specified.
no 16 bit coprocessor insns have been specified.
VLIW64 Mode:
16 bit core insn (core) and 48 bit coprocessor insn (cop1)
32 bit core insn (core) and 32 bit coprocessor insn (cop1)
64 bit coprocessor insn (cop1)
The framework for an internally parallel coprocessor is also
present (2nd coprocessor insn is cop2), but at this time it
present (2nd coprocessor insn is cop2), but at this time it
is not used. This only appears to be valid in VLIW64 mode. */
static int
@ -297,9 +297,9 @@ mep_examine_vliw32_insns (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info)
int corebuflength;
int cop1buflength;
int cop2buflength;
bfd_byte buf[CGEN_MAX_INSN_SIZE];
bfd_byte buf[CGEN_MAX_INSN_SIZE];
char indicator16[1];
char indicatorcop32[2];
char indicatorcop32[2];
/* At this time we're not supporting internally parallel coprocessors,
so cop2buflength will always be 0. */
@ -1189,7 +1189,7 @@ mep_cgen_print_operand (CGEN_CPU_DESC cd,
}
}
cgen_print_fn * const mep_cgen_print_handlers[] =
cgen_print_fn * const mep_cgen_print_handlers[] =
{
print_insn_normal,
};
@ -1379,7 +1379,7 @@ print_insn (CGEN_CPU_DESC cd,
int length;
unsigned long insn_value_cropped;
#ifdef CGEN_VALIDATE_INSN_SUPPORTED
#ifdef CGEN_VALIDATE_INSN_SUPPORTED
/* Not needed as insn shouldn't be in hash lists if not supported. */
/* Supported by this cpu? */
if (! mep_cgen_insn_supported (cd, insn))
@ -1397,7 +1397,7 @@ print_insn (CGEN_CPU_DESC cd,
relevant part from the buffer. */
if ((unsigned) (CGEN_INSN_BITSIZE (insn) / 8) < buflen &&
(unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long))
insn_value_cropped = bfd_get_bits (buf, CGEN_INSN_BITSIZE (insn),
insn_value_cropped = bfd_get_bits (buf, CGEN_INSN_BITSIZE (insn),
info->endian == BFD_ENDIAN_BIG);
else
insn_value_cropped = insn_value;
@ -1516,7 +1516,7 @@ print_insn_mep (bfd_vma pc, disassemble_info *info)
arch = info->arch;
if (arch == bfd_arch_unknown)
arch = CGEN_BFD_ARCH;
/* There's no standard way to compute the machine or isa number
so we leave it to the target. */
#ifdef CGEN_COMPUTE_MACH
@ -1557,7 +1557,7 @@ print_insn_mep (bfd_vma pc, disassemble_info *info)
break;
}
}
}
}
/* If we haven't initialized yet, initialize the opcode table. */
if (! cd)

8
opcodes/mep-ibld.c
View File

@ -154,7 +154,7 @@ insert_normal (CGEN_CPU_DESC cd,
{
long minval = - (1L << (length - 1));
unsigned long maxval = mask;
if ((value > 0 && (unsigned long) value > maxval)
|| value < minval)
{
@ -192,7 +192,7 @@ insert_normal (CGEN_CPU_DESC cd,
{
long minval = - (1L << (length - 1));
long maxval = (1L << (length - 1)) - 1;
if (value < minval || value > maxval)
{
sprintf
@ -1808,12 +1808,12 @@ mep_cgen_extract_operand (CGEN_CPU_DESC cd,
return length;
}
cgen_insert_fn * const mep_cgen_insert_handlers[] =
cgen_insert_fn * const mep_cgen_insert_handlers[] =
{
insert_insn_normal,
};
cgen_extract_fn * const mep_cgen_extract_handlers[] =
cgen_extract_fn * const mep_cgen_extract_handlers[] =
{
extract_insn_normal,
};

2
opcodes/mep-opc.h
View File

@ -87,7 +87,7 @@ extern CGEN_ATTR_VALUE_BITSET_TYPE mep_all_core_isas_mask;
)
/* A mask for all ISAs executed by a VLIW coprocessor. */
#define MEP_ALL_COP_ISAS_MASK mep_all_cop_isas_mask
#define MEP_ALL_COP_ISAS_MASK mep_all_cop_isas_mask
extern CGEN_ATTR_VALUE_BITSET_TYPE mep_all_cop_isas_mask;
#define MEP_INSN_COP_P(insn) ( \

4
opcodes/microblaze-dis.h
View File

@ -26,12 +26,12 @@
extern "C" {
#endif
extern enum microblaze_instr microblaze_decode_insn (long, int *, int *,
extern enum microblaze_instr microblaze_decode_insn (long, int *, int *,
int *, int *);
extern unsigned long microblaze_get_target_address (long, bfd_boolean, int,
long, long, long, bfd_boolean *, bfd_boolean *);
extern enum microblaze_instr get_insn_microblaze (long, bfd_boolean *,
extern enum microblaze_instr get_insn_microblaze (long, bfd_boolean *,
enum microblaze_instr_type *,
short *);

44
opcodes/microblaze-opc.h
View File

@ -1,5 +1,5 @@
/* microblaze-opc.h -- MicroBlaze Opcodes
Copyright (C) 2009-2015 Free Software Foundation, Inc.
This file is part of the GNU opcodes library.
@ -63,12 +63,12 @@
/* Instructions where the label address is resolved as a PC offset
/* Instructions where the label address is resolved as a PC offset
(for branch label). */
#define INST_PC_OFFSET 1
/* Instructions where the label address is resolved as an absolute
#define INST_PC_OFFSET 1
/* Instructions where the label address is resolved as an absolute
value (for data mem or abs address). */
#define INST_NO_OFFSET 0
#define INST_NO_OFFSET 0
#define IMMVAL_MASK_NON_SPECIAL 0x0000
#define IMMVAL_MASK_MTS 0x4000
@ -81,14 +81,14 @@
#define OPCODE_MASK_H4 0xFC0007FF /* High 6 and low 11 bits. */
#define OPCODE_MASK_H13S 0xFFE0E7F0 /* High 11 16:18 21:27 bits, 19:20 bits
and last nibble of last byte for spr. */
#define OPCODE_MASK_H23S 0xFC1FC000 /* High 6, 20-16 and 15:1 bits and last
#define OPCODE_MASK_H23S 0xFC1FC000 /* High 6, 20-16 and 15:1 bits and last
nibble of last byte for spr. */
#define OPCODE_MASK_H34 0xFC00FFFF /* High 6 and low 16 bits. */
#define OPCODE_MASK_H14 0xFFE007FF /* High 11 and low 11 bits. */
#define OPCODE_MASK_H24 0xFC1F07FF /* High 6, bits 20-16 and low 11 bits. */
#define OPCODE_MASK_H124 0xFFFF07FF /* High 16, and low 11 bits. */
#define OPCODE_MASK_H1234 0xFFFFFFFF /* All 32 bits. */
#define OPCODE_MASK_H3 0xFC000600 /* High 6 bits and bits 21, 22. */
#define OPCODE_MASK_H3 0xFC000600 /* High 6 bits and bits 21, 22. */
#define OPCODE_MASK_H32 0xFC00FC00 /* High 6 bits and bit 16-21. */
#define OPCODE_MASK_H34B 0xFC0000FF /* High 6 bits and low 8 bits. */
#define OPCODE_MASK_H34C 0xFC0007E0 /* High 6 bits and bits 21-26. */
@ -110,15 +110,15 @@ struct op_code_struct
short inst_offset_type; /* Immediate vals offset from PC? (= 1 for branches). */
short delay_slots; /* Info about delay slots needed after this instr. */
short immval_mask;
unsigned long bit_sequence; /* All the fixed bits for the op are set and
all the variable bits (reg names, imm vals)
are set to 0. */
unsigned long bit_sequence; /* All the fixed bits for the op are set and
all the variable bits (reg names, imm vals)
are set to 0. */
unsigned long opcode_mask; /* Which bits define the opcode. */
enum microblaze_instr instr;
enum microblaze_instr_type instr_type;
/* More info about output format here. */
} opcodes[MAX_OPCODES] =
{
} opcodes[MAX_OPCODES] =
{
{"add", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x00000000, OPCODE_MASK_H4, add, arithmetic_inst },
{"rsub", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x04000000, OPCODE_MASK_H4, rsub, arithmetic_inst },
{"addc", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x08000000, OPCODE_MASK_H4, addc, arithmetic_inst },
@ -277,7 +277,7 @@ struct op_code_struct
{"tcput", INST_TYPE_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00B000, OPCODE_MASK_H32, tcput, anyware_inst },
{"tnput", INST_TYPE_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00D000, OPCODE_MASK_H32, tnput, anyware_inst },
{"tncput", INST_TYPE_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00F000, OPCODE_MASK_H32, tncput, anyware_inst },
{"eget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C000400, OPCODE_MASK_H32, eget, anyware_inst },
{"ecget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C002400, OPCODE_MASK_H32, ecget, anyware_inst },
{"neget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C004400, OPCODE_MASK_H32, neget, anyware_inst },
@ -286,7 +286,7 @@ struct op_code_struct
{"ecput", INST_TYPE_R1_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00A400, OPCODE_MASK_H32, ecput, anyware_inst },
{"neput", INST_TYPE_R1_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00C400, OPCODE_MASK_H32, neput, anyware_inst },
{"necput", INST_TYPE_R1_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00E400, OPCODE_MASK_H32, necput, anyware_inst },
{"teget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C001400, OPCODE_MASK_H32, teget, anyware_inst },
{"tecget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C003400, OPCODE_MASK_H32, tecget, anyware_inst },
{"tneget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C005400, OPCODE_MASK_H32, tneget, anyware_inst },
@ -295,7 +295,7 @@ struct op_code_struct
{"tecput", INST_TYPE_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00B400, OPCODE_MASK_H32, tecput, anyware_inst },
{"tneput", INST_TYPE_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00D400, OPCODE_MASK_H32, tneput, anyware_inst },
{"tnecput", INST_TYPE_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00F400, OPCODE_MASK_H32, tnecput, anyware_inst },
{"aget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C000800, OPCODE_MASK_H32, aget, anyware_inst },
{"caget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C002800, OPCODE_MASK_H32, caget, anyware_inst },
{"naget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C004800, OPCODE_MASK_H32, naget, anyware_inst },
@ -304,7 +304,7 @@ struct op_code_struct
{"caput", INST_TYPE_R1_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00A800, OPCODE_MASK_H32, caput, anyware_inst },
{"naput", INST_TYPE_R1_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00C800, OPCODE_MASK_H32, naput, anyware_inst },
{"ncaput", INST_TYPE_R1_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00E800, OPCODE_MASK_H32, ncaput, anyware_inst },
{"taget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C001800, OPCODE_MASK_H32, taget, anyware_inst },
{"tcaget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C003800, OPCODE_MASK_H32, tcaget, anyware_inst },
{"tnaget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C005800, OPCODE_MASK_H32, tnaget, anyware_inst },
@ -313,7 +313,7 @@ struct op_code_struct
{"tcaput", INST_TYPE_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00B800, OPCODE_MASK_H32, tcaput, anyware_inst },
{"tnaput", INST_TYPE_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00D800, OPCODE_MASK_H32, tnaput, anyware_inst },
{"tncaput", INST_TYPE_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00F800, OPCODE_MASK_H32, tncaput, anyware_inst },
{"eaget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C000C00, OPCODE_MASK_H32, eget, anyware_inst },
{"ecaget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C002C00, OPCODE_MASK_H32, ecget, anyware_inst },
{"neaget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C004C00, OPCODE_MASK_H32, neget, anyware_inst },
@ -322,7 +322,7 @@ struct op_code_struct
{"ecaput", INST_TYPE_R1_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00AC00, OPCODE_MASK_H32, ecput, anyware_inst },
{"neaput", INST_TYPE_R1_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00CC00, OPCODE_MASK_H32, neput, anyware_inst },
{"necaput", INST_TYPE_R1_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00EC00, OPCODE_MASK_H32, necput, anyware_inst },
{"teaget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C001C00, OPCODE_MASK_H32, teaget, anyware_inst },
{"tecaget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C003C00, OPCODE_MASK_H32, tecaget, anyware_inst },
{"tneaget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C005C00, OPCODE_MASK_H32, tneaget, anyware_inst },
@ -331,7 +331,7 @@ struct op_code_struct
{"tecaput", INST_TYPE_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00BC00, OPCODE_MASK_H32, tecaput, anyware_inst },
{"tneaput", INST_TYPE_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00DC00, OPCODE_MASK_H32, tneaput, anyware_inst },
{"tnecaput", INST_TYPE_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00FC00, OPCODE_MASK_H32, tnecaput, anyware_inst },
{"getd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000000, OPCODE_MASK_H34C, getd, anyware_inst },
{"tgetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000080, OPCODE_MASK_H34C, tgetd, anyware_inst },
{"cgetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000100, OPCODE_MASK_H34C, cgetd, anyware_inst },
@ -348,7 +348,7 @@ struct op_code_struct
{"tnputd", INST_TYPE_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000680, OPCODE_MASK_H34C, tnputd, anyware_inst },
{"ncputd", INST_TYPE_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000700, OPCODE_MASK_H34C, ncputd, anyware_inst },
{"tncputd", INST_TYPE_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000780, OPCODE_MASK_H34C, tncputd, anyware_inst },
{"egetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000020, OPCODE_MASK_H34C, egetd, anyware_inst },
{"tegetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0000A0, OPCODE_MASK_H34C, tegetd, anyware_inst },
{"ecgetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000120, OPCODE_MASK_H34C, ecgetd, anyware_inst },
@ -365,7 +365,7 @@ struct op_code_struct
{"tneputd", INST_TYPE_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0006A0, OPCODE_MASK_H34C, tneputd, anyware_inst },
{"necputd", INST_TYPE_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000720, OPCODE_MASK_H34C, necputd, anyware_inst },
{"tnecputd", INST_TYPE_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0007A0, OPCODE_MASK_H34C, tnecputd, anyware_inst },
{"agetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000040, OPCODE_MASK_H34C, agetd, anyware_inst },
{"tagetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0000C0, OPCODE_MASK_H34C, tagetd, anyware_inst },
{"cagetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000140, OPCODE_MASK_H34C, cagetd, anyware_inst },
@ -382,7 +382,7 @@ struct op_code_struct
{"tnaputd", INST_TYPE_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0006C0, OPCODE_MASK_H34C, tnaputd, anyware_inst },
{"ncaputd", INST_TYPE_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000740, OPCODE_MASK_H34C, ncaputd, anyware_inst },
{"tncaputd", INST_TYPE_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0007C0, OPCODE_MASK_H34C, tncaputd, anyware_inst },
{"eagetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000060, OPCODE_MASK_H34C, eagetd, anyware_inst },
{"teagetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0000E0, OPCODE_MASK_H34C, teagetd, anyware_inst },
{"ecagetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000160, OPCODE_MASK_H34C, ecagetd, anyware_inst },

16
opcodes/microblaze-opcm.h
View File

@ -18,7 +18,7 @@
along with this file; see the file COPYING. If not, write to the
Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
MA 02110-1301, USA. */
#ifndef MICROBLAZE_OPCM
#define MICROBLAZE_OPCM
@ -26,23 +26,23 @@
enum microblaze_instr
{
add, rsub, addc, rsubc, addk, rsubk, addkc, rsubkc, clz, cmp, cmpu,
addi, rsubi, addic, rsubic, addik, rsubik, addikc, rsubikc, mul,
addi, rsubi, addic, rsubic, addik, rsubik, addikc, rsubikc, mul,
mulh, mulhu, mulhsu,swapb,swaph,
idiv, idivu, bsll, bsra, bsrl, get, put, nget, nput, cget, cput,
ncget, ncput, muli, bslli, bsrai, bsrli, mului,
/* 'or/and/xor' are C++ keywords. */
microblaze_or, microblaze_and, microblaze_xor,
andn, pcmpbf, pcmpbc, pcmpeq, pcmpne, sra, src, srl, sext8, sext16,
andn, pcmpbf, pcmpbc, pcmpeq, pcmpne, sra, src, srl, sext8, sext16,
wic, wdc, wdcclear, wdcflush, mts, mfs, mbar, br, brd,
brld, bra, brad, brald, microblaze_brk, beq, beqd, bne, bned, blt,
bltd, ble, bled, bgt, bgtd, bge, bged, ori, andi, xori, andni,
imm, rtsd, rtid, rtbd, rted, bri, brid, brlid, brai, braid, bralid,
brki, beqi, beqid, bnei, bneid, blti, bltid, blei, bleid, bgti,
bgtid, bgei, bgeid, lbu, lbur, lhu, lhur, lw, lwr, lwx, sb, sbr, sh,
bgtid, bgei, bgeid, lbu, lbur, lhu, lhur, lw, lwr, lwx, sb, sbr, sh,
shr, sw, swr, swx, lbui, lhui, lwi,
sbi, shi, swi, msrset, msrclr, tuqula, fadd, frsub, fmul, fdiv,
fcmp_lt, fcmp_eq, fcmp_le, fcmp_gt, fcmp_ne, fcmp_ge, fcmp_un, flt,
fint, fsqrt,
sbi, shi, swi, msrset, msrclr, tuqula, fadd, frsub, fmul, fdiv,
fcmp_lt, fcmp_eq, fcmp_le, fcmp_gt, fcmp_ne, fcmp_ge, fcmp_un, flt,
fint, fsqrt,
tget, tcget, tnget, tncget, tput, tcput, tnput, tncput,
eget, ecget, neget, necget, eput, ecput, neput, necput,
teget, tecget, tneget, tnecget, teput, tecput, tneput, tnecput,
@ -123,7 +123,7 @@ enum microblaze_instr_type
/* Assembler Register - Used in Delay Slot Optimization. */
#define REG_AS 18
#define REG_ZERO 0
#define RD_LOW 21 /* Low bit for RD. */
#define RA_LOW 16 /* Low bit for RA. */
#define RB_LOW 11 /* Low bit for RB. */

6
opcodes/mips-dis.c
View File

@ -875,8 +875,8 @@ parse_mips_dis_option (const char *option, unsigned int len)
mips_ase |= ASE_XPA;
return;
}
/* Look for the = that delimits the end of the option name. */
for (i = 0; i < len; i++)
if (option[i] == '=')
@ -1709,7 +1709,7 @@ print_insn_mips (bfd_vma memaddr,
{
for (; op < &mips_opcodes[NUMOPCODES]; op++)
{
if (op->pinfo != INSN_MACRO
if (op->pinfo != INSN_MACRO
&& !(no_aliases && (op->pinfo2 & INSN2_ALIAS))
&& (word & op->mask) == op->match)
{

8
opcodes/mips-opc.c
View File

@ -404,7 +404,7 @@ decode_mips_operand (const char *p)
Because of the lookup algorithm used, entries with the same opcode
name must be contiguous.
Many instructions are short hand for other instructions (i.e., The
jal <register> instruction is short for jalr <register>). */
@ -2062,8 +2062,8 @@ const struct mips_opcode mips_builtin_opcodes[] =
{"zcb", "(b)", 0x7000071f, 0xfc1fffff, RD_1|SM, 0, IOCT2, 0, 0 },
{"zcbt", "(b)", 0x7000075f, 0xfc1fffff, RD_1|SM, 0, IOCT2, 0, 0 },
/* Coprocessor 0 move instructions cfc0 and ctc0 conflict with the
mfhc0 and mthc0 XPA instructions, so they have been placed here
/* Coprocessor 0 move instructions cfc0 and ctc0 conflict with the
mfhc0 and mthc0 XPA instructions, so they have been placed here
to allow the XPA instructions to take precedence. */
{"ctc0", "t,G", 0x40c00000, 0xffe007ff, RD_1|WR_CC|CM, 0, I1, 0, IOCT|IOCTP|IOCT2 },
{"cfc0", "t,G", 0x40400000, 0xffe007ff, WR_1|RD_C0|LC, 0, I1, 0, IOCT|IOCTP|IOCT2 },
@ -2110,7 +2110,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
{"qmtc2", "t,+6", 0x48a00000, 0xffe007ff, RD_1|WR_C2, 0, EE, 0, 0 },
{"qmtc2.i", "t,+6", 0x48a00001, 0xffe007ff, RD_1|WR_C2, 0, EE, 0, 0 },
{"qmtc2.ni", "t,+6", 0x48a00000, 0xffe007ff, RD_1|WR_C2, 0, EE, 0, 0 },
/* Coprocessor 3 move/branch operations overlap with MIPS IV COP1X
/* Coprocessor 3 move/branch operations overlap with MIPS IV COP1X
instructions, so they are here for the latters to take precedence. */
{"bc3f", "p", 0x4d000000, 0xffff0000, RD_CC|CBD, 0, I1, 0, IOCT|IOCTP|IOCT2|EE|I37 },
{"bc3fl", "p", 0x4d020000, 0xffff0000, RD_CC|CBL, 0, I2|T3, 0, IOCT|IOCTP|IOCT2|EE|I37 },

2
opcodes/moxie-dis.c
View File

@ -210,7 +210,7 @@ print_insn_moxie (bfd_vma addr, struct disassemble_info * info)
{
case MOXIE_F3_PCREL:
fpr (stream, "%s\t", opcode->name);
info->print_address_func ((bfd_vma) (addr + INST2OFFSET(iword) + 2),
info->print_address_func ((bfd_vma) (addr + INST2OFFSET(iword) + 2),
info);
break;
case MOXIE_BAD:

86
opcodes/msp430-decode.c
View File

@ -375,7 +375,7 @@ msp430_decode_opcode (unsigned long pc,
ID (MSO_mov); SM (srcr, 0); DR (dstr);
msp430->size = 20;
msp430->ofs_430x = 1;
}
break;
case 0x10:
@ -399,7 +399,7 @@ msp430_decode_opcode (unsigned long pc,
ID (MSO_mov); SI (srcr); DR (dstr);
msp430->size = 20;
msp430->ofs_430x = 1;
}
break;
case 0x20:
@ -423,7 +423,7 @@ msp430_decode_opcode (unsigned long pc,
ID (MSO_mov); SA ((srcr << 16) + IMMU(2)); DR (dstr);
msp430->size = 20;
msp430->ofs_430x = 1;
}
break;
case 0x30:
@ -447,7 +447,7 @@ msp430_decode_opcode (unsigned long pc,
ID (MSO_mov); SM (srcr, IMMS(2)); DR (dstr);
msp430->size = 20;
msp430->ofs_430x = 1;
}
break;
case 0x40:
@ -477,7 +477,7 @@ msp430_decode_opcode (unsigned long pc,
msp430->size = w ? 16 : 20;
msp430->ofs_430x = 1;
F_0NZC;
}
break;
case 0x60:
@ -501,7 +501,7 @@ msp430_decode_opcode (unsigned long pc,
ID (MSO_mov); SR (srcr); DA ((dstr << 16) + IMMU(2));
msp430->size = 20;
msp430->ofs_430x = 1;
}
break;
case 0x70:
@ -525,7 +525,7 @@ msp430_decode_opcode (unsigned long pc,
ID (MSO_mov); SR (srcr); DM (dstr, IMMS(2));
msp430->size = 20;
msp430->ofs_430x = 1;
}
break;
case 0x80:
@ -549,7 +549,7 @@ msp430_decode_opcode (unsigned long pc,
ID (MSO_mov); SC ((srcr << 16) + IMMU(2)); DR (dstr);
msp430->size = 20;
msp430->ofs_430x = 1;
}
break;
case 0x90:
@ -574,7 +574,7 @@ msp430_decode_opcode (unsigned long pc,
msp430->size = 20;
msp430->ofs_430x = 1;
F_VNZC;
}
break;
case 0xa0:
@ -599,7 +599,7 @@ msp430_decode_opcode (unsigned long pc,
msp430->size = 20;
msp430->ofs_430x = 1;
F_VNZC;
}
break;
case 0xb0:
@ -624,7 +624,7 @@ msp430_decode_opcode (unsigned long pc,
msp430->size = 20;
msp430->ofs_430x = 1;
F_VNZC;
}
break;
case 0xc0:
@ -648,7 +648,7 @@ msp430_decode_opcode (unsigned long pc,
ID (MSO_mov); SR (srcr); DR (dstr);
msp430->size = 20;
msp430->ofs_430x = 1;
}
break;
case 0xd0:
@ -673,7 +673,7 @@ msp430_decode_opcode (unsigned long pc,
msp430->size = 20;
msp430->ofs_430x = 1;
F_VNZC;
}
break;
case 0xe0:
@ -698,7 +698,7 @@ msp430_decode_opcode (unsigned long pc,
msp430->size = 20;
msp430->ofs_430x = 1;
F_VNZC;
}
break;
case 0xf0:
@ -723,7 +723,7 @@ msp430_decode_opcode (unsigned long pc,
msp430->size = 20;
msp430->ofs_430x = 1;
F_VNZC;
}
break;
}
@ -771,7 +771,7 @@ msp430_decode_opcode (unsigned long pc,
msp430->size = w ? 16 : 20;
msp430->ofs_430x = 1;
F_0NZC;
}
break;
case 0x60:
@ -849,7 +849,7 @@ msp430_decode_opcode (unsigned long pc,
msp430->size = w ? 16 : 20;
msp430->ofs_430x = 1;
F_0NZC;
}
break;
case 0x60:
@ -927,7 +927,7 @@ msp430_decode_opcode (unsigned long pc,
msp430->size = w ? 16 : 20;
msp430->ofs_430x = 1;
F_0NZC;
}
break;
case 0x60:
@ -1617,20 +1617,20 @@ msp430_decode_opcode (unsigned long pc,
}
SYNTAX("%S%b %1");
#line 394 "msp430-decode.opc"
ID (sopc_to_id (so,c)); ASX (dreg, ad, srxt_bits); ABW (al_bit, b);
if (ad == 0)
REPZC (srxt_bits, dsxt_bits);
/* The helper functions encode for source, but it's
both source and dest, with a few documented exceptions. */
msp430->op[0] = msp430->op[1];
/* RETI ignores the operand. */
if (msp430->id == MSO_reti)
msp430->syntax = "%S";
switch (msp430->id)
{
case MSO_rrc: F_VNZC; break;
@ -1642,7 +1642,7 @@ msp430_decode_opcode (unsigned long pc,
case MSO_reti: F_VNZC; break;
default: break;
}
/* 20xx 0010 0000 ---- ----
3cxx 0011 1100 ---- ----
001j mp-- ---- ----. */
@ -1686,7 +1686,7 @@ msp430_decode_opcode (unsigned long pc,
ID (MSO_reti);
msp430->size = 20;
msp430->ofs_430x = 1;
}
break;
case 0x01:
@ -1917,7 +1917,7 @@ msp430_decode_opcode (unsigned long pc,
ID (MSO_call); AS (dstr, as);
msp430->size = 20;
msp430->ofs_430x = 1;
}
break;
case 0x80:
@ -1952,7 +1952,7 @@ msp430_decode_opcode (unsigned long pc,
ID (MSO_call); SA (IMMU(2) | (extb << 16));
msp430->size = 20;
msp430->ofs_430x = 1;
}
break;
case 0x90:
@ -1990,7 +1990,7 @@ msp430_decode_opcode (unsigned long pc,
ID (MSO_call); SA (pc + raddr + msp430->n_bytes);
msp430->size = 20;
msp430->ofs_430x = 1;
}
break;
case 0xb0:
@ -2025,7 +2025,7 @@ msp430_decode_opcode (unsigned long pc,
ID (MSO_call); SC (IMMU(2) | (extb << 16));
msp430->size = 20;
msp430->ofs_430x = 1;
}
break;
}
@ -2059,7 +2059,7 @@ msp430_decode_opcode (unsigned long pc,
msp430->size = w ? 16 : 20;
msp430->repeats = bits;
msp430->ofs_430x = 1;
}
break;
}
@ -2102,7 +2102,7 @@ msp430_decode_opcode (unsigned long pc,
msp430->size = w ? 16 : 20;
msp430->repeats = bits;
msp430->ofs_430x = 1;
}
break;
}
@ -2144,25 +2144,25 @@ msp430_decode_opcode (unsigned long pc,
}
SYNTAX("430x");
#line 350 "msp430-decode.opc"
al_bit = l;
srxt_bits = srx * 2 + t;
dsxt_bits = dsxt;
op = op_buf + lds.op_ptr;
msp430->ofs_430x = 1;
goto post_extension_word;
/* double-op insns:
opcode:4 sreg:4 Ad:1 BW:1 As:2 Dreg:4
single-op insn:
opcode:9 BW:1 Ad:2 DSreg:4
jumps:
opcode:3 Cond:3 pcrel:10. */
/* Double-Operand "opcode" fields. */
}
break;
default: UNSUPPORTED(); break;
@ -2263,7 +2263,7 @@ msp430_decode_opcode (unsigned long pc,
}
SYNTAX("%J %1");
#line 424 "msp430-decode.opc"
raddr = (aa << 9) | (addrlsbs << 1);
if (raddr & 0x400)
raddr = raddr - 0x800;
@ -2273,9 +2273,9 @@ msp430_decode_opcode (unsigned long pc,
data at that address. */
ID (MSO_jmp); SC (pc + raddr + msp430->n_bytes);
msp430->cond = jmp;
/* Extended instructions. */
}
break;
}
@ -2593,11 +2593,11 @@ msp430_decode_opcode (unsigned long pc,
}
SYNTAX("%D%b %1,%0");
#line 371 "msp430-decode.opc"
ID (dopc_to_id (dopc)); ASX (sreg, as, srxt_bits); ADX (dreg, a, dsxt_bits); ABW (al_bit, b);
if (a == 0 && as == 0)
REPZC (srxt_bits, dsxt_bits);
switch (msp430->id)
{
case MSO_mov: F_____; break;
@ -2614,7 +2614,7 @@ msp430_decode_opcode (unsigned long pc,
case MSO_and: F_0NZC; break;
default: break;
}
}
break;
}

18
opcodes/msp430-dis.c
View File

@ -2,7 +2,7 @@
Copyright (C) 2002-2015 Free Software Foundation, Inc.
Contributed by Dmitry Diky <diwil@mail.ru>
This file is part of the GNU opcodes library.
This library is free software; you can redistribute it and/or modify
@ -397,7 +397,7 @@ msp430_doubleoperand (disassemble_info *info,
Rm Register,
x(Rm) Indexed,
0xXXXX Relative,
&0xXXXX Absolute
&0xXXXX Absolute
emulated_ins dst
basic_ins dst, dst. */
@ -936,7 +936,7 @@ print_insn_msp430 (bfd_vma addr, disassemble_info *info)
sprintf (comm1, "20-bit words");
bc =".a";
}
cycles = 2; /*FIXME*/
cmd_len = 2;
break;
@ -984,7 +984,7 @@ print_insn_msp430 (bfd_vma addr, disassemble_info *info)
if (strcmp (opcode->name, "bra") != 0)
sprintf (op2, "r%d", reg);
break;
case 1: /* MOVA @Rsrc+, Rdst */
cmd_len = 2;
if (strcmp (opcode->name, "reta") != 0)
@ -994,7 +994,7 @@ print_insn_msp430 (bfd_vma addr, disassemble_info *info)
sprintf (op2, "r%d", reg);
}
break;
case 2: /* MOVA &abs20, Rdst */
cmd_len = 4;
n <<= 16;
@ -1005,7 +1005,7 @@ print_insn_msp430 (bfd_vma addr, disassemble_info *info)
if (strcmp (opcode->name, "bra") != 0)
sprintf (op2, "r%d", reg);
break;
case 3: /* MOVA x(Rsrc), Rdst */
cmd_len = 4;
if (strcmp (opcode->name, "bra") != 0)
@ -1051,7 +1051,7 @@ print_insn_msp430 (bfd_vma addr, disassemble_info *info)
sprintf (comm2, "0x%05x", n);
}
break;
case 8: /* MOVA #imm20, Rdst */
cmd_len = 4;
n <<= 16;
@ -1064,7 +1064,7 @@ print_insn_msp430 (bfd_vma addr, disassemble_info *info)
if (strcmp (opcode->name, "bra") != 0)
sprintf (op2, "r%d", reg);
break;
case 12: /* MOVA Rsrc, Rdst */
cmd_len = 2;
sprintf (op1, "r%d", n);
@ -1110,7 +1110,7 @@ print_insn_msp430 (bfd_vma addr, disassemble_info *info)
sprintf (comm2, _("Reserved use of A/L and B/W bits detected"));
}
}
break;
case 1:
cmd_len +=

56
opcodes/mt-asm.c
View File

@ -52,7 +52,7 @@ static const char * parse_insn_normal
/* Range checking for signed numbers. Returns 0 if acceptable
and 1 if the value is out of bounds for a signed quantity. */
static int
static int
signed_out_of_bounds (long val)
{
if ((val < -32768) || (val > 32767))
@ -72,7 +72,7 @@ parse_loopsize (CGEN_CPU_DESC cd,
enum cgen_parse_operand_result result_type;
bfd_vma value;
/* Is it a control transfer instructions? */
/* Is it a control transfer instructions? */
if (opindex == (CGEN_OPERAND_TYPE) MT_OPERAND_LOOPSIZE)
{
code = BFD_RELOC_MT_PCINSN8;
@ -97,7 +97,7 @@ parse_imm16 (CGEN_CPU_DESC cd,
bfd_reloc_code_real_type code = BFD_RELOC_NONE;
bfd_vma value;
/* Is it a control transfer instructions? */
/* Is it a control transfer instructions? */
if (opindex == (CGEN_OPERAND_TYPE) MT_OPERAND_IMM16O)
{
code = BFD_RELOC_16_PCREL;
@ -144,7 +144,7 @@ parse_imm16 (CGEN_CPU_DESC cd,
value = (value >> 16) & 0xFFFF;
else if (code == BFD_RELOC_LO16)
value = value & 0xFFFF;
else
else
errmsg = _("Biiiig Trouble in parse_imm16!");
break;
@ -173,27 +173,27 @@ parse_imm16 (CGEN_CPU_DESC cd,
if (parse_signed)
{
/* Parse as as signed integer. */
errmsg = cgen_parse_signed_integer (cd, strp, opindex, valuep);
if (errmsg == NULL)
if (errmsg == NULL)
{
#if 0
/* Manual range checking is needed for the signed case. */
if (*valuep & 0x8000)
value = 0xffff0000 | *valuep;
else
else
value = *valuep;
if (signed_out_of_bounds (value))
errmsg = _("Operand out of range. Must be between -32768 and 32767.");
/* Truncate to 16 bits. This is necessary
because cgen will have sign extended *valuep. */
*valuep &= 0xFFFF;
*valuep &= 0xFFFF;
#endif
}
}
else
else
{
/* MT_OPERAND_IMM16Z. Parse as an unsigned integer. */
errmsg = cgen_parse_unsigned_integer (cd, strp, opindex, (unsigned long *) valuep);
@ -598,7 +598,7 @@ mt_cgen_parse_operand (CGEN_CPU_DESC cd,
return errmsg;
}
cgen_parse_fn * const mt_cgen_parse_handlers[] =
cgen_parse_fn * const mt_cgen_parse_handlers[] =
{
parse_insn_normal,
};
@ -628,9 +628,9 @@ CGEN_ASM_INIT_HOOK
Returns NULL for success, an error message for failure. */
char *
char *
mt_cgen_build_insn_regex (CGEN_INSN *insn)
{
{
CGEN_OPCODE *opc = (CGEN_OPCODE *) CGEN_INSN_OPCODE (insn);
const char *mnem = CGEN_INSN_MNEMONIC (insn);
char rxbuf[CGEN_MAX_RX_ELEMENTS];
@ -669,18 +669,18 @@ mt_cgen_build_insn_regex (CGEN_INSN *insn)
/* Copy any remaining literals from the syntax string into the rx. */
for(; * syn != 0 && rx <= rxbuf + (CGEN_MAX_RX_ELEMENTS - 7 - 4); ++syn)
{
if (CGEN_SYNTAX_CHAR_P (* syn))
if (CGEN_SYNTAX_CHAR_P (* syn))
{
char c = CGEN_SYNTAX_CHAR (* syn);
switch (c)
switch (c)
{
/* Escape any regex metacharacters in the syntax. */
case '.': case '[': case '\\':
case '*': case '^': case '$':
case '.': case '[': case '\\':
case '*': case '^': case '$':
#ifdef CGEN_ESCAPE_EXTENDED_REGEX
case '?': case '{': case '}':
case '?': case '{': case '}':
case '(': case ')': case '*':
case '|': case '+': case ']':
#endif
@ -710,20 +710,20 @@ mt_cgen_build_insn_regex (CGEN_INSN *insn)
}
/* Trailing whitespace ok. */
* rx++ = '[';
* rx++ = ' ';
* rx++ = '\t';
* rx++ = ']';
* rx++ = '*';
* rx++ = '[';
* rx++ = ' ';
* rx++ = '\t';
* rx++ = ']';
* rx++ = '*';
/* But anchor it after that. */
* rx++ = '$';
* rx++ = '$';
* rx = '\0';
CGEN_INSN_RX (insn) = xmalloc (sizeof (regex_t));
reg_err = regcomp ((regex_t *) CGEN_INSN_RX (insn), rxbuf, REG_NOSUB);
if (reg_err == 0)
if (reg_err == 0)
return NULL;
else
{
@ -922,7 +922,7 @@ mt_cgen_assemble_insn (CGEN_CPU_DESC cd,
const CGEN_INSN *insn = ilist->insn;
recognized_mnemonic = 1;
#ifdef CGEN_VALIDATE_INSN_SUPPORTED
#ifdef CGEN_VALIDATE_INSN_SUPPORTED
/* Not usually needed as unsupported opcodes
shouldn't be in the hash lists. */
/* Is this insn supported by the selected cpu? */
@ -982,7 +982,7 @@ mt_cgen_assemble_insn (CGEN_CPU_DESC cd,
if (strlen (start) > 50)
/* xgettext:c-format */
sprintf (errbuf, "%s `%.50s...'", tmp_errmsg, start);
else
else
/* xgettext:c-format */
sprintf (errbuf, "%s `%.50s'", tmp_errmsg, start);
}
@ -991,11 +991,11 @@ mt_cgen_assemble_insn (CGEN_CPU_DESC cd,
if (strlen (start) > 50)
/* xgettext:c-format */
sprintf (errbuf, _("bad instruction `%.50s...'"), start);
else
else
/* xgettext:c-format */
sprintf (errbuf, _("bad instruction `%.50s'"), start);
}
*errmsg = errbuf;
return NULL;
}

114
opcodes/mt-desc.c
View File

@ -310,223 +310,223 @@ const CGEN_OPERAND mt_cgen_operand_table[] =
{
/* pc: program counter */
{ "pc", MT_OPERAND_PC, HW_H_PC, 0, 0,
{ 0, { (const PTR) &mt_cgen_ifld_table[MT_F_NIL] } },
{ 0, { (const PTR) &mt_cgen_ifld_table[MT_F_NIL] } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* frsr1: register */
{ "frsr1", MT_OPERAND_FRSR1, HW_H_SPR, 23, 4,
{ 0, { (const PTR) &mt_cgen_ifld_table[MT_F_SR1] } },
{ 0, { (const PTR) &mt_cgen_ifld_table[MT_F_SR1] } },
{ 0|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } } },
/* frsr2: register */
{ "frsr2", MT_OPERAND_FRSR2, HW_H_SPR, 19, 4,
{ 0, { (const PTR) &mt_cgen_ifld_table[MT_F_SR2] } },
{ 0, { (const PTR) &mt_cgen_ifld_table[MT_F_SR2] } },
{ 0|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } } },
/* frdr: register */
{ "frdr", MT_OPERAND_FRDR, HW_H_SPR, 19, 4,
{ 0, { (const PTR) &mt_cgen_ifld_table[MT_F_DR] } },
{ 0, { (const PTR) &mt_cgen_ifld_table[MT_F_DR] } },
{ 0|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } } },
/* frdrrr: register */
{ "frdrrr", MT_OPERAND_FRDRRR, HW_H_SPR, 15, 4,
{ 0, { (const PTR) &mt_cgen_ifld_table[MT_F_DRRR] } },
{ 0, { (const PTR) &mt_cgen_ifld_table[MT_F_DRRR] } },
{ 0|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } } },
/* imm16: immediate value - sign extd */
{ "imm16", MT_OPERAND_IMM16, HW_H_SINT, 15, 16,
{ 0, { (const PTR) &mt_cgen_ifld_table[MT_F_IMM16S] } },
{ 0, { (const PTR) &mt_cgen_ifld_table[MT_F_IMM16S] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* imm16z: immediate value - zero extd */
{ "imm16z", MT_OPERAND_IMM16Z, HW_H_UINT, 15, 16,
{ 0, { (const PTR) &mt_cgen_ifld_table[MT_F_IMM16U] } },
{ 0, { (const PTR) &mt_cgen_ifld_table[MT_F_IMM16U] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* imm16o: immediate value */
{ "imm16o", MT_OPERAND_IMM16O, HW_H_UINT, 15, 16,
{ 0, { (const PTR) &mt_cgen_ifld_table[MT_F_IMM16S] } },
{ 0, { (const PTR) &mt_cgen_ifld_table[MT_F_IMM16S] } },
{ 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } } },
/* rc: rc */
{ "rc", MT_OPERAND_RC, HW_H_UINT, 15, 1,
{ 0, { (const PTR) &mt_cgen_ifld_table[MT_F_RC] } },
{ 0, { (const PTR) &mt_cgen_ifld_table[MT_F_RC] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* rcnum: rcnum */
{ "rcnum", MT_OPERAND_RCNUM, HW_H_UINT, 14, 3,
{ 0, { (const PTR) &mt_cgen_ifld_table[MT_F_RCNUM] } },
{ 0, { (const PTR) &mt_cgen_ifld_table[MT_F_RCNUM] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* contnum: context number */
{ "contnum", MT_OPERAND_CONTNUM, HW_H_UINT, 8, 9,
{ 0, { (const PTR) &mt_cgen_ifld_table[MT_F_CONTNUM] } },
{ 0, { (const PTR) &mt_cgen_ifld_table[MT_F_CONTNUM] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* rbbc: omega network configuration */
{ "rbbc", MT_OPERAND_RBBC, HW_H_UINT, 25, 2,
{ 0, { (const PTR) &mt_cgen_ifld_table[MT_F_RBBC] } },
{ 0, { (const PTR) &mt_cgen_ifld_table[MT_F_RBBC] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* colnum: column number */
{ "colnum", MT_OPERAND_COLNUM, HW_H_UINT, 18, 3,
{ 0, { (const PTR) &mt_cgen_ifld_table[MT_F_COLNUM] } },
{ 0, { (const PTR) &mt_cgen_ifld_table[MT_F_COLNUM] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* rownum: row number */
{ "rownum", MT_OPERAND_ROWNUM, HW_H_UINT, 14, 3,
{ 0, { (const PTR) &mt_cgen_ifld_table[MT_F_ROWNUM] } },
{ 0, { (const PTR) &mt_cgen_ifld_table[MT_F_ROWNUM] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* rownum1: row number */
{ "rownum1", MT_OPERAND_ROWNUM1, HW_H_UINT, 12, 3,
{ 0, { (const PTR) &mt_cgen_ifld_table[MT_F_ROWNUM1] } },
{ 0, { (const PTR) &mt_cgen_ifld_table[MT_F_ROWNUM1] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* rownum2: row number */
{ "rownum2", MT_OPERAND_ROWNUM2, HW_H_UINT, 9, 3,
{ 0, { (const PTR) &mt_cgen_ifld_table[MT_F_ROWNUM2] } },
{ 0, { (const PTR) &mt_cgen_ifld_table[MT_F_ROWNUM2] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* rc1: rc1 */
{ "rc1", MT_OPERAND_RC1, HW_H_UINT, 11, 1,
{ 0, { (const PTR) &mt_cgen_ifld_table[MT_F_RC1] } },
{ 0, { (const PTR) &mt_cgen_ifld_table[MT_F_RC1] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* rc2: rc2 */
{ "rc2", MT_OPERAND_RC2, HW_H_UINT, 6, 1,
{ 0, { (const PTR) &mt_cgen_ifld_table[MT_F_RC2] } },
{ 0, { (const PTR) &mt_cgen_ifld_table[MT_F_RC2] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* cbrb: data-bus orientation */
{ "cbrb", MT_OPERAND_CBRB, HW_H_UINT, 10, 1,
{ 0, { (const PTR) &mt_cgen_ifld_table[MT_F_CBRB] } },
{ 0, { (const PTR) &mt_cgen_ifld_table[MT_F_CBRB] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* cell: cell */
{ "cell", MT_OPERAND_CELL, HW_H_UINT, 9, 3,
{ 0, { (const PTR) &mt_cgen_ifld_table[MT_F_CELL] } },
{ 0, { (const PTR) &mt_cgen_ifld_table[MT_F_CELL] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* dup: dup */
{ "dup", MT_OPERAND_DUP, HW_H_UINT, 6, 1,
{ 0, { (const PTR) &mt_cgen_ifld_table[MT_F_DUP] } },
{ 0, { (const PTR) &mt_cgen_ifld_table[MT_F_DUP] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* ctxdisp: context displacement */
{ "ctxdisp", MT_OPERAND_CTXDISP, HW_H_UINT, 5, 6,
{ 0, { (const PTR) &mt_cgen_ifld_table[MT_F_CTXDISP] } },
{ 0, { (const PTR) &mt_cgen_ifld_table[MT_F_CTXDISP] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* fbdisp: frame buffer displacement */
{ "fbdisp", MT_OPERAND_FBDISP, HW_H_UINT, 15, 6,
{ 0, { (const PTR) &mt_cgen_ifld_table[MT_F_FBDISP] } },
{ 0, { (const PTR) &mt_cgen_ifld_table[MT_F_FBDISP] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* type: type */
{ "type", MT_OPERAND_TYPE, HW_H_UINT, 21, 2,
{ 0, { (const PTR) &mt_cgen_ifld_table[MT_F_TYPE] } },
{ 0, { (const PTR) &mt_cgen_ifld_table[MT_F_TYPE] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* mask: mask */
{ "mask", MT_OPERAND_MASK, HW_H_UINT, 25, 16,
{ 0, { (const PTR) &mt_cgen_ifld_table[MT_F_MASK] } },
{ 0, { (const PTR) &mt_cgen_ifld_table[MT_F_MASK] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* bankaddr: bank address */
{ "bankaddr", MT_OPERAND_BANKADDR, HW_H_UINT, 25, 13,
{ 0, { (const PTR) &mt_cgen_ifld_table[MT_F_BANKADDR] } },
{ 0, { (const PTR) &mt_cgen_ifld_table[MT_F_BANKADDR] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* incamt: increment amount */
{ "incamt", MT_OPERAND_INCAMT, HW_H_UINT, 19, 8,
{ 0, { (const PTR) &mt_cgen_ifld_table[MT_F_INCAMT] } },
{ 0, { (const PTR) &mt_cgen_ifld_table[MT_F_INCAMT] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* xmode: xmode */
{ "xmode", MT_OPERAND_XMODE, HW_H_UINT, 23, 1,
{ 0, { (const PTR) &mt_cgen_ifld_table[MT_F_XMODE] } },
{ 0, { (const PTR) &mt_cgen_ifld_table[MT_F_XMODE] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* mask1: mask1 */
{ "mask1", MT_OPERAND_MASK1, HW_H_UINT, 22, 3,
{ 0, { (const PTR) &mt_cgen_ifld_table[MT_F_MASK1] } },
{ 0, { (const PTR) &mt_cgen_ifld_table[MT_F_MASK1] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* ball: b_all */
{ "ball", MT_OPERAND_BALL, HW_H_UINT, 19, 1,
{ 0, { (const PTR) &mt_cgen_ifld_table[MT_F_BALL] } },
{ 0, { (const PTR) &mt_cgen_ifld_table[MT_F_BALL] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* brc: b_r_c */
{ "brc", MT_OPERAND_BRC, HW_H_UINT, 18, 3,
{ 0, { (const PTR) &mt_cgen_ifld_table[MT_F_BRC] } },
{ 0, { (const PTR) &mt_cgen_ifld_table[MT_F_BRC] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* rda: rd */
{ "rda", MT_OPERAND_RDA, HW_H_UINT, 25, 1,
{ 0, { (const PTR) &mt_cgen_ifld_table[MT_F_RDA] } },
{ 0, { (const PTR) &mt_cgen_ifld_table[MT_F_RDA] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* wr: wr */
{ "wr", MT_OPERAND_WR, HW_H_UINT, 24, 1,
{ 0, { (const PTR) &mt_cgen_ifld_table[MT_F_WR] } },
{ 0, { (const PTR) &mt_cgen_ifld_table[MT_F_WR] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* ball2: b_all2 */
{ "ball2", MT_OPERAND_BALL2, HW_H_UINT, 15, 1,
{ 0, { (const PTR) &mt_cgen_ifld_table[MT_F_BALL2] } },
{ 0, { (const PTR) &mt_cgen_ifld_table[MT_F_BALL2] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* brc2: b_r_c2 */
{ "brc2", MT_OPERAND_BRC2, HW_H_UINT, 14, 3,
{ 0, { (const PTR) &mt_cgen_ifld_table[MT_F_BRC2] } },
{ 0, { (const PTR) &mt_cgen_ifld_table[MT_F_BRC2] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* perm: perm */
{ "perm", MT_OPERAND_PERM, HW_H_UINT, 25, 2,
{ 0, { (const PTR) &mt_cgen_ifld_table[MT_F_PERM] } },
{ 0, { (const PTR) &mt_cgen_ifld_table[MT_F_PERM] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* a23: a23 */
{ "a23", MT_OPERAND_A23, HW_H_UINT, 23, 1,
{ 0, { (const PTR) &mt_cgen_ifld_table[MT_F_A23] } },
{ 0, { (const PTR) &mt_cgen_ifld_table[MT_F_A23] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* cr: c-r */
{ "cr", MT_OPERAND_CR, HW_H_UINT, 22, 3,
{ 0, { (const PTR) &mt_cgen_ifld_table[MT_F_CR] } },
{ 0, { (const PTR) &mt_cgen_ifld_table[MT_F_CR] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* cbs: cbs */
{ "cbs", MT_OPERAND_CBS, HW_H_UINT, 19, 2,
{ 0, { (const PTR) &mt_cgen_ifld_table[MT_F_CBS] } },
{ 0, { (const PTR) &mt_cgen_ifld_table[MT_F_CBS] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* incr: incr */
{ "incr", MT_OPERAND_INCR, HW_H_UINT, 17, 6,
{ 0, { (const PTR) &mt_cgen_ifld_table[MT_F_INCR] } },
{ 0, { (const PTR) &mt_cgen_ifld_table[MT_F_INCR] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* length: length */
{ "length", MT_OPERAND_LENGTH, HW_H_UINT, 15, 3,
{ 0, { (const PTR) &mt_cgen_ifld_table[MT_F_LENGTH] } },
{ 0, { (const PTR) &mt_cgen_ifld_table[MT_F_LENGTH] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* cbx: cbx */
{ "cbx", MT_OPERAND_CBX, HW_H_UINT, 14, 3,
{ 0, { (const PTR) &mt_cgen_ifld_table[MT_F_CBX] } },
{ 0, { (const PTR) &mt_cgen_ifld_table[MT_F_CBX] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* ccb: ccb */
{ "ccb", MT_OPERAND_CCB, HW_H_UINT, 11, 1,
{ 0, { (const PTR) &mt_cgen_ifld_table[MT_F_CCB] } },
{ 0, { (const PTR) &mt_cgen_ifld_table[MT_F_CCB] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* cdb: cdb */
{ "cdb", MT_OPERAND_CDB, HW_H_UINT, 10, 1,
{ 0, { (const PTR) &mt_cgen_ifld_table[MT_F_CDB] } },
{ 0, { (const PTR) &mt_cgen_ifld_table[MT_F_CDB] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* mode: mode */
{ "mode", MT_OPERAND_MODE, HW_H_UINT, 25, 2,
{ 0, { (const PTR) &mt_cgen_ifld_table[MT_F_MODE] } },
{ 0, { (const PTR) &mt_cgen_ifld_table[MT_F_MODE] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* id: i/d */
{ "id", MT_OPERAND_ID, HW_H_UINT, 14, 1,
{ 0, { (const PTR) &mt_cgen_ifld_table[MT_F_ID] } },
{ 0, { (const PTR) &mt_cgen_ifld_table[MT_F_ID] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* size: size */
{ "size", MT_OPERAND_SIZE, HW_H_UINT, 13, 14,
{ 0, { (const PTR) &mt_cgen_ifld_table[MT_F_SIZE] } },
{ 0, { (const PTR) &mt_cgen_ifld_table[MT_F_SIZE] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* fbincr: fb incr */
{ "fbincr", MT_OPERAND_FBINCR, HW_H_UINT, 23, 4,
{ 0, { (const PTR) &mt_cgen_ifld_table[MT_F_FBINCR] } },
{ 0, { (const PTR) &mt_cgen_ifld_table[MT_F_FBINCR] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* loopsize: immediate value */
{ "loopsize", MT_OPERAND_LOOPSIZE, HW_H_UINT, 7, 8,
{ 0, { (const PTR) &mt_cgen_ifld_table[MT_F_LOOPO] } },
{ 0, { (const PTR) &mt_cgen_ifld_table[MT_F_LOOPO] } },
{ 0|A(PCREL_ADDR), { { { (1<<MACH_MS2), 0 } } } } },
/* imm16l: immediate value */
{ "imm16l", MT_OPERAND_IMM16L, HW_H_UINT, 23, 16,
{ 0, { (const PTR) &mt_cgen_ifld_table[MT_F_IMM16L] } },
{ 0, { (const PTR) &mt_cgen_ifld_table[MT_F_IMM16L] } },
{ 0, { { { (1<<MACH_MS2), 0 } } } } },
/* rc3: rc3 */
{ "rc3", MT_OPERAND_RC3, HW_H_UINT, 7, 1,
{ 0, { (const PTR) &mt_cgen_ifld_table[MT_F_RC3] } },
{ 0, { (const PTR) &mt_cgen_ifld_table[MT_F_RC3] } },
{ 0, { { { (1<<MACH_MS2), 0 } } } } },
/* cb1sel: cb1sel */
{ "cb1sel", MT_OPERAND_CB1SEL, HW_H_UINT, 25, 3,
{ 0, { (const PTR) &mt_cgen_ifld_table[MT_F_CB1SEL] } },
{ 0, { (const PTR) &mt_cgen_ifld_table[MT_F_CB1SEL] } },
{ 0, { { { (1<<MACH_MS2), 0 } } } } },
/* cb2sel: cb2sel */
{ "cb2sel", MT_OPERAND_CB2SEL, HW_H_UINT, 22, 3,
{ 0, { (const PTR) &mt_cgen_ifld_table[MT_F_CB2SEL] } },
{ 0, { (const PTR) &mt_cgen_ifld_table[MT_F_CB2SEL] } },
{ 0, { { { (1<<MACH_MS2), 0 } } } } },
/* cb1incr: cb1incr */
{ "cb1incr", MT_OPERAND_CB1INCR, HW_H_SINT, 19, 6,
{ 0, { (const PTR) &mt_cgen_ifld_table[MT_F_CB1INCR] } },
{ 0, { (const PTR) &mt_cgen_ifld_table[MT_F_CB1INCR] } },
{ 0|A(SIGNED), { { { (1<<MACH_MS2), 0 } } } } },
/* cb2incr: cb2incr */
{ "cb2incr", MT_OPERAND_CB2INCR, HW_H_SINT, 13, 6,
{ 0, { (const PTR) &mt_cgen_ifld_table[MT_F_CB2INCR] } },
{ 0, { (const PTR) &mt_cgen_ifld_table[MT_F_CB2INCR] } },
{ 0|A(SIGNED), { { { (1<<MACH_MS2), 0 } } } } },
/* sentinel */
{ 0, 0, 0, 0, 0,
@ -1249,7 +1249,7 @@ mt_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...)
/* Default to not allowing signed overflow. */
cd->signed_overflow_ok_p = 0;
return (CGEN_CPU_DESC) cd;
}
@ -1289,7 +1289,7 @@ mt_cgen_cpu_close (CGEN_CPU_DESC cd)
for (i = 0; i < cd->insn_table.num_init_entries; ++i, ++insns)
if (CGEN_INSN_RX (insns))
regfree (CGEN_INSN_RX (insns));
}
}
if (cd->macro_insn_table.init_entries)
free ((CGEN_INSN *) cd->macro_insn_table.init_entries);

10
opcodes/mt-dis.c
View File

@ -292,7 +292,7 @@ mt_cgen_print_operand (CGEN_CPU_DESC cd,
}
}
cgen_print_fn * const mt_cgen_print_handlers[] =
cgen_print_fn * const mt_cgen_print_handlers[] =
{
print_insn_normal,
};
@ -482,7 +482,7 @@ print_insn (CGEN_CPU_DESC cd,
int length;
unsigned long insn_value_cropped;
#ifdef CGEN_VALIDATE_INSN_SUPPORTED
#ifdef CGEN_VALIDATE_INSN_SUPPORTED
/* Not needed as insn shouldn't be in hash lists if not supported. */
/* Supported by this cpu? */
if (! mt_cgen_insn_supported (cd, insn))
@ -500,7 +500,7 @@ print_insn (CGEN_CPU_DESC cd,
relevant part from the buffer. */
if ((unsigned) (CGEN_INSN_BITSIZE (insn) / 8) < buflen &&
(unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long))
insn_value_cropped = bfd_get_bits (buf, CGEN_INSN_BITSIZE (insn),
insn_value_cropped = bfd_get_bits (buf, CGEN_INSN_BITSIZE (insn),
info->endian == BFD_ENDIAN_BIG);
else
insn_value_cropped = insn_value;
@ -619,7 +619,7 @@ print_insn_mt (bfd_vma pc, disassemble_info *info)
arch = info->arch;
if (arch == bfd_arch_unknown)
arch = CGEN_BFD_ARCH;
/* There's no standard way to compute the machine or isa number
so we leave it to the target. */
#ifdef CGEN_COMPUTE_MACH
@ -660,7 +660,7 @@ print_insn_mt (bfd_vma pc, disassemble_info *info)
break;
}
}
}
}
/* If we haven't initialized yet, initialize the opcode table. */
if (! cd)

8
opcodes/mt-ibld.c
View File

@ -154,7 +154,7 @@ insert_normal (CGEN_CPU_DESC cd,
{
long minval = - (1L << (length - 1));
unsigned long maxval = mask;
if ((value > 0 && (unsigned long) value > maxval)
|| value < minval)
{
@ -192,7 +192,7 @@ insert_normal (CGEN_CPU_DESC cd,
{
long minval = - (1L << (length - 1));
long maxval = (1L << (length - 1)) - 1;
if (value < minval || value > maxval)
{
sprintf
@ -970,12 +970,12 @@ mt_cgen_extract_operand (CGEN_CPU_DESC cd,
return length;
}
cgen_insert_fn * const mt_cgen_insert_handlers[] =
cgen_insert_fn * const mt_cgen_insert_handlers[] =
{
insert_insn_normal,
};
cgen_extract_fn * const mt_cgen_extract_handlers[] =
cgen_extract_fn * const mt_cgen_extract_handlers[] =
{
extract_insn_normal,
};

2
opcodes/mt-opc.c
View File

@ -43,7 +43,7 @@ mt_cgen_insn_supported (CGEN_CPU_DESC cd, const CGEN_INSN *insn)
/* No mach attribute? Assume it's supported for all machs. */
if (machs == 0)
return 1;
return ((machs & cd->machs) != 0);
}

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