aarch64: Prefer register ranges & support wrapping
Until now, binutils has supported register ranges such
as { v0.4s - v3.4s } as an unofficial shorthand for
{ v0.4s, v1.4s, v2.4s, v3.4s }. The SME2 ISA embraces this form
and makes it the preferred disassembly. It also embraces wrapped
lists such as { z31.s - z2.s }, which is something that binutils
didn't previously allow.
The range form was already binutils's preferred disassembly for 3- and
4-register lists. This patch prefers it for 2-register lists too.
The patch also adds support for wrap-around.
This commit is contained in:
Richard Sandiford
parent
f5b57feac2
commit
4eede8c244
@ -1358,7 +1358,6 @@ parse_vector_reg_list (char **ccp, aarch64_reg_type type,
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int val, val_range;
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int in_range;
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int ret_val;
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int i;
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bool error = false;
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bool expect_index = false;
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unsigned int ptr_flags = PTR_IN_REGLIST;
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@ -1409,13 +1408,13 @@ parse_vector_reg_list (char **ccp, aarch64_reg_type type,
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if (in_range)
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{
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if (val < val_range)
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if (val == val_range)
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{
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set_first_syntax_error
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(_("invalid range in vector register list"));
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error = true;
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}
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val_range++;
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val_range = (val_range + 1) & 0x1f;
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}
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else
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{
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@ -1430,10 +1429,13 @@ parse_vector_reg_list (char **ccp, aarch64_reg_type type,
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}
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}
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if (! error)
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for (i = val_range; i <= val; i++)
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for (;;)
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{
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ret_val |= i << (5 * nb_regs);
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ret_val |= val_range << (5 * nb_regs);
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nb_regs++;
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if (val_range == val)
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break;
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val_range = (val_range + 1) & 0x1f;
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}
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in_range = 0;
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ptr_flags |= PTR_GOOD_MATCH;
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@ -242,12 +242,12 @@
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[^ :]+:[0-9]+: Error: the register list must have a stride of 1 at operand 2 -- `ext z0\.b,{z0\.b,z2\.b},#0'
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[^ :]+:[0-9]+: Error: operand mismatch -- `ext z0\.h,{z0\.b,z1\.b},#0'
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[^ :]+:[0-9]+: Info: did you mean this\?
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[^ :]+:[0-9]+: Info: ext z0\.b, {z0\.b, z1\.b}, #0
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[^ :]+:[0-9]+: Info: ext z0\.b, {z0\.b-z1\.b}, #0
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[^ :]+:[0-9]+: Error: type mismatch in vector register list at operand 2 -- `ext z0\.b,{z0\.h,z1\.b},#0'
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[^ :]+:[0-9]+: Error: type mismatch in vector register list at operand 2 -- `ext z0\.b,{z0\.b,z1\.h},#0'
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[^ :]+:[0-9]+: Error: operand mismatch -- `ext z0\.b,{z0\.h,z1\.h},#0'
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[^ :]+:[0-9]+: Info: did you mean this\?
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[^ :]+:[0-9]+: Info: ext z0\.b, {z0\.b, z1\.b}, #0
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[^ :]+:[0-9]+: Info: ext z0\.b, {z0\.b-z1\.b}, #0
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[^ :]+:[0-9]+: Error: expected a list of 2 registers at operand 2 -- `ext z0\.b,{z0\.b,z1\.b,z2\.b},#0'
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[^ :]+:[0-9]+: Error: expected a list of 2 registers at operand 2 -- `ext z0\.b,{z0\.b},#0'
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[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `ext z0\.b,z0\.b,#0'
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@ -1280,11 +1280,11 @@
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[^ :]+:[0-9]+: Error: the register list must have a stride of 1 at operand 3 -- `splice z0\.b,p0,{z0\.b,z2\.b}'
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[^ :]+:[0-9]+: Error: operand mismatch -- `splice z0\.h,p0,{z0\.b,z1\.b}'
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[^ :]+:[0-9]+: Info: did you mean this\?
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[^ :]+:[0-9]+: Info: splice z0\.b, p0, {z0\.b, z1\.b}
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[^ :]+:[0-9]+: Info: splice z0\.b, p0, {z0\.b-z1\.b}
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[^ :]+:[0-9]+: Info: other valid variant\(s\):
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[^ :]+:[0-9]+: Info: splice z0\.h, p0, {z0\.h, z1\.h}
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[^ :]+:[0-9]+: Info: splice z0\.s, p0, {z0\.s, z1\.s}
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[^ :]+:[0-9]+: Info: splice z0\.d, p0, {z0\.d, z1\.d}
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[^ :]+:[0-9]+: Info: splice z0\.h, p0, {z0\.h-z1\.h}
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[^ :]+:[0-9]+: Info: splice z0\.s, p0, {z0\.s-z1\.s}
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[^ :]+:[0-9]+: Info: splice z0\.d, p0, {z0\.d-z1\.d}
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[^ :]+:[0-9]+: Error: type mismatch in vector register list at operand 3 -- `splice z0\.b,p0,{z0\.h,z1\.b}'
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[^ :]+:[0-9]+: Error: type mismatch in vector register list at operand 3 -- `splice z0\.b,p0,{z0\.b,z1\.h}'
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[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `splice z32\.b,p0,{z0\.b,z1\.b}'
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@ -2336,21 +2336,21 @@
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[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `tbl z0\.b,{z0\.b,z1\.b},z32\.b'
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[^ :]+:[0-9]+: Error: operand mismatch -- `tbl z0\.b,{z0\.b,z1\.b},z0\.h'
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[^ :]+:[0-9]+: Info: did you mean this\?
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[^ :]+:[0-9]+: Info: tbl z0\.b, {z0\.b, z1\.b}, z0\.b
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[^ :]+:[0-9]+: Info: tbl z0\.b, {z0\.b-z1\.b}, z0\.b
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[^ :]+:[0-9]+: Info: other valid variant\(s\):
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[^ :]+:[0-9]+: Info: tbl z0\.h, {z0\.h, z1\.h}, z0\.h
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[^ :]+:[0-9]+: Info: tbl z0\.s, {z0\.s, z1\.s}, z0\.s
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[^ :]+:[0-9]+: Info: tbl z0\.d, {z0\.d, z1\.d}, z0\.d
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[^ :]+:[0-9]+: Info: tbl z0\.h, {z0\.h-z1\.h}, z0\.h
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[^ :]+:[0-9]+: Info: tbl z0\.s, {z0\.s-z1\.s}, z0\.s
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[^ :]+:[0-9]+: Info: tbl z0\.d, {z0\.d-z1\.d}, z0\.d
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[^ :]+:[0-9]+: Error: type mismatch in vector register list at operand 2 -- `tbl z0\.b,{z0\.b,z1\.h},z0\.b'
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[^ :]+:[0-9]+: Error: type mismatch in vector register list at operand 2 -- `tbl z0\.b,{z0\.h,z0\.b},z0\.b'
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[^ :]+:[0-9]+: Error: invalid register list at operand 2 -- `tbl z0\.h,{z0\.b,z0\.b},z0\.b'
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[^ :]+:[0-9]+: Error: operand mismatch -- `tbl z0\.h,{z0\.b,z1\.b},z0\.b'
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[^ :]+:[0-9]+: Info: did you mean this\?
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[^ :]+:[0-9]+: Info: tbl z0\.b, {z0\.b, z1\.b}, z0\.b
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[^ :]+:[0-9]+: Info: tbl z0\.b, {z0\.b-z1\.b}, z0\.b
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[^ :]+:[0-9]+: Info: other valid variant\(s\):
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[^ :]+:[0-9]+: Info: tbl z0\.h, {z0\.h, z1\.h}, z0\.h
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[^ :]+:[0-9]+: Info: tbl z0\.s, {z0\.s, z1\.s}, z0\.s
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[^ :]+:[0-9]+: Info: tbl z0\.d, {z0\.d, z1\.d}, z0\.d
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[^ :]+:[0-9]+: Info: tbl z0\.h, {z0\.h-z1\.h}, z0\.h
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[^ :]+:[0-9]+: Info: tbl z0\.s, {z0\.s-z1\.s}, z0\.s
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[^ :]+:[0-9]+: Info: tbl z0\.d, {z0\.d-z1\.d}, z0\.d
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[^ :]+:[0-9]+: Error: expected a vector register at operand 1 -- `tbx z32\.h,z0\.b,z0\.b'
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[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `tbx z0\.h,z32\.b,z0\.b'
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[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `tbx z0\.h,z0\.b,z32\.b'
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@ -6,161 +6,161 @@ Disassembly of section \.text:
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0+ <.*>:
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0: 0cdf7000 ld1 {v0.8b}, \[x0\], #8
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4: 0cdfa000 ld1 {v0.8b, v1.8b}, \[x0\], #16
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4: 0cdfa000 ld1 {v0.8b-v1.8b}, \[x0\], #16
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8: 0cdf6000 ld1 {v0.8b-v2.8b}, \[x0\], #24
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c: 0cdf2000 ld1 {v0.8b-v3.8b}, \[x0\], #32
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10: 0cdf7400 ld1 {v0.4h}, \[x0\], #8
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14: 0cdfa400 ld1 {v0.4h, v1.4h}, \[x0\], #16
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14: 0cdfa400 ld1 {v0.4h-v1.4h}, \[x0\], #16
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18: 0cdf6400 ld1 {v0.4h-v2.4h}, \[x0\], #24
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1c: 0cdf2400 ld1 {v0.4h-v3.4h}, \[x0\], #32
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20: 0cdf7800 ld1 {v0.2s}, \[x0\], #8
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24: 0cdfa800 ld1 {v0.2s, v1.2s}, \[x0\], #16
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24: 0cdfa800 ld1 {v0.2s-v1.2s}, \[x0\], #16
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28: 0cdf6800 ld1 {v0.2s-v2.2s}, \[x0\], #24
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2c: 0cdf2800 ld1 {v0.2s-v3.2s}, \[x0\], #32
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30: 0cdf7c00 ld1 {v0.1d}, \[x0\], #8
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34: 0cdfac00 ld1 {v0.1d, v1.1d}, \[x0\], #16
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34: 0cdfac00 ld1 {v0.1d-v1.1d}, \[x0\], #16
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38: 0cdf6c00 ld1 {v0.1d-v2.1d}, \[x0\], #24
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3c: 0cdf2c00 ld1 {v0.1d-v3.1d}, \[x0\], #32
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40: 0c9f7000 st1 {v0.8b}, \[x0\], #8
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44: 0c9fa000 st1 {v0.8b, v1.8b}, \[x0\], #16
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44: 0c9fa000 st1 {v0.8b-v1.8b}, \[x0\], #16
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48: 0c9f6000 st1 {v0.8b-v2.8b}, \[x0\], #24
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4c: 0c9f2000 st1 {v0.8b-v3.8b}, \[x0\], #32
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50: 0c9f7400 st1 {v0.4h}, \[x0\], #8
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54: 0c9fa400 st1 {v0.4h, v1.4h}, \[x0\], #16
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54: 0c9fa400 st1 {v0.4h-v1.4h}, \[x0\], #16
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58: 0c9f6400 st1 {v0.4h-v2.4h}, \[x0\], #24
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5c: 0c9f2400 st1 {v0.4h-v3.4h}, \[x0\], #32
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60: 0c9f7800 st1 {v0.2s}, \[x0\], #8
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64: 0c9fa800 st1 {v0.2s, v1.2s}, \[x0\], #16
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64: 0c9fa800 st1 {v0.2s-v1.2s}, \[x0\], #16
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68: 0c9f6800 st1 {v0.2s-v2.2s}, \[x0\], #24
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6c: 0c9f2800 st1 {v0.2s-v3.2s}, \[x0\], #32
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70: 0c9f7c00 st1 {v0.1d}, \[x0\], #8
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74: 0c9fac00 st1 {v0.1d, v1.1d}, \[x0\], #16
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74: 0c9fac00 st1 {v0.1d-v1.1d}, \[x0\], #16
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78: 0c9f6c00 st1 {v0.1d-v2.1d}, \[x0\], #24
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7c: 0c9f2c00 st1 {v0.1d-v3.1d}, \[x0\], #32
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80: 4cdf7000 ld1 {v0.16b}, \[x0\], #16
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84: 4cdfa000 ld1 {v0.16b, v1.16b}, \[x0\], #32
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84: 4cdfa000 ld1 {v0.16b-v1.16b}, \[x0\], #32
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88: 4cdf6000 ld1 {v0.16b-v2.16b}, \[x0\], #48
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8c: 4cdf2000 ld1 {v0.16b-v3.16b}, \[x0\], #64
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90: 4cdf7400 ld1 {v0.8h}, \[x0\], #16
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94: 4cdfa400 ld1 {v0.8h, v1.8h}, \[x0\], #32
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94: 4cdfa400 ld1 {v0.8h-v1.8h}, \[x0\], #32
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98: 4cdf6400 ld1 {v0.8h-v2.8h}, \[x0\], #48
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9c: 4cdf2400 ld1 {v0.8h-v3.8h}, \[x0\], #64
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a0: 4cdf7800 ld1 {v0.4s}, \[x0\], #16
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a4: 4cdfa800 ld1 {v0.4s, v1.4s}, \[x0\], #32
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a4: 4cdfa800 ld1 {v0.4s-v1.4s}, \[x0\], #32
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a8: 4cdf6800 ld1 {v0.4s-v2.4s}, \[x0\], #48
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ac: 4cdf2800 ld1 {v0.4s-v3.4s}, \[x0\], #64
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b0: 4cdf7c00 ld1 {v0.2d}, \[x0\], #16
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b4: 4cdfac00 ld1 {v0.2d, v1.2d}, \[x0\], #32
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b4: 4cdfac00 ld1 {v0.2d-v1.2d}, \[x0\], #32
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b8: 4cdf6c00 ld1 {v0.2d-v2.2d}, \[x0\], #48
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bc: 4cdf2c00 ld1 {v0.2d-v3.2d}, \[x0\], #64
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c0: 4c9f7000 st1 {v0.16b}, \[x0\], #16
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c4: 4c9fa000 st1 {v0.16b, v1.16b}, \[x0\], #32
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c4: 4c9fa000 st1 {v0.16b-v1.16b}, \[x0\], #32
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c8: 4c9f6000 st1 {v0.16b-v2.16b}, \[x0\], #48
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cc: 4c9f2000 st1 {v0.16b-v3.16b}, \[x0\], #64
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d0: 4c9f7400 st1 {v0.8h}, \[x0\], #16
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d4: 4c9fa400 st1 {v0.8h, v1.8h}, \[x0\], #32
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d4: 4c9fa400 st1 {v0.8h-v1.8h}, \[x0\], #32
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d8: 4c9f6400 st1 {v0.8h-v2.8h}, \[x0\], #48
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dc: 4c9f2400 st1 {v0.8h-v3.8h}, \[x0\], #64
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e0: 4c9f7800 st1 {v0.4s}, \[x0\], #16
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e4: 4c9fa800 st1 {v0.4s, v1.4s}, \[x0\], #32
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e4: 4c9fa800 st1 {v0.4s-v1.4s}, \[x0\], #32
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e8: 4c9f6800 st1 {v0.4s-v2.4s}, \[x0\], #48
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ec: 4c9f2800 st1 {v0.4s-v3.4s}, \[x0\], #64
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f0: 4c9f7c00 st1 {v0.2d}, \[x0\], #16
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f4: 4c9fac00 st1 {v0.2d, v1.2d}, \[x0\], #32
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f4: 4c9fac00 st1 {v0.2d-v1.2d}, \[x0\], #32
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f8: 4c9f6c00 st1 {v0.2d-v2.2d}, \[x0\], #48
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fc: 4c9f2c00 st1 {v0.2d-v3.2d}, \[x0\], #64
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100: 0cc77000 ld1 {v0.8b}, \[x0\], x7
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104: 0cc7a000 ld1 {v0.8b, v1.8b}, \[x0\], x7
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104: 0cc7a000 ld1 {v0.8b-v1.8b}, \[x0\], x7
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108: 0cc76000 ld1 {v0.8b-v2.8b}, \[x0\], x7
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10c: 0cc72000 ld1 {v0.8b-v3.8b}, \[x0\], x7
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110: 0cc77400 ld1 {v0.4h}, \[x0\], x7
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114: 0cc7a400 ld1 {v0.4h, v1.4h}, \[x0\], x7
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114: 0cc7a400 ld1 {v0.4h-v1.4h}, \[x0\], x7
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118: 0cc76400 ld1 {v0.4h-v2.4h}, \[x0\], x7
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11c: 0cc72400 ld1 {v0.4h-v3.4h}, \[x0\], x7
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120: 0cc77800 ld1 {v0.2s}, \[x0\], x7
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124: 0cc7a800 ld1 {v0.2s, v1.2s}, \[x0\], x7
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124: 0cc7a800 ld1 {v0.2s-v1.2s}, \[x0\], x7
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128: 0cc76800 ld1 {v0.2s-v2.2s}, \[x0\], x7
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12c: 0cc72800 ld1 {v0.2s-v3.2s}, \[x0\], x7
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130: 0cc77c00 ld1 {v0.1d}, \[x0\], x7
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134: 0cc7ac00 ld1 {v0.1d, v1.1d}, \[x0\], x7
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134: 0cc7ac00 ld1 {v0.1d-v1.1d}, \[x0\], x7
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138: 0cc76c00 ld1 {v0.1d-v2.1d}, \[x0\], x7
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13c: 0cc72c00 ld1 {v0.1d-v3.1d}, \[x0\], x7
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140: 4cc77000 ld1 {v0.16b}, \[x0\], x7
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144: 4cc7a000 ld1 {v0.16b, v1.16b}, \[x0\], x7
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144: 4cc7a000 ld1 {v0.16b-v1.16b}, \[x0\], x7
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148: 4cc76000 ld1 {v0.16b-v2.16b}, \[x0\], x7
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14c: 4cc72000 ld1 {v0.16b-v3.16b}, \[x0\], x7
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150: 4cc77400 ld1 {v0.8h}, \[x0\], x7
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154: 4cc7a400 ld1 {v0.8h, v1.8h}, \[x0\], x7
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154: 4cc7a400 ld1 {v0.8h-v1.8h}, \[x0\], x7
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158: 4cc76400 ld1 {v0.8h-v2.8h}, \[x0\], x7
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15c: 4cc72400 ld1 {v0.8h-v3.8h}, \[x0\], x7
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160: 4cc77800 ld1 {v0.4s}, \[x0\], x7
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164: 4cc7a800 ld1 {v0.4s, v1.4s}, \[x0\], x7
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164: 4cc7a800 ld1 {v0.4s-v1.4s}, \[x0\], x7
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168: 4cc76800 ld1 {v0.4s-v2.4s}, \[x0\], x7
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16c: 4cc72800 ld1 {v0.4s-v3.4s}, \[x0\], x7
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170: 4cc77c00 ld1 {v0.2d}, \[x0\], x7
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174: 4cc7ac00 ld1 {v0.2d, v1.2d}, \[x0\], x7
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174: 4cc7ac00 ld1 {v0.2d-v1.2d}, \[x0\], x7
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178: 4cc76c00 ld1 {v0.2d-v2.2d}, \[x0\], x7
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17c: 4cc72c00 ld1 {v0.2d-v3.2d}, \[x0\], x7
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180: 0c877000 st1 {v0.8b}, \[x0\], x7
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184: 0c87a000 st1 {v0.8b, v1.8b}, \[x0\], x7
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184: 0c87a000 st1 {v0.8b-v1.8b}, \[x0\], x7
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188: 0c876000 st1 {v0.8b-v2.8b}, \[x0\], x7
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18c: 0c872000 st1 {v0.8b-v3.8b}, \[x0\], x7
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190: 0c877400 st1 {v0.4h}, \[x0\], x7
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194: 0c87a400 st1 {v0.4h, v1.4h}, \[x0\], x7
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194: 0c87a400 st1 {v0.4h-v1.4h}, \[x0\], x7
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198: 0c876400 st1 {v0.4h-v2.4h}, \[x0\], x7
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19c: 0c872400 st1 {v0.4h-v3.4h}, \[x0\], x7
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1a0: 0c877800 st1 {v0.2s}, \[x0\], x7
|
||||
1a4: 0c87a800 st1 {v0.2s, v1.2s}, \[x0\], x7
|
||||
1a4: 0c87a800 st1 {v0.2s-v1.2s}, \[x0\], x7
|
||||
1a8: 0c876800 st1 {v0.2s-v2.2s}, \[x0\], x7
|
||||
1ac: 0c872800 st1 {v0.2s-v3.2s}, \[x0\], x7
|
||||
1b0: 0c877c00 st1 {v0.1d}, \[x0\], x7
|
||||
1b4: 0c87ac00 st1 {v0.1d, v1.1d}, \[x0\], x7
|
||||
1b4: 0c87ac00 st1 {v0.1d-v1.1d}, \[x0\], x7
|
||||
1b8: 0c876c00 st1 {v0.1d-v2.1d}, \[x0\], x7
|
||||
1bc: 0c872c00 st1 {v0.1d-v3.1d}, \[x0\], x7
|
||||
1c0: 4c877000 st1 {v0.16b}, \[x0\], x7
|
||||
1c4: 4c87a000 st1 {v0.16b, v1.16b}, \[x0\], x7
|
||||
1c4: 4c87a000 st1 {v0.16b-v1.16b}, \[x0\], x7
|
||||
1c8: 4c876000 st1 {v0.16b-v2.16b}, \[x0\], x7
|
||||
1cc: 4c872000 st1 {v0.16b-v3.16b}, \[x0\], x7
|
||||
1d0: 4c877400 st1 {v0.8h}, \[x0\], x7
|
||||
1d4: 4c87a400 st1 {v0.8h, v1.8h}, \[x0\], x7
|
||||
1d4: 4c87a400 st1 {v0.8h-v1.8h}, \[x0\], x7
|
||||
1d8: 4c876400 st1 {v0.8h-v2.8h}, \[x0\], x7
|
||||
1dc: 4c872400 st1 {v0.8h-v3.8h}, \[x0\], x7
|
||||
1e0: 4c877800 st1 {v0.4s}, \[x0\], x7
|
||||
1e4: 4c87a800 st1 {v0.4s, v1.4s}, \[x0\], x7
|
||||
1e4: 4c87a800 st1 {v0.4s-v1.4s}, \[x0\], x7
|
||||
1e8: 4c876800 st1 {v0.4s-v2.4s}, \[x0\], x7
|
||||
1ec: 4c872800 st1 {v0.4s-v3.4s}, \[x0\], x7
|
||||
1f0: 4c877c00 st1 {v0.2d}, \[x0\], x7
|
||||
1f4: 4c87ac00 st1 {v0.2d, v1.2d}, \[x0\], x7
|
||||
1f4: 4c87ac00 st1 {v0.2d-v1.2d}, \[x0\], x7
|
||||
1f8: 4c876c00 st1 {v0.2d-v2.2d}, \[x0\], x7
|
||||
1fc: 4c872c00 st1 {v0.2d-v3.2d}, \[x0\], x7
|
||||
200: 0cdf8000 ld2 {v0.8b, v1.8b}, \[x0\], #16
|
||||
204: 0cc78000 ld2 {v0.8b, v1.8b}, \[x0\], x7
|
||||
208: 0cdf8400 ld2 {v0.4h, v1.4h}, \[x0\], #16
|
||||
20c: 0cc78400 ld2 {v0.4h, v1.4h}, \[x0\], x7
|
||||
210: 0cdf8800 ld2 {v0.2s, v1.2s}, \[x0\], #16
|
||||
214: 0cc78800 ld2 {v0.2s, v1.2s}, \[x0\], x7
|
||||
218: 0c9f8000 st2 {v0.8b, v1.8b}, \[x0\], #16
|
||||
21c: 0c878000 st2 {v0.8b, v1.8b}, \[x0\], x7
|
||||
220: 0c9f8400 st2 {v0.4h, v1.4h}, \[x0\], #16
|
||||
224: 0c878400 st2 {v0.4h, v1.4h}, \[x0\], x7
|
||||
228: 0c9f8800 st2 {v0.2s, v1.2s}, \[x0\], #16
|
||||
22c: 0c878800 st2 {v0.2s, v1.2s}, \[x0\], x7
|
||||
230: 4cdf8000 ld2 {v0.16b, v1.16b}, \[x0\], #32
|
||||
234: 4cc78000 ld2 {v0.16b, v1.16b}, \[x0\], x7
|
||||
238: 4cdf8400 ld2 {v0.8h, v1.8h}, \[x0\], #32
|
||||
23c: 4cc78400 ld2 {v0.8h, v1.8h}, \[x0\], x7
|
||||
240: 4cdf8800 ld2 {v0.4s, v1.4s}, \[x0\], #32
|
||||
244: 4cc78800 ld2 {v0.4s, v1.4s}, \[x0\], x7
|
||||
248: 4cdf8c00 ld2 {v0.2d, v1.2d}, \[x0\], #32
|
||||
24c: 4cc78c00 ld2 {v0.2d, v1.2d}, \[x0\], x7
|
||||
250: 4c9f8000 st2 {v0.16b, v1.16b}, \[x0\], #32
|
||||
254: 4c878000 st2 {v0.16b, v1.16b}, \[x0\], x7
|
||||
258: 4c9f8400 st2 {v0.8h, v1.8h}, \[x0\], #32
|
||||
25c: 4c878400 st2 {v0.8h, v1.8h}, \[x0\], x7
|
||||
260: 4c9f8800 st2 {v0.4s, v1.4s}, \[x0\], #32
|
||||
264: 4c878800 st2 {v0.4s, v1.4s}, \[x0\], x7
|
||||
268: 4c9f8c00 st2 {v0.2d, v1.2d}, \[x0\], #32
|
||||
26c: 4c878c00 st2 {v0.2d, v1.2d}, \[x0\], x7
|
||||
200: 0cdf8000 ld2 {v0.8b-v1.8b}, \[x0\], #16
|
||||
204: 0cc78000 ld2 {v0.8b-v1.8b}, \[x0\], x7
|
||||
208: 0cdf8400 ld2 {v0.4h-v1.4h}, \[x0\], #16
|
||||
20c: 0cc78400 ld2 {v0.4h-v1.4h}, \[x0\], x7
|
||||
210: 0cdf8800 ld2 {v0.2s-v1.2s}, \[x0\], #16
|
||||
214: 0cc78800 ld2 {v0.2s-v1.2s}, \[x0\], x7
|
||||
218: 0c9f8000 st2 {v0.8b-v1.8b}, \[x0\], #16
|
||||
21c: 0c878000 st2 {v0.8b-v1.8b}, \[x0\], x7
|
||||
220: 0c9f8400 st2 {v0.4h-v1.4h}, \[x0\], #16
|
||||
224: 0c878400 st2 {v0.4h-v1.4h}, \[x0\], x7
|
||||
228: 0c9f8800 st2 {v0.2s-v1.2s}, \[x0\], #16
|
||||
22c: 0c878800 st2 {v0.2s-v1.2s}, \[x0\], x7
|
||||
230: 4cdf8000 ld2 {v0.16b-v1.16b}, \[x0\], #32
|
||||
234: 4cc78000 ld2 {v0.16b-v1.16b}, \[x0\], x7
|
||||
238: 4cdf8400 ld2 {v0.8h-v1.8h}, \[x0\], #32
|
||||
23c: 4cc78400 ld2 {v0.8h-v1.8h}, \[x0\], x7
|
||||
240: 4cdf8800 ld2 {v0.4s-v1.4s}, \[x0\], #32
|
||||
244: 4cc78800 ld2 {v0.4s-v1.4s}, \[x0\], x7
|
||||
248: 4cdf8c00 ld2 {v0.2d-v1.2d}, \[x0\], #32
|
||||
24c: 4cc78c00 ld2 {v0.2d-v1.2d}, \[x0\], x7
|
||||
250: 4c9f8000 st2 {v0.16b-v1.16b}, \[x0\], #32
|
||||
254: 4c878000 st2 {v0.16b-v1.16b}, \[x0\], x7
|
||||
258: 4c9f8400 st2 {v0.8h-v1.8h}, \[x0\], #32
|
||||
25c: 4c878400 st2 {v0.8h-v1.8h}, \[x0\], x7
|
||||
260: 4c9f8800 st2 {v0.4s-v1.4s}, \[x0\], #32
|
||||
264: 4c878800 st2 {v0.4s-v1.4s}, \[x0\], x7
|
||||
268: 4c9f8c00 st2 {v0.2d-v1.2d}, \[x0\], #32
|
||||
26c: 4c878c00 st2 {v0.2d-v1.2d}, \[x0\], x7
|
||||
270: 0cdf4000 ld3 {v0.8b-v2.8b}, \[x0\], #24
|
||||
274: 0cdf0000 ld4 {v0.8b-v3.8b}, \[x0\], #32
|
||||
278: 0cc74000 ld3 {v0.8b-v2.8b}, \[x0\], x7
|
||||
@ -218,130 +218,130 @@ Disassembly of section \.text:
|
||||
348: 4c874c00 st3 {v0.2d-v2.2d}, \[x0\], x7
|
||||
34c: 4c870c00 st4 {v0.2d-v3.2d}, \[x0\], x7
|
||||
350: 0ddf0400 ld1 {v0.b}\[1\], \[x0\], #1
|
||||
354: 0dff0400 ld2 {v0.b, v1.b}\[1\], \[x0\], #2
|
||||
354: 0dff0400 ld2 {v0.b-v1.b}\[1\], \[x0\], #2
|
||||
358: 0ddf2400 ld3 {v0.b-v2.b}\[1\], \[x0\], #3
|
||||
35c: 0dff2400 ld4 {v0.b-v3.b}\[1\], \[x0\], #4
|
||||
360: 0ddfc000 ld1r {v0.8b}, \[x0\], #1
|
||||
364: 0dffc000 ld2r {v0.8b, v1.8b}, \[x0\], #2
|
||||
364: 0dffc000 ld2r {v0.8b-v1.8b}, \[x0\], #2
|
||||
368: 0ddfe000 ld3r {v0.8b-v2.8b}, \[x0\], #3
|
||||
36c: 0dffe000 ld4r {v0.8b-v3.8b}, \[x0\], #4
|
||||
370: 4ddfc000 ld1r {v0.16b}, \[x0\], #1
|
||||
374: 4dffc000 ld2r {v0.16b, v1.16b}, \[x0\], #2
|
||||
374: 4dffc000 ld2r {v0.16b-v1.16b}, \[x0\], #2
|
||||
378: 4ddfe000 ld3r {v0.16b-v2.16b}, \[x0\], #3
|
||||
37c: 4dffe000 ld4r {v0.16b-v3.16b}, \[x0\], #4
|
||||
380: 0d9f0400 st1 {v0.b}\[1\], \[x0\], #1
|
||||
384: 0dbf0400 st2 {v0.b, v1.b}\[1\], \[x0\], #2
|
||||
384: 0dbf0400 st2 {v0.b-v1.b}\[1\], \[x0\], #2
|
||||
388: 0d9f2400 st3 {v0.b-v2.b}\[1\], \[x0\], #3
|
||||
38c: 0dbf2400 st4 {v0.b-v3.b}\[1\], \[x0\], #4
|
||||
390: 0ddf4800 ld1 {v0.h}\[1\], \[x0\], #2
|
||||
394: 0dff4800 ld2 {v0.h, v1.h}\[1\], \[x0\], #4
|
||||
394: 0dff4800 ld2 {v0.h-v1.h}\[1\], \[x0\], #4
|
||||
398: 0ddf6800 ld3 {v0.h-v2.h}\[1\], \[x0\], #6
|
||||
39c: 0dff6800 ld4 {v0.h-v3.h}\[1\], \[x0\], #8
|
||||
3a0: 0ddfc400 ld1r {v0.4h}, \[x0\], #2
|
||||
3a4: 0dffc400 ld2r {v0.4h, v1.4h}, \[x0\], #4
|
||||
3a4: 0dffc400 ld2r {v0.4h-v1.4h}, \[x0\], #4
|
||||
3a8: 0ddfe400 ld3r {v0.4h-v2.4h}, \[x0\], #6
|
||||
3ac: 0dffe400 ld4r {v0.4h-v3.4h}, \[x0\], #8
|
||||
3b0: 4ddfc400 ld1r {v0.8h}, \[x0\], #2
|
||||
3b4: 4dffc400 ld2r {v0.8h, v1.8h}, \[x0\], #4
|
||||
3b4: 4dffc400 ld2r {v0.8h-v1.8h}, \[x0\], #4
|
||||
3b8: 4ddfe400 ld3r {v0.8h-v2.8h}, \[x0\], #6
|
||||
3bc: 4dffe400 ld4r {v0.8h-v3.8h}, \[x0\], #8
|
||||
3c0: 0d9f4800 st1 {v0.h}\[1\], \[x0\], #2
|
||||
3c4: 0dbf4800 st2 {v0.h, v1.h}\[1\], \[x0\], #4
|
||||
3c4: 0dbf4800 st2 {v0.h-v1.h}\[1\], \[x0\], #4
|
||||
3c8: 0d9f6800 st3 {v0.h-v2.h}\[1\], \[x0\], #6
|
||||
3cc: 0dbf6800 st4 {v0.h-v3.h}\[1\], \[x0\], #8
|
||||
3d0: 0ddf9000 ld1 {v0.s}\[1\], \[x0\], #4
|
||||
3d4: 0dff9000 ld2 {v0.s, v1.s}\[1\], \[x0\], #8
|
||||
3d4: 0dff9000 ld2 {v0.s-v1.s}\[1\], \[x0\], #8
|
||||
3d8: 0ddfb000 ld3 {v0.s-v2.s}\[1\], \[x0\], #12
|
||||
3dc: 0dffb000 ld4 {v0.s-v3.s}\[1\], \[x0\], #16
|
||||
3e0: 0ddfc800 ld1r {v0.2s}, \[x0\], #4
|
||||
3e4: 0dffc800 ld2r {v0.2s, v1.2s}, \[x0\], #8
|
||||
3e4: 0dffc800 ld2r {v0.2s-v1.2s}, \[x0\], #8
|
||||
3e8: 0ddfe800 ld3r {v0.2s-v2.2s}, \[x0\], #12
|
||||
3ec: 0dffe800 ld4r {v0.2s-v3.2s}, \[x0\], #16
|
||||
3f0: 4ddfc800 ld1r {v0.4s}, \[x0\], #4
|
||||
3f4: 4dffc800 ld2r {v0.4s, v1.4s}, \[x0\], #8
|
||||
3f4: 4dffc800 ld2r {v0.4s-v1.4s}, \[x0\], #8
|
||||
3f8: 4ddfe800 ld3r {v0.4s-v2.4s}, \[x0\], #12
|
||||
3fc: 4dffe800 ld4r {v0.4s-v3.4s}, \[x0\], #16
|
||||
400: 0d9f9000 st1 {v0.s}\[1\], \[x0\], #4
|
||||
404: 0dbf9000 st2 {v0.s, v1.s}\[1\], \[x0\], #8
|
||||
404: 0dbf9000 st2 {v0.s-v1.s}\[1\], \[x0\], #8
|
||||
408: 0d9fb000 st3 {v0.s-v2.s}\[1\], \[x0\], #12
|
||||
40c: 0dbfb000 st4 {v0.s-v3.s}\[1\], \[x0\], #16
|
||||
410: 4ddf8400 ld1 {v0.d}\[1\], \[x0\], #8
|
||||
414: 4dff8400 ld2 {v0.d, v1.d}\[1\], \[x0\], #16
|
||||
414: 4dff8400 ld2 {v0.d-v1.d}\[1\], \[x0\], #16
|
||||
418: 4ddfa400 ld3 {v0.d-v2.d}\[1\], \[x0\], #24
|
||||
41c: 4dffa400 ld4 {v0.d-v3.d}\[1\], \[x0\], #32
|
||||
420: 0ddfcc00 ld1r {v0.1d}, \[x0\], #8
|
||||
424: 0dffcc00 ld2r {v0.1d, v1.1d}, \[x0\], #16
|
||||
424: 0dffcc00 ld2r {v0.1d-v1.1d}, \[x0\], #16
|
||||
428: 0ddfec00 ld3r {v0.1d-v2.1d}, \[x0\], #24
|
||||
42c: 0dffec00 ld4r {v0.1d-v3.1d}, \[x0\], #32
|
||||
430: 4ddfcc00 ld1r {v0.2d}, \[x0\], #8
|
||||
434: 4dffcc00 ld2r {v0.2d, v1.2d}, \[x0\], #16
|
||||
434: 4dffcc00 ld2r {v0.2d-v1.2d}, \[x0\], #16
|
||||
438: 4ddfec00 ld3r {v0.2d-v2.2d}, \[x0\], #24
|
||||
43c: 4dffec00 ld4r {v0.2d-v3.2d}, \[x0\], #32
|
||||
440: 4d9f8400 st1 {v0.d}\[1\], \[x0\], #8
|
||||
444: 4dbf8400 st2 {v0.d, v1.d}\[1\], \[x0\], #16
|
||||
444: 4dbf8400 st2 {v0.d-v1.d}\[1\], \[x0\], #16
|
||||
448: 4d9fa400 st3 {v0.d-v2.d}\[1\], \[x0\], #24
|
||||
44c: 4dbfa400 st4 {v0.d-v3.d}\[1\], \[x0\], #32
|
||||
450: 0dc70400 ld1 {v0.b}\[1\], \[x0\], x7
|
||||
454: 0de70400 ld2 {v0.b, v1.b}\[1\], \[x0\], x7
|
||||
454: 0de70400 ld2 {v0.b-v1.b}\[1\], \[x0\], x7
|
||||
458: 0dc72400 ld3 {v0.b-v2.b}\[1\], \[x0\], x7
|
||||
45c: 0de72400 ld4 {v0.b-v3.b}\[1\], \[x0\], x7
|
||||
460: 0dc74800 ld1 {v0.h}\[1\], \[x0\], x7
|
||||
464: 0de74800 ld2 {v0.h, v1.h}\[1\], \[x0\], x7
|
||||
464: 0de74800 ld2 {v0.h-v1.h}\[1\], \[x0\], x7
|
||||
468: 0dc76800 ld3 {v0.h-v2.h}\[1\], \[x0\], x7
|
||||
46c: 0de76800 ld4 {v0.h-v3.h}\[1\], \[x0\], x7
|
||||
470: 0dc79000 ld1 {v0.s}\[1\], \[x0\], x7
|
||||
474: 0de79000 ld2 {v0.s, v1.s}\[1\], \[x0\], x7
|
||||
474: 0de79000 ld2 {v0.s-v1.s}\[1\], \[x0\], x7
|
||||
478: 0dc7b000 ld3 {v0.s-v2.s}\[1\], \[x0\], x7
|
||||
47c: 0de7b000 ld4 {v0.s-v3.s}\[1\], \[x0\], x7
|
||||
480: 4dc78400 ld1 {v0.d}\[1\], \[x0\], x7
|
||||
484: 4de78400 ld2 {v0.d, v1.d}\[1\], \[x0\], x7
|
||||
484: 4de78400 ld2 {v0.d-v1.d}\[1\], \[x0\], x7
|
||||
488: 4dc7a400 ld3 {v0.d-v2.d}\[1\], \[x0\], x7
|
||||
48c: 4de7a400 ld4 {v0.d-v3.d}\[1\], \[x0\], x7
|
||||
490: 0dc7c000 ld1r {v0.8b}, \[x0\], x7
|
||||
494: 0de7c000 ld2r {v0.8b, v1.8b}, \[x0\], x7
|
||||
494: 0de7c000 ld2r {v0.8b-v1.8b}, \[x0\], x7
|
||||
498: 0dc7e000 ld3r {v0.8b-v2.8b}, \[x0\], x7
|
||||
49c: 0de7e000 ld4r {v0.8b-v3.8b}, \[x0\], x7
|
||||
4a0: 4dc7c000 ld1r {v0.16b}, \[x0\], x7
|
||||
4a4: 4de7c000 ld2r {v0.16b, v1.16b}, \[x0\], x7
|
||||
4a4: 4de7c000 ld2r {v0.16b-v1.16b}, \[x0\], x7
|
||||
4a8: 4dc7e000 ld3r {v0.16b-v2.16b}, \[x0\], x7
|
||||
4ac: 4de7e000 ld4r {v0.16b-v3.16b}, \[x0\], x7
|
||||
4b0: 0dc7c400 ld1r {v0.4h}, \[x0\], x7
|
||||
4b4: 0de7c400 ld2r {v0.4h, v1.4h}, \[x0\], x7
|
||||
4b4: 0de7c400 ld2r {v0.4h-v1.4h}, \[x0\], x7
|
||||
4b8: 0dc7e400 ld3r {v0.4h-v2.4h}, \[x0\], x7
|
||||
4bc: 0de7e400 ld4r {v0.4h-v3.4h}, \[x0\], x7
|
||||
4c0: 4dc7c400 ld1r {v0.8h}, \[x0\], x7
|
||||
4c4: 4de7c400 ld2r {v0.8h, v1.8h}, \[x0\], x7
|
||||
4c4: 4de7c400 ld2r {v0.8h-v1.8h}, \[x0\], x7
|
||||
4c8: 4dc7e400 ld3r {v0.8h-v2.8h}, \[x0\], x7
|
||||
4cc: 4de7e400 ld4r {v0.8h-v3.8h}, \[x0\], x7
|
||||
4d0: 0dc7c800 ld1r {v0.2s}, \[x0\], x7
|
||||
4d4: 0de7c800 ld2r {v0.2s, v1.2s}, \[x0\], x7
|
||||
4d4: 0de7c800 ld2r {v0.2s-v1.2s}, \[x0\], x7
|
||||
4d8: 0dc7e800 ld3r {v0.2s-v2.2s}, \[x0\], x7
|
||||
4dc: 0de7e800 ld4r {v0.2s-v3.2s}, \[x0\], x7
|
||||
4e0: 4dc7c800 ld1r {v0.4s}, \[x0\], x7
|
||||
4e4: 4de7c800 ld2r {v0.4s, v1.4s}, \[x0\], x7
|
||||
4e4: 4de7c800 ld2r {v0.4s-v1.4s}, \[x0\], x7
|
||||
4e8: 4dc7e800 ld3r {v0.4s-v2.4s}, \[x0\], x7
|
||||
4ec: 4de7e800 ld4r {v0.4s-v3.4s}, \[x0\], x7
|
||||
4f0: 0dc7cc00 ld1r {v0.1d}, \[x0\], x7
|
||||
4f4: 0de7cc00 ld2r {v0.1d, v1.1d}, \[x0\], x7
|
||||
4f4: 0de7cc00 ld2r {v0.1d-v1.1d}, \[x0\], x7
|
||||
4f8: 0dc7ec00 ld3r {v0.1d-v2.1d}, \[x0\], x7
|
||||
4fc: 0de7ec00 ld4r {v0.1d-v3.1d}, \[x0\], x7
|
||||
500: 4dc7cc00 ld1r {v0.2d}, \[x0\], x7
|
||||
504: 4de7cc00 ld2r {v0.2d, v1.2d}, \[x0\], x7
|
||||
504: 4de7cc00 ld2r {v0.2d-v1.2d}, \[x0\], x7
|
||||
508: 4dc7ec00 ld3r {v0.2d-v2.2d}, \[x0\], x7
|
||||
50c: 4de7ec00 ld4r {v0.2d-v3.2d}, \[x0\], x7
|
||||
510: 0d870400 st1 {v0.b}\[1\], \[x0\], x7
|
||||
514: 0da70400 st2 {v0.b, v1.b}\[1\], \[x0\], x7
|
||||
514: 0da70400 st2 {v0.b-v1.b}\[1\], \[x0\], x7
|
||||
518: 0d872400 st3 {v0.b-v2.b}\[1\], \[x0\], x7
|
||||
51c: 0da72400 st4 {v0.b-v3.b}\[1\], \[x0\], x7
|
||||
520: 0d874800 st1 {v0.h}\[1\], \[x0\], x7
|
||||
524: 0da74800 st2 {v0.h, v1.h}\[1\], \[x0\], x7
|
||||
524: 0da74800 st2 {v0.h-v1.h}\[1\], \[x0\], x7
|
||||
528: 0d876800 st3 {v0.h-v2.h}\[1\], \[x0\], x7
|
||||
52c: 0da76800 st4 {v0.h-v3.h}\[1\], \[x0\], x7
|
||||
530: 0d879000 st1 {v0.s}\[1\], \[x0\], x7
|
||||
534: 0da79000 st2 {v0.s, v1.s}\[1\], \[x0\], x7
|
||||
534: 0da79000 st2 {v0.s-v1.s}\[1\], \[x0\], x7
|
||||
538: 0d87b000 st3 {v0.s-v2.s}\[1\], \[x0\], x7
|
||||
53c: 0da7b000 st4 {v0.s-v3.s}\[1\], \[x0\], x7
|
||||
540: 4d878400 st1 {v0.d}\[1\], \[x0\], x7
|
||||
544: 4da78400 st2 {v0.d, v1.d}\[1\], \[x0\], x7
|
||||
544: 4da78400 st2 {v0.d-v1.d}\[1\], \[x0\], x7
|
||||
548: 4d87a400 st3 {v0.d-v2.d}\[1\], \[x0\], x7
|
||||
54c: 4da7a400 st4 {v0.d-v3.d}\[1\], \[x0\], x7
|
||||
|
||||
@ -6,188 +6,188 @@ Disassembly of section \.text:
|
||||
|
||||
0+ <.*>:
|
||||
0: 0c407000 ld1 {v0.8b}, \[x0\]
|
||||
4: 0c40a000 ld1 {v0.8b, v1.8b}, \[x0\]
|
||||
4: 0c40a000 ld1 {v0.8b-v1.8b}, \[x0\]
|
||||
8: 0c406000 ld1 {v0.8b-v2.8b}, \[x0\]
|
||||
c: 0c402000 ld1 {v0.8b-v3.8b}, \[x0\]
|
||||
10: 0c408000 ld2 {v0.8b, v1.8b}, \[x0\]
|
||||
10: 0c408000 ld2 {v0.8b-v1.8b}, \[x0\]
|
||||
14: 0c404000 ld3 {v0.8b-v2.8b}, \[x0\]
|
||||
18: 0c400000 ld4 {v0.8b-v3.8b}, \[x0\]
|
||||
1c: 0c007000 st1 {v0.8b}, \[x0\]
|
||||
20: 0c00a000 st1 {v0.8b, v1.8b}, \[x0\]
|
||||
20: 0c00a000 st1 {v0.8b-v1.8b}, \[x0\]
|
||||
24: 0c006000 st1 {v0.8b-v2.8b}, \[x0\]
|
||||
28: 0c002000 st1 {v0.8b-v3.8b}, \[x0\]
|
||||
2c: 0c008000 st2 {v0.8b, v1.8b}, \[x0\]
|
||||
2c: 0c008000 st2 {v0.8b-v1.8b}, \[x0\]
|
||||
30: 0c004000 st3 {v0.8b-v2.8b}, \[x0\]
|
||||
34: 0c000000 st4 {v0.8b-v3.8b}, \[x0\]
|
||||
38: 4c407000 ld1 {v0.16b}, \[x0\]
|
||||
3c: 4c40a000 ld1 {v0.16b, v1.16b}, \[x0\]
|
||||
3c: 4c40a000 ld1 {v0.16b-v1.16b}, \[x0\]
|
||||
40: 4c406000 ld1 {v0.16b-v2.16b}, \[x0\]
|
||||
44: 4c402000 ld1 {v0.16b-v3.16b}, \[x0\]
|
||||
48: 4c408000 ld2 {v0.16b, v1.16b}, \[x0\]
|
||||
48: 4c408000 ld2 {v0.16b-v1.16b}, \[x0\]
|
||||
4c: 4c404000 ld3 {v0.16b-v2.16b}, \[x0\]
|
||||
50: 4c400000 ld4 {v0.16b-v3.16b}, \[x0\]
|
||||
54: 4c007000 st1 {v0.16b}, \[x0\]
|
||||
58: 4c00a000 st1 {v0.16b, v1.16b}, \[x0\]
|
||||
58: 4c00a000 st1 {v0.16b-v1.16b}, \[x0\]
|
||||
5c: 4c006000 st1 {v0.16b-v2.16b}, \[x0\]
|
||||
60: 4c002000 st1 {v0.16b-v3.16b}, \[x0\]
|
||||
64: 4c008000 st2 {v0.16b, v1.16b}, \[x0\]
|
||||
64: 4c008000 st2 {v0.16b-v1.16b}, \[x0\]
|
||||
68: 4c004000 st3 {v0.16b-v2.16b}, \[x0\]
|
||||
6c: 4c000000 st4 {v0.16b-v3.16b}, \[x0\]
|
||||
70: 0c407400 ld1 {v0.4h}, \[x0\]
|
||||
74: 0c40a400 ld1 {v0.4h, v1.4h}, \[x0\]
|
||||
74: 0c40a400 ld1 {v0.4h-v1.4h}, \[x0\]
|
||||
78: 0c406400 ld1 {v0.4h-v2.4h}, \[x0\]
|
||||
7c: 0c402400 ld1 {v0.4h-v3.4h}, \[x0\]
|
||||
80: 0c408400 ld2 {v0.4h, v1.4h}, \[x0\]
|
||||
80: 0c408400 ld2 {v0.4h-v1.4h}, \[x0\]
|
||||
84: 0c404400 ld3 {v0.4h-v2.4h}, \[x0\]
|
||||
88: 0c400400 ld4 {v0.4h-v3.4h}, \[x0\]
|
||||
8c: 0c007400 st1 {v0.4h}, \[x0\]
|
||||
90: 0c00a400 st1 {v0.4h, v1.4h}, \[x0\]
|
||||
90: 0c00a400 st1 {v0.4h-v1.4h}, \[x0\]
|
||||
94: 0c006400 st1 {v0.4h-v2.4h}, \[x0\]
|
||||
98: 0c002400 st1 {v0.4h-v3.4h}, \[x0\]
|
||||
9c: 0c008400 st2 {v0.4h, v1.4h}, \[x0\]
|
||||
9c: 0c008400 st2 {v0.4h-v1.4h}, \[x0\]
|
||||
a0: 0c004400 st3 {v0.4h-v2.4h}, \[x0\]
|
||||
a4: 0c000400 st4 {v0.4h-v3.4h}, \[x0\]
|
||||
a8: 4c407400 ld1 {v0.8h}, \[x0\]
|
||||
ac: 4c40a400 ld1 {v0.8h, v1.8h}, \[x0\]
|
||||
ac: 4c40a400 ld1 {v0.8h-v1.8h}, \[x0\]
|
||||
b0: 4c406400 ld1 {v0.8h-v2.8h}, \[x0\]
|
||||
b4: 4c402400 ld1 {v0.8h-v3.8h}, \[x0\]
|
||||
b8: 4c408400 ld2 {v0.8h, v1.8h}, \[x0\]
|
||||
b8: 4c408400 ld2 {v0.8h-v1.8h}, \[x0\]
|
||||
bc: 4c404400 ld3 {v0.8h-v2.8h}, \[x0\]
|
||||
c0: 4c400400 ld4 {v0.8h-v3.8h}, \[x0\]
|
||||
c4: 4c007400 st1 {v0.8h}, \[x0\]
|
||||
c8: 4c00a400 st1 {v0.8h, v1.8h}, \[x0\]
|
||||
c8: 4c00a400 st1 {v0.8h-v1.8h}, \[x0\]
|
||||
cc: 4c006400 st1 {v0.8h-v2.8h}, \[x0\]
|
||||
d0: 4c002400 st1 {v0.8h-v3.8h}, \[x0\]
|
||||
d4: 4c008400 st2 {v0.8h, v1.8h}, \[x0\]
|
||||
d4: 4c008400 st2 {v0.8h-v1.8h}, \[x0\]
|
||||
d8: 4c004400 st3 {v0.8h-v2.8h}, \[x0\]
|
||||
dc: 4c000400 st4 {v0.8h-v3.8h}, \[x0\]
|
||||
e0: 0c407800 ld1 {v0.2s}, \[x0\]
|
||||
e4: 0c40a800 ld1 {v0.2s, v1.2s}, \[x0\]
|
||||
e4: 0c40a800 ld1 {v0.2s-v1.2s}, \[x0\]
|
||||
e8: 0c406800 ld1 {v0.2s-v2.2s}, \[x0\]
|
||||
ec: 0c402800 ld1 {v0.2s-v3.2s}, \[x0\]
|
||||
f0: 0c408800 ld2 {v0.2s, v1.2s}, \[x0\]
|
||||
f0: 0c408800 ld2 {v0.2s-v1.2s}, \[x0\]
|
||||
f4: 0c404800 ld3 {v0.2s-v2.2s}, \[x0\]
|
||||
f8: 0c400800 ld4 {v0.2s-v3.2s}, \[x0\]
|
||||
fc: 0c007800 st1 {v0.2s}, \[x0\]
|
||||
100: 0c00a800 st1 {v0.2s, v1.2s}, \[x0\]
|
||||
100: 0c00a800 st1 {v0.2s-v1.2s}, \[x0\]
|
||||
104: 0c006800 st1 {v0.2s-v2.2s}, \[x0\]
|
||||
108: 0c002800 st1 {v0.2s-v3.2s}, \[x0\]
|
||||
10c: 0c008800 st2 {v0.2s, v1.2s}, \[x0\]
|
||||
10c: 0c008800 st2 {v0.2s-v1.2s}, \[x0\]
|
||||
110: 0c004800 st3 {v0.2s-v2.2s}, \[x0\]
|
||||
114: 0c000800 st4 {v0.2s-v3.2s}, \[x0\]
|
||||
118: 4c407800 ld1 {v0.4s}, \[x0\]
|
||||
11c: 4c40a800 ld1 {v0.4s, v1.4s}, \[x0\]
|
||||
11c: 4c40a800 ld1 {v0.4s-v1.4s}, \[x0\]
|
||||
120: 4c406800 ld1 {v0.4s-v2.4s}, \[x0\]
|
||||
124: 4c402800 ld1 {v0.4s-v3.4s}, \[x0\]
|
||||
128: 4c408800 ld2 {v0.4s, v1.4s}, \[x0\]
|
||||
128: 4c408800 ld2 {v0.4s-v1.4s}, \[x0\]
|
||||
12c: 4c404800 ld3 {v0.4s-v2.4s}, \[x0\]
|
||||
130: 4c400800 ld4 {v0.4s-v3.4s}, \[x0\]
|
||||
134: 4c007800 st1 {v0.4s}, \[x0\]
|
||||
138: 4c00a800 st1 {v0.4s, v1.4s}, \[x0\]
|
||||
138: 4c00a800 st1 {v0.4s-v1.4s}, \[x0\]
|
||||
13c: 4c006800 st1 {v0.4s-v2.4s}, \[x0\]
|
||||
140: 4c002800 st1 {v0.4s-v3.4s}, \[x0\]
|
||||
144: 4c008800 st2 {v0.4s, v1.4s}, \[x0\]
|
||||
144: 4c008800 st2 {v0.4s-v1.4s}, \[x0\]
|
||||
148: 4c004800 st3 {v0.4s-v2.4s}, \[x0\]
|
||||
14c: 4c000800 st4 {v0.4s-v3.4s}, \[x0\]
|
||||
150: 4c407c00 ld1 {v0.2d}, \[x0\]
|
||||
154: 4c40ac00 ld1 {v0.2d, v1.2d}, \[x0\]
|
||||
154: 4c40ac00 ld1 {v0.2d-v1.2d}, \[x0\]
|
||||
158: 4c406c00 ld1 {v0.2d-v2.2d}, \[x0\]
|
||||
15c: 4c402c00 ld1 {v0.2d-v3.2d}, \[x0\]
|
||||
160: 4c408c00 ld2 {v0.2d, v1.2d}, \[x0\]
|
||||
160: 4c408c00 ld2 {v0.2d-v1.2d}, \[x0\]
|
||||
164: 4c404c00 ld3 {v0.2d-v2.2d}, \[x0\]
|
||||
168: 4c400c00 ld4 {v0.2d-v3.2d}, \[x0\]
|
||||
16c: 4c007c00 st1 {v0.2d}, \[x0\]
|
||||
170: 4c00ac00 st1 {v0.2d, v1.2d}, \[x0\]
|
||||
170: 4c00ac00 st1 {v0.2d-v1.2d}, \[x0\]
|
||||
174: 4c006c00 st1 {v0.2d-v2.2d}, \[x0\]
|
||||
178: 4c002c00 st1 {v0.2d-v3.2d}, \[x0\]
|
||||
17c: 4c008c00 st2 {v0.2d, v1.2d}, \[x0\]
|
||||
17c: 4c008c00 st2 {v0.2d-v1.2d}, \[x0\]
|
||||
180: 4c004c00 st3 {v0.2d-v2.2d}, \[x0\]
|
||||
184: 4c000c00 st4 {v0.2d-v3.2d}, \[x0\]
|
||||
188: 0d400400 ld1 {v0.b}\[1\], \[x0\]
|
||||
18c: 0d600400 ld2 {v0.b, v1.b}\[1\], \[x0\]
|
||||
18c: 0d600400 ld2 {v0.b-v1.b}\[1\], \[x0\]
|
||||
190: 0d402400 ld3 {v0.b-v2.b}\[1\], \[x0\]
|
||||
194: 0d602400 ld4 {v0.b-v3.b}\[1\], \[x0\]
|
||||
198: 0d000400 st1 {v0.b}\[1\], \[x0\]
|
||||
19c: 0d200400 st2 {v0.b, v1.b}\[1\], \[x0\]
|
||||
19c: 0d200400 st2 {v0.b-v1.b}\[1\], \[x0\]
|
||||
1a0: 0d002400 st3 {v0.b-v2.b}\[1\], \[x0\]
|
||||
1a4: 0d202400 st4 {v0.b-v3.b}\[1\], \[x0\]
|
||||
1a8: 0d400400 ld1 {v0.b}\[1\], \[x0\]
|
||||
1ac: 0d600400 ld2 {v0.b, v1.b}\[1\], \[x0\]
|
||||
1ac: 0d600400 ld2 {v0.b-v1.b}\[1\], \[x0\]
|
||||
1b0: 0d402400 ld3 {v0.b-v2.b}\[1\], \[x0\]
|
||||
1b4: 0d602400 ld4 {v0.b-v3.b}\[1\], \[x0\]
|
||||
1b8: 0d000400 st1 {v0.b}\[1\], \[x0\]
|
||||
1bc: 0d200400 st2 {v0.b, v1.b}\[1\], \[x0\]
|
||||
1bc: 0d200400 st2 {v0.b-v1.b}\[1\], \[x0\]
|
||||
1c0: 0d002400 st3 {v0.b-v2.b}\[1\], \[x0\]
|
||||
1c4: 0d202400 st4 {v0.b-v3.b}\[1\], \[x0\]
|
||||
1c8: 0d404800 ld1 {v0.h}\[1\], \[x0\]
|
||||
1cc: 0d604800 ld2 {v0.h, v1.h}\[1\], \[x0\]
|
||||
1cc: 0d604800 ld2 {v0.h-v1.h}\[1\], \[x0\]
|
||||
1d0: 0d406800 ld3 {v0.h-v2.h}\[1\], \[x0\]
|
||||
1d4: 0d606800 ld4 {v0.h-v3.h}\[1\], \[x0\]
|
||||
1d8: 0d004800 st1 {v0.h}\[1\], \[x0\]
|
||||
1dc: 0d204800 st2 {v0.h, v1.h}\[1\], \[x0\]
|
||||
1dc: 0d204800 st2 {v0.h-v1.h}\[1\], \[x0\]
|
||||
1e0: 0d006800 st3 {v0.h-v2.h}\[1\], \[x0\]
|
||||
1e4: 0d206800 st4 {v0.h-v3.h}\[1\], \[x0\]
|
||||
1e8: 0d404800 ld1 {v0.h}\[1\], \[x0\]
|
||||
1ec: 0d604800 ld2 {v0.h, v1.h}\[1\], \[x0\]
|
||||
1ec: 0d604800 ld2 {v0.h-v1.h}\[1\], \[x0\]
|
||||
1f0: 0d406800 ld3 {v0.h-v2.h}\[1\], \[x0\]
|
||||
1f4: 0d606800 ld4 {v0.h-v3.h}\[1\], \[x0\]
|
||||
1f8: 0d004800 st1 {v0.h}\[1\], \[x0\]
|
||||
1fc: 0d204800 st2 {v0.h, v1.h}\[1\], \[x0\]
|
||||
1fc: 0d204800 st2 {v0.h-v1.h}\[1\], \[x0\]
|
||||
200: 0d006800 st3 {v0.h-v2.h}\[1\], \[x0\]
|
||||
204: 0d206800 st4 {v0.h-v3.h}\[1\], \[x0\]
|
||||
208: 0d409000 ld1 {v0.s}\[1\], \[x0\]
|
||||
20c: 0d609000 ld2 {v0.s, v1.s}\[1\], \[x0\]
|
||||
20c: 0d609000 ld2 {v0.s-v1.s}\[1\], \[x0\]
|
||||
210: 0d40b000 ld3 {v0.s-v2.s}\[1\], \[x0\]
|
||||
214: 0d60b000 ld4 {v0.s-v3.s}\[1\], \[x0\]
|
||||
218: 0d009000 st1 {v0.s}\[1\], \[x0\]
|
||||
21c: 0d209000 st2 {v0.s, v1.s}\[1\], \[x0\]
|
||||
21c: 0d209000 st2 {v0.s-v1.s}\[1\], \[x0\]
|
||||
220: 0d00b000 st3 {v0.s-v2.s}\[1\], \[x0\]
|
||||
224: 0d20b000 st4 {v0.s-v3.s}\[1\], \[x0\]
|
||||
228: 0d409000 ld1 {v0.s}\[1\], \[x0\]
|
||||
22c: 0d609000 ld2 {v0.s, v1.s}\[1\], \[x0\]
|
||||
22c: 0d609000 ld2 {v0.s-v1.s}\[1\], \[x0\]
|
||||
230: 0d40b000 ld3 {v0.s-v2.s}\[1\], \[x0\]
|
||||
234: 0d60b000 ld4 {v0.s-v3.s}\[1\], \[x0\]
|
||||
238: 0d009000 st1 {v0.s}\[1\], \[x0\]
|
||||
23c: 0d209000 st2 {v0.s, v1.s}\[1\], \[x0\]
|
||||
23c: 0d209000 st2 {v0.s-v1.s}\[1\], \[x0\]
|
||||
240: 0d00b000 st3 {v0.s-v2.s}\[1\], \[x0\]
|
||||
244: 0d20b000 st4 {v0.s-v3.s}\[1\], \[x0\]
|
||||
248: 4d408400 ld1 {v0.d}\[1\], \[x0\]
|
||||
24c: 4d608400 ld2 {v0.d, v1.d}\[1\], \[x0\]
|
||||
24c: 4d608400 ld2 {v0.d-v1.d}\[1\], \[x0\]
|
||||
250: 4d40a400 ld3 {v0.d-v2.d}\[1\], \[x0\]
|
||||
254: 4d60a400 ld4 {v0.d-v3.d}\[1\], \[x0\]
|
||||
258: 4d008400 st1 {v0.d}\[1\], \[x0\]
|
||||
25c: 4d208400 st2 {v0.d, v1.d}\[1\], \[x0\]
|
||||
25c: 4d208400 st2 {v0.d-v1.d}\[1\], \[x0\]
|
||||
260: 4d00a400 st3 {v0.d-v2.d}\[1\], \[x0\]
|
||||
264: 4d20a400 st4 {v0.d-v3.d}\[1\], \[x0\]
|
||||
268: 0d40c000 ld1r {v0.8b}, \[x0\]
|
||||
26c: 0d60c000 ld2r {v0.8b, v1.8b}, \[x0\]
|
||||
26c: 0d60c000 ld2r {v0.8b-v1.8b}, \[x0\]
|
||||
270: 0d40e000 ld3r {v0.8b-v2.8b}, \[x0\]
|
||||
274: 0d60e000 ld4r {v0.8b-v3.8b}, \[x0\]
|
||||
278: 4d40c000 ld1r {v0.16b}, \[x0\]
|
||||
27c: 4d60c000 ld2r {v0.16b, v1.16b}, \[x0\]
|
||||
27c: 4d60c000 ld2r {v0.16b-v1.16b}, \[x0\]
|
||||
280: 4d40e000 ld3r {v0.16b-v2.16b}, \[x0\]
|
||||
284: 4d60e000 ld4r {v0.16b-v3.16b}, \[x0\]
|
||||
288: 0d40c400 ld1r {v0.4h}, \[x0\]
|
||||
28c: 0d60c400 ld2r {v0.4h, v1.4h}, \[x0\]
|
||||
28c: 0d60c400 ld2r {v0.4h-v1.4h}, \[x0\]
|
||||
290: 0d40e400 ld3r {v0.4h-v2.4h}, \[x0\]
|
||||
294: 0d60e400 ld4r {v0.4h-v3.4h}, \[x0\]
|
||||
298: 4d40c400 ld1r {v0.8h}, \[x0\]
|
||||
29c: 4d60c400 ld2r {v0.8h, v1.8h}, \[x0\]
|
||||
29c: 4d60c400 ld2r {v0.8h-v1.8h}, \[x0\]
|
||||
2a0: 4d40e400 ld3r {v0.8h-v2.8h}, \[x0\]
|
||||
2a4: 4d60e400 ld4r {v0.8h-v3.8h}, \[x0\]
|
||||
2a8: 0d40c800 ld1r {v0.2s}, \[x0\]
|
||||
2ac: 0d60c800 ld2r {v0.2s, v1.2s}, \[x0\]
|
||||
2ac: 0d60c800 ld2r {v0.2s-v1.2s}, \[x0\]
|
||||
2b0: 0d40e800 ld3r {v0.2s-v2.2s}, \[x0\]
|
||||
2b4: 0d60e800 ld4r {v0.2s-v3.2s}, \[x0\]
|
||||
2b8: 4d40c800 ld1r {v0.4s}, \[x0\]
|
||||
2bc: 4d60c800 ld2r {v0.4s, v1.4s}, \[x0\]
|
||||
2bc: 4d60c800 ld2r {v0.4s-v1.4s}, \[x0\]
|
||||
2c0: 4d40e800 ld3r {v0.4s-v2.4s}, \[x0\]
|
||||
2c4: 4d60e800 ld4r {v0.4s-v3.4s}, \[x0\]
|
||||
2c8: 0d40cc00 ld1r {v0.1d}, \[x0\]
|
||||
2cc: 0d60cc00 ld2r {v0.1d, v1.1d}, \[x0\]
|
||||
2cc: 0d60cc00 ld2r {v0.1d-v1.1d}, \[x0\]
|
||||
2d0: 0d40ec00 ld3r {v0.1d-v2.1d}, \[x0\]
|
||||
2d4: 0d60ec00 ld4r {v0.1d-v3.1d}, \[x0\]
|
||||
2d8: 4d40cc00 ld1r {v0.2d}, \[x0\]
|
||||
2dc: 4d60cc00 ld2r {v0.2d, v1.2d}, \[x0\]
|
||||
2dc: 4d60cc00 ld2r {v0.2d-v1.2d}, \[x0\]
|
||||
2e0: 4d40ec00 ld3r {v0.2d-v2.2d}, \[x0\]
|
||||
2e4: 4d60ec00 ld4r {v0.2d-v3.2d}, \[x0\]
|
||||
|
||||
21
gas/testsuite/gas/aarch64/reglist-1.d
Normal file
21
gas/testsuite/gas/aarch64/reglist-1.d
Normal file
@ -0,0 +1,21 @@
|
||||
#as: -march=armv8-a+sve
|
||||
#objdump: -dr
|
||||
|
||||
[^:]+: file format .*
|
||||
|
||||
|
||||
[^:]+:
|
||||
|
||||
[^:]+:
|
||||
[^:]+: 4c40ac1f ld1 {v31\.2d-v0\.2d}, \[x0\]
|
||||
[^:]+: 4c40681f ld1 {v31\.4s-v1\.4s}, \[x0\]
|
||||
[^:]+: 4c40241f ld1 {v31\.8h-v2\.8h}, \[x0\]
|
||||
[^:]+: 4c40201e ld1 {v30\.16b-v1\.16b}, \[x0\]
|
||||
[^:]+: 0c40601e ld1 {v30\.8b-v0\.8b}, \[x0\]
|
||||
[^:]+: 0c40241d ld1 {v29\.4h-v0\.4h}, \[x0\]
|
||||
[^:]+: a420e01f ld2b {z31\.b-z0\.b}, p0/z, \[x0\]
|
||||
[^:]+: a440e01e ld3b {z30\.b-z0\.b}, p0/z, \[x0\]
|
||||
[^:]+: a440e01f ld3b {z31\.b-z1\.b}, p0/z, \[x0\]
|
||||
[^:]+: a460e01d ld4b {z29\.b-z0\.b}, p0/z, \[x0\]
|
||||
[^:]+: a460e01e ld4b {z30\.b-z1\.b}, p0/z, \[x0\]
|
||||
[^:]+: a460e01f ld4b {z31\.b-z2\.b}, p0/z, \[x0\]
|
||||
15
gas/testsuite/gas/aarch64/reglist-1.s
Normal file
15
gas/testsuite/gas/aarch64/reglist-1.s
Normal file
@ -0,0 +1,15 @@
|
||||
ld1 { v31.2d - v0.2d }, [x0]
|
||||
ld1 { v31.4s - v1.4s }, [x0]
|
||||
ld1 { v31.8h - v2.8h }, [x0]
|
||||
ld1 { v30.16b - v1.16b }, [x0]
|
||||
ld1 { v30.8b - v0.8b }, [x0]
|
||||
ld1 { v29.4h - v0.4h }, [x0]
|
||||
|
||||
ld2b { z31.b - z0.b }, p0/z, [x0]
|
||||
|
||||
ld3b { z30.b - z0.b }, p0/z, [x0]
|
||||
ld3b { z31.b - z1.b }, p0/z, [x0]
|
||||
|
||||
ld4b { z29.b - z0.b }, p0/z, [x0]
|
||||
ld4b { z30.b - z1.b }, p0/z, [x0]
|
||||
ld4b { z31.b - z2.b }, p0/z, [x0]
|
||||
3
gas/testsuite/gas/aarch64/reglist-2.d
Normal file
3
gas/testsuite/gas/aarch64/reglist-2.d
Normal file
@ -0,0 +1,3 @@
|
||||
#as: -march=armv8-a
|
||||
#source: reglist-2.s
|
||||
#error_output: reglist-2.l
|
||||
8
gas/testsuite/gas/aarch64/reglist-2.l
Normal file
8
gas/testsuite/gas/aarch64/reglist-2.l
Normal file
@ -0,0 +1,8 @@
|
||||
[^ :]+: Assembler messages:
|
||||
[^ :]+:[0-9]+: Error: too many registers in vector register list at operand 1 -- `ld1 {v1\.2d-v0\.2d},\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: too many registers in vector register list at operand 1 -- `ld1 {v31\.2d-v3\.2d},\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: too many registers in vector register list at operand 1 -- `ld1 {v30\.2d-v2\.2d},\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: too many registers in vector register list at operand 1 -- `ld1 {v29\.2d-v1\.2d},\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: too many registers in vector register list at operand 1 -- `ld1 {v31\.2d-v30\.2d},\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: invalid range in vector register list at operand 1 -- `ld1 {v0\.2d-v0\.2d},\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: invalid range in vector register list at operand 1 -- `ld1 {v31\.2d-v31\.2d},\[x0\]'
|
||||
7
gas/testsuite/gas/aarch64/reglist-2.s
Normal file
7
gas/testsuite/gas/aarch64/reglist-2.s
Normal file
@ -0,0 +1,7 @@
|
||||
ld1 { v1.2d - v0.2d }, [x0]
|
||||
ld1 { v31.2d - v3.2d }, [x0]
|
||||
ld1 { v30.2d - v2.2d }, [x0]
|
||||
ld1 { v29.2d - v1.2d }, [x0]
|
||||
ld1 { v31.2d - v30.2d }, [x0]
|
||||
ld1 { v0.2d - v0.2d }, [x0]
|
||||
ld1 { v31.2d - v31.2d }, [x0]
|
||||
File diff suppressed because it is too large
Load Diff
@ -113,9 +113,9 @@ Disassembly of section \.text:
|
||||
*[0-9a-f]+: 45409400 eortb z0\.h, z0\.h, z0\.h
|
||||
*[0-9a-f]+: 45809400 eortb z0\.s, z0\.s, z0\.s
|
||||
*[0-9a-f]+: 45c09400 eortb z0\.d, z0\.d, z0\.d
|
||||
*[0-9a-f]+: 057b16b1 ext z17\.b, {z21\.b, z22\.b}, #221
|
||||
*[0-9a-f]+: 05600000 ext z0\.b, {z0\.b, z1\.b}, #0
|
||||
*[0-9a-f]+: 056003e0 ext z0\.b, {z31\.b, z0\.b}, #0
|
||||
*[0-9a-f]+: 057b16b1 ext z17\.b, {z21\.b-z22\.b}, #221
|
||||
*[0-9a-f]+: 05600000 ext z0\.b, {z0\.b-z1\.b}, #0
|
||||
*[0-9a-f]+: 056003e0 ext z0\.b, {z31\.b-z0\.b}, #0
|
||||
*[0-9a-f]+: 645096b1 faddp z17\.h, p5/m, z17\.h, z21\.h
|
||||
*[0-9a-f]+: 64508000 faddp z0\.h, p0/m, z0\.h, z0\.h
|
||||
*[0-9a-f]+: 64908000 faddp z0\.s, p0/m, z0\.s, z0\.s
|
||||
@ -480,12 +480,12 @@ Disassembly of section \.text:
|
||||
*[0-9a-f]+: 45407400 smullt z0\.h, z0\.b, z0\.b
|
||||
*[0-9a-f]+: 45807400 smullt z0\.s, z0\.h, z0\.h
|
||||
*[0-9a-f]+: 45c07400 smullt z0\.d, z0\.s, z0\.s
|
||||
*[0-9a-f]+: 052d96b1 splice z17\.b, p5, {z21\.b, z22\.b}
|
||||
*[0-9a-f]+: 052d8000 splice z0\.b, p0, {z0\.b, z1\.b}
|
||||
*[0-9a-f]+: 056d8000 splice z0\.h, p0, {z0\.h, z1\.h}
|
||||
*[0-9a-f]+: 05ad8000 splice z0\.s, p0, {z0\.s, z1\.s}
|
||||
*[0-9a-f]+: 05ed8000 splice z0\.d, p0, {z0\.d, z1\.d}
|
||||
*[0-9a-f]+: 052d83e0 splice z0\.b, p0, {z31\.b, z0\.b}
|
||||
*[0-9a-f]+: 052d96b1 splice z17\.b, p5, {z21\.b-z22\.b}
|
||||
*[0-9a-f]+: 052d8000 splice z0\.b, p0, {z0\.b-z1\.b}
|
||||
*[0-9a-f]+: 056d8000 splice z0\.h, p0, {z0\.h-z1\.h}
|
||||
*[0-9a-f]+: 05ad8000 splice z0\.s, p0, {z0\.s-z1\.s}
|
||||
*[0-9a-f]+: 05ed8000 splice z0\.d, p0, {z0\.d-z1\.d}
|
||||
*[0-9a-f]+: 052d83e0 splice z0\.b, p0, {z31\.b-z0\.b}
|
||||
*[0-9a-f]+: 4408b6b1 sqabs z17\.b, p5/m, z21\.b
|
||||
*[0-9a-f]+: 4408a000 sqabs z0\.b, p0/m, z0\.b
|
||||
*[0-9a-f]+: 4448a000 sqabs z0\.h, p0/m, z0\.h
|
||||
@ -915,12 +915,12 @@ Disassembly of section \.text:
|
||||
*[0-9a-f]+: 445c8000 suqadd z0\.h, p0/m, z0\.h, z0\.h
|
||||
*[0-9a-f]+: 449c8000 suqadd z0\.s, p0/m, z0\.s, z0\.s
|
||||
*[0-9a-f]+: 44dc8000 suqadd z0\.d, p0/m, z0\.d, z0\.d
|
||||
*[0-9a-f]+: 053b2ab1 tbl z17\.b, {z21\.b, z22\.b}, z27\.b
|
||||
*[0-9a-f]+: 05202800 tbl z0\.b, {z0\.b, z1\.b}, z0\.b
|
||||
*[0-9a-f]+: 05602800 tbl z0\.h, {z0\.h, z1\.h}, z0\.h
|
||||
*[0-9a-f]+: 05a02800 tbl z0\.s, {z0\.s, z1\.s}, z0\.s
|
||||
*[0-9a-f]+: 05e02800 tbl z0\.d, {z0\.d, z1\.d}, z0\.d
|
||||
*[0-9a-f]+: 05202be0 tbl z0\.b, {z31\.b, z0\.b}, z0\.b
|
||||
*[0-9a-f]+: 053b2ab1 tbl z17\.b, {z21\.b-z22\.b}, z27\.b
|
||||
*[0-9a-f]+: 05202800 tbl z0\.b, {z0\.b-z1\.b}, z0\.b
|
||||
*[0-9a-f]+: 05602800 tbl z0\.h, {z0\.h-z1\.h}, z0\.h
|
||||
*[0-9a-f]+: 05a02800 tbl z0\.s, {z0\.s-z1\.s}, z0\.s
|
||||
*[0-9a-f]+: 05e02800 tbl z0\.d, {z0\.d-z1\.d}, z0\.d
|
||||
*[0-9a-f]+: 05202be0 tbl z0\.b, {z31\.b-z0\.b}, z0\.b
|
||||
*[0-9a-f]+: 053b2eb1 tbx z17\.b, z21\.b, z27\.b
|
||||
*[0-9a-f]+: 05202c00 tbx z0\.b, z0\.b, z0\.b
|
||||
*[0-9a-f]+: 05602c00 tbx z0\.h, z0\.h, z0\.h
|
||||
|
||||
@ -3246,7 +3246,7 @@ print_register_list (char *buf, size_t size, const aarch64_opnd_info *opnd,
|
||||
/* The hyphenated form is preferred for disassembly if there are
|
||||
more than two registers in the list, and the register numbers
|
||||
are monotonically increasing in increments of one. */
|
||||
if (stride == 1 && num_regs > 2 && last_reg > first_reg)
|
||||
if (stride == 1 && num_regs > 1)
|
||||
snprintf (buf, size, "{%s-%s}%s",
|
||||
style_reg (styler, "%s%d.%s", prefix, first_reg, qlf_name),
|
||||
style_reg (styler, "%s%d.%s", prefix, last_reg, qlf_name), tb);
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user