aarch64: rcpc3: New RCPC3_ADDR operand types

The particular choices of address indexing, along with their encoding
for RCPC3 instructions lead to the requirement of a new set of operand
descriptions, along with the relevant inserter/extractor set.

That is, for the integer load/stores, there is only a single valid
indexing offset quantity and offset mode is allowed - The value is
always equivalent to the amount of data read/stored by the
operation and the offset is post-indexed for Load-Acquire RCpc, and
pre-indexed with writeback for Store-Release insns.

This indexing quantity/mode pair is selected by the setting of a
single bit in the instruction. To represent these insns, we add the
following operand types:

  - AARCH64_OPND_RCPC3_ADDR_OPT_POSTIND
  - AARCH64_OPND_RCPC3_ADDR_OPT_PREIND_WB

In the case of loads and stores involving SIMD/FP registers, the
optional offset is encoded as an 8-bit signed immediate, but neither
post-indexing or pre-indexing with writeback is available.  This
created the need for an operand type similar to
AARCH64_OPND_ADDR_OFFSET, with the difference that FLD_index should
not be checked.

We thus introduce the AARCH64_OPND_RCPC3_ADDR_OFFSET operand, a
variant of AARCH64_OPND_ADDR_OFFSET, w/o the FLD_index bitfield.

include/opcode/aarch64.h

@@ -799,6 +799,11 @@ enum aarch64_opnd
   AARCH64_OPND_SME_Zt2,		/* Qobule SVE vector register list.  */
   AARCH64_OPND_SME_Zt3,		/* Trible SVE vector register list.  */
   AARCH64_OPND_SME_Zt4,		/* Quad SVE vector register list.  */
+  AARCH64_OPND_RCPC3_ADDR_OPT_POSTIND,   /* [<Xn|SP>]{, #<imm>}.  */
+  AARCH64_OPND_RCPC3_ADDR_OPT_PREIND_WB, /* [<Xn|SP>] or [<Xn|SP>, #<imm>]!.  */
+  AARCH64_OPND_RCPC3_ADDR_POSTIND,	 /* [<Xn|SP>], #<imm>.  */
+  AARCH64_OPND_RCPC3_ADDR_PREIND_WB, 	 /* [<Xn|SP>, #<imm>]!.  */
+  AARCH64_OPND_RCPC3_ADDR_OFFSET
 };
 
 /* Qualifier constrains an operand.  It either specifies a variant of an