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aarch64: Apply narrowing of allowed immediate values for SYSP

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While CRn and CRm fields in the SYSP instruction are 4-bit wide and
are thus able to accommodate values in the range 0-15, the
specifications for the SYSP instructions limit their ranges to 8-9 for
CRm and 0-7 in the case of CRn.

This led to the need to signal in some way to the operand parser that
a given operand is under special restrictions regarding its use.  This
is done via the new `F_OPD_NARROW' flag, indicating a narrowing in the
range of operand values for fields in the instruction tagged with the
flag.

The flag is then used in `parse_operands' when the instruction is
assembled, but needs not be taken into consideration during
disassembly.
This commit is contained in:
Victor Do Nascimento
2023-11-20 15:32:15 +00:00
parent 3521a28f10
commit 5517af8298
6 changed files with 41 additions and 3 deletions
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include/opcode/aarch64.h
+6 -1
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@@ -1224,7 +1224,12 @@ extern const aarch64_opcode aarch64_opcode_table[];
to be optional, then we also implicitly specify (N+1)th operand to also be
optional. */
#define F_OPD_PAIR_OPT (1ULL << 32)
/* Next bit is 33. */
/* This instruction does not allow the full range of values that the
width of fields in the assembler instruction would theoretically
allow. This impacts the constraintts on assembly but yelds no
impact on disassembly. */
#define F_OPD_NARROW (1ULL << 33)
/* Next bit is 34. */
/* Instruction constraints. */
/* This instruction has a predication constraint on the instruction at PC+4. */