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x86: Support Intel AVX VNNI

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Intel AVX VNNI instructions are marked with CpuVEX_PREFIX.  Without the
pseudo {vex} prefix, mnemonics of Intel VNNI instructions are encoded
with the EVEX prefix.  The pseudo {vex} prefix can be used to encode
mnemonics of Intel VNNI instructions with the VEX prefix.

gas/

	* NEWS: Add Intel AVX VNNI.
	* config/tc-i386.c (cpu_arch): Add .avx_vnni and noavx_vnni.
	(cpu_flags_match): Support CpuVEX_PREFIX.
	* doc/c-i386.texi: Document .avx_vnni, noavx_vnni and how to
	encode Intel VNNI instructions with VEX prefix.
	* testsuite/gas/i386/avx-vnni.d: New file.
	* testsuite/gas/i386/avx-vnni.s: Likewise.
	* testsuite/gas/i386/x86-64-avx-vnni.d: Likewise.
	* testsuite/gas/i386/x86-64-avx-vnni.s: Likewise.
	* testsuite/gas/i386/i386.exp: Run AVX VNNI tests.

opcodes/

	* i386-dis.c (PREFIX_VEX_0F3850): New.
	(PREFIX_VEX_0F3851): Likewise.
	(PREFIX_VEX_0F3852): Likewise.
	(PREFIX_VEX_0F3853): Likewise.
	(VEX_W_0F3850_P_2): Likewise.
	(VEX_W_0F3851_P_2): Likewise.
	(VEX_W_0F3852_P_2): Likewise.
	(VEX_W_0F3853_P_2): Likewise.
	(prefix_table): Add PREFIX_VEX_0F3850, PREFIX_VEX_0F3851,
	PREFIX_VEX_0F3852 and PREFIX_VEX_0F3853.
	(vex_table): Add VEX_W_0F3850_P_2, VEX_W_0F3851_P_2,
	VEX_W_0F3852_P_2 and VEX_W_0F3853_P_2.
	(putop): Add support for "XV" to print "{vex3}" pseudo prefix.
	* i386-gen.c (cpu_flag_init): Clear the CpuAVX_VNNI bit in
	CPU_UNKNOWN_FLAGS.  Add CPU_AVX_VNNI_FLAGS and
	CPU_ANY_AVX_VNNI_FLAGS.
	(cpu_flags): Add CpuAVX_VNNI and CpuVEX_PREFIX.
	* i386-opc.h (CpuAVX_VNNI): New.
	(CpuVEX_PREFIX): Likewise.
	(i386_cpu_flags): Add cpuavx_vnni and cpuvex_prefix.
	* i386-opc.tbl: Add Intel AVX VNNI instructions.
	* i386-init.h: Regenerated.
	* i386-tbl.h: Likewise.
This commit is contained in:
H.J. Lu 2020-10-14 05:02:13 -07:00
parent c1fa250ae1
commit 58bf9b6a7f
16 changed files with 4876 additions and 4541 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

14
gas/ChangeLog
View File

@ -1,3 +1,17 @@
2020-10-14 H.J. Lu <hongjiu.lu@intel.com>
Lili Cui <lili.cui@intel.com>
* NEWS: Add Intel AVX VNNI.
* config/tc-i386.c (cpu_arch): Add .avx_vnni and noavx_vnni.
(cpu_flags_match): Support CpuVEX_PREFIX.
* doc/c-i386.texi: Document .avx_vnni, noavx_vnni and how to
encode Intel VNNI instructions with VEX prefix.
* testsuite/gas/i386/avx-vnni.d: New file.
* testsuite/gas/i386/avx-vnni.s: Likewise.
* testsuite/gas/i386/x86-64-avx-vnni.d: Likewise.
* testsuite/gas/i386/x86-64-avx-vnni.s: Likewise.
* testsuite/gas/i386/i386.exp: Run AVX VNNI tests.
2020-10-14 Lili Cui <lili.cui@intel.com>
* NEWS: Add Intel HRESET.

2
gas/NEWS
View File

@ -1,5 +1,7 @@
-*- text -*-
* Add support for Intel AVX VNNI instructions.
* Add support for Intel HRESET instruction.
* Add support for Intel UINTR instructions.

12
gas/config/tc-i386.c
View File

@ -1180,6 +1180,8 @@ static const arch_entry cpu_arch[] =
CPU_AVX512_VNNI_FLAGS, 0 },
{ STRING_COMMA_LEN (".avx512_bitalg"), PROCESSOR_UNKNOWN,
CPU_AVX512_BITALG_FLAGS, 0 },
{ STRING_COMMA_LEN (".avx_vnni"), PROCESSOR_UNKNOWN,
CPU_AVX_VNNI_FLAGS, 0 },
{ STRING_COMMA_LEN (".clzero"), PROCESSOR_UNKNOWN,
CPU_CLZERO_FLAGS, 0 },
{ STRING_COMMA_LEN (".mwaitx"), PROCESSOR_UNKNOWN,
@ -1280,6 +1282,7 @@ static const noarch_entry cpu_noarch[] =
{ STRING_COMMA_LEN ("noavx512_vbmi2"), CPU_ANY_AVX512_VBMI2_FLAGS },
{ STRING_COMMA_LEN ("noavx512_vnni"), CPU_ANY_AVX512_VNNI_FLAGS },
{ STRING_COMMA_LEN ("noavx512_bitalg"), CPU_ANY_AVX512_BITALG_FLAGS },
{ STRING_COMMA_LEN ("noavx_vnni"), CPU_ANY_AVX_VNNI_FLAGS },
{ STRING_COMMA_LEN ("noibt"), CPU_ANY_IBT_FLAGS },
{ STRING_COMMA_LEN ("noshstk"), CPU_ANY_SHSTK_FLAGS },
{ STRING_COMMA_LEN ("noamx_int8"), CPU_ANY_AMX_INT8_FLAGS },
@ -1970,7 +1973,14 @@ cpu_flags_match (const insn_template *t)
cpu = cpu_flags_and (x, cpu);
if (!cpu_flags_all_zero (&cpu))
{
if (x.bitfield.cpuavx)
if (x.bitfield.cpuvex_prefix)
{
/* We need to check a few extra flags with VEX_PREFIX. */
if (i.vec_encoding == vex_encoding_vex
|| i.vec_encoding == vex_encoding_vex3)
match |= CPU_FLAGS_ARCH_MATCH;
}
else if (x.bitfield.cpuavx)
{
/* We need to check a few extra flags with AVX. */
if (cpu.bitfield.cpuavx

8
gas/doc/c-i386.texi
View File

@ -212,6 +212,7 @@ accept various extension mnemonics. For example,
@code{avx512_vp2intersect},
@code{tdx},
@code{avx512_bf16},
@code{avx_vnni},
@code{noavx512f},
@code{noavx512cd},
@code{noavx512er},
@ -230,6 +231,7 @@ accept various extension mnemonics. For example,
@code{noavx512_vp2intersect},
@code{notdx},
@code{noavx512_bf16},
@code{noavx_vnni},
@code{noenqcmd},
@code{noserialize},
@code{notsxldtrk},
@ -861,6 +863,10 @@ prefix which generates REX prefix unconditionally.
@samp{@{nooptimize@}} -- disable instruction size optimization.
@end itemize
Mnemonics of Intel VNNI instructions are encoded with the EVEX prefix
by default. The pseudo @samp{@{vex@}} prefix can be used to encode
mnemonics of Intel VNNI instructions with the VEX prefix.
@cindex conversion instructions, i386
@cindex i386 conversion instructions
@cindex conversion instructions, x86-64
@ -1509,7 +1515,7 @@ supported on the CPU specified. The choices for @var{cpu_type} are:
@item @samp{.avx512vbmi} @tab @samp{.avx512_4fmaps} @tab @samp{.avx512_4vnniw}
@item @samp{.avx512_vpopcntdq} @tab @samp{.avx512_vbmi2} @tab @samp{.avx512_vnni}
@item @samp{.avx512_bitalg} @tab @samp{.avx512_bf16} @tab @samp{.avx512_vp2intersect}
@item @samp{.tdx}
@item @samp{.tdx} @tab @samp{.avx_vnni}
@item @samp{.clwb} @tab @samp{.rdpid} @tab @samp{.ptwrite} @tab @item @samp{.ibt}
@item @samp{.wbnoinvd} @tab @samp{.pconfig} @tab @samp{.waitpkg} @tab @samp{.cldemote}
@item @samp{.shstk} @tab @samp{.gfni} @tab @samp{.vaes} @tab @samp{.vpclmulqdq}

43
gas/testsuite/gas/i386/avx-vnni.d Normal file
View File

@ -0,0 +1,43 @@
#objdump: -dw
#name: i386 AVX VNNI insns
.*: +file format .*
Disassembly of section .text:
0+ <_start>:
+[a-f0-9]+: 62 f2 5d 08 50 d2 vpdpbusd %xmm2,%xmm4,%xmm2
+[a-f0-9]+: 62 f2 5d 08 50 d2 vpdpbusd %xmm2,%xmm4,%xmm2
+[a-f0-9]+: c4 e2 59 50 d2 \{vex3\} vpdpbusd %xmm2,%xmm4,%xmm2
+[a-f0-9]+: c4 e2 59 50 d2 \{vex3\} vpdpbusd %xmm2,%xmm4,%xmm2
+[a-f0-9]+: c4 e2 59 50 d2 \{vex3\} vpdpbusd %xmm2,%xmm4,%xmm2
+[a-f0-9]+: c4 e2 59 50 11 \{vex3\} vpdpbusd \(%ecx\),%xmm4,%xmm2
+[a-f0-9]+: c4 e2 59 50 11 \{vex3\} vpdpbusd \(%ecx\),%xmm4,%xmm2
+[a-f0-9]+: c4 e2 59 50 11 \{vex3\} vpdpbusd \(%ecx\),%xmm4,%xmm2
+[a-f0-9]+: 62 f2 5d 08 52 d2 vpdpwssd %xmm2,%xmm4,%xmm2
+[a-f0-9]+: 62 f2 5d 08 52 d2 vpdpwssd %xmm2,%xmm4,%xmm2
+[a-f0-9]+: c4 e2 59 52 d2 \{vex3\} vpdpwssd %xmm2,%xmm4,%xmm2
+[a-f0-9]+: c4 e2 59 52 d2 \{vex3\} vpdpwssd %xmm2,%xmm4,%xmm2
+[a-f0-9]+: c4 e2 59 52 d2 \{vex3\} vpdpwssd %xmm2,%xmm4,%xmm2
+[a-f0-9]+: c4 e2 59 52 11 \{vex3\} vpdpwssd \(%ecx\),%xmm4,%xmm2
+[a-f0-9]+: c4 e2 59 52 11 \{vex3\} vpdpwssd \(%ecx\),%xmm4,%xmm2
+[a-f0-9]+: c4 e2 59 52 11 \{vex3\} vpdpwssd \(%ecx\),%xmm4,%xmm2
+[a-f0-9]+: 62 f2 5d 08 51 d2 vpdpbusds %xmm2,%xmm4,%xmm2
+[a-f0-9]+: 62 f2 5d 08 51 d2 vpdpbusds %xmm2,%xmm4,%xmm2
+[a-f0-9]+: c4 e2 59 51 d2 \{vex3\} vpdpbusds %xmm2,%xmm4,%xmm2
+[a-f0-9]+: c4 e2 59 51 d2 \{vex3\} vpdpbusds %xmm2,%xmm4,%xmm2
+[a-f0-9]+: c4 e2 59 51 d2 \{vex3\} vpdpbusds %xmm2,%xmm4,%xmm2
+[a-f0-9]+: c4 e2 59 51 11 \{vex3\} vpdpbusds \(%ecx\),%xmm4,%xmm2
+[a-f0-9]+: c4 e2 59 51 11 \{vex3\} vpdpbusds \(%ecx\),%xmm4,%xmm2
+[a-f0-9]+: c4 e2 59 51 11 \{vex3\} vpdpbusds \(%ecx\),%xmm4,%xmm2
+[a-f0-9]+: 62 f2 5d 08 53 d2 vpdpwssds %xmm2,%xmm4,%xmm2
+[a-f0-9]+: 62 f2 5d 08 53 d2 vpdpwssds %xmm2,%xmm4,%xmm2
+[a-f0-9]+: c4 e2 59 53 d2 \{vex3\} vpdpwssds %xmm2,%xmm4,%xmm2
+[a-f0-9]+: c4 e2 59 53 d2 \{vex3\} vpdpwssds %xmm2,%xmm4,%xmm2
+[a-f0-9]+: c4 e2 59 53 d2 \{vex3\} vpdpwssds %xmm2,%xmm4,%xmm2
+[a-f0-9]+: c4 e2 59 53 11 \{vex3\} vpdpwssds \(%ecx\),%xmm4,%xmm2
+[a-f0-9]+: c4 e2 59 53 11 \{vex3\} vpdpwssds \(%ecx\),%xmm4,%xmm2
+[a-f0-9]+: c4 e2 59 53 11 \{vex3\} vpdpwssds \(%ecx\),%xmm4,%xmm2
+[a-f0-9]+: 62 f2 5d 08 50 d2 vpdpbusd %xmm2,%xmm4,%xmm2
#pass

22
gas/testsuite/gas/i386/avx-vnni.s Normal file
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@ -0,0 +1,22 @@
.allow_index_reg
.macro test_insn mnemonic
\mnemonic %xmm2, %xmm4, %xmm2
{evex} \mnemonic %xmm2, %xmm4, %xmm2
{vex} \mnemonic %xmm2, %xmm4, %xmm2
{vex2} \mnemonic %xmm2, %xmm4, %xmm2
{vex3} \mnemonic %xmm2, %xmm4, %xmm2
{vex} \mnemonic (%ecx), %xmm4, %xmm2
{vex2} \mnemonic (%ecx), %xmm4, %xmm2
{vex3} \mnemonic (%ecx), %xmm4, %xmm2
.endm
.text
_start:
test_insn vpdpbusd
test_insn vpdpwssd
test_insn vpdpbusds
test_insn vpdpwssds
.arch .avx_vnni
vpdpbusd %xmm2, %xmm4, %xmm2

2
gas/testsuite/gas/i386/i386.exp
View File

@ -458,6 +458,7 @@ if [gas_32_check] then {
run_dump_test "avx512_bf16"
run_dump_test "avx512_bf16_vl"
run_list_test "avx512_bf16_vl-inval"
run_dump_test "avx-vnni"
run_list_test "sg"
run_dump_test "clzero"
run_dump_test "disassem"
@ -1075,6 +1076,7 @@ if [gas_64_check] then {
run_dump_test "x86-64-avx512_bf16"
run_dump_test "x86-64-avx512_bf16_vl"
run_list_test "x86-64-avx512_bf16_vl-inval"
run_dump_test "x86-64-avx-vnni"
run_dump_test "x86-64-clzero"
run_dump_test "x86-64-mwaitx-bdver4"
run_list_test "x86-64-mwaitx-reg"

47
gas/testsuite/gas/i386/x86-64-avx-vnni.d Normal file
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@ -0,0 +1,47 @@
#objdump: -dw
#name: x86-64 AVX VNNI insns
.*: +file format .*
Disassembly of section .text:
0+ <_start>:
+[a-f0-9]+: 62 d2 5d 08 50 d4 vpdpbusd %xmm12,%xmm4,%xmm2
+[a-f0-9]+: 62 d2 5d 08 50 d4 vpdpbusd %xmm12,%xmm4,%xmm2
+[a-f0-9]+: c4 c2 59 50 d4 \{vex3\} vpdpbusd %xmm12,%xmm4,%xmm2
+[a-f0-9]+: c4 c2 59 50 d4 \{vex3\} vpdpbusd %xmm12,%xmm4,%xmm2
+[a-f0-9]+: c4 c2 59 50 d4 \{vex3\} vpdpbusd %xmm12,%xmm4,%xmm2
+[a-f0-9]+: c4 e2 59 50 11 \{vex3\} vpdpbusd \(%rcx\),%xmm4,%xmm2
+[a-f0-9]+: c4 e2 59 50 11 \{vex3\} vpdpbusd \(%rcx\),%xmm4,%xmm2
+[a-f0-9]+: c4 e2 59 50 11 \{vex3\} vpdpbusd \(%rcx\),%xmm4,%xmm2
+[a-f0-9]+: 62 b2 5d 08 50 d6 vpdpbusd %xmm22,%xmm4,%xmm2
+[a-f0-9]+: 62 d2 5d 08 52 d4 vpdpwssd %xmm12,%xmm4,%xmm2
+[a-f0-9]+: 62 d2 5d 08 52 d4 vpdpwssd %xmm12,%xmm4,%xmm2
+[a-f0-9]+: c4 c2 59 52 d4 \{vex3\} vpdpwssd %xmm12,%xmm4,%xmm2
+[a-f0-9]+: c4 c2 59 52 d4 \{vex3\} vpdpwssd %xmm12,%xmm4,%xmm2
+[a-f0-9]+: c4 c2 59 52 d4 \{vex3\} vpdpwssd %xmm12,%xmm4,%xmm2
+[a-f0-9]+: c4 e2 59 52 11 \{vex3\} vpdpwssd \(%rcx\),%xmm4,%xmm2
+[a-f0-9]+: c4 e2 59 52 11 \{vex3\} vpdpwssd \(%rcx\),%xmm4,%xmm2
+[a-f0-9]+: c4 e2 59 52 11 \{vex3\} vpdpwssd \(%rcx\),%xmm4,%xmm2
+[a-f0-9]+: 62 b2 5d 08 52 d6 vpdpwssd %xmm22,%xmm4,%xmm2
+[a-f0-9]+: 62 d2 5d 08 51 d4 vpdpbusds %xmm12,%xmm4,%xmm2
+[a-f0-9]+: 62 d2 5d 08 51 d4 vpdpbusds %xmm12,%xmm4,%xmm2
+[a-f0-9]+: c4 c2 59 51 d4 \{vex3\} vpdpbusds %xmm12,%xmm4,%xmm2
+[a-f0-9]+: c4 c2 59 51 d4 \{vex3\} vpdpbusds %xmm12,%xmm4,%xmm2
+[a-f0-9]+: c4 c2 59 51 d4 \{vex3\} vpdpbusds %xmm12,%xmm4,%xmm2
+[a-f0-9]+: c4 e2 59 51 11 \{vex3\} vpdpbusds \(%rcx\),%xmm4,%xmm2
+[a-f0-9]+: c4 e2 59 51 11 \{vex3\} vpdpbusds \(%rcx\),%xmm4,%xmm2
+[a-f0-9]+: c4 e2 59 51 11 \{vex3\} vpdpbusds \(%rcx\),%xmm4,%xmm2
+[a-f0-9]+: 62 b2 5d 08 51 d6 vpdpbusds %xmm22,%xmm4,%xmm2
+[a-f0-9]+: 62 d2 5d 08 53 d4 vpdpwssds %xmm12,%xmm4,%xmm2
+[a-f0-9]+: 62 d2 5d 08 53 d4 vpdpwssds %xmm12,%xmm4,%xmm2
+[a-f0-9]+: c4 c2 59 53 d4 \{vex3\} vpdpwssds %xmm12,%xmm4,%xmm2
+[a-f0-9]+: c4 c2 59 53 d4 \{vex3\} vpdpwssds %xmm12,%xmm4,%xmm2
+[a-f0-9]+: c4 c2 59 53 d4 \{vex3\} vpdpwssds %xmm12,%xmm4,%xmm2
+[a-f0-9]+: c4 e2 59 53 11 \{vex3\} vpdpwssds \(%rcx\),%xmm4,%xmm2
+[a-f0-9]+: c4 e2 59 53 11 \{vex3\} vpdpwssds \(%rcx\),%xmm4,%xmm2
+[a-f0-9]+: c4 e2 59 53 11 \{vex3\} vpdpwssds \(%rcx\),%xmm4,%xmm2
+[a-f0-9]+: 62 b2 5d 08 53 d6 vpdpwssds %xmm22,%xmm4,%xmm2
+[a-f0-9]+: 62 d2 5d 08 50 d4 vpdpbusd %xmm12,%xmm4,%xmm2
#pass

23
gas/testsuite/gas/i386/x86-64-avx-vnni.s Normal file
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@ -0,0 +1,23 @@
.allow_index_reg
.macro test_insn mnemonic
\mnemonic %xmm12, %xmm4, %xmm2
{evex} \mnemonic %xmm12, %xmm4, %xmm2
{vex} \mnemonic %xmm12, %xmm4, %xmm2
{vex2} \mnemonic %xmm12, %xmm4, %xmm2
{vex3} \mnemonic %xmm12, %xmm4, %xmm2
{vex} \mnemonic (%rcx), %xmm4, %xmm2
{vex2} \mnemonic (%rcx), %xmm4, %xmm2
{vex3} \mnemonic (%rcx), %xmm4, %xmm2
\mnemonic %xmm22, %xmm4, %xmm2
.endm
.text
_start:
test_insn vpdpbusd
test_insn vpdpwssd
test_insn vpdpbusds
test_insn vpdpwssds
.arch .avx_vnni
vpdpbusd %xmm12, %xmm4, %xmm2

27
opcodes/ChangeLog
View File

@ -1,3 +1,30 @@
2020-10-14 H.J. Lu <hongjiu.lu@intel.com>
Lili Cui <lili.cui@intel.com>
* i386-dis.c (PREFIX_VEX_0F3850): New.
(PREFIX_VEX_0F3851): Likewise.
(PREFIX_VEX_0F3852): Likewise.
(PREFIX_VEX_0F3853): Likewise.
(VEX_W_0F3850_P_2): Likewise.
(VEX_W_0F3851_P_2): Likewise.
(VEX_W_0F3852_P_2): Likewise.
(VEX_W_0F3853_P_2): Likewise.
(prefix_table): Add PREFIX_VEX_0F3850, PREFIX_VEX_0F3851,
PREFIX_VEX_0F3852 and PREFIX_VEX_0F3853.
(vex_table): Add VEX_W_0F3850_P_2, VEX_W_0F3851_P_2,
VEX_W_0F3852_P_2 and VEX_W_0F3853_P_2.
(putop): Add support for "XV" to print "{vex3}" pseudo prefix.
* i386-gen.c (cpu_flag_init): Clear the CpuAVX_VNNI bit in
CPU_UNKNOWN_FLAGS. Add CPU_AVX_VNNI_FLAGS and
CPU_ANY_AVX_VNNI_FLAGS.
(cpu_flags): Add CpuAVX_VNNI and CpuVEX_PREFIX.
* i386-opc.h (CpuAVX_VNNI): New.
(CpuVEX_PREFIX): Likewise.
(i386_cpu_flags): Add cpuavx_vnni and cpuvex_prefix.
* i386-opc.tbl: Add Intel AVX VNNI instructions.
* i386-init.h: Regenerated.
* i386-tbl.h: Likewise.
2020-10-14 Lili Cui <lili.cui@intel.com>
H.J. Lu <hongjiu.lu@intel.com>

43
opcodes/i386-dis.c
View File

@ -1513,6 +1513,10 @@ enum
VEX_W_0F384B_X86_64_P_1,
VEX_W_0F384B_X86_64_P_2,
VEX_W_0F384B_X86_64_P_3,
VEX_W_0F3850,
VEX_W_0F3851,
VEX_W_0F3852,
VEX_W_0F3853,
VEX_W_0F3858,
VEX_W_0F3859,
VEX_W_0F385A_M_0_L_0,
@ -1800,6 +1804,7 @@ struct dis386 {
"XZ" => print 'x', 'y', or 'z' if suffix_always is true or no
register operands and no broadcast.
"XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
"XV" => print "{vex3}" pseudo prefix
"LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand, cond
being false, or no operand at all in 64bit mode, or if suffix_always
is true.
@ -6233,10 +6238,10 @@ static const struct dis386 vex_table[][256] = {
{ Bad_Opcode },
{ Bad_Opcode },
/* 50 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ VEX_W_TABLE (VEX_W_0F3850) },
{ VEX_W_TABLE (VEX_W_0F3851) },
{ VEX_W_TABLE (VEX_W_0F3852) },
{ VEX_W_TABLE (VEX_W_0F3853) },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
@ -7767,6 +7772,22 @@ static const struct dis386 vex_w_table[][2] = {
/* VEX_W_0F384B_X86_64_P_3 */
{ MOD_TABLE (MOD_VEX_0F384B_X86_64_P_3_W_0) },
},
{
/* VEX_W_0F3850 */
{ "%XV vpdpbusd", { XM, Vex, EXx }, 0 },
},
{
/* VEX_W_0F3851 */
{ "%XV vpdpbusds", { XM, Vex, EXx }, 0 },
},
{
/* VEX_W_0F3852 */
{ "%XV vpdpwssd", { XM, Vex, EXx }, 0 },
},
{
/* VEX_W_0F3853 */
{ "%XV vpdpwssds", { XM, Vex, EXx }, 0 },
},
{
/* VEX_W_0F3858 */
{ "vpbroadcastd", { XM, EXxmm_md }, PREFIX_DATA },
@ -11020,9 +11041,19 @@ putop (const char *in_template, int sizeflag)
case 'V':
if (l == 0)
abort ();
else if (l == 1 && last[0] == 'L')
else if (l == 1
&& (last[0] == 'L' || last[0] == 'X'))
{
if (rex & REX_W)
if (last[0] == 'X')
{
*obufp++ = '{';
*obufp++ = 'v';
*obufp++ = 'e';
*obufp++ = 'x';
*obufp++ = '3';
*obufp++ = '}';
}
else if (rex & REX_W)
{
*obufp++ = 'a';
*obufp++ = 'b';

6
opcodes/i386-gen.c
View File

@ -207,6 +207,8 @@ static initializer cpu_flag_init[] =
"CPU_SSE4_2_FLAGS|CPU_XSAVE_FLAGS|CpuAVX" },
{ "CPU_AVX2_FLAGS",
"CPU_AVX_FLAGS|CpuAVX2" },
{ "CPU_AVX_VNNI_FLAGS",
"CPU_AVX2_FLAGS|CpuAVX_VNNI" },
{ "CPU_AVX512F_FLAGS",
"CPU_AVX2_FLAGS|CpuAVX512F" },
{ "CPU_AVX512CD_FLAGS",
@ -405,6 +407,8 @@ static initializer cpu_flag_init[] =
"CpuAMX_BF16" },
{ "CPU_ANY_AMX_TILE_FLAGS",
"CpuAMX_TILE|CpuAMX_INT8|CpuAMX_BF16" },
{ "CPU_ANY_AVX_VNNI_FLAGS",
"CpuAVX_VNNI|CpuVEX_PREFIX" },
{ "CPU_ANY_MOVDIRI_FLAGS",
"CpuMOVDIRI" },
{ "CPU_ANY_UINTR_FLAGS",
@ -632,6 +636,8 @@ static bitfield cpu_flags[] =
BITFIELD (CpuAVX512_BF16),
BITFIELD (CpuAVX512_VP2INTERSECT),
BITFIELD (CpuTDX),
BITFIELD (CpuAVX_VNNI),
BITFIELD (CpuVEX_PREFIX),
BITFIELD (CpuMWAITX),
BITFIELD (CpuCLZERO),
BITFIELD (CpuOSPKE),

500
opcodes/i386-init.h
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6
opcodes/i386-opc.h
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@ -212,6 +212,10 @@ enum
CpuAVX512_VP2INTERSECT,
/* TDX Instructions support required. */
CpuTDX,
/* Intel AVX VNNI Instructions support required. */
CpuAVX_VNNI,
/* Intel AVX Instructions support via {vex} prefix required. */
CpuVEX_PREFIX,
/* mwaitx instruction required */
CpuMWAITX,
/* Clzero instruction required */
@ -382,6 +386,8 @@ typedef union i386_cpu_flags
unsigned int cpuavx512_bf16:1;
unsigned int cpuavx512_vp2intersect:1;
unsigned int cputdx:1;
unsigned int cpuavx_vnni:1;
unsigned int cpuvex_prefix:1;
unsigned int cpumwaitx:1;
unsigned int cpuclzero:1;
unsigned int cpuospke:1;

10
opcodes/i386-opc.tbl
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@ -3904,6 +3904,16 @@ vpshrdw, 4, 0x6672, None, 1, CpuAVX512_VBMI2, Modrm|Masking=3|OpcodePrefix=2|Vex
// AVX512_VBMI2 instructions end
// AVX_VNNI instructions
vpdpbusd, 3, 0x6650, None, 1, CpuAVX_VNNI|CpuVEX_PREFIX, Modrm|Vex|OpcodePrefix=1|VexVVVV=1|VexW=1|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
vpdpwssd, 3, 0x6652, None, 1, CpuAVX_VNNI|CpuVEX_PREFIX, Modrm|Vex|OpcodePrefix=1|VexVVVV=1|VexW=1|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
vpdpbusds, 3, 0x6651, None, 1, CpuAVX_VNNI|CpuVEX_PREFIX, Modrm|Vex|OpcodePrefix=1|VexVVVV=1|VexW=1|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
vpdpwssds, 3, 0x6653, None, 1, CpuAVX_VNNI|CpuVEX_PREFIX, Modrm|Vex|OpcodePrefix=1|VexVVVV=1|VexW=1|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
// AVX_VNNI instructions end
// AVX512_VNNI instructions
vpdpbusd, 3, 0x6650, None, 1, CpuAVX512_VNNI, Modrm|Masking=3|OpcodePrefix=1|VexVVVV=1|VexW=1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }

8652
opcodes/i386-tbl.h
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