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Use bool in gas

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* as.h (POISON_BFD_BOOLEAN): Define.
	* as.c, * as.h, * atof-generic.c, * config/atof-ieee.c,
	* config/bfin-aux.h, * config/obj-coff.c, * config/obj-ecoff.c,
	* config/obj-elf.c, * config/obj-elf.h, * config/obj-som.c,
	* config/tc-aarch64.c, * config/tc-alpha.c, * config/tc-arc.c,
	* config/tc-arc.h, * config/tc-arm.c, * config/tc-arm.h,
	* config/tc-avr.c, * config/tc-avr.h, * config/tc-bfin.c,
	* config/tc-bfin.h, * config/tc-bpf.c, * config/tc-cris.c,
	* config/tc-csky.c, * config/tc-csky.h, * config/tc-d10v.c,
	* config/tc-d10v.h, * config/tc-d30v.c, * config/tc-d30v.h,
	* config/tc-dlx.c, * config/tc-dlx.h, * config/tc-epiphany.c,
	* config/tc-epiphany.h, * config/tc-fr30.c, * config/tc-fr30.h,
	* config/tc-frv.c, * config/tc-frv.h, * config/tc-ft32.c,
	* config/tc-ft32.h, * config/tc-h8300.c, * config/tc-hppa.c,
	* config/tc-i386-intel.c, * config/tc-i386.c, * config/tc-ia64.c,
	* config/tc-ip2k.c, * config/tc-iq2000.c, * config/tc-iq2000.h,
	* config/tc-lm32.c, * config/tc-lm32.h, * config/tc-m32c.c,
	* config/tc-m32c.h, * config/tc-m32r.c, * config/tc-m32r.h,
	* config/tc-m68hc11.c, * config/tc-m68k.c, * config/tc-mcore.c,
	* config/tc-mcore.h, * config/tc-mep.c, * config/tc-mep.h,
	* config/tc-metag.c, * config/tc-metag.h,
	* config/tc-microblaze.c, * config/tc-mips.c, * config/tc-mips.h,
	* config/tc-mmix.c, * config/tc-mn10200.c, * config/tc-mn10300.c,
	* config/tc-mn10300.h, * config/tc-moxie.c, * config/tc-msp430.c,
	* config/tc-msp430.h, * config/tc-mt.c, * config/tc-mt.h,
	* config/tc-nds32.c, * config/tc-nds32.h, * config/tc-nios2.c,
	* config/tc-ns32k.c, * config/tc-or1k.c, * config/tc-or1k.h,
	* config/tc-pdp11.c, * config/tc-ppc.c, * config/tc-pru.c,
	* config/tc-pru.h, * config/tc-riscv.c, * config/tc-riscv.h,
	* config/tc-rx.c, * config/tc-rx.h, * config/tc-s12z.c,
	* config/tc-s12z.h, * config/tc-s390.c, * config/tc-score.c,
	* config/tc-score.h, * config/tc-score7.c, * config/tc-sh.c,
	* config/tc-sh.h, * config/tc-spu.c, * config/tc-tic54x.c,
	* config/tc-tic6x.c, * config/tc-tic6x.h, * config/tc-tilegx.c,
	* config/tc-tilepro.c, * config/tc-v850.c, * config/tc-v850.h,
	* config/tc-visium.c, * config/tc-visium.h, * config/tc-wasm32.c,
	* config/tc-wasm32.h, * config/tc-xc16x.c, * config/tc-xgate.c,
	* config/tc-xstormy16.c, * config/tc-xstormy16.h,
	* config/tc-xtensa.c, * config/tc-xtensa.h, * config/tc-z80.c,
	* config/tc-z8k.c, * config/xtensa-istack.h,
	* config/xtensa-relax.c, * config/xtensa-relax.h, * dw2gencfi.c,
	* dwarf2dbg.c, * dwarf2dbg.h, * expr.c, * expr.h, * frags.c,
	* frags.h, * listing.c, * macro.c, * output-file.c, * read.c,
	* read.h, * stabs.c, * symbols.c, * write.c: Replace bfd_boolean
	with bool, FALSE with false, and TRUE with true.
This commit is contained in:
Alan Modra 2021-03-31 10:42:05 +10:30
parent f38a2680c2
commit 5b7c81bd8c
133 changed files with 4274 additions and 4236 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

48
gas/ChangeLog
View File

@ -1,3 +1,51 @@
2021-03-31 Alan Modra <amodra@gmail.com>
* as.h (POISON_BFD_BOOLEAN): Define.
* as.c, * as.h, * atof-generic.c, * config/atof-ieee.c,
* config/bfin-aux.h, * config/obj-coff.c, * config/obj-ecoff.c,
* config/obj-elf.c, * config/obj-elf.h, * config/obj-som.c,
* config/tc-aarch64.c, * config/tc-alpha.c, * config/tc-arc.c,
* config/tc-arc.h, * config/tc-arm.c, * config/tc-arm.h,
* config/tc-avr.c, * config/tc-avr.h, * config/tc-bfin.c,
* config/tc-bfin.h, * config/tc-bpf.c, * config/tc-cris.c,
* config/tc-csky.c, * config/tc-csky.h, * config/tc-d10v.c,
* config/tc-d10v.h, * config/tc-d30v.c, * config/tc-d30v.h,
* config/tc-dlx.c, * config/tc-dlx.h, * config/tc-epiphany.c,
* config/tc-epiphany.h, * config/tc-fr30.c, * config/tc-fr30.h,
* config/tc-frv.c, * config/tc-frv.h, * config/tc-ft32.c,
* config/tc-ft32.h, * config/tc-h8300.c, * config/tc-hppa.c,
* config/tc-i386-intel.c, * config/tc-i386.c, * config/tc-ia64.c,
* config/tc-ip2k.c, * config/tc-iq2000.c, * config/tc-iq2000.h,
* config/tc-lm32.c, * config/tc-lm32.h, * config/tc-m32c.c,
* config/tc-m32c.h, * config/tc-m32r.c, * config/tc-m32r.h,
* config/tc-m68hc11.c, * config/tc-m68k.c, * config/tc-mcore.c,
* config/tc-mcore.h, * config/tc-mep.c, * config/tc-mep.h,
* config/tc-metag.c, * config/tc-metag.h,
* config/tc-microblaze.c, * config/tc-mips.c, * config/tc-mips.h,
* config/tc-mmix.c, * config/tc-mn10200.c, * config/tc-mn10300.c,
* config/tc-mn10300.h, * config/tc-moxie.c, * config/tc-msp430.c,
* config/tc-msp430.h, * config/tc-mt.c, * config/tc-mt.h,
* config/tc-nds32.c, * config/tc-nds32.h, * config/tc-nios2.c,
* config/tc-ns32k.c, * config/tc-or1k.c, * config/tc-or1k.h,
* config/tc-pdp11.c, * config/tc-ppc.c, * config/tc-pru.c,
* config/tc-pru.h, * config/tc-riscv.c, * config/tc-riscv.h,
* config/tc-rx.c, * config/tc-rx.h, * config/tc-s12z.c,
* config/tc-s12z.h, * config/tc-s390.c, * config/tc-score.c,
* config/tc-score.h, * config/tc-score7.c, * config/tc-sh.c,
* config/tc-sh.h, * config/tc-spu.c, * config/tc-tic54x.c,
* config/tc-tic6x.c, * config/tc-tic6x.h, * config/tc-tilegx.c,
* config/tc-tilepro.c, * config/tc-v850.c, * config/tc-v850.h,
* config/tc-visium.c, * config/tc-visium.h, * config/tc-wasm32.c,
* config/tc-wasm32.h, * config/tc-xc16x.c, * config/tc-xgate.c,
* config/tc-xstormy16.c, * config/tc-xstormy16.h,
* config/tc-xtensa.c, * config/tc-xtensa.h, * config/tc-z80.c,
* config/tc-z8k.c, * config/xtensa-istack.h,
* config/xtensa-relax.c, * config/xtensa-relax.h, * dw2gencfi.c,
* dwarf2dbg.c, * dwarf2dbg.h, * expr.c, * expr.h, * frags.c,
* frags.h, * listing.c, * macro.c, * output-file.c, * read.c,
* read.h, * stabs.c, * symbols.c, * write.c: Replace bfd_boolean
with bool, FALSE with false, and TRUE with true.
2021-03-31 Alan Modra <amodra@gmail.com>
* config/tc-aarch64.c: Include stdint.h in place of bfd_stdint.h.

12
gas/as.c
View File

@ -108,7 +108,7 @@ unsigned int dwarf_level = 3;
#if defined OBJ_ELF || defined OBJ_MAYBE_ELF
int flag_use_elf_stt_common = DEFAULT_GENERATE_ELF_STT_COMMON;
bfd_boolean flag_generate_build_notes = DEFAULT_GENERATE_BUILD_NOTES;
bool flag_generate_build_notes = DEFAULT_GENERATE_BUILD_NOTES;
#endif
/* Keep the output file. */
@ -862,7 +862,7 @@ This program has absolutely no warranty.\n"));
break;
case OPTION_GDWARF_SECTIONS:
flag_dwarf_sections = TRUE;
flag_dwarf_sections = true;
break;
case OPTION_GDWARF_CIE_VERSION:
@ -961,9 +961,9 @@ This program has absolutely no warranty.\n"));
case OPTION_SIZE_CHECK:
if (strcasecmp (optarg, "error") == 0)
flag_allow_nonconst_size = FALSE;
flag_allow_nonconst_size = false;
else if (strcasecmp (optarg, "warning") == 0)
flag_allow_nonconst_size = TRUE;
flag_allow_nonconst_size = true;
else
as_fatal (_("Invalid --size-check= option: `%s'"), optarg);
break;
@ -984,9 +984,9 @@ This program has absolutely no warranty.\n"));
case OPTION_ELF_BUILD_NOTES:
if (strcasecmp (optarg, "no") == 0)
flag_generate_build_notes = FALSE;
flag_generate_build_notes = false;
else if (strcasecmp (optarg, "yes") == 0)
flag_generate_build_notes = TRUE;
flag_generate_build_notes = true;
else
as_fatal (_("Invalid --generate-missing-build-notes option: `%s'"),
optarg);

8
gas/as.h
View File

@ -411,7 +411,7 @@ enum debug_info_type
extern enum debug_info_type debug_type;
extern int use_gnu_debug_info_extensions;
COMMON bfd_boolean flag_dwarf_sections;
COMMON bool flag_dwarf_sections;
extern int flag_dwarf_cie_version;
extern unsigned int dwarf_level;
@ -487,7 +487,7 @@ char * app_push (void);
char * atof_ieee (char *, int, LITTLENUM_TYPE *);
char * atof_ieee_detail (char *, int, int, LITTLENUM_TYPE *, FLONUM_TYPE *);
const char * ieee_md_atof (int, char *, int *, bfd_boolean);
const char * ieee_md_atof (int, char *, int *, bool);
const char * vax_md_atof (int, char *, int *);
char * input_scrub_include_file (const char *, char *);
void input_scrub_insert_line (const char *);
@ -609,7 +609,7 @@ extern int flag_use_elf_stt_common;
/* TRUE iff GNU Build attribute notes should
be generated if none are in the input files. */
extern bfd_boolean flag_generate_build_notes;
extern bool flag_generate_build_notes;
/* If section name substitution sequences should be honored */
COMMON int flag_sectname_subst;
@ -662,4 +662,6 @@ COMMON int flag_sectname_subst;
#define SEC_OCTETS 0
#endif
#define POISON_BFD_BOOLEAN 1
#endif /* GAS */

2
gas/atof-generic.c
View File

@ -233,7 +233,7 @@ atof_generic (/* return pointer to just AFTER number we read. */
if ( /* seen_significant_digit || */ c > '0')
{
seen_significant_digit = TRUE;
seen_significant_digit = true;
}
}
else

2
gas/config/atof-ieee.c
View File

@ -755,7 +755,7 @@ const char *
ieee_md_atof (int type,
char *litP,
int *sizeP,
bfd_boolean big_wordian)
bool big_wordian)
{
LITTLENUM_TYPE words[MAX_LITTLENUMS];
LITTLENUM_TYPE *wordP;

2
gas/config/bfin-aux.h
View File

@ -64,5 +64,5 @@ INSTR_T bfin_gen_linkage (int, int);
INSTR_T bfin_gen_pseudodbg (int, int, int);
INSTR_T bfin_gen_pseudodbg_assert (int, REG_T, int);
INSTR_T bfin_gen_pseudochr (int);
bfd_boolean bfin_resource_conflict (INSTR_T, INSTR_T, INSTR_T);
bool bfin_resource_conflict (INSTR_T, INSTR_T, INSTR_T);
INSTR_T bfin_gen_multi_instr (INSTR_T, INSTR_T, INSTR_T);

8
gas/config/obj-coff.c
View File

@ -374,7 +374,7 @@ coff_obj_symbol_new_hook (symbolS *symbolP)
memset (s, 0, sz);
coffsymbol (symbol_get_bfdsym (symbolP))->native = (combined_entry_type *) s;
coffsymbol (symbol_get_bfdsym (symbolP))->native->is_sym = TRUE;
coffsymbol (symbol_get_bfdsym (symbolP))->native->is_sym = true;
S_SET_DATA_TYPE (symbolP, T_NULL);
S_SET_STORAGE_CLASS (symbolP, 0);
@ -1527,7 +1527,7 @@ obj_coff_section (int ignore ATTRIBUTE_UNUSED)
unsigned int exp;
flagword flags, oldflags;
asection *sec;
bfd_boolean is_bss = FALSE;
bool is_bss = false;
if (flag_mri)
{
@ -1577,7 +1577,7 @@ obj_coff_section (int ignore ATTRIBUTE_UNUSED)
/* Uninitialised data section. */
flags |= SEC_ALLOC;
flags &=~ SEC_LOAD;
is_bss = TRUE;
is_bss = true;
break;
case 'n':
@ -1800,7 +1800,7 @@ obj_coff_init_stab_section (segT seg)
memset (p, 0, 12);
file = as_where ((unsigned int *) NULL);
stabstr_name = concat (seg->name, "str", (char *) NULL);
stroff = get_stab_string_offset (file, stabstr_name, TRUE);
stroff = get_stab_string_offset (file, stabstr_name, true);
know (stroff == 1);
md_number_to_chars (p, stroff, 4);
}

2
gas/config/obj-ecoff.c
View File

@ -189,7 +189,7 @@ obj_ecoff_set_ext (symbolS *sym, EXTR *ext)
know (bfd_asymbol_flavour (symbol_get_bfdsym (sym))
== bfd_target_ecoff_flavour);
esym = ecoffsymbol (symbol_get_bfdsym (sym));
esym->local = FALSE;
esym->local = false;
esym->native = xmalloc (debug_swap->external_ext_size);
(*debug_swap->swap_ext_out) (stdoutput, ext, esym->native);
}

58
gas/config/obj-elf.c
View File

@ -520,7 +520,7 @@ static struct section_stack *section_stack;
/* Return TRUE iff SEC matches the section info INF. */
static bfd_boolean
static bool
get_section_by_match (bfd *abfd ATTRIBUTE_UNUSED, asection *sec, void *inf)
{
struct elf_section_match *match = (struct elf_section_match *) inf;
@ -621,7 +621,7 @@ obj_elf_change_section (const char *name,
if (ssect != NULL)
{
bfd_boolean override = FALSE;
bool override = false;
if (type == SHT_NULL)
type = ssect->type;
@ -694,15 +694,15 @@ obj_elf_change_section (const char *name,
&& (strcmp (name, ".interp") == 0
|| strcmp (name, ".strtab") == 0
|| strcmp (name, ".symtab") == 0))
override = TRUE;
override = true;
/* .note.GNU-stack can have SHF_EXECINSTR. */
else if (generic_attr == SHF_EXECINSTR
&& strcmp (name, ".note.GNU-stack") == 0)
override = TRUE;
override = true;
#ifdef TC_ALPHA
/* A section on Alpha may have SHF_ALPHA_GPREL. */
else if ((generic_attr & ~ssect->attr) == SHF_ALPHA_GPREL)
override = TRUE;
override = true;
#endif
#ifdef TC_RX
else if (generic_attr == (SHF_EXECINSTR | SHF_WRITE | SHF_ALLOC)
@ -717,7 +717,7 @@ obj_elf_change_section (const char *name,
if (match_p->group_name == NULL)
as_warn (_("setting incorrect section attributes for %s"),
name);
override = TRUE;
override = true;
}
}
@ -832,10 +832,10 @@ obj_elf_change_section (const char *name,
static bfd_vma
obj_elf_parse_section_letters (char *str, size_t len,
bfd_boolean *is_clone, bfd_vma *gnu_attr)
bool *is_clone, bfd_vma *gnu_attr)
{
bfd_vma attr = 0;
*is_clone = FALSE;
*is_clone = false;
while (len > 0)
{
@ -875,7 +875,7 @@ obj_elf_parse_section_letters (char *str, size_t len,
*gnu_attr |= SHF_GNU_RETAIN;
break;
case '?':
*is_clone = TRUE;
*is_clone = true;
break;
/* Compatibility. */
case 'm':
@ -947,7 +947,7 @@ obj_elf_parse_section_letters (char *str, size_t len,
}
static int
obj_elf_section_type (char *str, size_t len, bfd_boolean warn)
obj_elf_section_type (char *str, size_t len, bool warn)
{
if (len == 8 && strncmp (str, "progbits", 8) == 0)
return SHT_PROGBITS;
@ -1010,7 +1010,7 @@ obj_elf_section_word (char *str, size_t len, int *type)
}
#endif
ret = obj_elf_section_type (str, len, FALSE);
ret = obj_elf_section_type (str, len, false);
if (ret != 0)
*type = ret;
else
@ -1184,7 +1184,7 @@ obj_elf_section (int push)
if (*input_line_pointer == '"')
{
bfd_boolean is_clone;
bool is_clone;
beg = demand_copy_C_string (&dummy);
if (beg == NULL)
@ -1212,7 +1212,7 @@ obj_elf_section (int push)
ignore_rest_of_line ();
return;
}
type = obj_elf_section_type (beg, strlen (beg), TRUE);
type = obj_elf_section_type (beg, strlen (beg), true);
}
else if (c == '@' || c == '%')
{
@ -1226,7 +1226,7 @@ obj_elf_section (int push)
(void) restore_line_pointer (c);
type = obj_elf_section_type (beg,
input_line_pointer - beg,
TRUE);
true);
}
}
else
@ -1278,7 +1278,7 @@ obj_elf_section (int push)
if ((attr & SHF_GROUP) != 0 && is_clone)
{
as_warn (_("? section flag ignored with G present"));
is_clone = FALSE;
is_clone = false;
}
if ((attr & SHF_GROUP) != 0 && *input_line_pointer == ',')
@ -1356,7 +1356,7 @@ obj_elf_section (int push)
if (ISDIGIT (* input_line_pointer))
{
bfd_vma id;
bfd_boolean overflow;
bool overflow;
char *t = input_line_pointer;
if (sizeof (bfd_vma) <= sizeof (unsigned long))
{
@ -1430,7 +1430,7 @@ obj_elf_section (int push)
if ((gnu_attr & (SHF_GNU_MBIND | SHF_GNU_RETAIN)) != 0)
{
const struct elf_backend_data *bed;
bfd_boolean mbind_p = (gnu_attr & SHF_GNU_MBIND) != 0;
bool mbind_p = (gnu_attr & SHF_GNU_MBIND) != 0;
if (mbind_p && (attr & SHF_ALLOC) == 0)
as_bad (_("SHF_ALLOC isn't set for GNU_MBIND section: %s"), name);
@ -1654,7 +1654,7 @@ obj_elf_find_and_add_versioned_name (const char *version_name,
return NULL;
}
}
sy_obj->rename = TRUE;
sy_obj->rename = true;
break;
default:
as_bad (_("invalid version name '%s' for symbol `%s'"),
@ -1735,7 +1735,7 @@ obj_elf_symver (int ignore ATTRIBUTE_UNUSED)
if (obj_elf_find_and_add_versioned_name (name, sym_name,
p, sy_obj) == NULL)
{
sy_obj->bad_version = TRUE;
sy_obj->bad_version = true;
ignore_rest_of_line ();
return;
}
@ -1946,7 +1946,7 @@ record_attribute (int vendor, unsigned int tag)
/* Return true if we have seen an explicit specification of attribute TAG
for vendor VENDOR. */
bfd_boolean
bool
obj_elf_seen_attribute (int vendor, unsigned int tag)
{
unsigned int base;
@ -1958,7 +1958,7 @@ obj_elf_seen_attribute (int vendor, unsigned int tag)
for (rai = recorded_attributes; rai; rai = rai->next)
if (rai->vendor == vendor && rai->base == base)
return (rai->mask & mask) != 0;
return FALSE;
return false;
}
/* Parse an attribute directive for VENDOR.
@ -2489,7 +2489,7 @@ obj_elf_init_stab_section (segT seg)
memset (p, 0, 12);
file = remap_debug_filename (as_where (NULL));
stabstr_name = concat (segment_name (seg), "str", (char *) NULL);
stroff = get_stab_string_offset (file, stabstr_name, TRUE);
stroff = get_stab_string_offset (file, stabstr_name, true);
know (stroff == 1 || (stroff == 0 && file[0] == '\0'));
md_number_to_chars (p, stroff, 4);
seg_info (seg)->stabu.p = p;
@ -2550,13 +2550,13 @@ elf_ecoff_set_ext (symbolS *sym, struct ecoff_extr *ext)
supposed to *EXT to the external symbol information, and return
whether the symbol should be used at all. */
static bfd_boolean
static bool
elf_get_extr (asymbol *sym, EXTR *ext)
{
if (sym->udata.p == NULL)
return FALSE;
return false;
*ext = *(EXTR *) sym->udata.p;
return TRUE;
return true;
}
/* This function is called by bfd_ecoff_debug_externals. It has
@ -2613,7 +2613,7 @@ elf_frob_symbol (symbolS *symp, int *puntp)
/* We will have already reported an version error. */
if (sy_obj->bad_version)
*puntp = TRUE;
*puntp = true;
/* elf_frob_file_before_adjust only allows one version symbol for
renamed symbol. */
else if (sy_obj->rename)
@ -2622,7 +2622,7 @@ elf_frob_symbol (symbolS *symp, int *puntp)
{
as_bad (_("`%s' can't be versioned to common symbol '%s'"),
versioned_name->name, S_GET_NAME (symp));
*puntp = TRUE;
*puntp = true;
}
else
{
@ -2912,7 +2912,7 @@ elf_frob_file_before_adjust (void)
return;
}
sy_obj->rename = TRUE;
sy_obj->rename = true;
}
}
@ -2994,7 +2994,7 @@ elf_frob_file_after_relocs (void)
/* Set up the external symbols. */
debug.ssext = debug.ssext_end = NULL;
debug.external_ext = debug.external_ext_end = NULL;
if (! bfd_ecoff_debug_externals (stdoutput, &debug, debug_swap, TRUE,
if (! bfd_ecoff_debug_externals (stdoutput, &debug, debug_swap, true,
elf_get_extr, elf_set_index))
as_fatal (_("failed to set up debugging information: %s"),
bfd_errmsg (bfd_get_error ()));

2
gas/config/obj-elf.h
View File

@ -198,7 +198,7 @@ extern void obj_elf_vtable_inherit (int);
extern void obj_elf_vtable_entry (int);
extern struct fix * obj_elf_get_vtable_inherit (void);
extern struct fix * obj_elf_get_vtable_entry (void);
extern bfd_boolean obj_elf_seen_attribute
extern bool obj_elf_seen_attribute
(int, unsigned int);
extern int obj_elf_vendor_attribute (int);

2
gas/config/obj-som.c
View File

@ -247,7 +247,7 @@ obj_som_init_stab_section (segT seg)
p = frag_more (12);
memset (p, 0, 12);
file = as_where ((unsigned int *) NULL);
stroff = get_stab_string_offset (file, "$GDB_STRINGS$", FALSE);
stroff = get_stab_string_offset (file, "$GDB_STRINGS$", false);
know (stroff == 1);
md_number_to_chars (p, stroff, 4);
seg_info (seg)->stabu.p = p;

408
gas/config/tc-aarch64.c
View File

File diff suppressed because it is too large Load Diff

2
gas/config/tc-alpha.c
View File

@ -5584,7 +5584,7 @@ md_atof (int type, char *litP, int *sizeP)
return vax_md_atof (type, litP, sizeP);
default:
return ieee_md_atof (type, litP, sizeP, FALSE);
return ieee_md_atof (type, litP, sizeP, false);
}
}

224
gas/config/tc-arc.c
View File

@ -312,7 +312,7 @@ struct arc_fixup
unsigned char pcrel;
/* TRUE if this fixup is for LIMM operand. */
bfd_boolean islong;
bool islong;
};
struct arc_insn
@ -321,11 +321,9 @@ struct arc_insn
int nfixups;
struct arc_fixup fixups[MAX_INSN_FIXUPS];
long limm;
unsigned int len; /* Length of instruction in bytes. */
bfd_boolean has_limm; /* Boolean value: TRUE if limm field is
valid. */
bfd_boolean relax; /* Boolean value: TRUE if needs
relaxation. */
unsigned int len; /* Length of instruction in bytes. */
bool has_limm; /* Boolean value: TRUE if limm field is valid. */
bool relax; /* Boolean value: TRUE if needs relaxation. */
};
/* Structure to hold any last two instructions. */
@ -335,10 +333,10 @@ static struct arc_last_insn
const struct arc_opcode *opcode;
/* Boolean value: TRUE if current insn is short. */
bfd_boolean has_limm;
bool has_limm;
/* Boolean value: TRUE if current insn has delay slot. */
bfd_boolean has_delay_slot;
bool has_delay_slot;
} arc_last_insns[2];
/* Extension instruction suffix classes. */
@ -472,7 +470,7 @@ static const struct cpu_type
static struct cpu_type selected_cpu = { 0, 0, 0, E_ARC_OSABI_CURRENT, 0 };
/* TRUE if current assembly code uses RF16 only registers. */
static bfd_boolean rf16_only = TRUE;
static bool rf16_only = true;
/* MPY option. */
static unsigned mpy_option = 0;
@ -688,10 +686,10 @@ const unsigned arc_num_relaxable_ins = ARRAY_SIZE (arc_relaxable_insns);
symbolS * GOT_symbol = 0;
/* Set to TRUE when we assemble instructions. */
static bfd_boolean assembling_insn = FALSE;
static bool assembling_insn = false;
/* List with attributes set explicitly. */
static bfd_boolean attributes_set_explicitly[NUM_KNOWN_OBJ_ATTRIBUTES];
static bool attributes_set_explicitly[NUM_KNOWN_OBJ_ATTRIBUTES];
/* Functions implementation. */
@ -946,7 +944,7 @@ arc_extra_reloc (int r_type)
0, /* size: 1, 2, or 4 usually. */
sym, /* X_add_symbol. */
0, /* X_add_number. */
FALSE, /* TRUE if PC-relative relocation. */
false, /* TRUE if PC-relative relocation. */
r_type /* Relocation type. */);
fixP->fx_subsy = lab;
}
@ -1201,8 +1199,8 @@ tokenize_arguments (char *str,
int ntok)
{
char *old_input_line_pointer;
bfd_boolean saw_comma = FALSE;
bfd_boolean saw_arg = FALSE;
bool saw_comma = false;
bool saw_arg = false;
int brk_lvl = 0;
int num_args = 0;
@ -1224,7 +1222,7 @@ tokenize_arguments (char *str,
input_line_pointer++;
if (saw_comma || !saw_arg)
goto err;
saw_comma = TRUE;
saw_comma = true;
break;
case '}':
@ -1254,7 +1252,7 @@ tokenize_arguments (char *str,
if (!saw_arg || num_args == ntok)
goto err;
tok->X_op = O_colon;
saw_arg = FALSE;
saw_arg = false;
++tok;
++num_args;
break;
@ -1281,8 +1279,8 @@ tokenize_arguments (char *str,
|| num_args == ntok)
goto err;
saw_comma = FALSE;
saw_arg = TRUE;
saw_comma = false;
saw_arg = true;
tok++;
num_args++;
break;
@ -1313,8 +1311,8 @@ tokenize_arguments (char *str,
|| num_args == ntok)
goto err;
saw_comma = FALSE;
saw_arg = TRUE;
saw_comma = false;
saw_arg = true;
tok++;
num_args++;
break;
@ -1349,8 +1347,8 @@ tokenize_flags (const char *str,
int nflg)
{
char *old_input_line_pointer;
bfd_boolean saw_flg = FALSE;
bfd_boolean saw_dot = FALSE;
bool saw_flg = false;
bool saw_dot = false;
int num_flags = 0;
size_t flgnamelen;
@ -1372,8 +1370,8 @@ tokenize_flags (const char *str,
input_line_pointer++;
if (saw_dot)
goto err;
saw_dot = TRUE;
saw_flg = FALSE;
saw_dot = true;
saw_flg = false;
break;
default:
@ -1392,8 +1390,8 @@ tokenize_flags (const char *str,
input_line_pointer += flgnamelen;
flags++;
saw_dot = FALSE;
saw_flg = TRUE;
saw_dot = false;
saw_flg = true;
num_flags++;
break;
}
@ -1479,7 +1477,7 @@ offset %d + %d\n",
/* Actually output an instruction with its fixup. */
static void
emit_insn0 (struct arc_insn *insn, char *where, bfd_boolean relax)
emit_insn0 (struct arc_insn *insn, char *where, bool relax)
{
char *f = where;
size_t total_len;
@ -1550,12 +1548,12 @@ emit_insn (struct arc_insn *insn)
if (insn->relax)
emit_insn1 (insn);
else
emit_insn0 (insn, NULL, FALSE);
emit_insn0 (insn, NULL, false);
}
/* Check whether a symbol involves a register. */
static bfd_boolean
static bool
contains_register (symbolS *sym)
{
if (sym)
@ -1567,7 +1565,7 @@ contains_register (symbolS *sym)
&& !contains_register (ex->X_op_symbol));
}
return FALSE;
return false;
}
/* Returns the register number within a symbol. */
@ -1585,11 +1583,11 @@ get_register (symbolS *sym)
/* Return true if a RELOC is generic. A generic reloc is PC-rel of a
simple ME relocation (e.g. RELOC_ARC_32_ME, BFD_RELOC_ARC_PC32. */
static bfd_boolean
static bool
generic_reloc_p (extended_bfd_reloc_code_real_type reloc)
{
if (!reloc)
return FALSE;
return false;
switch (reloc)
{
@ -1601,9 +1599,9 @@ generic_reloc_p (extended_bfd_reloc_code_real_type reloc)
case BFD_RELOC_ARC_SDA16_LD2:
case BFD_RELOC_ARC_SDA16_ST2:
case BFD_RELOC_ARC_SDA32_ME:
return FALSE;
return false;
default:
return TRUE;
return true;
}
}
@ -1627,25 +1625,25 @@ allocate_tok (expressionS *tok, int ntok, int cidx)
/* Check if an particular ARC feature is enabled. */
static bfd_boolean
static bool
check_cpu_feature (insn_subclass_t sc)
{
if (is_code_density_p (sc) && !(selected_cpu.features & CD))
return FALSE;
return false;
if (is_spfp_p (sc) && !(selected_cpu.features & SPX))
return FALSE;
return false;
if (is_dpfp_p (sc) && !(selected_cpu.features & DPX))
return FALSE;
return false;
if (is_fpuda_p (sc) && !(selected_cpu.features & DPA))
return FALSE;
return false;
if (is_nps400_p (sc) && !(selected_cpu.features & NPS400))
return FALSE;
return false;
return TRUE;
return true;
}
/* Parse the flags described by FIRST_PFLAG and NFLGS against the flag
@ -1654,7 +1652,7 @@ check_cpu_feature (insn_subclass_t sc)
returns FALSE, in which case the FIRST_PFLAG array may have been
modified. */
static bfd_boolean
static bool
parse_opcode_flags (const struct arc_opcode *opcode,
int nflgs,
struct arc_flags *first_pflag)
@ -1692,7 +1690,7 @@ parse_opcode_flags (const struct arc_opcode *opcode,
if (!strcmp (pf->name, pflag->name))
{
if (pflag->flgp != NULL)
return FALSE;
return false;
/* Found it. */
cl_matches++;
pflag->flgp = pf;
@ -1716,7 +1714,7 @@ parse_opcode_flags (const struct arc_opcode *opcode,
if (!strcmp (flg_operand->name, pflag->name))
{
if (pflag->flgp != NULL)
return FALSE;
return false;
cl_matches++;
pflag->flgp = flg_operand;
lnflg--;
@ -1726,9 +1724,9 @@ parse_opcode_flags (const struct arc_opcode *opcode,
}
if ((cl_flags->flag_class & F_CLASS_REQUIRED) && cl_matches == 0)
return FALSE;
return false;
if ((cl_flags->flag_class & F_CLASS_OPTIONAL) && cl_matches > 1)
return FALSE;
return false;
}
/* Did I check all the parsed flags? */
@ -2131,15 +2129,15 @@ swap_operand (expressionS *operand_array,
/* Check if *op matches *tok type.
Returns FALSE if they don't match, TRUE if they match. */
static bfd_boolean
static bool
pseudo_operand_match (const expressionS *tok,
const struct arc_operand_operation *op)
{
offsetT min, max, val;
bfd_boolean ret;
bool ret;
const struct arc_operand *operand_real = &arc_operands[op->operand_idx];
ret = FALSE;
ret = false;
switch (tok->X_op)
{
case O_constant:
@ -2159,7 +2157,7 @@ pseudo_operand_match (const expressionS *tok,
min = 0;
}
if (min <= val && val <= max)
ret = TRUE;
ret = true;
}
break;
@ -2168,17 +2166,17 @@ pseudo_operand_match (const expressionS *tok,
if (operand_real->flags & ARC_OPERAND_LIMM
|| ((operand_real->flags & ARC_OPERAND_SIGNED)
&& operand_real->bits == 9))
ret = TRUE;
ret = true;
break;
case O_register:
if (operand_real->flags & ARC_OPERAND_IR)
ret = TRUE;
ret = true;
break;
case O_bracket:
if (operand_real->flags & ARC_OPERAND_BRAKET)
ret = TRUE;
ret = true;
break;
default:
@ -2433,7 +2431,7 @@ autodetect_attributes (const struct arc_opcode *opcode,
case O_register:
if ((tok[i].X_add_number >= 4 && tok[i].X_add_number <= 9)
|| (tok[i].X_add_number >= 16 && tok[i].X_add_number <= 25))
rf16_only = FALSE;
rf16_only = false;
break;
default:
break;
@ -2451,7 +2449,7 @@ assemble_tokens (const char *opname,
struct arc_flags *pflags,
int nflgs)
{
bfd_boolean found_something = FALSE;
bool found_something = false;
const struct arc_opcode_hash_entry *entry;
int cpumatch = 1;
const char *errmsg = NULL;
@ -2469,7 +2467,7 @@ assemble_tokens (const char *opname,
pr_debug ("%s:%d: assemble_tokens: %s\n",
frag_now->fr_file, frag_now->fr_line, opname);
found_something = TRUE;
found_something = true;
opcode = find_opcode_match (entry, tok, &ntok, pflags,
nflgs, &cpumatch, &errmsg);
if (opcode != NULL)
@ -2514,7 +2512,7 @@ md_assemble (char *str)
opname = xmemdup0 (str, opnamelen);
/* Signalize we are assembling the instructions. */
assembling_insn = TRUE;
assembling_insn = true;
/* Tokenize the flags. */
if ((nflg = tokenize_flags (str + opnamelen, flags, MAX_INSN_FLGS)) == -1)
@ -2539,7 +2537,7 @@ md_assemble (char *str)
/* Finish it off. */
assemble_tokens (opname, tok, ntok, flags, nflg);
assembling_insn = FALSE;
assembling_insn = false;
}
/* Callback to insert a register into the hash table. */
@ -2957,19 +2955,19 @@ md_apply_fix (fixS *fixP,
value += S_GET_VALUE (fx_addsy);
value -= md_pcrel_from_section (fixP, seg);
fx_addsy = NULL;
fixP->fx_pcrel = FALSE;
fixP->fx_pcrel = false;
}
else if (add_symbol_segment == absolute_section)
{
value = fixP->fx_offset;
fx_offset += S_GET_VALUE (fixP->fx_addsy);
fx_addsy = NULL;
fixP->fx_pcrel = FALSE;
fixP->fx_pcrel = false;
}
}
if (!fx_addsy)
fixP->fx_done = TRUE;
fixP->fx_done = true;
if (fixP->fx_pcrel)
{
@ -3316,7 +3314,7 @@ md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED,
size = insn.len + (insn.has_limm ? 4 : 0);
gas_assert (table_entry->rlx_length == size);
emit_insn0 (&insn, dest, TRUE);
emit_insn0 (&insn, dest, true);
fragP->fr_fix += table_entry->rlx_length;
fragP->fr_var = 0;
@ -3383,25 +3381,25 @@ md_operand (expressionS *expressionP)
the expression with the identified register. It returns TRUE if
it is a register and FALSE otherwise. */
bfd_boolean
bool
arc_parse_name (const char *name,
struct expressionS *e)
{
struct symbol *sym;
if (!assembling_insn)
return FALSE;
return false;
if (e->X_op == O_symbol
&& e->X_md == O_absent)
return FALSE;
return false;
sym = str_hash_find (arc_reg_hash, name);
if (sym)
{
e->X_op = O_register;
e->X_add_number = S_GET_VALUE (sym);
return TRUE;
return true;
}
sym = str_hash_find (arc_addrtype_hash, name);
@ -3409,10 +3407,10 @@ arc_parse_name (const char *name,
{
e->X_op = O_addrtype;
e->X_add_number = S_GET_VALUE (sym);
return TRUE;
return true;
}
return FALSE;
return false;
}
/* md_parse_option
@ -3539,7 +3537,7 @@ arc_show_cpu_list (FILE *stream)
offset = strlen (space_buf);
for (i = 0; cpu_types[i].name != NULL; ++i)
{
bfd_boolean last = (cpu_types[i + 1].name == NULL);
bool last = (cpu_types[i + 1].name == NULL);
/* If displaying the new cpu name string, and the ', ' (for all
but the last one) will take us past a target width of 80
@ -3628,7 +3626,7 @@ find_reloc (const char *name,
{
unsigned int i;
int j;
bfd_boolean found_flag, tmp;
bool found_flag, tmp;
extended_bfd_reloc_code_real_type ret = BFD_RELOC_UNUSED;
for (i = 0; i < arc_num_equiv_tab; i++)
@ -3644,26 +3642,26 @@ find_reloc (const char *name,
{
if (!nflg)
continue;
found_flag = FALSE;
found_flag = false;
unsigned * psflg = (unsigned *)r->flags;
do
{
tmp = FALSE;
tmp = false;
for (j = 0; j < nflg; j++)
if (!strcmp (pflags[j].name,
arc_flag_operands[*psflg].name))
{
tmp = TRUE;
tmp = true;
break;
}
if (!tmp)
{
found_flag = FALSE;
found_flag = false;
break;
}
else
{
found_flag = TRUE;
found_flag = true;
}
++ psflg;
} while (*psflg);
@ -3688,7 +3686,7 @@ find_reloc (const char *name,
/* All the symbol types that are allowed to be used for
relaxation. */
static bfd_boolean
static bool
may_relax_expr (expressionS tok)
{
/* Check if we have unrelaxable relocs. */
@ -3697,7 +3695,7 @@ may_relax_expr (expressionS tok)
default:
break;
case O_plt:
return FALSE;
return false;
}
switch (tok.X_op)
@ -3711,14 +3709,14 @@ may_relax_expr (expressionS tok)
break;
default:
return FALSE;
return false;
}
return TRUE;
return true;
}
/* Checks if flags are in line with relaxable insn. */
static bfd_boolean
static bool
relaxable_flag (const struct arc_relaxable_ins *ins,
const struct arc_flags *pflags,
int nflgs)
@ -3759,7 +3757,7 @@ relaxable_flag (const struct arc_relaxable_ins *ins,
/* Checks if operands are in line with relaxable insn. */
static bfd_boolean
static bool
relaxable_operand (const struct arc_relaxable_ins *ins,
const expressionS *tok,
int ntok)
@ -3772,7 +3770,7 @@ relaxable_operand (const struct arc_relaxable_ins *ins,
const expressionS *epr = &tok[i];
if (i != 0 && i >= ntok)
return FALSE;
return false;
switch (*operand)
{
@ -3783,22 +3781,22 @@ relaxable_operand (const struct arc_relaxable_ins *ins,
|| epr->X_op == O_add
|| epr->X_op == O_subtract
|| epr->X_op == O_symbol))
return FALSE;
return false;
break;
case REGISTER_DUP:
if ((i <= 0)
|| (epr->X_add_number != tok[i - 1].X_add_number))
return FALSE;
return false;
/* Fall through. */
case REGISTER:
if (epr->X_op != O_register)
return FALSE;
return false;
break;
case REGISTER_S:
if (epr->X_op != O_register)
return FALSE;
return false;
switch (epr->X_add_number)
{
@ -3806,24 +3804,24 @@ relaxable_operand (const struct arc_relaxable_ins *ins,
case 12: case 13: case 14: case 15:
break;
default:
return FALSE;
return false;
}
break;
case REGISTER_NO_GP:
if ((epr->X_op != O_register)
|| (epr->X_add_number == 26)) /* 26 is the gp register. */
return FALSE;
return false;
break;
case BRACKET:
if (epr->X_op != O_bracket)
return FALSE;
return false;
break;
default:
/* Don't understand, bail out. */
return FALSE;
return false;
break;
}
@ -3836,7 +3834,7 @@ relaxable_operand (const struct arc_relaxable_ins *ins,
/* Return TRUE if this OPDCODE is a candidate for relaxation. */
static bfd_boolean
static bool
relax_insn_p (const struct arc_opcode *opcode,
const expressionS *tok,
int ntok,
@ -3844,7 +3842,7 @@ relax_insn_p (const struct arc_opcode *opcode,
int nflg)
{
unsigned i;
bfd_boolean rv = FALSE;
bool rv = false;
/* Check the relaxation table. */
for (i = 0; i < arc_num_relaxable_ins && relaxation_state; ++i)
@ -3856,7 +3854,7 @@ relax_insn_p (const struct arc_opcode *opcode,
&& relaxable_operand (arc_rlx_ins, tok, ntok)
&& relaxable_flag (arc_rlx_ins, pflags, nflg))
{
rv = TRUE;
rv = true;
frag_now->fr_subtype = arc_relaxable_insns[i].subtype;
memcpy (&frag_now->tc_frag_data.tok, tok,
sizeof (expressionS) * ntok);
@ -3888,8 +3886,8 @@ assemble_insn (const struct arc_opcode *opcode,
int i;
int tokidx = 0;
unsigned char pcrel = 0;
bfd_boolean needGOTSymbol;
bfd_boolean has_delay_slot = FALSE;
bool needGOTSymbol;
bool has_delay_slot = false;
extended_bfd_reloc_code_real_type reloc = BFD_RELOC_UNUSED;
memset (insn, 0, sizeof (*insn));
@ -3925,7 +3923,7 @@ assemble_insn (const struct arc_opcode *opcode,
/* Regardless if we have a reloc or not mark the instruction
limm if it is the case. */
if (operand->flags & ARC_OPERAND_LIMM)
insn->has_limm = TRUE;
insn->has_limm = true;
switch (t->X_op)
{
@ -3969,7 +3967,7 @@ assemble_insn (const struct arc_opcode *opcode,
default:
/* This operand needs a relocation. */
needGOTSymbol = FALSE;
needGOTSymbol = false;
switch (t->X_md)
{
@ -3977,7 +3975,7 @@ assemble_insn (const struct arc_opcode *opcode,
if (opcode->insn_class == JUMP)
as_bad (_("Unable to use @plt relocation for insn %s"),
opcode->name);
needGOTSymbol = TRUE;
needGOTSymbol = true;
reloc = find_reloc ("plt", opcode->name,
pflags, nflg,
operand->default_reloc);
@ -3985,7 +3983,7 @@ assemble_insn (const struct arc_opcode *opcode,
case O_gotoff:
case O_gotpc:
needGOTSymbol = TRUE;
needGOTSymbol = true;
reloc = ARC_RELOC_TABLE (t->X_md)->reloc;
break;
case O_pcl:
@ -4012,7 +4010,7 @@ assemble_insn (const struct arc_opcode *opcode,
break;
case O_tlsgd:
case O_tlsie:
needGOTSymbol = TRUE;
needGOTSymbol = true;
/* Fall-through. */
case O_tpoff:
@ -4085,7 +4083,7 @@ assemble_insn (const struct arc_opcode *opcode,
/* Check if the instruction has a delay slot. */
if (!strcmp (flg_operand->name, "d"))
has_delay_slot = TRUE;
has_delay_slot = true;
/* There is an exceptional case when we cannot insert a flag just as
it is. On ARCv2 the '.t' and '.nt' flags must be handled in
@ -4136,7 +4134,7 @@ assemble_insn (const struct arc_opcode *opcode,
fixup->exp = *reloc_exp;
fixup->reloc = -bitYoperand;
fixup->pcrel = pcrel;
fixup->islong = FALSE;
fixup->islong = false;
}
}
else
@ -4666,7 +4664,7 @@ arc_extinsn (int ignore ATTRIBUTE_UNUSED)
create_extinst_section (&einsn);
}
static bfd_boolean
static bool
tokenize_extregister (extRegister_t *ereg, int opertype)
{
char *name;
@ -4674,8 +4672,8 @@ tokenize_extregister (extRegister_t *ereg, int opertype)
char c;
char *p;
int number, imode = 0;
bfd_boolean isCore_p = opertype == EXT_CORE_REGISTER;
bfd_boolean isReg_p = opertype == EXT_CORE_REGISTER || opertype == EXT_AUX_REGISTER;
bool isCore_p = opertype == EXT_CORE_REGISTER;
bool isReg_p = opertype == EXT_CORE_REGISTER || opertype == EXT_AUX_REGISTER;
/* 1st: get register name. */
SKIP_WHITESPACE ();
@ -4693,7 +4691,7 @@ tokenize_extregister (extRegister_t *ereg, int opertype)
as_bad (_("expected comma after name"));
ignore_rest_of_line ();
free (name);
return FALSE;
return false;
}
input_line_pointer++;
number = get_absolute_expression ();
@ -4706,7 +4704,7 @@ tokenize_extregister (extRegister_t *ereg, int opertype)
number);
ignore_rest_of_line ();
free (name);
return FALSE;
return false;
}
if (isReg_p)
@ -4719,7 +4717,7 @@ tokenize_extregister (extRegister_t *ereg, int opertype)
as_bad (_("expected comma after register number"));
ignore_rest_of_line ();
free (name);
return FALSE;
return false;
}
input_line_pointer++;
@ -4740,7 +4738,7 @@ tokenize_extregister (extRegister_t *ereg, int opertype)
as_bad (_("invalid mode"));
ignore_rest_of_line ();
free (name);
return FALSE;
return false;
}
else
{
@ -4758,7 +4756,7 @@ tokenize_extregister (extRegister_t *ereg, int opertype)
as_bad (_("expected comma after register mode"));
ignore_rest_of_line ();
free (name);
return FALSE;
return false;
}
input_line_pointer++;
@ -4773,7 +4771,7 @@ tokenize_extregister (extRegister_t *ereg, int opertype)
as_bad (_("shortcut designator invalid"));
ignore_rest_of_line ();
free (name);
return FALSE;
return false;
}
else
{
@ -4785,7 +4783,7 @@ tokenize_extregister (extRegister_t *ereg, int opertype)
ereg->name = name;
ereg->number = number;
ereg->imode = imode;
return TRUE;
return true;
}
/* Create an extension register/condition description in the arc
@ -4916,7 +4914,7 @@ arc_attribute (int ignored ATTRIBUTE_UNUSED)
int tag = obj_elf_vendor_attribute (OBJ_ATTR_PROC);
if (tag < NUM_KNOWN_OBJ_ATTRIBUTES)
attributes_set_explicitly[tag] = TRUE;
attributes_set_explicitly[tag] = true;
}
/* Set an attribute if it has not already been set by the user. */

2
gas/config/tc-arc.h
View File

@ -202,7 +202,7 @@ extern int arc_convert_symbolic_attribute (const char *);
extern void arc_md_end (void);
extern void arc_adjust_symtab (void);
extern int arc_pcrel_adjust (fragS *);
extern bfd_boolean arc_parse_name (const char *, struct expressionS *);
extern bool arc_parse_name (const char *, struct expressionS *);
extern int tc_arc_fix_adjustable (struct fix *);
extern void arc_handle_align (fragS *);
extern void arc_cons_fix_new (fragS *, int, int, expressionS *,

856
gas/config/tc-arm.c
View File

File diff suppressed because it is too large Load Diff

14
gas/config/tc-arm.h
View File

@ -67,7 +67,7 @@ struct fix;
/* We conditionally support labels without a colon. */
#define LABELS_WITHOUT_COLONS codecomposer_syntax
extern bfd_boolean codecomposer_syntax;
extern bool codecomposer_syntax;
#define tc_symbol_chars arm_symbol_chars
extern const char arm_symbol_chars[];
@ -82,7 +82,7 @@ extern unsigned int arm_frag_max_var (struct frag *);
extern int arm_relax_frag (asection *, struct frag *, long);
#define md_optimize_expr(l,o,r) arm_optimize_expr (l, o, r)
extern bfd_boolean arm_optimize_expr (expressionS *, operatorT, expressionS *);
extern bool arm_optimize_expr (expressionS *, operatorT, expressionS *);
#define md_cleanup() arm_cleanup ()
@ -90,7 +90,7 @@ extern bfd_boolean arm_optimize_expr (expressionS *, operatorT, expressionS *);
#define TC_START_LABEL_WITHOUT_COLON(NUL_CHAR, NEXT_CHAR) \
tc_start_label_without_colon ()
extern bfd_boolean tc_start_label_without_colon (void);
extern bool tc_start_label_without_colon (void);
#define tc_frob_label(S) arm_frob_label (S)
@ -100,7 +100,7 @@ extern bfd_boolean tc_start_label_without_colon (void);
#ifdef OBJ_ELF
#define md_end arm_md_end
extern void arm_md_end (void);
bfd_boolean arm_is_eabi (void);
bool arm_is_eabi (void);
#define md_post_relax_hook arm_md_post_relax ()
extern void arm_md_post_relax (void);
@ -348,7 +348,7 @@ extern int arm_force_relocation (struct fix *);
extern void arm_cleanup (void);
extern void arm_start_line_hook (void);
extern void arm_frob_label (symbolS *);
extern bfd_boolean arm_data_in_code (void);
extern bool arm_data_in_code (void);
extern char * arm_canonicalize_symbol_name (char *);
extern void arm_adjust_symtab (void);
extern void armelf_frob_symbol (symbolS *, int *);
@ -356,7 +356,7 @@ extern void cons_fix_new_arm (fragS *, int, int, expressionS *,
bfd_reloc_code_real_type);
extern void arm_init_frag (struct frag *, int);
extern void arm_handle_align (struct frag *);
extern bfd_boolean arm_fix_adjustable (struct fix *);
extern bool arm_fix_adjustable (struct fix *);
extern int arm_elf_section_type (const char *, size_t);
extern int tc_arm_regname_to_dw2regnum (char *regname);
extern void tc_arm_frame_initial_instructions (void);
@ -383,7 +383,7 @@ extern char arm_comment_chars[];
extern char arm_line_separator_chars[];
#define TC_EQUAL_IN_INSN(c, s) arm_tc_equal_in_insn ((c), (s))
extern bfd_boolean arm_tc_equal_in_insn (int, char *);
extern bool arm_tc_equal_in_insn (int, char *);
#define TC_LARGEST_EXPONENT_IS_NORMAL(PRECISION) \
arm_is_largest_exponent_ok ((PRECISION))

64
gas/config/tc-avr.c
View File

@ -37,12 +37,12 @@ struct avr_property_record_link
struct avr_opcodes_s
{
const char * name;
const char * constraints;
const char * opcode;
int insn_size; /* In words. */
int isa;
unsigned int bin_opcode;
const char *name;
const char *constraints;
const char *opcode;
int insn_size; /* In words. */
int isa;
unsigned int bin_opcode;
};
#define AVR_INSN(NAME, CONSTR, OPCODE, SIZE, ISA, BIN) \
@ -791,7 +791,7 @@ avr_undefined_symbol (char *name)
const char *
md_atof (int type, char *litP, int *sizeP)
{
return ieee_md_atof (type, litP, sizeP, FALSE);
return ieee_md_atof (type, litP, sizeP, false);
}
void
@ -1206,7 +1206,7 @@ avr_operand (struct avr_opcodes_s *opcode,
avr_offset_expression (& op_expr);
str = input_line_pointer;
fix_new_exp (frag_now, where, 3,
&op_expr, FALSE, BFD_RELOC_AVR_6);
&op_expr, false, BFD_RELOC_AVR_6);
}
}
break;
@ -1214,31 +1214,31 @@ avr_operand (struct avr_opcodes_s *opcode,
case 'h':
str = parse_exp (str, &op_expr);
fix_new_exp (frag_now, where, opcode->insn_size * 2,
&op_expr, FALSE, BFD_RELOC_AVR_CALL);
&op_expr, false, BFD_RELOC_AVR_CALL);
break;
case 'L':
str = parse_exp (str, &op_expr);
fix_new_exp (frag_now, where, opcode->insn_size * 2,
&op_expr, TRUE, BFD_RELOC_AVR_13_PCREL);
&op_expr, true, BFD_RELOC_AVR_13_PCREL);
break;
case 'l':
str = parse_exp (str, &op_expr);
fix_new_exp (frag_now, where, opcode->insn_size * 2,
&op_expr, TRUE, BFD_RELOC_AVR_7_PCREL);
&op_expr, true, BFD_RELOC_AVR_7_PCREL);
break;
case 'i':
str = parse_exp (str, &op_expr);
fix_new_exp (frag_now, where + 2, opcode->insn_size * 2,
&op_expr, FALSE, BFD_RELOC_16);
&op_expr, false, BFD_RELOC_16);
break;
case 'j':
str = parse_exp (str, &op_expr);
fix_new_exp (frag_now, where, opcode->insn_size * 2,
&op_expr, FALSE, BFD_RELOC_AVR_LDS_STS_16);
&op_expr, false, BFD_RELOC_AVR_LDS_STS_16);
break;
case 'M':
@ -1249,7 +1249,7 @@ avr_operand (struct avr_opcodes_s *opcode,
r_type = avr_ldi_expression (&op_expr);
str = input_line_pointer;
fix_new_exp (frag_now, where, 3,
&op_expr, FALSE, r_type);
&op_expr, false, r_type);
}
break;
@ -1278,7 +1278,7 @@ avr_operand (struct avr_opcodes_s *opcode,
avr_offset_expression (& op_expr);
str = input_line_pointer;
fix_new_exp (frag_now, where, 3,
& op_expr, FALSE, BFD_RELOC_AVR_6_ADIW);
& op_expr, false, BFD_RELOC_AVR_6_ADIW);
break;
case 'S':
@ -1297,13 +1297,13 @@ avr_operand (struct avr_opcodes_s *opcode,
case 'P':
str = parse_exp (str, &op_expr);
fix_new_exp (frag_now, where, opcode->insn_size * 2,
&op_expr, FALSE, BFD_RELOC_AVR_PORT6);
&op_expr, false, BFD_RELOC_AVR_PORT6);
break;
case 'p':
str = parse_exp (str, &op_expr);
fix_new_exp (frag_now, where, opcode->insn_size * 2,
&op_expr, FALSE, BFD_RELOC_AVR_PORT5);
&op_expr, false, BFD_RELOC_AVR_PORT5);
break;
case 'E':
@ -1452,7 +1452,7 @@ md_pcrel_from_section (fixS *fixp, segT sec)
return fixp->fx_frag->fr_address + fixp->fx_where;
}
static bfd_boolean
static bool
relaxable_section (asection *sec)
{
return ((sec->flags & SEC_DEBUGGING) == 0
@ -2020,11 +2020,11 @@ avr_cons_fix_new (fragS *frag,
{
default:
if (nbytes == 1)
fix_new_exp (frag, where, nbytes, exp, FALSE, BFD_RELOC_8);
fix_new_exp (frag, where, nbytes, exp, false, BFD_RELOC_8);
else if (nbytes == 2)
fix_new_exp (frag, where, nbytes, exp, FALSE, BFD_RELOC_16);
fix_new_exp (frag, where, nbytes, exp, false, BFD_RELOC_16);
else if (nbytes == 4)
fix_new_exp (frag, where, nbytes, exp, FALSE, BFD_RELOC_32);
fix_new_exp (frag, where, nbytes, exp, false, BFD_RELOC_32);
else
bad = 1;
break;
@ -2034,7 +2034,7 @@ avr_cons_fix_new (fragS *frag,
case BFD_RELOC_AVR_8_HI:
case BFD_RELOC_AVR_8_HLO:
if (nbytes == pexp_mod_data->nbytes)
fix_new_exp (frag, where, nbytes, exp, FALSE, pexp_mod_data->reloc);
fix_new_exp (frag, where, nbytes, exp, false, pexp_mod_data->reloc);
else
bad = 1;
break;
@ -2044,7 +2044,7 @@ avr_cons_fix_new (fragS *frag,
as_bad (_("illegal %s relocation size: %d"), pexp_mod_data->error, nbytes);
}
static bfd_boolean
static bool
mcu_has_3_byte_pc (void)
{
int mach = avr_mcu->mach;
@ -2069,26 +2069,26 @@ tc_cfi_frame_initial_instructions (void)
cfi_add_CFA_offset (DWARF2_DEFAULT_RETURN_COLUMN, 1-return_size);
}
bfd_boolean
bool
avr_allow_local_subtract (expressionS * left,
expressionS * right,
segT section)
{
/* If we are not in relaxation mode, subtraction is OK. */
if (!linkrelax)
return TRUE;
return true;
/* If the symbols are not in a code section then they are OK. */
if ((section->flags & SEC_CODE) == 0)
return TRUE;
return true;
if (left->X_add_symbol == right->X_add_symbol)
return TRUE;
return true;
/* We have to assume that there may be instructions between the
two symbols and that relaxation may increase the distance between
them. */
return FALSE;
return false;
}
void
@ -2178,7 +2178,7 @@ avr_output_property_record (char * const frag_base, char *frag_ptr,
where = frag_ptr - frag_base;
fix = fix_new (frag_now, where, 4,
section_symbol (record->section),
record->offset, FALSE, BFD_RELOC_32);
record->offset, false, BFD_RELOC_32);
fix->fx_file = "<internal>";
fix->fx_line = 0;
frag_ptr += 4;
@ -2253,7 +2253,7 @@ avr_handle_align (fragS *fragP)
{
char *p = fragP->fr_literal + fragP->fr_fix;
fragP->tc_frag_data.is_align = TRUE;
fragP->tc_frag_data.is_align = true;
fragP->tc_frag_data.alignment = fragP->fr_offset;
fragP->tc_frag_data.fill = *p;
fragP->tc_frag_data.has_fill = (fragP->tc_frag_data.fill != 0);
@ -2263,7 +2263,7 @@ avr_handle_align (fragS *fragP)
{
char *p = fragP->fr_literal + fragP->fr_fix;
fragP->tc_frag_data.is_org = TRUE;
fragP->tc_frag_data.is_org = true;
fragP->tc_frag_data.fill = *p;
fragP->tc_frag_data.has_fill = (fragP->tc_frag_data.fill != 0);
}
@ -2273,7 +2273,7 @@ avr_handle_align (fragS *fragP)
/* Return TRUE if this section is not one for which we need to record
information in the avr property section. */
static bfd_boolean
static bool
exclude_section_from_property_tables (segT sec)
{
/* Only generate property information for sections on which linker

2
gas/config/tc-avr.h
View File

@ -214,7 +214,7 @@ extern void tc_cfi_frame_initial_instructions (void);
/* The difference between same-section symbols may be affected by linker
relaxation, so do not resolve such expressions in the assembler. */
#define md_allow_local_subtract(l,r,s) avr_allow_local_subtract (l, r, s)
extern bfd_boolean avr_allow_local_subtract (expressionS *, expressionS *, segT);
extern bool avr_allow_local_subtract (expressionS *, expressionS *, segT);
#define elf_tc_final_processing avr_elf_final_processing
extern void avr_elf_final_processing (void);

30
gas/config/tc-bfin.c
View File

@ -700,7 +700,7 @@ md_apply_fix (fixS *fixP, valueT *valueP, segT seg ATTRIBUTE_UNUSED)
case BFD_RELOC_BFIN_16_LOW:
case BFD_RELOC_BFIN_16_HIGH:
fixP->fx_done = FALSE;
fixP->fx_done = false;
break;
case BFD_RELOC_BFIN_24_PCREL_JUMP_L:
@ -769,7 +769,7 @@ md_apply_fix (fixS *fixP, valueT *valueP, segT seg ATTRIBUTE_UNUSED)
case BFD_RELOC_BFIN_FUNCDESC:
case BFD_RELOC_VTABLE_INHERIT:
case BFD_RELOC_VTABLE_ENTRY:
fixP->fx_done = FALSE;
fixP->fx_done = false;
break;
default:
@ -781,7 +781,7 @@ md_apply_fix (fixS *fixP, valueT *valueP, segT seg ATTRIBUTE_UNUSED)
}
if (!fixP->fx_addsy)
fixP->fx_done = TRUE;
fixP->fx_done = true;
}
@ -797,7 +797,7 @@ md_section_align (segT segment, valueT size)
const char *
md_atof (int type, char * litP, int * sizeP)
{
return ieee_md_atof (type, litP, sizeP, FALSE);
return ieee_md_atof (type, litP, sizeP, false);
}
@ -852,7 +852,7 @@ md_pcrel_from_section (fixS *fixP, segT sec)
/* Return true if the fix can be handled by GAS, false if it must
be passed through to the linker. */
bfd_boolean
bool
bfin_fix_adjustable (fixS *fixP)
{
switch (fixP->fx_r_type)
@ -1932,7 +1932,7 @@ bfin_loop_beginend (Expr_Node *exp, int begin)
*symbol_X_add_number (linelabel) -= last_insn_size;
}
bfd_boolean
bool
bfin_eol_in_insn (char *line)
{
/* Allow a new-line to appear in the middle of a multi-issue instruction. */
@ -1940,36 +1940,36 @@ bfin_eol_in_insn (char *line)
char *temp = line;
if (*line != '\n')
return FALSE;
return false;
/* A semi-colon followed by a newline is always the end of a line. */
if (line[-1] == ';')
return FALSE;
return false;
if (line[-1] == '|')
return TRUE;
return true;
/* If the || is on the next line, there might be leading whitespace. */
temp++;
while (*temp == ' ' || *temp == '\t') temp++;
if (*temp == '|')
return TRUE;
return true;
return FALSE;
return false;
}
bfd_boolean
bool
bfin_start_label (char *s)
{
while (*s != 0)
{
if (*s == '(' || *s == '[')
return FALSE;
return false;
s++;
}
return TRUE;
return true;
}
int
@ -1977,7 +1977,7 @@ bfin_force_relocation (struct fix *fixp)
{
if (fixp->fx_r_type ==BFD_RELOC_BFIN_16_LOW
|| fixp->fx_r_type == BFD_RELOC_BFIN_16_HIGH)
return TRUE;
return true;
return generic_force_reloc (fixp);
}

6
gas/config/tc-bfin.h
View File

@ -38,7 +38,7 @@
#define WORKING_DOT_WORD
extern bfd_boolean bfin_start_label (char *);
extern bool bfin_start_label (char *);
#define md_number_to_chars number_to_chars_littleendian
#define md_convert_frag(b,s,f) as_fatal ("bfin convert_frag\n");
@ -47,7 +47,7 @@ extern bfd_boolean bfin_start_label (char *);
#define LEX_BR 6
#define TC_EOL_IN_INSN(PTR) (bfin_eol_in_insn(PTR) ? 1 : 0)
extern bfd_boolean bfin_eol_in_insn (char *);
extern bool bfin_eol_in_insn (char *);
/* Almost all instructions of Blackfin contain an = character. */
#define TC_EQUAL_IN_INSN(C, NAME) (NAME[0] != '.' || NAME[1] != 0)
@ -61,7 +61,7 @@ extern bfd_boolean bfin_eol_in_insn (char *);
#define TC_START_LABEL(STR, NUL_CHAR, NEXT_CHAR) \
(NEXT_CHAR == ':' && bfin_start_label (STR))
#define tc_fix_adjustable(FIX) bfin_fix_adjustable (FIX)
extern bfd_boolean bfin_fix_adjustable (struct fix *);
extern bool bfin_fix_adjustable (struct fix *);
#define TC_FORCE_RELOCATION(FIX) bfin_force_relocation (FIX)
extern int bfin_force_relocation (struct fix *);

2
gas/config/tc-bpf.c
View File

@ -419,5 +419,5 @@ md_undefined_symbol (char *name ATTRIBUTE_UNUSED)
const char *
md_atof (int type, char *litP, int *sizeP)
{
return ieee_md_atof (type, litP, sizeP, FALSE);
return ieee_md_atof (type, litP, sizeP, false);
}

38
gas/config/tc-cris.c
View File

@ -166,23 +166,23 @@ static htab_t op_hash = NULL;
we default to no underscore and required register-prefixes. The
difference is in the default values. */
#ifdef TE_LINUX
#define DEFAULT_CRIS_AXIS_LINUX_GNU TRUE
#define DEFAULT_CRIS_AXIS_LINUX_GNU true
#else
#define DEFAULT_CRIS_AXIS_LINUX_GNU FALSE
#define DEFAULT_CRIS_AXIS_LINUX_GNU false
#endif
/* Whether we demand that registers have a `$' prefix. Default here. */
static bfd_boolean demand_register_prefix = DEFAULT_CRIS_AXIS_LINUX_GNU;
static bool demand_register_prefix = DEFAULT_CRIS_AXIS_LINUX_GNU;
/* Whether global user symbols have a leading underscore. Default here. */
static bfd_boolean symbols_have_leading_underscore
static bool symbols_have_leading_underscore
= !DEFAULT_CRIS_AXIS_LINUX_GNU;
/* Whether or not we allow PIC, and expand to PIC-friendly constructs. */
static bfd_boolean pic = FALSE;
static bool pic = false;
/* Whether or not we allow TLS suffixes. For the moment, we always do. */
static const bfd_boolean tls = TRUE;
static const bool tls = true;
/* If we're configured for "cris", default to allow all v0..v10
instructions and register names. */
@ -3491,14 +3491,14 @@ cris_get_reloc_suffix (char **cPP, bfd_reloc_code_real_type *relocp,
const char *const suffix;
unsigned int len;
bfd_reloc_code_real_type reloc;
bfd_boolean pic_p;
bfd_boolean tls_p;
bool pic_p;
bool tls_p;
} pic_suffixes[] =
{
#undef PICMAP
#define PICMAP(s, r) {s, sizeof (s) - 1, r, TRUE, FALSE}
#define PICTLSMAP(s, r) {s, sizeof (s) - 1, r, TRUE, TRUE}
#define TLSMAP(s, r) {s, sizeof (s) - 1, r, FALSE, TRUE}
#define PICMAP(s, r) {s, sizeof (s) - 1, r, true, false}
#define PICTLSMAP(s, r) {s, sizeof (s) - 1, r, true, true}
#define TLSMAP(s, r) {s, sizeof (s) - 1, r, false, true}
/* Keep this in order with longest unambiguous prefix first. */
PICMAP ("GOTPLT16", BFD_RELOC_CRIS_16_GOTPLT),
PICMAP ("GOTPLT", BFD_RELOC_CRIS_32_GOTPLT),
@ -3811,23 +3811,23 @@ md_parse_option (int arg, const char *argp ATTRIBUTE_UNUSED)
break;
case OPTION_NO_US:
demand_register_prefix = TRUE;
demand_register_prefix = true;
if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
as_bad (_("--no-underscore is invalid with a.out format"));
else
symbols_have_leading_underscore = FALSE;
symbols_have_leading_underscore = false;
break;
case OPTION_US:
demand_register_prefix = FALSE;
symbols_have_leading_underscore = TRUE;
demand_register_prefix = false;
symbols_have_leading_underscore = true;
break;
case OPTION_PIC:
if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
as_bad (_("--pic is invalid for this object format"));
pic = TRUE;
pic = true;
if (cris_arch != arch_crisv32)
md_long_jump_size = cris_any_v0_v10_long_jump_size_pic;
else
@ -4133,7 +4133,7 @@ tc_cris_check_adjusted_broken_word (offsetT new_offset, struct broken_word *brok
static void
cris_force_reg_prefix (void)
{
demand_register_prefix = TRUE;
demand_register_prefix = true;
}
/* Do not demand a leading REGISTER_PREFIX_CHAR for all registers. */
@ -4141,7 +4141,7 @@ cris_force_reg_prefix (void)
static void
cris_relax_reg_prefix (void)
{
demand_register_prefix = FALSE;
demand_register_prefix = false;
}
/* Adjust for having a leading '_' on all user symbols. */
@ -4244,7 +4244,7 @@ s_cris_dtpoff (int bytes)
p = frag_more (bytes);
md_number_to_chars (p, 0, bytes);
fix_new_exp (frag_now, p - frag_now->fr_literal, bytes, &ex, FALSE,
fix_new_exp (frag_now, p - frag_now->fr_literal, bytes, &ex, false,
BFD_RELOC_CRIS_32_DTPREL);
demand_empty_rest_of_line ();

666
gas/config/tc-csky.c
View File

File diff suppressed because it is too large Load Diff

2
gas/config/tc-csky.h
View File

@ -97,7 +97,7 @@ extern void csky_cons_fix_new (fragS *,
expressionS *,
bfd_reloc_code_real_type);
extern int csky_force_relocation (fixS *);
extern bfd_boolean csky_fix_adjustable (fixS *);
extern bool csky_fix_adjustable (fixS *);
extern void csky_cfi_frame_initial_instructions (void);
extern int tc_csky_regname_to_dw2regnum (char *);
extern long csky_relax_frag (segT, fragS *, long);

14
gas/config/tc-d10v.c
View File

@ -73,11 +73,11 @@ static packing_type etype = PACK_UNSPEC; /* Used by d10v_cleanup. */
/* TRUE if instruction swapping warnings should be inhibited.
--nowarnswap. */
static bfd_boolean flag_warn_suppress_instructionswap;
static bool flag_warn_suppress_instructionswap;
/* TRUE if instruction packing should be performed when --gstabs is specified.
--gstabs-packing, --no-gstabs-packing. */
static bfd_boolean flag_allow_gstabs_packing = 1;
static bool flag_allow_gstabs_packing = 1;
/* Local functions. */
@ -254,7 +254,7 @@ md_undefined_symbol (char *name ATTRIBUTE_UNUSED)
const char *
md_atof (int type, char *litP, int *sizeP)
{
return ieee_md_atof (type, litP, sizeP, TRUE);
return ieee_md_atof (type, litP, sizeP, true);
}
void
@ -1216,14 +1216,14 @@ find_opcode (struct d10v_opcode *opcode, expressionS myops[])
unsigned long current_position;
unsigned long symbol_position;
unsigned long value;
bfd_boolean found_symbol;
bool found_symbol;
/* Calculate the address of the current instruction
and the address of the symbol. Do this by summing
the offsets of previous frags until we reach the
frag containing the symbol, and the current frag. */
sym_frag = symbol_get_frag (myops[opnum].X_add_symbol);
found_symbol = FALSE;
found_symbol = false;
current_position = frag_now_fix_octets ();
symbol_position = S_GET_VALUE (myops[opnum].X_add_symbol);
@ -1233,7 +1233,7 @@ find_opcode (struct d10v_opcode *opcode, expressionS myops[])
current_position += f->fr_fix + f->fr_offset;
if (f == sym_frag)
found_symbol = TRUE;
found_symbol = true;
if (! found_symbol)
symbol_position += f->fr_fix + f->fr_offset;
@ -1698,7 +1698,7 @@ md_operand (expressionS *expressionP)
}
}
bfd_boolean
bool
d10v_fix_adjustable (fixS *fixP)
{
/* We need the symbol name for the VTABLE entries. */

2
gas/config/tc-d10v.h
View File

@ -51,7 +51,7 @@ void d10v_frob_label (symbolS *);
#define tc_frob_label(sym) d10v_frob_label (sym)
#define tc_fix_adjustable(FIX) d10v_fix_adjustable(FIX)
bfd_boolean d10v_fix_adjustable (struct fix *);
bool d10v_fix_adjustable (struct fix *);
/* Values passed to md_apply_fix don't include the symbol value. */
#define MD_APPLY_SYM_VALUE(FIX) 0

34
gas/config/tc-d30v.c
View File

@ -288,7 +288,7 @@ md_undefined_symbol (char *name ATTRIBUTE_UNUSED)
const char *
md_atof (int type, char *litP, int *sizeP)
{
return ieee_md_atof (type, litP, sizeP, TRUE);
return ieee_md_atof (type, litP, sizeP, true);
}
void
@ -953,7 +953,7 @@ write_2_short (struct d30v_insn *opcode1,
we are not optimizing, then we have been asked to produce
an error about such constructs. For the purposes of this
test, subroutine calls are considered to be branches. */
write_1_short (opcode1, insn1, fx->next, FALSE);
write_1_short (opcode1, insn1, fx->next, false);
return 1;
}
@ -993,14 +993,14 @@ write_2_short (struct d30v_insn *opcode1,
/* We must treat repeat instructions likewise, since the
following instruction has to be separate from the repeat
in order to be repeated. */
write_1_short (opcode1, insn1, fx->next, FALSE);
write_1_short (opcode1, insn1, fx->next, false);
return 1;
}
else if (prev_left_kills_right_p)
{
/* The left instruction kills the right slot, so we
must leave it empty. */
write_1_short (opcode1, insn1, fx->next, FALSE);
write_1_short (opcode1, insn1, fx->next, false);
return 1;
}
else if (opcode1->op->unit == IU)
@ -1010,7 +1010,7 @@ write_2_short (struct d30v_insn *opcode1,
/* Case 103810 is a request from Mitsubishi that opcodes
with EITHER_BUT_PREFER_MU should not be executed in
reverse sequential order. */
write_1_short (opcode1, insn1, fx->next, FALSE);
write_1_short (opcode1, insn1, fx->next, false);
return 1;
}
@ -1485,7 +1485,7 @@ d30v_align (int n, char *pfill, symbolS *label)
this alignment request. The alignment of the current frag
can be changed under our feet, for example by a .ascii
directive in the source code. cf testsuite/gas/d30v/reloc.s */
d30v_cleanup (FALSE);
d30v_cleanup (false);
if (pfill == NULL)
{
@ -1512,7 +1512,7 @@ d30v_align (int n, char *pfill, symbolS *label)
if (label != NULL)
{
symbolS *sym;
int label_seen = FALSE;
int label_seen = false;
struct frag *old_frag;
valueT old_value;
valueT new_value;
@ -1539,7 +1539,7 @@ d30v_align (int n, char *pfill, symbolS *label)
if (symbol_get_frag (sym) == old_frag
&& S_GET_VALUE (sym) == old_value)
{
label_seen = TRUE;
label_seen = true;
symbol_set_frag (sym, frag_now);
S_SET_VALUE (sym, new_value);
}
@ -1575,7 +1575,7 @@ md_assemble (char *str)
if ((prev_insn != -1) && prev_seg
&& ((prev_seg != now_seg) || (prev_subseg != now_subseg)))
d30v_cleanup (FALSE);
d30v_cleanup (false);
if (d30v_current_align < 3)
d30v_align (3, NULL, d30v_last_label);
@ -1614,7 +1614,7 @@ md_assemble (char *str)
/* If two instructions are present and we already have one saved,
then first write it out. */
d30v_cleanup (FALSE);
d30v_cleanup (false);
/* Assemble first instruction and save it. */
prev_insn = do_assemble (str, &prev_opcode, 1, 0);
@ -1675,13 +1675,13 @@ md_assemble (char *str)
of NOPs for us. */
if (prev_insn != -1 && (strcmp (prev_opcode.op->name, "nop") == 0))
d30v_cleanup (FALSE);
d30v_cleanup (false);
else
{
char *f;
if (prev_insn != -1)
d30v_cleanup (TRUE);
d30v_cleanup (true);
else
{
f = frag_more (8);
@ -1707,7 +1707,7 @@ md_assemble (char *str)
{
/* Can't parallelize, flush current instruction and add a
sequential NOP. */
write_1_short (&opcode, (long) insn, fixups->next->next, TRUE);
write_1_short (&opcode, (long) insn, fixups->next->next, true);
/* Make the previous instruction the current one. */
extype = EXEC_UNKNOWN;
@ -1726,7 +1726,7 @@ md_assemble (char *str)
{
if (extype != EXEC_UNKNOWN)
as_bad (_("Instruction uses long version, so it cannot be mixed as specified"));
d30v_cleanup (FALSE);
d30v_cleanup (false);
write_long (&opcode, insn, fixups);
prev_insn = -1;
}
@ -1817,7 +1817,7 @@ d30v_cleanup (int use_sequential)
subseg_set (seg, subseg);
prev_insn = -1;
if (use_sequential)
prev_mul32_p = FALSE;
prev_mul32_p = false;
}
return 1;
@ -1836,7 +1836,7 @@ d30v_start_line (void)
c++;
if (*c == '.')
d30v_cleanup (FALSE);
d30v_cleanup (false);
}
static void
@ -1861,7 +1861,7 @@ void
d30v_frob_label (symbolS *lab)
{
/* Emit any pending instructions. */
d30v_cleanup (FALSE);
d30v_cleanup (false);
/* Update the label's address with the current output pointer. */
symbol_set_frag (lab, frag_now);

4
gas/config/tc-d30v.h
View File

@ -43,9 +43,9 @@
#define md_number_to_chars number_to_chars_bigendian
int d30v_cleanup (int);
#define md_cleanup() d30v_cleanup (FALSE)
#define md_cleanup() d30v_cleanup (false)
#define TC_START_LABEL(STR, NUL_CHAR, NEXT_CHAR) \
(NEXT_CHAR == ':' && d30v_cleanup (FALSE))
(NEXT_CHAR == ':' && d30v_cleanup (false))
void d30v_start_line (void);
#define md_start_line_hook() d30v_start_line ()

4
gas/config/tc-dlx.c
View File

@ -968,7 +968,7 @@ md_assemble (char *str)
const char *
md_atof (int type, char *litP, int *sizeP)
{
return ieee_md_atof (type, litP, sizeP, TRUE);
return ieee_md_atof (type, litP, sizeP, true);
}
/* Write out big-endian. */
@ -978,7 +978,7 @@ md_number_to_chars (char *buf, valueT val, int n)
number_to_chars_bigendian (buf, val, n);
}
bfd_boolean
bool
md_dlx_fix_adjustable (fixS *fixP)
{
/* We need the symbol name for the VTABLE entries. */

2
gas/config/tc-dlx.h
View File

@ -39,7 +39,7 @@
extern void dlx_pop_insert (void);
extern int dlx_unrecognized_line (int);
extern bfd_boolean md_dlx_fix_adjustable (struct fix *);
extern bool md_dlx_fix_adjustable (struct fix *);
#define md_pop_insert() dlx_pop_insert ()

32
gas/config/tc-epiphany.c
View File

@ -59,7 +59,7 @@ const char FLT_CHARS[] = "fFdD";
/* Flag to detect when switching to code section where insn alignment is
implied. */
static bfd_boolean force_code_align = FALSE;
static bool force_code_align = false;
static void
epiphany_elf_section_rtn (int i)
@ -69,7 +69,7 @@ epiphany_elf_section_rtn (int i)
if (force_code_align)
{
do_align (1, NULL, 0, 0);
force_code_align = FALSE;
force_code_align = false;
}
}
@ -79,7 +79,7 @@ epiphany_elf_section_text (int i)
obj_elf_text (i);
do_align (1, NULL, 0, 0);
force_code_align = FALSE;
force_code_align = false;
}
/* The target specific pseudo-ops which we support. */
@ -146,7 +146,7 @@ md_begin (void)
/* Set the machine type. */
bfd_default_set_arch_mach (stdoutput, bfd_arch_epiphany, bfd_mach_epiphany32);
literal_prefix_dollar_hex = TRUE;
literal_prefix_dollar_hex = true;
}
valueT
@ -184,7 +184,7 @@ epiphany_elf_section_flags (int flags,
executable section specifier we set an internal flag to denote when
word alignment should be forced. */
if (flags & SEC_CODE)
force_code_align = TRUE;
force_code_align = true;
return flags;
}
@ -222,16 +222,16 @@ struct epiphany_hi_fixup
#define GOT_NAME "_GLOBAL_OFFSET_TABLE_"
static symbolS * GOT_symbol;
static inline bfd_boolean
static inline bool
epiphany_PIC_related_p (symbolS *sym)
{
expressionS *exp;
if (! sym)
return FALSE;
return false;
if (sym == GOT_symbol)
return TRUE;
return true;
exp = symbol_get_value_expression (sym);
@ -1018,13 +1018,13 @@ md_cgen_lookup_reloc (const CGEN_INSN *insn ATTRIBUTE_UNUSED,
const char *
md_atof (int type, char *litP, int *sizeP)
{
return ieee_md_atof (type, litP, sizeP, FALSE);
return ieee_md_atof (type, litP, sizeP, false);
}
/* Return true if can adjust the reloc to be relative to its section
(such as .data) instead of relative to some symbol. */
bfd_boolean
bool
epiphany_fix_adjustable (fixS *fixP)
{
bfd_reloc_code_real_type reloc_type;
@ -1042,28 +1042,28 @@ epiphany_fix_adjustable (fixS *fixP)
reloc_type = fixP->fx_r_type;
if (fixP->fx_addsy == NULL)
return TRUE;
return true;
/* Prevent all adjustments to global symbols. */
if (S_IS_EXTERNAL (fixP->fx_addsy))
return FALSE;
return false;
if (S_IS_WEAK (fixP->fx_addsy))
return FALSE;
return false;
if (pic_code
&& (reloc_type == BFD_RELOC_EPIPHANY_SIMM24
|| reloc_type == BFD_RELOC_EPIPHANY_SIMM8
|| reloc_type == BFD_RELOC_EPIPHANY_HIGH
|| reloc_type == BFD_RELOC_EPIPHANY_LOW))
return FALSE;
return false;
/* Since we don't use partial_inplace, we must not reduce symbols in
mergeable sections to their section symbol. */
if ((S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0)
return FALSE;
return false;
return TRUE;
return true;
}
void

2
gas/config/tc-epiphany.h
View File

@ -46,7 +46,7 @@
#define MD_APPLY_SYM_VALUE(FIX) 0
#define tc_fix_adjustable(FIX) epiphany_fix_adjustable (FIX)
extern bfd_boolean epiphany_fix_adjustable (struct fix *);
extern bool epiphany_fix_adjustable (struct fix *);
#define MD_PCREL_FROM_SECTION(FIXP, SEC) md_pcrel_from_section (FIXP,SEC)

4
gas/config/tc-fr30.c
View File

@ -320,7 +320,7 @@ md_number_to_chars (char * buf, valueT val, int n)
const char *
md_atof (int type, char * litP, int * sizeP)
{
return ieee_md_atof (type, litP, sizeP, TRUE);
return ieee_md_atof (type, litP, sizeP, true);
}
/* Worker function for fr30_is_colon_insn(). */
@ -409,7 +409,7 @@ fr30_is_colon_insn (char *start, char *nul_char)
return 0;
}
bfd_boolean
bool
fr30_fix_adjustable (fixS * fixP)
{
/* We need the symbol name for the VTABLE entries. */

2
gas/config/tc-fr30.h
View File

@ -44,7 +44,7 @@
#define tc_fix_adjustable(FIX) fr30_fix_adjustable (FIX)
struct fix;
extern bfd_boolean fr30_fix_adjustable (struct fix *);
extern bool fr30_fix_adjustable (struct fix *);
#define tc_gen_reloc gas_cgen_tc_gen_reloc

30
gas/config/tc-frv.c
View File

@ -65,8 +65,8 @@ enum vliw_insn_type
#define NOP_KEEP 1 /* Keep these NOPS. */
#define NOP_DELETE 2 /* Delete these NOPS. */
#define DO_COUNT TRUE
#define DONT_COUNT FALSE
#define DO_COUNT true
#define DONT_COUNT false
/* A list of insns within a VLIW insn. */
struct vliw_insn_list
@ -168,7 +168,7 @@ static FRV_VLIW vliw;
#endif
static unsigned long frv_mach = bfd_mach_frv;
static bfd_boolean fr400_audio;
static bool fr400_audio;
/* Flags to set in the elf header */
static flagword frv_flags = DEFAULT_FLAGS | DEFAULT_FDPIC;
@ -369,14 +369,14 @@ md_parse_option (int c, const char *arg)
{
cpu_flags = EF_FRV_CPU_FR405;
frv_mach = bfd_mach_fr400;
fr400_audio = TRUE;
fr400_audio = true;
}
else if (strcmp (p, "fr400") == 0)
{
cpu_flags = EF_FRV_CPU_FR400;
frv_mach = bfd_mach_fr400;
fr400_audio = FALSE;
fr400_audio = false;
}
else if (strcmp (p, "fr300") == 0)
@ -507,7 +507,7 @@ md_begin (void)
frv_vliw_reset (& vliw, frv_mach, frv_flags);
}
bfd_boolean
bool
frv_md_fdpic_enabled (void)
{
return (frv_flags & EF_FRV_FDPIC) != 0;
@ -516,7 +516,7 @@ frv_md_fdpic_enabled (void)
int chain_num = 0;
static struct vliw_insn_list *
frv_insert_vliw_insn (bfd_boolean count)
frv_insert_vliw_insn (bool count)
{
struct vliw_insn_list *vliw_insn_list_entry;
struct vliw_chain *vliw_chain_entry;
@ -672,7 +672,7 @@ frv_tomcat_shuffle (enum vliw_nop_type this_nop_type,
struct vliw_insn_list *insert_before_insn)
{
bfd_boolean pack_prev = FALSE;
bool pack_prev = false;
struct vliw_chain *return_me = NULL;
struct vliw_insn_list *prev_insn = NULL;
struct vliw_insn_list *curr_insn = vliw_to_split->insn_list;
@ -693,7 +693,7 @@ frv_tomcat_shuffle (enum vliw_nop_type this_nop_type,
Then don't set pack bit later. */
if (curr_insn->type != VLIW_LABEL_TYPE)
pack_prev = TRUE;
pack_prev = true;
prev_insn = curr_insn;
curr_insn = curr_insn->next;
}
@ -1055,14 +1055,14 @@ fr550_check_acc_range (FRV_VLIW *vlw, frv_insn *insn)
/* Return true if the target implements instruction INSN. */
static bfd_boolean
static bool
target_implements_insn_p (const CGEN_INSN *insn)
{
switch (frv_mach)
{
default:
/* bfd_mach_frv or generic. */
return TRUE;
return true;
case bfd_mach_fr300:
case bfd_mach_frvsimple:
@ -1336,11 +1336,11 @@ md_cgen_lookup_reloc (const CGEN_INSN *insn ATTRIBUTE_UNUSED,
switch (operand->type)
{
case FRV_OPERAND_LABEL16:
fixP->fx_pcrel = TRUE;
fixP->fx_pcrel = true;
return BFD_RELOC_FRV_LABEL16;
case FRV_OPERAND_LABEL24:
fixP->fx_pcrel = TRUE;
fixP->fx_pcrel = true;
if (fixP->fx_cgen.opinfo != 0)
return fixP->fx_cgen.opinfo;
@ -1515,10 +1515,10 @@ frv_md_number_to_chars (char *buf, valueT val, int n)
const char *
md_atof (int type, char *litP, int *sizeP)
{
return ieee_md_atof (type, litP, sizeP, TRUE);
return ieee_md_atof (type, litP, sizeP, true);
}
bfd_boolean
bool
frv_fix_adjustable (fixS *fixP)
{
bfd_reloc_code_real_type reloc_type;

4
gas/config/tc-frv.h
View File

@ -27,7 +27,7 @@
#define TARGET_FORMAT (frv_md_fdpic_enabled () \
? "elf32-frvfdpic" : "elf32-frv")
extern bfd_boolean frv_md_fdpic_enabled (void);
extern bool frv_md_fdpic_enabled (void);
#define TARGET_BYTES_BIG_ENDIAN 1
@ -53,7 +53,7 @@ extern long frv_relax_frag (fragS *, long);
#define tc_fix_adjustable(FIX) frv_fix_adjustable (FIX)
struct fix;
extern bfd_boolean frv_fix_adjustable (struct fix *);
extern bool frv_fix_adjustable (struct fix *);
/* When relaxing, we need to emit various relocs we otherwise wouldn't. */
#define TC_FORCE_RELOCATION(fix) frv_force_relocation (fix)

28
gas/config/tc-ft32.c
View File

@ -207,9 +207,9 @@ md_assemble (char *str)
unsigned int b;
int f;
expressionS arg;
bfd_boolean fixed = FALSE;
bool fixed = false;
unsigned int sc;
bfd_boolean can_sc;
bool can_sc;
/* Drop leading whitespace. */
while (*str == ' ')
@ -313,7 +313,7 @@ md_assemble (char *str)
{
b |= 0x400 << FT32_FLD_RIMM_BIT;
op_end = parse_exp_save_ilp (op_end, &arg);
fixed = TRUE;
fixed = true;
fix_new_exp (frag_now,
(output - frag_now->fr_literal),
2,
@ -327,7 +327,7 @@ md_assemble (char *str)
break;
case FT32_FLD_K20:
op_end = parse_exp_save_ilp (op_end, &arg);
fixed = TRUE;
fixed = true;
fix_new_exp (frag_now,
(output - frag_now->fr_literal),
3,
@ -337,7 +337,7 @@ md_assemble (char *str)
break;
case FT32_FLD_PA:
op_end = parse_exp_save_ilp (op_end, &arg);
fixed = TRUE;
fixed = true;
fix_new_exp (frag_now,
(output - frag_now->fr_literal),
3,
@ -347,7 +347,7 @@ md_assemble (char *str)
break;
case FT32_FLD_AA:
op_end = parse_exp_save_ilp (op_end, &arg);
fixed = TRUE;
fixed = true;
fix_new_exp (frag_now,
(output - frag_now->fr_literal),
3,
@ -357,7 +357,7 @@ md_assemble (char *str)
break;
case FT32_FLD_K16:
op_end = parse_exp_save_ilp (op_end, &arg);
fixed = TRUE;
fixed = true;
fix_new_exp (frag_now,
(output - frag_now->fr_literal),
2,
@ -369,7 +369,7 @@ md_assemble (char *str)
op_end = parse_exp_save_ilp (op_end, &arg);
if (arg.X_add_number & 0x80)
arg.X_add_number ^= 0x7f00;
fixed = TRUE;
fixed = true;
fix_new_exp (frag_now,
(output - frag_now->fr_literal),
2,
@ -716,7 +716,7 @@ tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixP)
/* TC_FORCE_RELOCATION hook */
static bfd_boolean
static bool
relaxable_section (asection *sec)
{
return ((sec->flags & SEC_DEBUGGING) == 0
@ -769,24 +769,24 @@ ft32_force_relocation (fixS *fix)
return generic_force_reloc (fix);
}
bfd_boolean
bool
ft32_allow_local_subtract (expressionS * left,
expressionS * right,
segT section)
{
/* If we are not in relaxation mode, subtraction is OK. */
if (!linkrelax)
return TRUE;
return true;
/* If the symbols are not in a code section then they are OK. */
if ((section->flags & SEC_CODE) == 0)
return TRUE;
return true;
if (left->X_add_symbol == right->X_add_symbol)
return TRUE;
return true;
/* We have to assume that there may be instructions between the
two symbols and that relaxation may increase the distance between
them. */
return FALSE;
return false;
}

4
gas/config/tc-ft32.h
View File

@ -61,8 +61,6 @@ extern int ft32_validate_fix_sub (struct fix *);
/* The difference between same-section symbols may be affected by linker
relaxation, so do not resolve such expressions in the assembler. */
#define md_allow_local_subtract(l,r,s) ft32_allow_local_subtract (l, r, s)
extern bfd_boolean ft32_allow_local_subtract (expressionS *,
expressionS *,
segT);
extern bool ft32_allow_local_subtract (expressionS *, expressionS *, segT);
#define md_operand(x)

2
gas/config/tc-h8300.c
View File

@ -2074,7 +2074,7 @@ md_undefined_symbol (char *name ATTRIBUTE_UNUSED)
const char *
md_atof (int type, char *litP, int *sizeP)
{
return ieee_md_atof (type, litP, sizeP, TRUE);
return ieee_md_atof (type, litP, sizeP, true);
}
#define OPTION_H_TICK_HEX (OPTION_MD_BASE)

44
gas/config/tc-hppa.c
View File

@ -1322,7 +1322,7 @@ pa_parse_nullif (char **s)
const char *
md_atof (int type, char *litP, int *sizeP)
{
return ieee_md_atof (type, litP, sizeP, TRUE);
return ieee_md_atof (type, litP, sizeP, true);
}
/* Write out big-endian. */
@ -2029,7 +2029,7 @@ pa_parse_number (char **s, int is_float)
symbolS *sym;
int status;
char *p = *s;
bfd_boolean have_prefix;
bool have_prefix;
/* Skip whitespace before the number. */
while (*p == ' ' || *p == '\t')
@ -2168,7 +2168,7 @@ pa_parse_number (char **s, int is_float)
num = S_GET_VALUE (sym);
/* Well, we don't really have one, but we do have a
register, so... */
have_prefix = TRUE;
have_prefix = true;
}
else if (S_GET_SEGMENT (sym) == bfd_abs_section_ptr)
num = S_GET_VALUE (sym);
@ -2223,10 +2223,10 @@ need_pa11_opcode (void)
if (!bfd_set_arch_mach (stdoutput, bfd_arch_hppa, pa11))
as_warn (_("could not update architecture and machine"));
}
return TRUE;
return true;
}
else
return FALSE;
return false;
}
/* Parse a condition for a fcmp instruction. Return the numerical
@ -3170,7 +3170,7 @@ pa_ip (char *str)
const char *error_message = "";
char *s, c, *argstart, *name, *save_s;
const char *args;
int match = FALSE;
int match = false;
int comma = 0;
int cmpltr, nullif, flag, cond, need_cond, num;
int immediate_check = 0, pos = -1, len = -1;
@ -3253,7 +3253,7 @@ pa_ip (char *str)
/* End of arguments. */
case '\0':
if (*s == '\0')
match = TRUE;
match = true;
break;
case '+':
@ -5690,7 +5690,7 @@ pa_ip (char *str)
&& !bfd_set_arch_mach (stdoutput, bfd_arch_hppa, insn->arch))
{
as_warn (_("could not update architecture and machine"));
match = FALSE;
match = false;
}
failed:
@ -6070,7 +6070,7 @@ pa_callinfo (int unused ATTRIBUTE_UNUSED)
/* Mark the fact that we found the .CALLINFO for the
current procedure. */
callinfo_found = TRUE;
callinfo_found = true;
/* Iterate over the .CALLINFO arguments. */
while (!is_end_of_statement ())
@ -6304,7 +6304,7 @@ pa_entry (int unused ATTRIBUTE_UNUSED)
as_bad (_("Missing .callinfo."));
}
demand_empty_rest_of_line ();
within_entry_exit = TRUE;
within_entry_exit = true;
#ifdef OBJ_SOM
/* SOM defers building of unwind descriptors until the link phase.
@ -6510,7 +6510,7 @@ pa_exit (int unused ATTRIBUTE_UNUSED)
as_bad (_("No .ENTRY for this .EXIT"));
else
{
within_entry_exit = FALSE;
within_entry_exit = false;
process_exit ();
}
}
@ -6907,8 +6907,8 @@ pa_proc (int unused ATTRIBUTE_UNUSED)
as_fatal (_("Nested procedures"));
/* Reset global variables for new procedure. */
callinfo_found = FALSE;
within_procedure = TRUE;
callinfo_found = false;
within_procedure = true;
/* Create another call_info structure. */
call_info = XNEW (struct call_info);
@ -7026,7 +7026,7 @@ pa_procend (int unused ATTRIBUTE_UNUSED)
hppa_elf_mark_end_of_function ();
#endif
within_procedure = FALSE;
within_procedure = false;
demand_empty_rest_of_line ();
pa_undefine_label ();
}
@ -7077,9 +7077,9 @@ pa_parse_space_stmt (const char *space_name, int create_flag)
/* Load default values. */
spnum = 0;
sort = 0;
loadable = TRUE;
defined = TRUE;
private = FALSE;
loadable = true;
defined = true;
private = false;
if (strcmp (space_name, "$TEXT$") == 0)
{
seg = pa_def_spaces[0].segment;
@ -7099,7 +7099,7 @@ pa_parse_space_stmt (const char *space_name, int create_flag)
if (!is_end_of_statement ())
{
print_errors = FALSE;
print_errors = false;
ptemp = input_line_pointer + 1;
/* First see if the space was specified as a number rather than
as a name. According to the PA assembly manual the rest of
@ -7132,17 +7132,17 @@ pa_parse_space_stmt (const char *space_name, int create_flag)
else if ((strncasecmp (name, "unloadable", 10) == 0))
{
(void) restore_line_pointer (c);
loadable = FALSE;
loadable = false;
}
else if ((strncasecmp (name, "notdefined", 10) == 0))
{
(void) restore_line_pointer (c);
defined = FALSE;
defined = false;
}
else if ((strncasecmp (name, "private", 7) == 0))
{
(void) restore_line_pointer (c);
private = TRUE;
private = true;
}
else
{
@ -7153,7 +7153,7 @@ pa_parse_space_stmt (const char *space_name, int create_flag)
}
}
}
print_errors = TRUE;
print_errors = true;
}
if (create_flag && seg == NULL)

14
gas/config/tc-i386-intel.c
View File

@ -767,19 +767,19 @@ i386_intel_operand (char *operand_string, int got_a_float)
|| current_templates->start->opcode_modifier.jump == JUMP_DWORD
|| current_templates->start->opcode_modifier.jump == JUMP_INTERSEGMENT)
{
bfd_boolean jumpabsolute = FALSE;
bool jumpabsolute = false;
if (i.op[this_operand].regs
|| intel_state.base
|| intel_state.index
|| intel_state.is_mem > 1)
jumpabsolute = TRUE;
jumpabsolute = true;
else
switch (intel_state.op_modifier)
{
case O_near_ptr:
if (intel_state.seg)
jumpabsolute = TRUE;
jumpabsolute = true;
else
intel_state.is_mem = 1;
break;
@ -791,14 +791,14 @@ i386_intel_operand (char *operand_string, int got_a_float)
if (intel_state.op_modifier == O_absent)
{
if (intel_state.is_indirect == 1)
jumpabsolute = TRUE;
jumpabsolute = true;
break;
}
as_bad (_("cannot infer the segment part of the operand"));
return 0;
}
else if (S_GET_SEGMENT (intel_state.seg) == reg_section)
jumpabsolute = TRUE;
jumpabsolute = true;
else
{
i386_operand_type types;
@ -832,12 +832,12 @@ i386_intel_operand (char *operand_string, int got_a_float)
}
break;
default:
jumpabsolute = TRUE;
jumpabsolute = true;
break;
}
if (jumpabsolute)
{
i.jumpabsolute = TRUE;
i.jumpabsolute = true;
intel_state.is_mem |= 1;
}
}

136
gas/config/tc-i386.c
View File

@ -322,10 +322,10 @@ struct _i386_insn
unsigned char prefix[MAX_PREFIXES];
/* Register is in low 3 bits of opcode. */
bfd_boolean short_form;
bool short_form;
/* The operand to a branch insn indicates an absolute branch. */
bfd_boolean jumpabsolute;
bool jumpabsolute;
/* Extended states. */
enum
@ -345,7 +345,7 @@ struct _i386_insn
} xstate;
/* Has GOTPC or TLS relocation. */
bfd_boolean has_gotpc_tls_reloc;
bool has_gotpc_tls_reloc;
/* RM and SIB are the modrm byte and the sib byte where the
addressing modes of this insn are encoded. */
@ -422,10 +422,10 @@ struct _i386_insn
} disp_encoding;
/* Prefer the REX byte in encoding. */
bfd_boolean rex_encoding;
bool rex_encoding;
/* Disable instruction size optimization. */
bfd_boolean no_optimize;
bool no_optimize;
/* How to encode vector instructions. */
enum
@ -3806,7 +3806,7 @@ build_vex_prefix (const insn_template *t)
}
}
static INLINE bfd_boolean
static INLINE bool
is_evex_encoding (const insn_template *t)
{
return t->opcode_modifier.evex || t->opcode_modifier.disp8memshift
@ -3814,7 +3814,7 @@ is_evex_encoding (const insn_template *t)
|| t->opcode_modifier.sae;
}
static INLINE bfd_boolean
static INLINE bool
is_any_vex_encoding (const insn_template *t)
{
return t->opcode_modifier.vex || is_evex_encoding (t);
@ -5022,7 +5022,7 @@ md_assemble (char *line)
&& i.op[x].regs->reg_num > 3)
{
gas_assert (!(i.op[x].regs->reg_flags & RegRex));
i.rex_encoding = FALSE;
i.rex_encoding = false;
break;
}
@ -5164,11 +5164,11 @@ parse_insn (char *line, char *mnemonic)
break;
case Prefix_REX:
/* {rex} */
i.rex_encoding = TRUE;
i.rex_encoding = true;
break;
case Prefix_NoOptimize:
/* {nooptimize} */
i.no_optimize = TRUE;
i.no_optimize = true;
break;
default:
abort ();
@ -6375,7 +6375,7 @@ match_template (char mnem_suffix)
break;
if (j < MAX_OPERANDS)
{
bfd_boolean override = (i.prefix[ADDR_PREFIX] != 0);
bool override = (i.prefix[ADDR_PREFIX] != 0);
addr_prefix_disp = j;
@ -6785,7 +6785,7 @@ check_string (void)
static int
process_suffix (void)
{
bfd_boolean is_crc32 = FALSE, is_movx = FALSE;
bool is_crc32 = false, is_movx = false;
/* If matched instruction specifies an explicit instruction mnemonic
suffix, use it. */
@ -7810,7 +7810,7 @@ process_operands (void)
}
static INLINE void set_rex_vrex (const reg_entry *r, unsigned int rex_bit,
bfd_boolean do_sse2avx)
bool do_sse2avx)
{
if (r->reg_flags & RegRex)
{
@ -8042,14 +8042,14 @@ build_modrm_byte (void)
i.rm.reg = i.op[dest].regs->reg_num;
i.rm.regmem = i.op[source].regs->reg_num;
set_rex_vrex (i.op[dest].regs, REX_R, i.tm.opcode_modifier.sse2avx);
set_rex_vrex (i.op[source].regs, REX_B, FALSE);
set_rex_vrex (i.op[source].regs, REX_B, false);
}
else
{
i.rm.reg = i.op[source].regs->reg_num;
i.rm.regmem = i.op[dest].regs->reg_num;
set_rex_vrex (i.op[dest].regs, REX_B, i.tm.opcode_modifier.sse2avx);
set_rex_vrex (i.op[source].regs, REX_R, FALSE);
set_rex_vrex (i.op[source].regs, REX_R, false);
}
if (flag_code != CODE_64BIT && (i.rex & REX_R))
{
@ -8111,7 +8111,7 @@ build_modrm_byte (void)
i.sib.index = NO_INDEX_REGISTER;
else
i.sib.index = i.index_reg->reg_num;
set_rex_vrex (i.index_reg, REX_X, FALSE);
set_rex_vrex (i.index_reg, REX_X, false);
}
}
@ -8628,41 +8628,41 @@ output_branch (void)
/* Return TRUE iff PLT32 relocation should be used for branching to
symbol S. */
static bfd_boolean
static bool
need_plt32_p (symbolS *s)
{
/* PLT32 relocation is ELF only. */
if (!IS_ELF)
return FALSE;
return false;
#ifdef TE_SOLARIS
/* Don't emit PLT32 relocation on Solaris: neither native linker nor
krtld support it. */
return FALSE;
return false;
#endif
/* Since there is no need to prepare for PLT branch on x86-64, we
can generate R_X86_64_PLT32, instead of R_X86_64_PC32, which can
be used as a marker for 32-bit PC-relative branches. */
if (!object_64bit)
return FALSE;
return false;
if (s == NULL)
return FALSE;
return false;
/* Weak or undefined symbol need PLT32 relocation. */
if (S_IS_WEAK (s) || !S_IS_DEFINED (s))
return TRUE;
return true;
/* Non-global symbol doesn't need PLT32 relocation. */
if (! S_IS_EXTERNAL (s))
return FALSE;
return false;
/* Other global symbols need PLT32 relocation. NB: Symbol with
non-default visibilities are treated as normal global symbol
so that PLT32 relocation can be used as a marker for 32-bit
PC-relative branches. It is useful for linker relaxation. */
return TRUE;
return true;
}
#endif
@ -9815,7 +9815,7 @@ output_disp (fragS *insn_start_frag, offsetT insn_start_off)
if (!object_64bit)
{
reloc_type = BFD_RELOC_386_GOTPC;
i.has_gotpc_tls_reloc = TRUE;
i.has_gotpc_tls_reloc = true;
i.op[n].imms->X_add_number +=
encoding_length (insn_start_frag, insn_start_off, p);
}
@ -9843,7 +9843,7 @@ output_disp (fragS *insn_start_frag, offsetT insn_start_off)
case BFD_RELOC_X86_64_GOTTPOFF:
case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
case BFD_RELOC_X86_64_TLSDESC_CALL:
i.has_gotpc_tls_reloc = TRUE;
i.has_gotpc_tls_reloc = true;
default:
break;
}
@ -9992,7 +9992,7 @@ output_imm (fragS *insn_start_frag, offsetT insn_start_off)
reloc_type = BFD_RELOC_X86_64_GOTPC32;
else if (size == 8)
reloc_type = BFD_RELOC_X86_64_GOTPC64;
i.has_gotpc_tls_reloc = TRUE;
i.has_gotpc_tls_reloc = true;
i.op[n].imms->X_add_number +=
encoding_length (insn_start_frag, insn_start_off, p);
}
@ -10063,64 +10063,64 @@ lex_got (enum bfd_reloc_code_real *rel,
int len;
const enum bfd_reloc_code_real rel[2];
const i386_operand_type types64;
bfd_boolean need_GOT_symbol;
bool need_GOT_symbol;
} gotrel[] = {
#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
{ STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32,
BFD_RELOC_SIZE32 },
OPERAND_TYPE_IMM32_64, FALSE },
OPERAND_TYPE_IMM32_64, false },
#endif
{ STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real,
BFD_RELOC_X86_64_PLTOFF64 },
OPERAND_TYPE_IMM64, TRUE },
OPERAND_TYPE_IMM64, true },
{ STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32,
BFD_RELOC_X86_64_PLT32 },
OPERAND_TYPE_IMM32_32S_DISP32, FALSE },
OPERAND_TYPE_IMM32_32S_DISP32, false },
{ STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real,
BFD_RELOC_X86_64_GOTPLT64 },
OPERAND_TYPE_IMM64_DISP64, TRUE },
OPERAND_TYPE_IMM64_DISP64, true },
{ STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF,
BFD_RELOC_X86_64_GOTOFF64 },
OPERAND_TYPE_IMM64_DISP64, TRUE },
OPERAND_TYPE_IMM64_DISP64, true },
{ STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real,
BFD_RELOC_X86_64_GOTPCREL },
OPERAND_TYPE_IMM32_32S_DISP32, TRUE },
OPERAND_TYPE_IMM32_32S_DISP32, true },
{ STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD,
BFD_RELOC_X86_64_TLSGD },
OPERAND_TYPE_IMM32_32S_DISP32, TRUE },
OPERAND_TYPE_IMM32_32S_DISP32, true },
{ STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM,
_dummy_first_bfd_reloc_code_real },
OPERAND_TYPE_NONE, TRUE },
OPERAND_TYPE_NONE, true },
{ STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real,
BFD_RELOC_X86_64_TLSLD },
OPERAND_TYPE_IMM32_32S_DISP32, TRUE },
OPERAND_TYPE_IMM32_32S_DISP32, true },
{ STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32,
BFD_RELOC_X86_64_GOTTPOFF },
OPERAND_TYPE_IMM32_32S_DISP32, TRUE },
OPERAND_TYPE_IMM32_32S_DISP32, true },
{ STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32,
BFD_RELOC_X86_64_TPOFF32 },
OPERAND_TYPE_IMM32_32S_64_DISP32_64, TRUE },
OPERAND_TYPE_IMM32_32S_64_DISP32_64, true },
{ STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE,
_dummy_first_bfd_reloc_code_real },
OPERAND_TYPE_NONE, TRUE },
OPERAND_TYPE_NONE, true },
{ STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32,
BFD_RELOC_X86_64_DTPOFF32 },
OPERAND_TYPE_IMM32_32S_64_DISP32_64, TRUE },
OPERAND_TYPE_IMM32_32S_64_DISP32_64, true },
{ STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE,
_dummy_first_bfd_reloc_code_real },
OPERAND_TYPE_NONE, TRUE },
OPERAND_TYPE_NONE, true },
{ STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE,
_dummy_first_bfd_reloc_code_real },
OPERAND_TYPE_NONE, TRUE },
OPERAND_TYPE_NONE, true },
{ STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32,
BFD_RELOC_X86_64_GOT32 },
OPERAND_TYPE_IMM32_32S_64_DISP32, TRUE },
OPERAND_TYPE_IMM32_32S_64_DISP32, true },
{ STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC,
BFD_RELOC_X86_64_GOTPC32_TLSDESC },
OPERAND_TYPE_IMM32_32S_DISP32, TRUE },
OPERAND_TYPE_IMM32_32S_DISP32, true },
{ STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL,
BFD_RELOC_X86_64_TLSDESC_CALL },
OPERAND_TYPE_IMM32_32S_DISP32, TRUE },
OPERAND_TYPE_IMM32_32S_DISP32, true },
};
char *cp;
unsigned int j;
@ -10757,7 +10757,7 @@ i386_displacement (char *disp_start, char *disp_end)
branch template. */
static templates aux_templates;
const insn_template *t = current_templates->start;
bfd_boolean has_intel64 = FALSE;
bool has_intel64 = false;
aux_templates.start = t;
while (++t < current_templates->end)
@ -10766,7 +10766,7 @@ i386_displacement (char *disp_start, char *disp_end)
!= current_templates->start->opcode_modifier.jump)
break;
if ((t->opcode_modifier.isa64 >= INTEL64))
has_intel64 = TRUE;
has_intel64 = true;
}
if (t < current_templates->end)
{
@ -11272,7 +11272,7 @@ maybe_adjust_templates (void)
if (t < current_templates->end)
{
static templates aux_templates;
bfd_boolean recheck;
bool recheck;
aux_templates.start = t;
for (; t < current_templates->end; ++t)
@ -11319,7 +11319,7 @@ i386_att_operand (char *operand_string)
++op_string;
if (is_space_char (*op_string))
++op_string;
i.jumpabsolute = TRUE;
i.jumpabsolute = true;
}
/* Check if operand is a register. */
@ -11358,7 +11358,7 @@ i386_att_operand (char *operand_string)
++op_string;
if (is_space_char (*op_string))
++op_string;
i.jumpabsolute = TRUE;
i.jumpabsolute = true;
}
goto do_memory_reference;
}
@ -12593,7 +12593,7 @@ md_atof (int type, char *litP, int *sizeP)
{
/* This outputs the LITTLENUMs in REVERSE order;
in accord with the bigendian 386. */
return ieee_md_atof (type, litP, sizeP, FALSE);
return ieee_md_atof (type, litP, sizeP, false);
}
static char output_invalid_buf[sizeof (unsigned char) * 2 + 6];
@ -12612,58 +12612,58 @@ output_invalid (int c)
/* Verify that @r can be used in the current context. */
static bfd_boolean check_register (const reg_entry *r)
static bool check_register (const reg_entry *r)
{
if (allow_pseudo_reg)
return TRUE;
return true;
if (operand_type_all_zero (&r->reg_type))
return FALSE;
return false;
if ((r->reg_type.bitfield.dword
|| (r->reg_type.bitfield.class == SReg && r->reg_num > 3)
|| r->reg_type.bitfield.class == RegCR
|| r->reg_type.bitfield.class == RegDR)
&& !cpu_arch_flags.bitfield.cpui386)
return FALSE;
return false;
if (r->reg_type.bitfield.class == RegTR
&& (flag_code == CODE_64BIT
|| !cpu_arch_flags.bitfield.cpui386
|| cpu_arch_isa_flags.bitfield.cpui586
|| cpu_arch_isa_flags.bitfield.cpui686))
return FALSE;
return false;
if (r->reg_type.bitfield.class == RegMMX && !cpu_arch_flags.bitfield.cpummx)
return FALSE;
return false;
if (!cpu_arch_flags.bitfield.cpuavx512f)
{
if (r->reg_type.bitfield.zmmword
|| r->reg_type.bitfield.class == RegMask)
return FALSE;
return false;
if (!cpu_arch_flags.bitfield.cpuavx)
{
if (r->reg_type.bitfield.ymmword)
return FALSE;
return false;
if (!cpu_arch_flags.bitfield.cpusse && r->reg_type.bitfield.xmmword)
return FALSE;
return false;
}
}
if (r->reg_type.bitfield.tmmword
&& (!cpu_arch_flags.bitfield.cpuamx_tile
|| flag_code != CODE_64BIT))
return FALSE;
return false;
if (r->reg_type.bitfield.class == RegBND && !cpu_arch_flags.bitfield.cpumpx)
return FALSE;
return false;
/* Don't allow fake index register unless allow_index_reg isn't 0. */
if (!allow_index_reg && r->reg_num == RegIZ)
return FALSE;
return false;
/* Upper 16 vector registers are only available with VREX in 64bit
mode, and require EVEX encoding. */
@ -12671,7 +12671,7 @@ static bfd_boolean check_register (const reg_entry *r)
{
if (!cpu_arch_flags.bitfield.cpuavx512f
|| flag_code != CODE_64BIT)
return FALSE;
return false;
if (i.vec_encoding == vex_encoding_default)
i.vec_encoding = vex_encoding_evex;
@ -12682,13 +12682,13 @@ static bfd_boolean check_register (const reg_entry *r)
if (((r->reg_flags & (RegRex64 | RegRex)) || r->reg_type.bitfield.qword)
&& (!cpu_arch_flags.bitfield.cpulm || r->reg_type.bitfield.class != RegCR)
&& flag_code != CODE_64BIT)
return FALSE;
return false;
if (r->reg_type.bitfield.class == SReg && r->reg_num == RegFlat
&& !intel_syntax)
return FALSE;
return false;
return TRUE;
return true;
}
/* REG_STRING starts *before* REGISTER_PREFIX. */

12
gas/config/tc-ia64.c
View File

@ -164,7 +164,7 @@ struct label_fix
{
struct label_fix *next;
struct symbol *sym;
bfd_boolean dw2_mark_labels;
bool dw2_mark_labels;
};
#ifdef TE_VMS
@ -947,7 +947,7 @@ ia64_flush_insns (void)
segT saved_seg;
subsegT saved_subseg;
unw_rec_list *ptr;
bfd_boolean mark;
bool mark;
if (!md.last_text_seg)
return;
@ -962,7 +962,7 @@ ia64_flush_insns (void)
/* In case there are labels following the last instruction, resolve
those now. */
mark = FALSE;
mark = false;
for (lfix = CURR_SLOT.label_fixups; lfix; lfix = lfix->next)
{
symbol_set_value_now (lfix->sym);
@ -6520,7 +6520,7 @@ emit_one_bundle (void)
int n, i, j, first, curr, last_slot;
bfd_vma t0 = 0, t1 = 0;
struct label_fix *lfix;
bfd_boolean mark_label;
bool mark_label;
struct insn_fix *ifix;
char mnemonic[16];
fixS *fix;
@ -6847,7 +6847,7 @@ emit_one_bundle (void)
continue; /* Try next slot. */
/* Now is a good time to fix up the labels for this insn. */
mark_label = FALSE;
mark_label = false;
for (lfix = md.slot[curr].label_fixups; lfix; lfix = lfix->next)
{
S_SET_VALUE (lfix->sym, frag_now_fix () - 16);
@ -7755,7 +7755,7 @@ ia64_frob_label (struct symbol *sym)
fix = XOBNEW (&notes, struct label_fix);
fix->sym = sym;
fix->next = CURR_SLOT.tag_fixups;
fix->dw2_mark_labels = FALSE;
fix->dw2_mark_labels = false;
CURR_SLOT.tag_fixups = fix;
return;

4
gas/config/tc-ip2k.c
View File

@ -161,7 +161,7 @@ md_begin (void)
/* Set the machine type. */
bfd_default_set_arch_mach (stdoutput, bfd_arch_ip2k, ip2k_mach);
literal_prefix_dollar_hex = TRUE;
literal_prefix_dollar_hex = true;
}
@ -315,7 +315,7 @@ md_number_to_chars (char * buf, valueT val, int n)
const char *
md_atof (int type, char * litP, int * sizeP)
{
return ieee_md_atof (type, litP, sizeP, TRUE);
return ieee_md_atof (type, litP, sizeP, true);
}

14
gas/config/tc-iq2000.c
View File

@ -731,10 +731,10 @@ md_operand (expressionS * exp)
const char *
md_atof (int type, char * litP, int * sizeP)
{
return ieee_md_atof (type, litP, sizeP, TRUE);
return ieee_md_atof (type, litP, sizeP, true);
}
bfd_boolean
bool
iq2000_fix_adjustable (fixS * fixP)
{
bfd_reloc_code_real_type reloc_type;
@ -751,21 +751,21 @@ iq2000_fix_adjustable (fixS * fixP)
reloc_type = fixP->fx_r_type;
if (fixP->fx_addsy == NULL)
return TRUE;
return true;
/* Prevent all adjustments to global symbols. */
if (S_IS_EXTERNAL (fixP->fx_addsy))
return FALSE;
return false;
if (S_IS_WEAK (fixP->fx_addsy))
return FALSE;
return false;
/* We need the symbol name for the VTABLE entries. */
if ( reloc_type == BFD_RELOC_VTABLE_INHERIT
|| reloc_type == BFD_RELOC_VTABLE_ENTRY)
return FALSE;
return false;
return TRUE;
return true;
}
static void

6
gas/config/tc-iq2000.h
View File

@ -57,6 +57,6 @@
#define tc_gen_reloc gas_cgen_tc_gen_reloc
extern void iq2000_frob_file (void);
extern bfd_boolean iq2000_fix_adjustable (struct fix *);
extern int iq2000_force_relocation (struct fix *);
extern void iq2000_frob_file (void);
extern bool iq2000_fix_adjustable (struct fix *);
extern int iq2000_force_relocation (struct fix *);

6
gas/config/tc-lm32.c
View File

@ -380,15 +380,15 @@ md_pcrel_from_section (fixS * fixP, segT sec)
/* Return true if we can partially resolve a relocation now. */
bfd_boolean
bool
lm32_fix_adjustable (fixS * fixP)
{
/* We need the symbol name for the VTABLE entries */
if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
|| fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
return FALSE;
return false;
return TRUE;
return true;
}
/* Relaxation isn't required/supported on this target. */

2
gas/config/tc-lm32.h
View File

@ -42,7 +42,7 @@
/* Call md_pcrel_from_section(), not md_pcrel_from(). */
#define MD_PCREL_FROM_SECTION(FIXP, SEC) md_pcrel_from_section (FIXP, SEC)
extern bfd_boolean lm32_fix_adjustable (struct fix *);
extern bool lm32_fix_adjustable (struct fix *);
#define tc_fix_adjustable(FIX) lm32_fix_adjustable (FIX)
#endif /* TC_LM32_H */

12
gas/config/tc-m32c.c
View File

@ -215,7 +215,7 @@ m32c_start_line_hook (void)
/* Process [[indirect-operands]] in instruction str. */
static bfd_boolean
static bool
m32c_indirect_operand (char *str)
{
char *new_str;
@ -245,7 +245,7 @@ m32c_indirect_operand (char *str)
}
if (indirection[1] == none && indirection[2] == none)
return FALSE;
return false;
operand = 1;
ns_len = strlen (str);
@ -287,7 +287,7 @@ m32c_indirect_operand (char *str)
*ns = s[0];
ns += 1;
if (ns >= ns_end)
return FALSE;
return false;
if (s[0] == 0)
break;
}
@ -307,7 +307,7 @@ m32c_indirect_operand (char *str)
md_assemble (new_str);
free (new_str);
return TRUE;
return true;
}
void
@ -1138,10 +1138,10 @@ md_number_to_chars (char * buf, valueT val, int n)
const char *
md_atof (int type, char * litP, int * sizeP)
{
return ieee_md_atof (type, litP, sizeP, TRUE);
return ieee_md_atof (type, litP, sizeP, true);
}
bfd_boolean
bool
m32c_fix_adjustable (fixS * fixP)
{
int reloc;

2
gas/config/tc-m32c.h
View File

@ -44,7 +44,7 @@ extern void m32c_start_line_hook (void);
extern void m32c_apply_fix (struct fix *, valueT *, segT);
#define tc_fix_adjustable(fixP) m32c_fix_adjustable (fixP)
extern bfd_boolean m32c_fix_adjustable (struct fix *);
extern bool m32c_fix_adjustable (struct fix *);
/* When relaxing, we need to emit various relocs we otherwise wouldn't. */
#define TC_FORCE_RELOCATION(fix) m32c_force_relocation (fix)

14
gas/config/tc-m32r.c
View File

@ -844,7 +844,7 @@ can_make_parallel (m32r_insn *a, m32r_insn *b)
|| CGEN_FIELDS_BITSIZE (&b->fields) != 16)
abort ();
if (first_writes_to_seconds_operands (a, b, TRUE))
if (first_writes_to_seconds_operands (a, b, true))
return _("instructions write to the same destination register.");
a_pipe = CGEN_INSN_ATTR_VALUE (a->insn, CGEN_INSN_PIPE);
@ -1118,11 +1118,11 @@ assemble_two_insns (char *str1, char *str2, int parallel_p)
if (parallel_p && warn_explicit_parallel_conflicts)
{
if (first_writes_to_seconds_operands (&first, &second, FALSE))
if (first_writes_to_seconds_operands (&first, &second, false))
/* xgettext:c-format */
as_warn (_("%s: output of 1st instruction is the same as an input to 2nd instruction - is this intentional ?"), str2);
if (first_writes_to_seconds_operands (&second, &first, FALSE))
if (first_writes_to_seconds_operands (&second, &first, false))
/* xgettext:c-format */
as_warn (_("%s: output of 2nd instruction is the same as an input to 1st instruction - is this intentional ?"), str2);
}
@ -1287,7 +1287,7 @@ md_assemble (char *str)
else
{
int on_32bit_boundary_p;
int swap = FALSE;
int swap = false;
if (CGEN_INSN_BITSIZE (insn.insn) != 16)
abort ();
@ -1342,12 +1342,12 @@ md_assemble (char *str)
&& parallel ()
&& CGEN_INSN_ATTR_VALUE (insn.orig_insn, CGEN_INSN_RELAXABLE) == 0
&& ! writes_to_pc (&prev_insn)
&& ! first_writes_to_seconds_operands (&prev_insn, &insn, FALSE))
&& ! first_writes_to_seconds_operands (&prev_insn, &insn, false))
{
if (can_make_parallel (&prev_insn, &insn) == NULL)
make_parallel (insn.buffer);
else if (can_make_parallel (&insn, &prev_insn) == NULL)
swap = TRUE;
swap = true;
}
expand_debug_syms (insn.debug_sym_link, 1);
@ -2125,7 +2125,7 @@ m32r_elf_section_change_hook (void)
/* Return true if can adjust the reloc to be relative to its section
(such as .data) instead of relative to some symbol. */
bfd_boolean
bool
m32r_fix_adjustable (fixS *fixP)
{
bfd_reloc_code_real_type reloc_type;

2
gas/config/tc-m32r.h
View File

@ -70,7 +70,7 @@ extern void m32r_handle_align (fragS *);
#define md_apply_fix gas_cgen_md_apply_fix
#define tc_fix_adjustable(FIX) m32r_fix_adjustable (FIX)
extern bfd_boolean m32r_fix_adjustable (struct fix *);
extern bool m32r_fix_adjustable (struct fix *);
/* After creating a fixup for an instruction operand, we need to check for
HI16 relocs and queue them up for later sorting. */

20
gas/config/tc-m68hc11.c
View File

@ -577,7 +577,7 @@ md_undefined_symbol (char *name ATTRIBUTE_UNUSED)
const char *
md_atof (int type, char *litP, int *sizeP)
{
return ieee_md_atof (type, litP, sizeP, TRUE);
return ieee_md_atof (type, litP, sizeP, true);
}
valueT
@ -1599,7 +1599,7 @@ fixup8 (expressionS *oper, int mode, int opmode)
if (mode == M6811_OP_JUMP_REL)
{
fix_new_exp (frag_now, f - frag_now->fr_literal, 1,
oper, TRUE, BFD_RELOC_8_PCREL);
oper, true, BFD_RELOC_8_PCREL);
}
else
{
@ -1618,7 +1618,7 @@ fixup8 (expressionS *oper, int mode, int opmode)
reloc = BFD_RELOC_8;
fixp = fix_new_exp (frag_now, f - frag_now->fr_literal, 1,
oper, FALSE, reloc);
oper, false, reloc);
if (reloc != BFD_RELOC_8)
fixp->fx_no_overflow = 1;
}
@ -1700,7 +1700,7 @@ fixup24 (expressionS *oper, int mode, int opmode ATTRIBUTE_UNUSED)
{
/* Now create a 24-bit fixup. */
fix_new_exp (frag_now, f - frag_now->fr_literal, 3,
oper, FALSE, BFD_RELOC_M68HC11_24);
oper, false, BFD_RELOC_M68HC11_24);
number_to_chars_bigendian (f, 0, 3);
}
else
@ -1731,7 +1731,7 @@ fixup8_xg (expressionS *oper, int mode, int opmode)
reloc = BFD_RELOC_M68HC11_LO8;
fixp = fix_new_exp (frag_now, f - frag_now->fr_literal, 1,
oper, FALSE, reloc);
oper, false, reloc);
fixp->fx_no_overflow = 1;
number_to_chars_bigendian (f, 0, 1);
}
@ -1750,14 +1750,14 @@ fixup8_xg (expressionS *oper, int mode, int opmode)
/* Future improvement:
This fixup/reloc isn't adding on constants to symbols. */
fix_new_exp (frag_now, f - frag_now->fr_literal -1, 2,
oper, TRUE, BFD_RELOC_M68HC12_9_PCREL);
oper, true, BFD_RELOC_M68HC12_9_PCREL);
}
else if (mode == M68XG_OP_REL10)
{
/* Future improvement:
This fixup/reloc isn't adding on constants to symbols. */
fix_new_exp (frag_now, f - frag_now->fr_literal -1, 2,
oper, TRUE, BFD_RELOC_M68HC12_10_PCREL);
oper, true, BFD_RELOC_M68HC12_10_PCREL);
}
else
{
@ -1774,7 +1774,7 @@ fixup8_xg (expressionS *oper, int mode, int opmode)
reloc = BFD_RELOC_8;
fixp = fix_new_exp (frag_now, f - frag_now->fr_literal, 1,
oper, FALSE, reloc);
oper, false, reloc);
if (reloc != BFD_RELOC_8)
fixp->fx_no_overflow = 1;
}
@ -2398,7 +2398,7 @@ build_insn_xg (struct m68hc11_opcode *opcode,
operands[0].mode = M6811_OP_LOW_ADDR;
f = frag_more (1);
fixp = fix_new_exp (frag_now, f - frag_now->fr_literal, 1,
&operands[0].exp, FALSE, BFD_RELOC_M68HC12_LO8XG);
&operands[0].exp, false, BFD_RELOC_M68HC12_LO8XG);
fixp->fx_no_overflow = 1;
number_to_chars_bigendian (f, 0, 1);
@ -2408,7 +2408,7 @@ build_insn_xg (struct m68hc11_opcode *opcode,
operands[0].mode = M6811_OP_HIGH_ADDR;
f = frag_more (1);
fixp = fix_new_exp (frag_now, f - frag_now->fr_literal, 1,
&operands[0].exp, FALSE, BFD_RELOC_M68HC12_HI8XG);
&operands[0].exp, false, BFD_RELOC_M68HC12_HI8XG);
fixp->fx_no_overflow = 1;
number_to_chars_bigendian (f, 0, 1);

2
gas/config/tc-m68k.c
View File

@ -4790,7 +4790,7 @@ m68k_mri_mode_change (int on)
const char *
md_atof (int type, char *litP, int *sizeP)
{
return ieee_md_atof (type, litP, sizeP, TRUE);
return ieee_md_atof (type, litP, sizeP, true);
}
void

2
gas/config/tc-mcore.c
View File

@ -2229,7 +2229,7 @@ mcore_force_relocation (fixS * fix)
/* Return true if the fix can be handled by GAS, false if it must
be passed through to the linker. */
bfd_boolean
bool
mcore_fix_adjustable (fixS * fixP)
{
/* We need the symbol name for the VTABLE entries. */

8
gas/config/tc-mcore.h
View File

@ -86,9 +86,9 @@ struct mcore_tc_sy
#include "write.h" /* For definition of fixS */
extern void md_mcore_end (void);
extern arelent * tc_gen_reloc (asection *, fixS *);
extern int mcore_force_relocation (fixS *);
extern bfd_boolean mcore_fix_adjustable (fixS *);
extern void md_mcore_end (void);
extern arelent *tc_gen_reloc (asection *, fixS *);
extern int mcore_force_relocation (fixS *);
extern bool mcore_fix_adjustable (fixS *);
#endif /* TC_MCORE */

4
gas/config/tc-mep.c
View File

@ -2043,10 +2043,10 @@ md_number_to_chars (char *buf, valueT val, int n)
const char *
md_atof (int type, char *litP, int *sizeP)
{
return ieee_md_atof (type, litP, sizeP, TRUE);
return ieee_md_atof (type, litP, sizeP, true);
}
bfd_boolean
bool
mep_fix_adjustable (fixS *fixP)
{
bfd_reloc_code_real_type reloc_type;

2
gas/config/tc-mep.h
View File

@ -58,7 +58,7 @@ extern void mep_apply_fix (struct fix *, valueT *, segT);
extern void mep_frob_file (void);
#define tc_fix_adjustable(fixP) mep_fix_adjustable (fixP)
extern bfd_boolean mep_fix_adjustable (struct fix *);
extern bool mep_fix_adjustable (struct fix *);
/* After creating a fixup for an instruction operand, we need
to check for HI16 relocs and queue them up for later sorting. */

348
gas/config/tc-metag.c
View File

@ -380,7 +380,7 @@ parse_fpu_regs (const char *line, const metag_reg **regs, size_t count)
}
/* Return TRUE if REG1 and REG2 are in paired units. */
static bfd_boolean
static bool
is_unit_pair (const metag_reg *reg1, const metag_reg *reg2)
{
if ((reg1->unit == UNIT_A0 &&
@ -391,22 +391,22 @@ is_unit_pair (const metag_reg *reg1, const metag_reg *reg2)
(reg2->unit == UNIT_D1)) ||
(reg1->unit == UNIT_D1 &&
(reg2->unit == UNIT_D0)))
return TRUE;
return true;
return FALSE;
return false;
}
/* Return TRUE if REG1 and REG2 form a register pair. */
static bfd_boolean
static bool
is_reg_pair (const metag_reg *reg1, const metag_reg *reg2)
{
if (reg1->unit == UNIT_FX &&
reg2->unit == UNIT_FX &&
reg2->no == reg1->no + 1)
return TRUE;
return true;
if (reg1->no != reg2->no)
return FALSE;
return false;
return is_unit_pair (reg1, reg2);
}
@ -472,7 +472,7 @@ parse_mov_port (const char *line, metag_insn *insn,
const insn_template *template)
{
const char *l = line;
bfd_boolean is_movl = MINOR_OPCODE (template->meta_opcode) == MOVL_MINOR;
bool is_movl = MINOR_OPCODE (template->meta_opcode) == MOVL_MINOR;
const metag_reg *dest_regs[2];
const metag_reg *port_regs[1];
@ -847,7 +847,7 @@ parse_addr (const char *line, metag_addr *addr, unsigned int size)
/* Parse a GET or pipeline MOV instruction. */
static const char *
parse_get (const char *line, const metag_reg **regs, metag_addr *addr,
unsigned int size, bfd_boolean is_mov)
unsigned int size, bool is_mov)
{
const char *l = line;
@ -946,7 +946,7 @@ parse_set (const char *line, const metag_reg **regs, metag_addr *addr,
/* Check a signed integer value can be represented in the given number
of bits. */
static bfd_boolean
static bool
within_signed_range (int value, unsigned int bits)
{
int min_val = -(1 << (bits - 1));
@ -956,14 +956,14 @@ within_signed_range (int value, unsigned int bits)
/* Check an unsigned integer value can be represented in the given number
of bits. */
static bfd_boolean
static bool
within_unsigned_range (unsigned int value, unsigned int bits)
{
return value < (unsigned int)(1 << bits);
}
/* Return TRUE if UNIT can be expressed using a short code. */
static bfd_boolean
static bool
is_short_unit (enum metag_unit unit)
{
switch (unit)
@ -972,9 +972,9 @@ is_short_unit (enum metag_unit unit)
case UNIT_A1:
case UNIT_D0:
case UNIT_D1:
return TRUE;
return true;
default:
return FALSE;
return false;
}
}
@ -995,7 +995,7 @@ parse_get_set (const char *line, metag_insn *insn,
const metag_reg *regs[2];
metag_addr addr;
unsigned int size = metag_get_set_size_bytes (template->meta_opcode);
bfd_boolean is_get = MAJOR_OPCODE (template->meta_opcode) == OPC_GET;
bool is_get = MAJOR_OPCODE (template->meta_opcode) == OPC_GET;
unsigned int reg_no;
memset(&addr, 0, sizeof(addr));
@ -1003,7 +1003,7 @@ parse_get_set (const char *line, metag_insn *insn,
if (is_get)
{
bfd_boolean is_mov = strncmp (template->name, "MOV", 3) == 0;
bool is_mov = strncmp (template->name, "MOV", 3) == 0;
l = parse_get (l, regs, &addr, size, is_mov);
@ -1139,8 +1139,8 @@ parse_get_set_ext (const char *line, metag_insn *insn,
const metag_reg *regs[2];
metag_addr addr;
unsigned int size = metag_get_set_ext_size_bytes (template->meta_opcode);
bfd_boolean is_get = MINOR_OPCODE (template->meta_opcode) == GET_EXT_MINOR;
bfd_boolean is_mov = MINOR_OPCODE (template->meta_opcode) == MOV_EXT_MINOR;
bool is_get = MINOR_OPCODE (template->meta_opcode) == GET_EXT_MINOR;
bool is_mov = MINOR_OPCODE (template->meta_opcode) == MOV_EXT_MINOR;
unsigned int reg_unit;
memset(&addr, 0, sizeof(addr));
@ -1334,9 +1334,9 @@ parse_mset (const char *line, const metag_reg **regs, metag_addr *addr,
rmask value if possible. Return the rmask value in RMASK and the
lowest numbered register in LOWEST_REG. Return TRUE if the conversion
was successful. */
static bfd_boolean
check_rmask (const metag_reg **regs, size_t regs_read, bfd_boolean is_fpu,
bfd_boolean is_64bit, unsigned int *lowest_reg,
static bool
check_rmask (const metag_reg **regs, size_t regs_read, bool is_fpu,
bool is_64bit, unsigned int *lowest_reg,
unsigned int *rmask)
{
unsigned int reg_unit = regs[0]->unit;
@ -1349,13 +1349,13 @@ check_rmask (const metag_reg **regs, size_t regs_read, bfd_boolean is_fpu,
if (is_64bit && regs[i]->no % 2)
{
as_bad (_("register list must be even numbered"));
return FALSE;
return false;
}
}
else if (regs[i]->unit != reg_unit)
{
as_bad (_("register list must be from the same unit"));
return FALSE;
return false;
}
if (regs[i]->no < *lowest_reg)
@ -1378,13 +1378,13 @@ check_rmask (const metag_reg **regs, size_t regs_read, bfd_boolean is_fpu,
if (*rmask & next_bit)
{
as_bad (_("register list must not contain duplicates"));
return FALSE;
return false;
}
*rmask |= next_bit;
}
return TRUE;
return true;
}
/* Parse an MGET or MSET instruction. */
@ -1395,9 +1395,9 @@ parse_mget_mset (const char *line, metag_insn *insn,
const char *l = line;
const metag_reg *regs[MGET_MSET_MAX_REGS];
metag_addr addr;
bfd_boolean is_get = MAJOR_OPCODE (template->meta_opcode) == OPC_GET;
bfd_boolean is_fpu = (MINOR_OPCODE (template->meta_opcode) & 0x6) == 0x6;
bfd_boolean is_64bit = (MINOR_OPCODE (template->meta_opcode) & 0x1) == 0x1;
bool is_get = MAJOR_OPCODE (template->meta_opcode) == OPC_GET;
bool is_fpu = (MINOR_OPCODE (template->meta_opcode) & 0x6) == 0x6;
bool is_64bit = (MINOR_OPCODE (template->meta_opcode) & 0x1) == 0x1;
size_t regs_read = 0;
unsigned int rmask = 0, reg_unit = 0, lowest_reg = 0xffffffff;
@ -1501,9 +1501,9 @@ parse_mmov (const char *line, metag_insn *insn,
const insn_template *template)
{
const char *l = line;
bfd_boolean is_fpu = template->insn_type == INSN_FPU;
bfd_boolean is_prime = (MINOR_OPCODE (template->meta_opcode) & 0x2) != 0 && !is_fpu;
bfd_boolean is_64bit = (MINOR_OPCODE (template->meta_opcode) & 0x1) != 0;
bool is_fpu = template->insn_type == INSN_FPU;
bool is_prime = (MINOR_OPCODE (template->meta_opcode) & 0x2) != 0 && !is_fpu;
bool is_64bit = (MINOR_OPCODE (template->meta_opcode) & 0x1) != 0;
unsigned int rmask = 0;
if (is_prime)
@ -1834,8 +1834,8 @@ parse_imm16 (const char *line, metag_insn *insn, int *value)
const char *l = line;
char *save_input_line_pointer;
expressionS *exp = &insn->reloc_exp;
bfd_boolean is_hi = FALSE;
bfd_boolean is_lo = FALSE;
bool is_hi = false;
bool is_lo = false;
/* Skip #. */
if (*l == '#')
@ -1845,12 +1845,12 @@ parse_imm16 (const char *line, metag_insn *insn, int *value)
if (strncasecmp (l, "HI", 2) == 0)
{
is_hi = TRUE;
is_hi = true;
l += 2;
}
else if (strncasecmp (l, "LO", 2) == 0)
{
is_lo = TRUE;
is_lo = true;
l += 2;
}
@ -1965,9 +1965,9 @@ parse_mov_ct (const char *line, metag_insn *insn,
{
const char *l = line;
const metag_reg *regs[1];
bfd_boolean top = (template->meta_opcode & 0x1) != 0;
bfd_boolean is_trace = ((template->meta_opcode >> 2) & 0x1) != 0;
bfd_boolean sign_extend = 0;
bool top = (template->meta_opcode & 0x1) != 0;
bool is_trace = ((template->meta_opcode >> 2) & 0x1) != 0;
bool sign_extend = 0;
int value = 0;
l = parse_gp_regs (l, regs, 1);
@ -2078,7 +2078,7 @@ parse_jump (const char *line, metag_insn *insn,
if (!is_short_unit (regs[0]->unit))
{
as_bad (_("register unit must be one of %s"), SHORT_UNITS);
return FALSE;
return false;
}
l = skip_comma (l);
@ -2290,16 +2290,16 @@ parse_alu (const char *line, metag_insn *insn,
const metag_reg *dest_regs[1];
const metag_reg *src_regs[2];
int value = 0;
bfd_boolean o1z = 0;
bfd_boolean imm = ((template->meta_opcode >> 25) & 0x1) != 0;
bfd_boolean cond = ((template->meta_opcode >> 26) & 0x1) != 0;
bfd_boolean ca = ((template->meta_opcode >> 5) & 0x1) != 0;
bfd_boolean top = (template->meta_opcode & 0x1) != 0;
bfd_boolean sign_extend = 0;
bfd_boolean is_addr_op = MAJOR_OPCODE (template->meta_opcode) == OPC_ADDR;
bfd_boolean is_mul = MAJOR_OPCODE (template->meta_opcode) == OPC_MUL;
bool o1z = 0;
bool imm = ((template->meta_opcode >> 25) & 0x1) != 0;
bool cond = ((template->meta_opcode >> 26) & 0x1) != 0;
bool ca = ((template->meta_opcode >> 5) & 0x1) != 0;
bool top = (template->meta_opcode & 0x1) != 0;
bool sign_extend = 0;
bool is_addr_op = MAJOR_OPCODE (template->meta_opcode) == OPC_ADDR;
bool is_mul = MAJOR_OPCODE (template->meta_opcode) == OPC_MUL;
unsigned int unit_bit = 0;
bfd_boolean is_quickrot = (template->arg_type & GP_ARGS_QR) != 0;
bool is_quickrot = (template->arg_type & GP_ARGS_QR) != 0;
l = parse_gp_regs (l, dest_regs, 1);
@ -2510,7 +2510,7 @@ parse_alu (const char *line, metag_insn *insn,
}
else
{
bfd_boolean o2r = 0;
bool o2r = 0;
int rs2;
if (cond || !o1z)
@ -2652,7 +2652,7 @@ parse_alu (const char *line, metag_insn *insn,
if (is_quickrot)
{
const metag_reg *qr_regs[1];
bfd_boolean limit_regs = imm && cond;
bool limit_regs = imm && cond;
l = skip_comma (l);
@ -2786,8 +2786,8 @@ parse_shift (const char *line, metag_insn *insn,
const metag_reg *regs[2];
const metag_reg *src2_regs[1];
int value = 0;
bfd_boolean cond = ((template->meta_opcode >> 26) & 0x1) != 0;
bfd_boolean ca = ((template->meta_opcode >> 5) & 0x1) != 0;
bool cond = ((template->meta_opcode >> 26) & 0x1) != 0;
bool ca = ((template->meta_opcode >> 5) & 0x1) != 0;
unsigned int unit_bit = 0;
l = parse_gp_regs (l, regs, 2);
@ -2909,8 +2909,8 @@ parse_bitop (const char *line, metag_insn *insn,
{
const char *l = line;
const metag_reg *regs[2];
bfd_boolean swap_inst = MAJOR_OPCODE (template->meta_opcode) == OPC_MISC;
bfd_boolean is_bexl = 0;
bool swap_inst = MAJOR_OPCODE (template->meta_opcode) == OPC_MISC;
bool is_bexl = 0;
if (swap_inst && ((template->meta_opcode >> 1) & 0xb) == 0xa)
is_bexl = 1;
@ -2964,10 +2964,10 @@ parse_cmp (const char *line, metag_insn *insn,
const metag_reg *dest_regs[1];
const metag_reg *src_regs[1];
int value = 0;
bfd_boolean imm = ((template->meta_opcode >> 25) & 0x1) != 0;
bfd_boolean cond = ((template->meta_opcode >> 26) & 0x1) != 0;
bfd_boolean top = (template->meta_opcode & 0x1) != 0;
bfd_boolean sign_extend = 0;
bool imm = ((template->meta_opcode >> 25) & 0x1) != 0;
bool cond = ((template->meta_opcode >> 26) & 0x1) != 0;
bool top = (template->meta_opcode & 0x1) != 0;
bool sign_extend = 0;
unsigned int unit_bit = 0;
l = parse_gp_regs (l, dest_regs, 1);
@ -3037,7 +3037,7 @@ parse_cmp (const char *line, metag_insn *insn,
}
else
{
bfd_boolean o2r = 0;
bool o2r = 0;
int rs2;
l = parse_gp_regs (l, src_regs, 1);
@ -3343,8 +3343,8 @@ parse_fmmov (const char *line, metag_insn *insn,
const insn_template *template)
{
const char *l = line;
bfd_boolean to_fpu = MAJOR_OPCODE (template->meta_opcode) == OPC_GET;
bfd_boolean is_mmovl = (MINOR_OPCODE (template->meta_opcode) & 0x1) != 0;
bool to_fpu = MAJOR_OPCODE (template->meta_opcode) == OPC_GET;
bool is_mmovl = (MINOR_OPCODE (template->meta_opcode) & 0x1) != 0;
size_t regs_read = 0;
const metag_reg *regs[16];
unsigned int lowest_data_reg = 0xffffffff;
@ -3397,7 +3397,7 @@ parse_fmmov (const char *line, metag_insn *insn,
else
return NULL;
if (!check_rmask (&regs[i], regs_read / 2, TRUE, FALSE, &lowest_data_reg,
if (!check_rmask (&regs[i], regs_read / 2, true, false, &lowest_data_reg,
&rmask))
return NULL;
}
@ -3410,7 +3410,7 @@ parse_fmmov (const char *line, metag_insn *insn,
else
return NULL;
if (!check_rmask (regs, regs_read / 2, TRUE, FALSE, &lowest_data_reg,
if (!check_rmask (regs, regs_read / 2, true, false, &lowest_data_reg,
&rmask))
return NULL;
@ -3455,7 +3455,7 @@ parse_fmov_data (const char *line, metag_insn *insn,
const insn_template *template)
{
const char *l = line;
bfd_boolean to_fpu = ((template->meta_opcode >> 7) & 0x1) != 0;
bool to_fpu = ((template->meta_opcode >> 7) & 0x1) != 0;
const metag_reg *regs[2];
unsigned int base_unit;
@ -3862,11 +3862,11 @@ parse_fearith (const char *line, metag_insn *insn,
{
const char *l = line;
const metag_reg *regs[3];
bfd_boolean is_muz = (MINOR_OPCODE (template->meta_opcode) == 0x6
&& ((template->meta_opcode >> 4) & 0x1) != 0);
bfd_boolean is_o3o = (template->meta_opcode & 0x1) != 0;
bfd_boolean is_mac = 0;
bfd_boolean is_maw = 0;
bool is_muz = (MINOR_OPCODE (template->meta_opcode) == 0x6
&& ((template->meta_opcode >> 4) & 0x1) != 0);
bool is_o3o = (template->meta_opcode & 0x1) != 0;
bool is_mac = 0;
bool is_maw = 0;
if (!strncasecmp (template->name, "MAW", 3))
is_maw = 1;
@ -4014,7 +4014,7 @@ parse_fget_set_acf (const char *line, metag_insn *insn,
const char *l = line;
int part;
metag_addr addr;
bfd_boolean is_get = MAJOR_OPCODE (template->meta_opcode) == OPC_GET;
bool is_get = MAJOR_OPCODE (template->meta_opcode) == OPC_GET;
memset(&addr, 0, sizeof(addr));
addr.reloc_type = BFD_RELOC_UNUSED;
@ -4138,7 +4138,7 @@ parse_dsp_insn_reg (const char *line, const metag_reg **reg)
definition. "load" specifies which table to look at. */
static const char *
parse_dsp_template_reg (const char *line, const metag_reg **reg,
bfd_boolean load)
bool load)
{
return __parse_dsp_reg (line, reg, dsp_tmpl_reg_htab[load]);
}
@ -4146,7 +4146,7 @@ parse_dsp_template_reg (const char *line, const metag_reg **reg,
/* Parse a single DSP register from LINE. */
static const char *
parse_dsp_reg (const char *line, const metag_reg **reg,
bfd_boolean tmpl, bfd_boolean load)
bool tmpl, bool load)
{
if (tmpl)
return parse_dsp_template_reg (line, reg, load);
@ -4155,95 +4155,95 @@ parse_dsp_reg (const char *line, const metag_reg **reg,
}
/* Return TRUE if UNIT is an address unit. */
static bfd_boolean
static bool
is_addr_unit (enum metag_unit unit)
{
switch (unit)
{
case UNIT_A0:
case UNIT_A1:
return TRUE;
return true;
default:
return FALSE;
return false;
}
}
/* Return TRUE if UNIT1 and UNIT2 are equivalent units. */
static bfd_boolean
static bool
is_same_data_unit (enum metag_unit unit1, enum metag_unit unit2)
{
if (unit1 == unit2)
return TRUE;
return true;
switch (unit1)
{
case UNIT_D0:
if (unit2 == UNIT_ACC_D0 || unit2 == UNIT_RAM_D0)
return TRUE;
return true;
break;
case UNIT_D1:
if (unit2 == UNIT_ACC_D1 || unit2 == UNIT_RAM_D1)
return TRUE;
return true;
break;
case UNIT_ACC_D0:
if (unit2 == UNIT_D0 || unit2 == UNIT_RAM_D0)
return TRUE;
return true;
break;
case UNIT_ACC_D1:
if (unit2 == UNIT_D1 || unit2 == UNIT_RAM_D1)
return TRUE;
return true;
break;
case UNIT_RAM_D0:
if (unit2 == UNIT_ACC_D0 || unit2 == UNIT_D0)
return TRUE;
return true;
break;
case UNIT_RAM_D1:
if (unit2 == UNIT_ACC_D1 || unit2 == UNIT_D1)
return TRUE;
return true;
break;
default:
return FALSE;
return false;
}
return FALSE;
return false;
}
/* Return TRUE if the register NUM is a quickrot control register. */
static bfd_boolean
static bool
is_quickrot_reg (unsigned int num)
{
switch (num)
{
case 2:
case 3:
return TRUE;
return true;
}
return FALSE;
return false;
}
/* Return TRUE if REG is an accumulator register. */
static bfd_boolean
static bool
is_accumulator_reg (const metag_reg *reg)
{
if (reg->unit == UNIT_ACC_D0 || reg->unit == UNIT_ACC_D1)
return TRUE;
return true;
return FALSE;
return false;
}
/* Return TRUE if REG is a DSP RAM register. */
static bfd_boolean
static bool
is_dspram_reg (const metag_reg *reg)
{
if (reg->unit == UNIT_RAM_D0 || reg->unit == UNIT_RAM_D1)
return TRUE;
return true;
return FALSE;
return false;
}
static const char *
__parse_gp_reg (const char *line, const metag_reg **reg, bfd_boolean load)
__parse_gp_reg (const char *line, const metag_reg **reg, bool load)
{
const char *l = line;
char reg_buf[MAX_REG_LEN];
@ -4260,7 +4260,7 @@ __parse_gp_reg (const char *line, const metag_reg **reg, bfd_boolean load)
if (l == NULL)
return NULL;
l = parse_dsp_reg (l, reg, TRUE, load);
l = parse_dsp_reg (l, reg, true, load);
if (l == NULL)
return NULL;
@ -4299,8 +4299,8 @@ __parse_gp_reg (const char *line, const metag_reg **reg, bfd_boolean load)
a destination operand. */
static const char *
parse_dsp_regs_list (const char *line, const metag_reg **regs, size_t count,
size_t *regs_read, bfd_boolean try_gp, bfd_boolean tmpl,
bfd_boolean load, bfd_boolean first_dst)
size_t *regs_read, bool try_gp, bool tmpl,
bool load, bool first_dst)
{
const char *l = line;
int seen_regs = 0;
@ -4370,7 +4370,7 @@ parse_dsp_regs_list (const char *line, const metag_reg **regs, size_t count,
- [DSPRam-DSPRam--] */
static const char *
parse_dsp_addr (const char *line, metag_addr *addr, unsigned int size,
bfd_boolean load)
bool load)
{
const char *l = line, *ll;
const metag_reg *regs[1];
@ -4379,7 +4379,7 @@ parse_dsp_addr (const char *line, metag_addr *addr, unsigned int size,
/* Skip opening square bracket. */
l++;
l = parse_dsp_regs_list (l, regs, 1, &regs_read, TRUE, TRUE, load, FALSE);
l = parse_dsp_regs_list (l, regs, 1, &regs_read, true, true, load, false);
if (l == NULL)
return NULL;
@ -4433,7 +4433,7 @@ parse_dsp_addr (const char *line, metag_addr *addr, unsigned int size,
if (l == NULL)
return NULL;
l = parse_dsp_regs_list (l, regs, 1, &regs_read, TRUE, TRUE, load, FALSE);
l = parse_dsp_regs_list (l, regs, 1, &regs_read, true, true, load, false);
if (l == NULL)
return NULL;
@ -4475,9 +4475,9 @@ parse_dget_set (const char *line, metag_insn *insn,
metag_addr addr;
int unit = 0;
int rd_reg = 0;
bfd_boolean is_get = (template->meta_opcode & 0x100) != 0;
bfd_boolean is_dual = (template->meta_opcode & 0x4) != 0;
bfd_boolean is_template = FALSE;
bool is_get = (template->meta_opcode & 0x100) != 0;
bool is_dual = (template->meta_opcode & 0x4) != 0;
bool is_template = false;
const metag_reg *regs[2];
unsigned int size;
size_t count, regs_read;
@ -4494,8 +4494,8 @@ parse_dget_set (const char *line, metag_insn *insn,
if (*l == 'T')
count = 1;
l = parse_dsp_regs_list (l, regs, count, &regs_read, FALSE,
FALSE, FALSE, FALSE);
l = parse_dsp_regs_list (l, regs, count, &regs_read, false,
false, false, false);
l = skip_comma (l);
if (l == NULL)
@ -4519,8 +4519,8 @@ parse_dget_set (const char *line, metag_insn *insn,
if (*l == 'T')
count = 1;
l = parse_dsp_regs_list (l, regs, count, &regs_read, FALSE, FALSE,
FALSE, FALSE);
l = parse_dsp_regs_list (l, regs, count, &regs_read, false, false,
false, false);
}
if (l == NULL)
@ -4528,7 +4528,7 @@ parse_dget_set (const char *line, metag_insn *insn,
/* The first register dictates the unit. */
if (regs[0]->unit == UNIT_DT)
is_template = TRUE;
is_template = true;
else
{
if (regs[0]->unit == UNIT_D0 || regs[0]->unit == UNIT_RAM_D0 ||
@ -4619,7 +4619,7 @@ parse_dtemplate (const char *line, metag_insn *insn,
{
const char *l = line;
const metag_reg *regs[TEMPLATE_NUM_REGS];
bfd_boolean daop_only = FALSE;
bool daop_only = false;
int regs_val[4];
int regs_which[4] = { -1, -1, -1, -1}; /* Register or immediate? */
int i;
@ -4635,7 +4635,7 @@ parse_dtemplate (const char *line, metag_insn *insn,
/* We may only have 3 register operands. */
if (*l == END_OF_INSN && i == 3)
{
daop_only = TRUE;
daop_only = true;
break;
}
@ -4662,11 +4662,11 @@ parse_dtemplate (const char *line, metag_insn *insn,
this is a load or store. So we have to try looking up the
register name in both the load and store tables. */
const char *l2 = l;
l = __parse_gp_reg (l, &regs[i], TRUE);
l = __parse_gp_reg (l, &regs[i], true);
if (l == NULL)
{
/* Try the store table too. */
l = __parse_gp_reg (l2, &regs[i], FALSE);
l = __parse_gp_reg (l2, &regs[i], false);
if (l == NULL)
{
/* Then try a DSP register. */
@ -4720,7 +4720,7 @@ parse_dtemplate (const char *line, metag_insn *insn,
template definition is a DSP RAM template definition. */
static const char *
template_mem_ref(const char *line, metag_addr *addr,
bfd_boolean *dspram, int size, bfd_boolean load)
bool *dspram, int size, bool load)
{
const char *l = line;
@ -4729,9 +4729,9 @@ template_mem_ref(const char *line, metag_addr *addr,
if (l != NULL)
{
if (is_addr_unit(addr->base_reg->unit))
*dspram = FALSE;
*dspram = false;
else
*dspram = TRUE;
*dspram = true;
}
return l;
@ -4740,10 +4740,10 @@ template_mem_ref(const char *line, metag_addr *addr,
/* Sets LOAD to TRUE if this is a Template load definition (otherwise
it's a store). Fills out ADDR, TEMPLATE_REG and ADDR_UNIT. */
static const char *
parse_template_regs (const char *line, bfd_boolean *load,
parse_template_regs (const char *line, bool *load,
unsigned int *addr_unit,
const metag_reg **template_reg, metag_addr *addr,
bfd_boolean *dspram, int size)
bool *dspram, int size)
{
const char *l = line;
@ -4753,8 +4753,8 @@ parse_template_regs (const char *line, bfd_boolean *load,
/* DSP Template load definition (Tx, [Ax]) */
if (*l == 'T')
{
*load = TRUE;
l = parse_dsp_reg (l, &template_reg[0], FALSE, FALSE);
*load = true;
l = parse_dsp_reg (l, &template_reg[0], false, false);
if (l == NULL)
return NULL;
@ -4768,14 +4768,14 @@ parse_template_regs (const char *line, bfd_boolean *load,
}
else if (*l == ADDR_BEGIN_CHAR) /* DSP Template store ([Ax], Tx) */
{
*load = FALSE;
*load = false;
l = template_mem_ref (l, addr, dspram, size, *load);
l = skip_comma(l);
if (l == NULL)
return NULL;
l = parse_dsp_reg (l, &template_reg[0], FALSE, FALSE);
l = parse_dsp_reg (l, &template_reg[0], false, false);
if (l == NULL)
return NULL;
@ -4799,7 +4799,7 @@ static metag_reg _reg;
static const char *
interpret_template_regs(const char *line, metag_insn *insn,
const metag_reg **regs,
int *regs_shift, bfd_boolean *load, bfd_boolean *dspram,
int *regs_shift, bool *load, bool *dspram,
int size, int *ls_shift, int *au_shift,
unsigned int *au, int *imm, int *imm_shift,
unsigned int *imm_mask)
@ -4888,16 +4888,16 @@ interpret_template_regs(const char *line, metag_insn *insn,
}
/* Does this combination of units need the O2R bit and can it be encoded? */
static bfd_boolean
static bool
units_need_o2r (enum metag_unit unit1, enum metag_unit unit2)
{
if (unit1 == unit2)
return FALSE;
return false;
if (unit1 == UNIT_D0 || unit1 == UNIT_ACC_D0 || unit1 == UNIT_RAM_D0)
{
if (unit2 == UNIT_ACC_D0 || unit2 == UNIT_RAM_D0 || unit2 == UNIT_D0)
return FALSE;
return false;
switch (unit2)
{
@ -4905,16 +4905,16 @@ units_need_o2r (enum metag_unit unit1, enum metag_unit unit2)
case UNIT_D1:
case UNIT_RD:
case UNIT_A0:
return TRUE;
return true;
default:
return FALSE;
return false;
}
}
if (unit1 == UNIT_D1 || unit1 == UNIT_ACC_D1 || unit1 == UNIT_RAM_D1)
{
if (unit2 == UNIT_ACC_D1 || unit2 == UNIT_RAM_D1 || unit2 == UNIT_D1)
return FALSE;
return false;
switch (unit2)
{
@ -4922,17 +4922,17 @@ units_need_o2r (enum metag_unit unit1, enum metag_unit unit2)
case UNIT_D0:
case UNIT_RD:
case UNIT_A0:
return TRUE;
return true;
default:
return FALSE;
return false;
}
}
return FALSE;
return false;
}
/* Return TRUE if this is a DSP data unit. */
static bfd_boolean
static bool
is_dsp_data_unit (const metag_reg *reg)
{
switch (reg->unit)
@ -4943,9 +4943,9 @@ is_dsp_data_unit (const metag_reg *reg)
case UNIT_ACC_D1:
case UNIT_RAM_D0:
case UNIT_RAM_D1:
return TRUE;
return true;
default:
return FALSE;
return false;
}
}
@ -4961,15 +4961,15 @@ parse_dalu (const char *line, metag_insn *insn,
const metag_reg *regs[4];
metag_addr addr;
size_t regs_read;
bfd_boolean is_mov = MAJOR_OPCODE (template->meta_opcode) == OPC_ADD;
bfd_boolean is_cmp = ((MAJOR_OPCODE (template->meta_opcode) == OPC_CMP) &&
((template->meta_opcode & 0xee) == 0));
bfd_boolean is_dual = insn->dsp_width == DSP_WIDTH_DUAL;
bfd_boolean is_quickrot64 = ((insn->dsp_action_flags & DSP_ACTION_QR64) != 0);
bool is_mov = MAJOR_OPCODE (template->meta_opcode) == OPC_ADD;
bool is_cmp = (MAJOR_OPCODE (template->meta_opcode) == OPC_CMP
&& (template->meta_opcode & 0xee) == 0);
bool is_dual = insn->dsp_width == DSP_WIDTH_DUAL;
bool is_quickrot64 = (insn->dsp_action_flags & DSP_ACTION_QR64) != 0;
int l1_shift = INVALID_SHIFT;
bfd_boolean load = FALSE;
bool load = false;
int ls_shift = INVALID_SHIFT;
bfd_boolean ar = FALSE;
bool ar = false;
int ar_shift = INVALID_SHIFT;
int regs_shift[3] = { INVALID_SHIFT, INVALID_SHIFT, INVALID_SHIFT };
int imm = 0;
@ -5002,8 +5002,8 @@ parse_dalu (const char *line, metag_insn *insn,
(insn->dsp_daoppame_flags & DSP_DAOPPAME_16) != 0);
int mx_shift = INVALID_SHIFT;
int size = is_dual ? 8 : 4;
bfd_boolean dspram;
bfd_boolean conditional = (MINOR_OPCODE (template->meta_opcode) & 0x4) != 0;
bool dspram;
bool conditional = (MINOR_OPCODE (template->meta_opcode) & 0x4) != 0;
/* XFIXME: check the flags are valid with the instruction. */
if (is_quickrot64 && !(template->arg_type & DSP_ARGS_QR))
@ -5056,8 +5056,8 @@ parse_dalu (const char *line, metag_insn *insn,
e.g. ACe.e,ACx.r,ACo.e */
if (template->arg_type & DSP_ARGS_XACC)
{
ll = parse_dsp_regs_list (l, regs, 3, &regs_read, FALSE, FALSE,
FALSE, FALSE);
ll = parse_dsp_regs_list (l, regs, 3, &regs_read, false, false,
false, false);
if (ll != NULL && regs_read == 3
&& is_accumulator_reg (regs[0]))
{
@ -5098,7 +5098,7 @@ parse_dalu (const char *line, metag_insn *insn,
a1_shift = 2;
om_shift = 3;
ll = parse_dsp_reg (l, &regs[0], FALSE, FALSE);
ll = parse_dsp_reg (l, &regs[0], false, false);
if (ll != NULL)
{
/* Using ACe.r as the dst requires one of the P,N or Z
@ -5113,7 +5113,7 @@ parse_dalu (const char *line, metag_insn *insn,
l = ll;
l = skip_comma (l);
l = parse_dsp_regs_list (l, &regs[1], 2, &regs_read,
TRUE, FALSE, FALSE, FALSE);
true, false, false, false);
if (l == NULL || regs_read != 2)
{
as_bad (_("invalid register"));
@ -5142,7 +5142,7 @@ parse_dalu (const char *line, metag_insn *insn,
regs_shift[0] = 19;
l = parse_dsp_regs_list (l, regs, 2, &regs_read, TRUE, FALSE, FALSE, TRUE);
l = parse_dsp_regs_list (l, regs, 2, &regs_read, true, false, false, true);
if (l == NULL || regs_read != 2)
return NULL;
@ -5202,7 +5202,7 @@ parse_dalu (const char *line, metag_insn *insn,
regs_shift[2] = 9;
/* Is Rs2 an accumulator reg, e.g. De.r,Dx.r,De.r|ACe.r */
ll = parse_dsp_reg (l, &regs[2], FALSE, FALSE);
ll = parse_dsp_reg (l, &regs[2], false, false);
if (ll != NULL)
{
l = ll;
@ -5215,12 +5215,12 @@ parse_dalu (const char *line, metag_insn *insn,
om_shift = 3;
ar_shift = 7;
ar = TRUE;
ar = true;
}
else
{
/* De.r,Dx.r,De.r */
l = __parse_gp_reg (l, &regs[2], TRUE);
l = __parse_gp_reg (l, &regs[2], true);
if (l == NULL)
return NULL;
}
@ -5247,7 +5247,7 @@ parse_dalu (const char *line, metag_insn *insn,
return NULL;
}
l = __parse_gp_reg (l, &regs[3], TRUE);
l = __parse_gp_reg (l, &regs[3], true);
if (l == NULL)
{
as_bad (_("invalid fourth register"));
@ -5309,10 +5309,10 @@ parse_dalu (const char *line, metag_insn *insn,
/* Group 2. */
if (template->arg_type & DSP_ARGS_2)
{
bfd_boolean is_xsd = (MAJOR_OPCODE (template->meta_opcode) == OPC_MISC
&& MINOR_OPCODE (template->meta_opcode) == 0xa);
bfd_boolean is_fpu_mov = template->insn_type == INSN_DSP_FPU;
bfd_boolean to_fpu = ((template->meta_opcode >> 7) & 0x1) != 0;
bool is_xsd = (MAJOR_OPCODE (template->meta_opcode) == OPC_MISC
&& MINOR_OPCODE (template->meta_opcode) == 0xa);
bool is_fpu_mov = template->insn_type == INSN_DSP_FPU;
bool to_fpu = ((template->meta_opcode >> 7) & 0x1) != 0;
if (is_xsd)
du_shift = 0;
@ -5328,7 +5328,7 @@ parse_dalu (const char *line, metag_insn *insn,
/* DSPe.r,Dx.r or DSPx.r,#I16 */
if (template->arg_type & DSP_ARGS_DSP_SRC1)
{
l = parse_dsp_reg (l, regs, FALSE, FALSE);
l = parse_dsp_reg (l, regs, false, false);
if (l == NULL)
{
as_bad (_("invalid register operand #1"));
@ -5421,12 +5421,12 @@ parse_dalu (const char *line, metag_insn *insn,
l1_shift = 4;
}
ll = __parse_gp_reg (l, &regs[1], TRUE);
ll = __parse_gp_reg (l, &regs[1], true);
if (ll == NULL)
{
if (template->arg_type & DSP_ARGS_DSP_SRC2)
{
l = parse_dsp_reg (l, &regs[1], FALSE, FALSE);
l = parse_dsp_reg (l, &regs[1], false, false);
if (l == NULL)
{
as_bad (_("invalid register operand #3"));
@ -5522,7 +5522,7 @@ parse_dalu (const char *line, metag_insn *insn,
du_shift = 24;
l1_shift = 4;
l = __parse_gp_reg (l, regs, FALSE);
l = __parse_gp_reg (l, regs, false);
if (l == NULL)
{
as_bad (_("invalid register operand"));
@ -5533,7 +5533,7 @@ parse_dalu (const char *line, metag_insn *insn,
if (*l == 'A')
{
l = parse_dsp_reg (l, &regs[1], FALSE, FALSE);
l = parse_dsp_reg (l, &regs[1], false, false);
if (l == NULL)
{
as_bad (_("invalid accumulator register"));
@ -5544,7 +5544,7 @@ parse_dalu (const char *line, metag_insn *insn,
}
else
{
l = __parse_gp_reg (l, &regs[1], TRUE);
l = __parse_gp_reg (l, &regs[1], true);
if (l == NULL)
{
as_bad (_("invalid register operand"));
@ -5581,7 +5581,7 @@ parse_dalu (const char *line, metag_insn *insn,
else
{
regs_shift[2] = 9;
l = __parse_gp_reg (l, &regs[2], TRUE);
l = __parse_gp_reg (l, &regs[2], true);
if (l == NULL)
return NULL;
}
@ -5819,7 +5819,7 @@ static const struct metag_core_option metag_dsps[] =
};
/* Parse a CPU command line option. */
static bfd_boolean
static bool
metag_parse_cpu (const char * str)
{
const struct metag_core_option * opt;
@ -5845,7 +5845,7 @@ metag_parse_cpu (const char * str)
}
/* Parse an FPU command line option. */
static bfd_boolean
static bool
metag_parse_fpu (const char * str)
{
const struct metag_core_option * opt;
@ -5871,7 +5871,7 @@ metag_parse_fpu (const char * str)
}
/* Parse a DSP command line option. */
static bfd_boolean
static bool
metag_parse_dsp (const char * str)
{
const struct metag_core_option * opt;
@ -5900,7 +5900,7 @@ struct metag_long_option
{
const char *option; /* Substring to match. */
const char *help; /* Help information. */
bfd_boolean (*func) (const char *subopt); /* Function to decode sub-option. */
bool (*func) (const char *subopt); /* Function to decode sub-option. */
const char *deprecated; /* If non-null, print this message. */
};
@ -6491,7 +6491,7 @@ create_scond_htab (void)
}
/* Entry point for instruction parsing. */
static bfd_boolean
static bool
parse_insn (const char *line, metag_insn *insn)
{
char mnemonic[MAX_MNEMONIC_LEN];
@ -6510,7 +6510,7 @@ parse_insn (const char *line, metag_insn *insn)
if (mnemonic_len >= MAX_MNEMONIC_LEN)
{
as_bad (_("instruction mnemonic too long: %s"), line);
return FALSE;
return false;
}
strncpy(mnemonic, line, mnemonic_len);
@ -6566,7 +6566,7 @@ parse_insn (const char *line, metag_insn *insn)
if (*end != END_OF_INSN)
as_bad (_("junk at end of line: \"%s\""), line);
else
return TRUE;
return true;
}
}
}
@ -6580,7 +6580,7 @@ parse_insn (const char *line, metag_insn *insn)
else
as_bad (_("unknown mnemonic: \"%s\""), mnemonic);
}
return FALSE;
return false;
}
static void
@ -6773,7 +6773,7 @@ metag_force_relocation (fixS * fix)
return generic_force_reloc (fix);
}
bfd_boolean
bool
metag_fix_adjustable (fixS * fixP)
{
if (fixP->fx_addsy == NULL)
@ -7063,7 +7063,7 @@ md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
case BFD_RELOC_METAG_LOADDR16:
case BFD_RELOC_VTABLE_INHERIT:
case BFD_RELOC_VTABLE_ENTRY:
fixP->fx_done = FALSE;
fixP->fx_done = false;
break;
case BFD_RELOC_METAG_REL8:
@ -7132,5 +7132,5 @@ md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
}
if (fixP->fx_addsy == NULL)
fixP->fx_done = TRUE;
fixP->fx_done = true;
}

2
gas/config/tc-metag.h
View File

@ -42,7 +42,7 @@
#define MD_APPLY_SYM_VALUE(FIX) 0
#define tc_fix_adjustable(FIX) metag_fix_adjustable (FIX)
extern bfd_boolean metag_fix_adjustable (struct fix *);
extern bool metag_fix_adjustable (struct fix *);
#define TC_FORCE_RELOCATION(fix) metag_force_relocation (fix)
extern int metag_force_relocation (struct fix *);

38
gas/config/tc-microblaze.c
View File

@ -39,7 +39,7 @@
#define OPTION_EL (OPTION_MD_BASE + 1)
void microblaze_generate_symbol (char *sym);
static bfd_boolean check_spl_reg (unsigned *);
static bool check_spl_reg (unsigned *);
/* Several places in this file insert raw instructions into the
object. They should generate the instruction
@ -858,7 +858,7 @@ parse_cons_expression_microblaze (expressionS *exp, int size)
static const char * str_microblaze_ro_anchor = "RO";
static const char * str_microblaze_rw_anchor = "RW";
static bfd_boolean
static bool
check_spl_reg (unsigned * reg)
{
if ((*reg == REG_MSR) || (*reg == REG_PC)
@ -869,9 +869,9 @@ check_spl_reg (unsigned * reg)
|| (*reg == REG_TLBHI) || (*reg == REG_TLBSX)
|| (*reg == REG_SHR) || (*reg == REG_SLR)
|| (*reg >= REG_PVR+MIN_PVR_REGNUM && *reg <= REG_PVR+MAX_PVR_REGNUM))
return TRUE;
return true;
return FALSE;
return false;
}
/* Here we decide which fixups can be adjusted to make them relative to
@ -1894,65 +1894,65 @@ md_convert_frag (bfd * abfd ATTRIBUTE_UNUSED,
{
case UNDEFINED_PC_OFFSET:
fix_new (fragP, fragP->fr_fix, INST_WORD_SIZE * 2, fragP->fr_symbol,
fragP->fr_offset, TRUE, BFD_RELOC_64_PCREL);
fragP->fr_offset, true, BFD_RELOC_64_PCREL);
fragP->fr_fix += INST_WORD_SIZE * 2;
fragP->fr_var = 0;
break;
case DEFINED_ABS_SEGMENT:
if (fragP->fr_symbol == GOT_symbol)
fix_new (fragP, fragP->fr_fix, INST_WORD_SIZE * 2, fragP->fr_symbol,
fragP->fr_offset, TRUE, BFD_RELOC_MICROBLAZE_64_GOTPC);
fragP->fr_offset, true, BFD_RELOC_MICROBLAZE_64_GOTPC);
else
fix_new (fragP, fragP->fr_fix, INST_WORD_SIZE * 2, fragP->fr_symbol,
fragP->fr_offset, FALSE, BFD_RELOC_64);
fragP->fr_offset, false, BFD_RELOC_64);
fragP->fr_fix += INST_WORD_SIZE * 2;
fragP->fr_var = 0;
break;
case DEFINED_RO_SEGMENT:
fix_new (fragP, fragP->fr_fix, INST_WORD_SIZE, fragP->fr_symbol,
fragP->fr_offset, FALSE, BFD_RELOC_MICROBLAZE_32_ROSDA);
fragP->fr_offset, false, BFD_RELOC_MICROBLAZE_32_ROSDA);
fragP->fr_fix += INST_WORD_SIZE;
fragP->fr_var = 0;
break;
case DEFINED_RW_SEGMENT:
fix_new (fragP, fragP->fr_fix, INST_WORD_SIZE, fragP->fr_symbol,
fragP->fr_offset, FALSE, BFD_RELOC_MICROBLAZE_32_RWSDA);
fragP->fr_offset, false, BFD_RELOC_MICROBLAZE_32_RWSDA);
fragP->fr_fix += INST_WORD_SIZE;
fragP->fr_var = 0;
break;
case DEFINED_PC_OFFSET:
fix_new (fragP, fragP->fr_fix, INST_WORD_SIZE, fragP->fr_symbol,
fragP->fr_offset, TRUE, BFD_RELOC_MICROBLAZE_32_LO_PCREL);
fragP->fr_offset, true, BFD_RELOC_MICROBLAZE_32_LO_PCREL);
fragP->fr_fix += INST_WORD_SIZE;
fragP->fr_var = 0;
break;
case LARGE_DEFINED_PC_OFFSET:
fix_new (fragP, fragP->fr_fix, INST_WORD_SIZE * 2, fragP->fr_symbol,
fragP->fr_offset, TRUE, BFD_RELOC_64_PCREL);
fragP->fr_offset, true, BFD_RELOC_64_PCREL);
fragP->fr_fix += INST_WORD_SIZE * 2;
fragP->fr_var = 0;
break;
case GOT_OFFSET:
fix_new (fragP, fragP->fr_fix, INST_WORD_SIZE * 2, fragP->fr_symbol,
fragP->fr_offset, FALSE, BFD_RELOC_MICROBLAZE_64_GOT);
fragP->fr_offset, false, BFD_RELOC_MICROBLAZE_64_GOT);
fragP->fr_fix += INST_WORD_SIZE * 2;
fragP->fr_var = 0;
break;
case TEXT_OFFSET:
fix_new (fragP, fragP->fr_fix, INST_WORD_SIZE * 2, fragP->fr_symbol,
fragP->fr_offset, FALSE, BFD_RELOC_MICROBLAZE_64_TEXTREL);
fragP->fr_offset, false, BFD_RELOC_MICROBLAZE_64_TEXTREL);
fragP->fr_fix += INST_WORD_SIZE * 2;
fragP->fr_var = 0;
break;
case TEXT_PC_OFFSET:
fix_new (fragP, fragP->fr_fix, INST_WORD_SIZE * 2, fragP->fr_symbol,
fragP->fr_offset, FALSE, BFD_RELOC_MICROBLAZE_64_TEXTPCREL);
fragP->fr_offset, false, BFD_RELOC_MICROBLAZE_64_TEXTPCREL);
fragP->fr_fix += INST_WORD_SIZE * 2;
fragP->fr_var = 0;
break;
case PLT_OFFSET:
fixP = fix_new (fragP, fragP->fr_fix, INST_WORD_SIZE * 2, fragP->fr_symbol,
fragP->fr_offset, TRUE, BFD_RELOC_MICROBLAZE_64_PLT);
fragP->fr_offset, true, BFD_RELOC_MICROBLAZE_64_PLT);
/* fixP->fx_plt = 1; */
(void) fixP;
fragP->fr_fix += INST_WORD_SIZE * 2;
@ -1960,25 +1960,25 @@ md_convert_frag (bfd * abfd ATTRIBUTE_UNUSED,
break;
case GOTOFF_OFFSET:
fix_new (fragP, fragP->fr_fix, INST_WORD_SIZE * 2, fragP->fr_symbol,
fragP->fr_offset, FALSE, BFD_RELOC_MICROBLAZE_64_GOTOFF);
fragP->fr_offset, false, BFD_RELOC_MICROBLAZE_64_GOTOFF);
fragP->fr_fix += INST_WORD_SIZE * 2;
fragP->fr_var = 0;
break;
case TLSGD_OFFSET:
fix_new (fragP, fragP->fr_fix, INST_WORD_SIZE * 2, fragP->fr_symbol,
fragP->fr_offset, FALSE, BFD_RELOC_MICROBLAZE_64_TLSGD);
fragP->fr_offset, false, BFD_RELOC_MICROBLAZE_64_TLSGD);
fragP->fr_fix += INST_WORD_SIZE * 2;
fragP->fr_var = 0;
break;
case TLSLD_OFFSET:
fix_new (fragP, fragP->fr_fix, INST_WORD_SIZE * 2, fragP->fr_symbol,
fragP->fr_offset, FALSE, BFD_RELOC_MICROBLAZE_64_TLSLD);
fragP->fr_offset, false, BFD_RELOC_MICROBLAZE_64_TLSLD);
fragP->fr_fix += INST_WORD_SIZE * 2;
fragP->fr_var = 0;
break;
case TLSDTPREL_OFFSET:
fix_new (fragP, fragP->fr_fix, INST_WORD_SIZE * 2, fragP->fr_symbol,
fragP->fr_offset, FALSE, BFD_RELOC_MICROBLAZE_64_TLSDTPREL);
fragP->fr_offset, false, BFD_RELOC_MICROBLAZE_64_TLSDTPREL);
fragP->fr_fix += INST_WORD_SIZE * 2;
fragP->fr_var = 0;
break;

1035
gas/config/tc-mips.c
View File

File diff suppressed because it is too large Load Diff

2
gas/config/tc-mips.h
View File

@ -149,7 +149,7 @@ extern int mips_force_relocation (struct fix *);
|| mips_force_relocation (FIX))
#define TC_FORCE_RELOCATION_ABS(FIX) mips_force_relocation_abs (FIX)
extern bfd_boolean mips_force_relocation_abs (struct fix *);
extern bool mips_force_relocation_abs (struct fix *);
/* Register mask variables. These are set by the MIPS assembly code
and used by ECOFF and possibly other object file formats. */

2
gas/config/tc-mmix.c
View File

@ -2287,7 +2287,7 @@ md_atof (int type, char *litP, int *sizeP)
The testsuite wants it, and it's customary.
We'll deal with the real problems when they come; we share the
problem with most other ports. */
return ieee_md_atof (type, litP, sizeP, TRUE);
return ieee_md_atof (type, litP, sizeP, true);
}
/* Convert variable-sized frags into one or more fixups. */

20
gas/config/tc-mn10200.c
View File

@ -172,7 +172,7 @@ reg_name_search (const struct reg_name *regs,
Input_line_pointer->(next non-blank) char after operand, or is in
its original state. */
static bfd_boolean
static bool
data_register_name (expressionS *expressionP)
{
int reg_number;
@ -198,12 +198,12 @@ data_register_name (expressionS *expressionP)
expressionP->X_add_symbol = NULL;
expressionP->X_op_symbol = NULL;
return TRUE;
return true;
}
/* Reset the line as if we had not done anything. */
input_line_pointer = start;
return FALSE;
return false;
}
/* Summary of register_name().
@ -216,7 +216,7 @@ data_register_name (expressionS *expressionP)
Input_line_pointer->(next non-blank) char after operand, or is in
its original state. */
static bfd_boolean
static bool
address_register_name (expressionS *expressionP)
{
int reg_number;
@ -242,12 +242,12 @@ address_register_name (expressionS *expressionP)
expressionP->X_add_symbol = NULL;
expressionP->X_op_symbol = NULL;
return TRUE;
return true;
}
/* Reset the line as if we had not done anything. */
input_line_pointer = start;
return FALSE;
return false;
}
/* Summary of register_name().
@ -260,7 +260,7 @@ address_register_name (expressionS *expressionP)
Input_line_pointer->(next non-blank) char after operand, or is in
its original state. */
static bfd_boolean
static bool
other_register_name (expressionS *expressionP)
{
int reg_number;
@ -286,12 +286,12 @@ other_register_name (expressionS *expressionP)
expressionP->X_add_symbol = NULL;
expressionP->X_op_symbol = NULL;
return TRUE;
return true;
}
/* Reset the line as if we had not done anything. */
input_line_pointer = start;
return FALSE;
return false;
}
void
@ -317,7 +317,7 @@ md_undefined_symbol (char *name ATTRIBUTE_UNUSED)
const char *
md_atof (int type, char *litp, int *sizep)
{
return ieee_md_atof (type, litp, sizep, FALSE);
return ieee_md_atof (type, litp, sizep, false);
}
void

72
gas/config/tc-mn10300.c
View File

@ -323,7 +323,7 @@ reg_name_search (const struct reg_name *regs,
the name and the function returns TRUE. Otherwise the input pointer
is left alone and the function returns FALSE. */
static bfd_boolean
static bool
get_register_name (expressionS * expressionP,
const struct reg_name * table,
size_t table_length)
@ -352,52 +352,52 @@ get_register_name (expressionS * expressionP,
expressionP->X_add_symbol = NULL;
expressionP->X_op_symbol = NULL;
return TRUE;
return true;
}
/* Reset the line as if we had not done anything. */
input_line_pointer = start;
return FALSE;
return false;
}
static bfd_boolean
static bool
r_register_name (expressionS *expressionP)
{
return get_register_name (expressionP, r_registers, ARRAY_SIZE (r_registers));
}
static bfd_boolean
static bool
xr_register_name (expressionS *expressionP)
{
return get_register_name (expressionP, xr_registers, ARRAY_SIZE (xr_registers));
}
static bfd_boolean
static bool
data_register_name (expressionS *expressionP)
{
return get_register_name (expressionP, data_registers, ARRAY_SIZE (data_registers));
}
static bfd_boolean
static bool
address_register_name (expressionS *expressionP)
{
return get_register_name (expressionP, address_registers, ARRAY_SIZE (address_registers));
}
static bfd_boolean
static bool
float_register_name (expressionS *expressionP)
{
return get_register_name (expressionP, float_registers, ARRAY_SIZE (float_registers));
}
static bfd_boolean
static bool
double_register_name (expressionS *expressionP)
{
return get_register_name (expressionP, double_registers, ARRAY_SIZE (double_registers));
}
static bfd_boolean
static bool
other_register_name (expressionS *expressionP)
{
int reg_number;
@ -425,12 +425,12 @@ other_register_name (expressionS *expressionP)
expressionP->X_add_symbol = NULL;
expressionP->X_op_symbol = NULL;
return TRUE;
return true;
}
/* Reset the line as if we had not done anything. */
input_line_pointer = start;
return FALSE;
return false;
}
void
@ -455,7 +455,7 @@ md_undefined_symbol (char *name ATTRIBUTE_UNUSED)
const char *
md_atof (int type, char *litp, int *sizep)
{
return ieee_md_atof (type, litp, sizep, FALSE);
return ieee_md_atof (type, litp, sizep, false);
}
void
@ -1073,7 +1073,7 @@ mn10300_cons_fix_new (fragS *frag, int off, int size, expressionS *exp,
fix_new_exp (frag, off, size, &fixup.exp, 0, fixup.reloc);
}
static bfd_boolean
static bool
check_operand (const struct mn10300_operand *operand,
offsetT val)
{
@ -1104,9 +1104,9 @@ check_operand (const struct mn10300_operand *operand,
test = val;
if (test < (offsetT) min || test > (offsetT) max)
return FALSE;
return false;
}
return TRUE;
return true;
}
/* Insert an operand value into an instruction. */
@ -2155,7 +2155,7 @@ md_assemble (char *str)
}
/* Label this frag as one that contains instructions. */
frag_now->tc_frag_data = TRUE;
frag_now->tc_frag_data = true;
}
/* If while processing a fixup, a reloc really needs to be created
@ -2278,7 +2278,7 @@ tc_gen_reloc (asection *seg ATTRIBUTE_UNUSED, fixS *fixp)
/* Returns true iff the symbol attached to the frag is at a known location
in the given section, (and hence the relocation to it can be relaxed by
the assembler). */
static inline bfd_boolean
static inline bool
has_known_symbol_location (fragS * fragp, asection * sec)
{
symbolS * sym = fragp->fr_symbol;
@ -2400,37 +2400,37 @@ md_apply_fix (fixS * fixP, valueT * valP, segT seg)
/* Return zero if the fixup in fixp should be left alone and not
adjusted. */
bfd_boolean
bool
mn10300_fix_adjustable (struct fix *fixp)
{
if (fixp->fx_pcrel)
{
if (TC_FORCE_RELOCATION_LOCAL (fixp))
return FALSE;
return false;
}
/* Non-relative relocs can (and must) be adjusted if they do
not meet the criteria below, or the generic criteria. */
else if (TC_FORCE_RELOCATION (fixp))
return FALSE;
return false;
/* Do not adjust relocations involving symbols in code sections,
because it breaks linker relaxations. This could be fixed in the
linker, but this fix is simpler, and it pretty much only affects
object size a little bit. */
if (S_GET_SEGMENT (fixp->fx_addsy)->flags & SEC_CODE)
return FALSE;
return false;
/* Likewise, do not adjust symbols that won't be merged, or debug
symbols, because they too break relaxation. We do want to adjust
other mergeable symbols, like .rodata, because code relaxations
need section-relative symbols to properly relax them. */
if (! (S_GET_SEGMENT (fixp->fx_addsy)->flags & SEC_MERGE))
return FALSE;
return false;
if (strncmp (S_GET_SEGMENT (fixp->fx_addsy)->name, ".debug", 6) == 0)
return FALSE;
return false;
return TRUE;
return true;
}
static void
@ -2549,10 +2549,10 @@ const pseudo_typeS md_pseudo_table[] =
subtraction of two same-section symbols cannot be computed by
the assembler. */
bfd_boolean
bool
mn10300_allow_local_subtract (expressionS * left, expressionS * right, segT section)
{
bfd_boolean result;
bool result;
fragS * left_frag;
fragS * right_frag;
fragS * frag;
@ -2560,11 +2560,11 @@ mn10300_allow_local_subtract (expressionS * left, expressionS * right, segT sect
/* If we are not performing linker relaxation then we have nothing
to worry about. */
if (linkrelax == 0)
return TRUE;
return true;
/* If the symbols are not in a code section then they are OK. */
if ((section->flags & SEC_CODE) == 0)
return TRUE;
return true;
/* Otherwise we have to scan the fragments between the two symbols.
If any instructions are found then we have to assume that linker
@ -2576,11 +2576,11 @@ mn10300_allow_local_subtract (expressionS * left, expressionS * right, segT sect
if (left_frag == right_frag)
return ! left_frag->tc_frag_data;
result = TRUE;
result = true;
for (frag = left_frag; frag != NULL; frag = frag->fr_next)
{
if (frag->tc_frag_data)
result = FALSE;
result = false;
if (frag == right_frag)
break;
}
@ -2589,7 +2589,7 @@ mn10300_allow_local_subtract (expressionS * left, expressionS * right, segT sect
for (frag = right_frag; frag != NULL; frag = frag->fr_next)
{
if (frag->tc_frag_data)
result = FALSE;
result = false;
if (frag == left_frag)
break;
}
@ -2597,7 +2597,7 @@ mn10300_allow_local_subtract (expressionS * left, expressionS * right, segT sect
if (frag == NULL)
/* The two symbols are on disjoint fragment chains
- we cannot possibly compute their difference. */
return FALSE;
return false;
return result;
}
@ -2622,17 +2622,17 @@ mn10300_handle_align (fragS *frag)
The offset from the symbol is used to record the power-of-two alignment
value. The size is set to 0 because the frag may already be aligned,
thus causing cvt_frag_to_fill to reduce the size of the frag to zero. */
fix_new (frag, frag->fr_fix, 0, & abs_symbol, frag->fr_offset, FALSE,
fix_new (frag, frag->fr_fix, 0, & abs_symbol, frag->fr_offset, false,
BFD_RELOC_MN10300_ALIGN);
}
bfd_boolean
bool
mn10300_force_relocation (struct fix * fixp)
{
if (linkrelax
&& (fixp->fx_pcrel
|| fixp->fx_r_type == BFD_RELOC_MN10300_ALIGN))
return TRUE;
return true;
return generic_force_reloc (fixp);
}

8
gas/config/tc-mn10300.h
View File

@ -26,7 +26,7 @@
#define GLOBAL_OFFSET_TABLE_NAME "_GLOBAL_OFFSET_TABLE_"
#define TC_FORCE_RELOCATION(FIX) mn10300_force_relocation (FIX)
extern bfd_boolean mn10300_force_relocation (struct fix *);
extern bool mn10300_force_relocation (struct fix *);
/* tc-mn10300.c uses TC_FORCE_RELOCATION_LOCAL, a macro that should
only appear in write.c. The use is likely incorrect. Duplicating
@ -107,7 +107,7 @@ void mn10300_cons_fix_new (fragS *, int, int, expressionS *,
#define md_number_to_chars number_to_chars_littleendian
#define tc_fix_adjustable(FIX) mn10300_fix_adjustable (FIX)
extern bfd_boolean mn10300_fix_adjustable (struct fix *);
extern bool mn10300_fix_adjustable (struct fix *);
/* We do relaxing in the assembler as well as the linker. */
extern const struct relax_type md_relax_table[];
@ -118,12 +118,12 @@ extern const struct relax_type md_relax_table[];
/* The difference between same-section symbols may be affected by linker
relaxation, so do not resolve such expressions in the assembler. */
#define md_allow_local_subtract(l,r,s) mn10300_allow_local_subtract (l, r, s)
extern bfd_boolean mn10300_allow_local_subtract (expressionS *, expressionS *, segT);
extern bool mn10300_allow_local_subtract (expressionS *, expressionS *, segT);
#define RELOC_EXPANSION_POSSIBLE
#define MAX_RELOC_EXPANSION 2
#define TC_FRAG_TYPE bfd_boolean
#define TC_FRAG_TYPE bool
#define HANDLE_ALIGN(frag) mn10300_handle_align (frag)
extern void mn10300_handle_align (fragS *);

2
gas/config/tc-moxie.c
View File

@ -529,7 +529,7 @@ md_assemble (char *str)
(p - frag_now->fr_literal),
2,
&arg,
TRUE,
true,
BFD_RELOC_MOXIE_10_PCREL);
}
break;

276
gas/config/tc-msp430.c
View File

@ -263,13 +263,13 @@ typedef enum msp_isa
static enum msp_isa selected_isa = MSP_ISA_430Xv2;
static inline bfd_boolean
static inline bool
target_is_430x (void)
{
return selected_isa >= MSP_ISA_430X;
}
static inline bfd_boolean
static inline bool
target_is_430xv2 (void)
{
return selected_isa == MSP_ISA_430Xv2;
@ -674,21 +674,21 @@ extract_word (char * from, char * to, int limit)
#define OPTION_RELAX 'Q'
#define OPTION_POLYMORPHS 'P'
#define OPTION_LARGE 'l'
static bfd_boolean large_model = FALSE;
static bool large_model = false;
#define OPTION_NO_INTR_NOPS 'N'
#define OPTION_INTR_NOPS 'n'
static bfd_boolean gen_interrupt_nops = FALSE;
static bool gen_interrupt_nops = false;
#define OPTION_WARN_INTR_NOPS 'y'
#define OPTION_NO_WARN_INTR_NOPS 'Y'
static bfd_boolean warn_interrupt_nops = TRUE;
static bool warn_interrupt_nops = true;
#define OPTION_UNKNOWN_INTR_NOPS 'u'
#define OPTION_NO_UNKNOWN_INTR_NOPS 'U'
static bfd_boolean do_unknown_interrupt_nops = TRUE;
static bool do_unknown_interrupt_nops = true;
#define OPTION_MCPU 'c'
#define OPTION_DATA_REGION 'r'
static bfd_boolean upper_data_region_in_use = FALSE;
static bool upper_data_region_in_use = false;
/* The default is to use the lower region only. */
static bfd_boolean lower_data_region_only = TRUE;
static bool lower_data_region_only = true;
/* Deprecated option, silently ignore it for compatibility with GCC <= 10. */
#define OPTION_MOVE_DATA 'd'
@ -1444,28 +1444,28 @@ md_parse_option (int c, const char * arg)
return 1;
case OPTION_LARGE:
large_model = TRUE;
large_model = true;
return 1;
case OPTION_NO_INTR_NOPS:
gen_interrupt_nops = FALSE;
gen_interrupt_nops = false;
return 1;
case OPTION_INTR_NOPS:
gen_interrupt_nops = TRUE;
gen_interrupt_nops = true;
return 1;
case OPTION_WARN_INTR_NOPS:
warn_interrupt_nops = TRUE;
warn_interrupt_nops = true;
return 1;
case OPTION_NO_WARN_INTR_NOPS:
warn_interrupt_nops = FALSE;
warn_interrupt_nops = false;
return 1;
case OPTION_UNKNOWN_INTR_NOPS:
do_unknown_interrupt_nops = TRUE;
do_unknown_interrupt_nops = true;
return 1;
case OPTION_NO_UNKNOWN_INTR_NOPS:
do_unknown_interrupt_nops = FALSE;
do_unknown_interrupt_nops = false;
return 1;
case OPTION_MOVE_DATA:
@ -1475,14 +1475,14 @@ md_parse_option (int c, const char * arg)
case OPTION_DATA_REGION:
if (strcmp (arg, "upper") == 0
|| strcmp (arg, "either") == 0)
upper_data_region_in_use = TRUE;
upper_data_region_in_use = true;
if (strcmp (arg, "upper") == 0
|| strcmp (arg, "either") == 0
/* With data-region=none, the compiler has generated code assuming
data could be in the upper region, but nothing has been explicitly
placed there. */
|| strcmp (arg, "none") == 0)
lower_data_region_only = FALSE;
lower_data_region_only = false;
return 1;
}
@ -1826,7 +1826,7 @@ extract_cmd (char * from, char * to, int limit)
const char *
md_atof (int type, char * litP, int * sizeP)
{
return ieee_md_atof (type, litP, sizeP, FALSE);
return ieee_md_atof (type, litP, sizeP, false);
}
void
@ -1845,7 +1845,7 @@ md_begin (void)
linkrelax = 1;
}
static inline bfd_boolean
static inline bool
is_regname_end (char c)
{
return (c == 0 || ! ISALNUM (c));
@ -1895,9 +1895,9 @@ static int
msp430_srcoperand (struct msp430_operand_s * op,
char * l,
int bin,
bfd_boolean * imm_op,
bfd_boolean allow_20bit_values,
bfd_boolean constants_allowed)
bool * imm_op,
bool allow_20bit_values,
bool constants_allowed)
{
char * end;
char *__tl = l;
@ -1918,7 +1918,7 @@ msp430_srcoperand (struct msp430_operand_s * op,
hhi(x) - x = (x >> 48) & 0xffff
The value _MUST_ be an immediate expression: #hlo(1231231231). */
*imm_op = TRUE;
*imm_op = true;
if (strncasecmp (h, "#llo(", 5) == 0)
{
@ -2250,7 +2250,7 @@ msp430_srcoperand (struct msp430_operand_s * op,
char *m = strrchr (l, ')');
char *t;
*imm_op = TRUE;
*imm_op = true;
if (!h)
break;
@ -2374,10 +2374,10 @@ static int
msp430_dstoperand (struct msp430_operand_s * op,
char * l,
int bin,
bfd_boolean allow_20bit_values,
bfd_boolean constants_allowed)
bool allow_20bit_values,
bool constants_allowed)
{
bfd_boolean dummy;
bool dummy;
int ret = msp430_srcoperand (op, l, bin, & dummy,
allow_20bit_values,
constants_allowed);
@ -2420,7 +2420,7 @@ msp430_dstoperand (struct msp430_operand_s * op,
will be returned if a pointer is provided. */
static int
try_encode_mova (bfd_boolean imm_op,
try_encode_mova (bool imm_op,
int bin,
struct msp430_operand_s * op1,
struct msp430_operand_s * op2,
@ -2458,7 +2458,7 @@ try_encode_mova (bfd_boolean imm_op,
else
{
bfd_putl16 ((bfd_vma) bin, frag);
fix_new_exp (frag_now, where, 4, &(op1->exp), FALSE,
fix_new_exp (frag_now, where, 4, &(op1->exp), false,
BFD_RELOC_MSP430X_ABS20_ADR_SRC);
bfd_putl16 ((bfd_vma) ZEROS, frag + 2);
}
@ -2486,7 +2486,7 @@ try_encode_mova (bfd_boolean imm_op,
else
{
bfd_putl16 ((bfd_vma) ZEROS, frag + 2);
fix_new_exp (frag_now, where + 2, 2, &(op1->exp), FALSE,
fix_new_exp (frag_now, where + 2, 2, &(op1->exp), false,
op1->reg == 0 ?
BFD_RELOC_MSP430X_PCR16 :
BFD_RELOC_MSP430X_ABS16);
@ -2527,7 +2527,7 @@ try_encode_mova (bfd_boolean imm_op,
{
bfd_putl16 ((bfd_vma) bin, frag);
bfd_putl16 ((bfd_vma) ZEROS, frag + 2);
fix_new_exp (frag_now, where, 4, &(op2->exp), FALSE,
fix_new_exp (frag_now, where, 4, &(op2->exp), false,
BFD_RELOC_MSP430X_ABS20_ADR_DST);
}
return 4;
@ -2552,7 +2552,7 @@ try_encode_mova (bfd_boolean imm_op,
else
{
bfd_putl16 ((bfd_vma) ZEROS, frag + 2);
fix_new_exp (frag_now, where + 2, 2, &(op2->exp), FALSE,
fix_new_exp (frag_now, where + 2, 2, &(op2->exp), false,
op2->reg == 0 ?
BFD_RELOC_MSP430X_PCR16 :
BFD_RELOC_MSP430X_ABS16);
@ -2566,7 +2566,7 @@ try_encode_mova (bfd_boolean imm_op,
}
}
/* imm_op == FALSE. */
/* imm_op == false. */
if (op1->reg == 2 && op1->am == 1 && op1->mode == OP_EXP)
{
@ -2598,7 +2598,7 @@ try_encode_mova (bfd_boolean imm_op,
{
bfd_putl16 ((bfd_vma) bin, frag);
bfd_putl16 ((bfd_vma) ZEROS, frag + 2);
fix_new_exp (frag_now, where, 4, &(op1->exp), FALSE,
fix_new_exp (frag_now, where, 4, &(op1->exp), false,
BFD_RELOC_MSP430X_ABS20_ADR_SRC);
}
return 4;
@ -2720,7 +2720,7 @@ gen_nop (void)
/* Insert/inform about adding a NOP if this insn enables interrupts. */
static void
warn_eint_nop (bfd_boolean prev_insn_is_nop, bfd_boolean prev_insn_is_dint)
warn_eint_nop (bool prev_insn_is_nop, bool prev_insn_is_dint)
{
if (prev_insn_is_nop
/* If the last insn was a DINT, we will have already warned that a NOP is
@ -2744,8 +2744,8 @@ warn_eint_nop (bfd_boolean prev_insn_is_nop, bfd_boolean prev_insn_is_dint)
to insert/warn about adding a NOP before the current insn. */
static void
warn_unsure_interrupt (bfd_boolean prev_insn_is_nop,
bfd_boolean prev_insn_is_dint)
warn_unsure_interrupt (bool prev_insn_is_nop,
bool prev_insn_is_dint)
{
if (prev_insn_is_nop
/* If the last insn was a DINT, we will have already warned that a NOP is
@ -2780,22 +2780,22 @@ msp430_operands (struct msp430_opcode_s * opcode, char * line)
struct msp430_operand_s op1, op2;
int res = 0;
static short ZEROS = 0;
bfd_boolean byte_op, imm_op;
bool byte_op, imm_op;
int op_length = 0;
int fmt;
int extended = 0x1800;
bfd_boolean extended_op = FALSE;
bfd_boolean addr_op;
bool extended_op = false;
bool addr_op;
const char * error_message;
static signed int repeat_count = 0;
static bfd_boolean prev_insn_is_nop = FALSE;
static bfd_boolean prev_insn_is_dint = FALSE;
static bfd_boolean prev_insn_is_eint = FALSE;
static bool prev_insn_is_nop = false;
static bool prev_insn_is_dint = false;
static bool prev_insn_is_eint = false;
/* We might decide before the end of the function that the current insn is
equivalent to DINT/EINT. */
bfd_boolean this_insn_is_dint = FALSE;
bfd_boolean this_insn_is_eint = FALSE;
bfd_boolean fix_emitted;
bool this_insn_is_dint = false;
bool this_insn_is_eint = false;
bool fix_emitted;
/* Opcode is the one from opcodes table
line contains something like
@ -2803,11 +2803,11 @@ msp430_operands (struct msp430_opcode_s * opcode, char * line)
or
.b @r2+, 5(R1). */
byte_op = FALSE;
addr_op = FALSE;
byte_op = false;
addr_op = false;
if (*line == '.')
{
bfd_boolean check = FALSE;
bool check = false;
++ line;
switch (TOLOWER (* line))
@ -2815,20 +2815,20 @@ msp430_operands (struct msp430_opcode_s * opcode, char * line)
case 'b':
/* Byte operation. */
bin |= BYTE_OPERATION;
byte_op = TRUE;
check = TRUE;
byte_op = true;
check = true;
break;
case 'a':
/* "Address" ops work on 20-bit values. */
addr_op = TRUE;
addr_op = true;
bin |= BYTE_OPERATION;
check = TRUE;
check = true;
break;
case 'w':
/* Word operation - this is the default. */
check = TRUE;
check = true;
break;
case 0:
@ -2879,7 +2879,7 @@ msp430_operands (struct msp430_opcode_s * opcode, char * line)
#if 0 /* Enable for debugging. */
as_warn ("treating %s.a as %s", old_name, real_name);
#endif
addr_op = FALSE;
addr_op = false;
bin = opcode->bin_opcode;
}
@ -2899,7 +2899,7 @@ msp430_operands (struct msp430_opcode_s * opcode, char * line)
memset (&op1, 0, sizeof (op1));
memset (&op2, 0, sizeof (op2));
imm_op = FALSE;
imm_op = false;
if ((fmt = opcode->fmt) < 0)
{
@ -2911,7 +2911,7 @@ msp430_operands (struct msp430_opcode_s * opcode, char * line)
}
fmt = (-fmt) - 1;
extended_op = TRUE;
extended_op = true;
}
if (repeat_count)
@ -3053,7 +3053,7 @@ msp430_operands (struct msp430_opcode_s * opcode, char * line)
case 1:
/* Something which works with destination operand. */
line = extract_operand (line, l1, sizeof (l1));
res = msp430_dstoperand (&op1, l1, opcode->bin_opcode, extended_op, TRUE);
res = msp430_dstoperand (&op1, l1, opcode->bin_opcode, extended_op, true);
if (res)
break;
@ -3111,10 +3111,10 @@ msp430_operands (struct msp430_opcode_s * opcode, char * line)
extended |= ((op1.exp.X_add_number >> 16) & 0xf) << 7;
else if (op1.reg || op1.am == 3) /* Not PC relative. */
fix_new_exp (frag_now, where, 6, &(op1.exp), FALSE,
fix_new_exp (frag_now, where, 6, &(op1.exp), false,
BFD_RELOC_MSP430X_ABS20_EXT_SRC);
else
fix_new_exp (frag_now, where, 6, &(op1.exp), FALSE,
fix_new_exp (frag_now, where, 6, &(op1.exp), false,
BFD_RELOC_MSP430X_PCR20_EXT_SRC);
}
@ -3142,10 +3142,10 @@ msp430_operands (struct msp430_opcode_s * opcode, char * line)
{
if (op1.reg)
fix_new_exp (frag_now, where, 2,
&(op1.exp), FALSE, CHECK_RELOC_MSP430 (op1));
&(op1.exp), false, CHECK_RELOC_MSP430 (op1));
else
fix_new_exp (frag_now, where, 2,
&(op1.exp), TRUE, CHECK_RELOC_MSP430_PCREL);
&(op1.exp), true, CHECK_RELOC_MSP430_PCREL);
}
}
}
@ -3158,8 +3158,8 @@ msp430_operands (struct msp430_opcode_s * opcode, char * line)
line = extract_operand (line, l1, sizeof (l1));
strncpy (l2, l1, sizeof (l2));
l2[sizeof (l2) - 1] = '\0';
res = msp430_srcoperand (&op1, l1, opcode->bin_opcode, &imm_op, extended_op, TRUE);
res += msp430_dstoperand (&op2, l2, opcode->bin_opcode, extended_op, TRUE);
res = msp430_srcoperand (&op1, l1, opcode->bin_opcode, &imm_op, extended_op, true);
res += msp430_dstoperand (&op2, l2, opcode->bin_opcode, extended_op, true);
if (res)
break; /* An error occurred. All warnings were done before. */
@ -3212,10 +3212,10 @@ msp430_operands (struct msp430_opcode_s * opcode, char * line)
extended |= ((op1.exp.X_add_number >> 16) & 0xf) << 7;
else if (op1.reg || op1.am == 3) /* Not PC relative. */
fix_new_exp (frag_now, where, 6, &(op1.exp), FALSE,
fix_new_exp (frag_now, where, 6, &(op1.exp), false,
BFD_RELOC_MSP430X_ABS20_EXT_SRC);
else
fix_new_exp (frag_now, where, 6, &(op1.exp), FALSE,
fix_new_exp (frag_now, where, 6, &(op1.exp), false,
BFD_RELOC_MSP430X_PCR20_EXT_SRC);
}
@ -3225,11 +3225,11 @@ msp430_operands (struct msp430_opcode_s * opcode, char * line)
extended |= (op2.exp.X_add_number >> 16) & 0xf;
else if (op1.mode == OP_EXP)
fix_new_exp (frag_now, where, 8, &(op2.exp), FALSE,
fix_new_exp (frag_now, where, 8, &(op2.exp), false,
op2.reg ? BFD_RELOC_MSP430X_ABS20_EXT_ODST
: BFD_RELOC_MSP430X_PCR20_EXT_ODST);
else
fix_new_exp (frag_now, where, 6, &(op2.exp), FALSE,
fix_new_exp (frag_now, where, 6, &(op2.exp), false,
op2.reg ? BFD_RELOC_MSP430X_ABS20_EXT_DST
: BFD_RELOC_MSP430X_PCR20_EXT_DST);
}
@ -3259,10 +3259,10 @@ msp430_operands (struct msp430_opcode_s * opcode, char * line)
{
if (op1.reg || op1.am == 3) /* Not PC relative. */
fix_new_exp (frag_now, where, 2,
&(op1.exp), FALSE, CHECK_RELOC_MSP430 (op1));
&(op1.exp), false, CHECK_RELOC_MSP430 (op1));
else
fix_new_exp (frag_now, where, 2,
&(op1.exp), TRUE, CHECK_RELOC_MSP430_PCREL);
&(op1.exp), true, CHECK_RELOC_MSP430_PCREL);
}
}
frag += 2;
@ -3283,10 +3283,10 @@ msp430_operands (struct msp430_opcode_s * opcode, char * line)
{
if (op2.reg) /* Not PC relative. */
fix_new_exp (frag_now, where, 2,
&(op2.exp), FALSE, CHECK_RELOC_MSP430 (op2));
&(op2.exp), false, CHECK_RELOC_MSP430 (op2));
else
fix_new_exp (frag_now, where, 2,
&(op2.exp), TRUE, CHECK_RELOC_MSP430_PCREL);
&(op2.exp), true, CHECK_RELOC_MSP430_PCREL);
}
}
}
@ -3303,12 +3303,12 @@ msp430_operands (struct msp430_opcode_s * opcode, char * line)
}
line = extract_operand (line, l1, sizeof (l1));
res = msp430_srcoperand (&op1, l1, opcode->bin_opcode, &imm_op, extended_op, FALSE);
res = msp430_srcoperand (&op1, l1, opcode->bin_opcode, &imm_op, extended_op, false);
if (res)
break;
byte_op = FALSE;
imm_op = FALSE;
byte_op = false;
imm_op = false;
bin |= ((op1.reg << 8) | (op1.am << 4));
op_length = 2 + 2 * op1.ol;
frag = frag_more (op_length);
@ -3329,10 +3329,10 @@ msp430_operands (struct msp430_opcode_s * opcode, char * line)
if (op1.reg || op1.am == 3)
fix_new_exp (frag_now, where, 2,
&(op1.exp), FALSE, CHECK_RELOC_MSP430 (op1));
&(op1.exp), false, CHECK_RELOC_MSP430 (op1));
else
fix_new_exp (frag_now, where, 2,
&(op1.exp), TRUE, CHECK_RELOC_MSP430_PCREL);
&(op1.exp), true, CHECK_RELOC_MSP430_PCREL);
}
}
@ -3341,17 +3341,17 @@ msp430_operands (struct msp430_opcode_s * opcode, char * line)
case 4:
/* CALLA instructions. */
fix_emitted = FALSE;
fix_emitted = false;
line = extract_operand (line, l1, sizeof (l1));
imm_op = FALSE;
imm_op = false;
res = msp430_srcoperand (&op1, l1, opcode->bin_opcode, &imm_op,
extended_op, FALSE);
extended_op, false);
if (res)
break;
byte_op = FALSE;
byte_op = false;
op_length = 2 + 2 * op1.ol;
frag = frag_more (op_length);
@ -3363,9 +3363,9 @@ msp430_operands (struct msp430_opcode_s * opcode, char * line)
{
bin |= 0xb0;
fix_new_exp (frag_now, where, 4, &(op1.exp), FALSE,
fix_new_exp (frag_now, where, 4, &(op1.exp), false,
BFD_RELOC_MSP430X_ABS20_ADR_DST);
fix_emitted = TRUE;
fix_emitted = true;
}
else if (op1.am == 1)
{
@ -3373,9 +3373,9 @@ msp430_operands (struct msp430_opcode_s * opcode, char * line)
{
bin |= 0x90;
fix_new_exp (frag_now, where, 4, &(op1.exp), FALSE,
fix_new_exp (frag_now, where, 4, &(op1.exp), false,
BFD_RELOC_MSP430X_PCR20_CALL);
fix_emitted = TRUE;
fix_emitted = true;
}
else
bin |= 0x50 | op1.reg;
@ -3387,9 +3387,9 @@ msp430_operands (struct msp430_opcode_s * opcode, char * line)
{
bin |= 0x80;
fix_new_exp (frag_now, where, 4, &(op1.exp), FALSE,
fix_new_exp (frag_now, where, 4, &(op1.exp), false,
BFD_RELOC_MSP430X_ABS20_ADR_DST);
fix_emitted = TRUE;
fix_emitted = true;
}
else if (op1.am == 2)
bin |= 0x60 | op1.reg;
@ -3410,7 +3410,7 @@ msp430_operands (struct msp430_opcode_s * opcode, char * line)
if (! fix_emitted)
fix_new_exp (frag_now, where + 2, 2,
&(op1.exp), FALSE, BFD_RELOC_16);
&(op1.exp), false, BFD_RELOC_16);
}
dwarf2_emit_insn (insn_length + op_length);
@ -3556,7 +3556,7 @@ msp430_operands (struct msp430_opcode_s * opcode, char * line)
case 8:
{
bfd_boolean need_reloc = FALSE;
bool need_reloc = false;
int n;
int reg;
@ -3596,7 +3596,7 @@ msp430_operands (struct msp430_opcode_s * opcode, char * line)
else
{
n = 0;
need_reloc = TRUE;
need_reloc = true;
}
op_length = 4;
@ -3625,7 +3625,7 @@ msp430_operands (struct msp430_opcode_s * opcode, char * line)
where = frag - frag_now->fr_literal;
bin |= reg;
if (need_reloc)
fix_new_exp (frag_now, where, 4, &(op1.exp), FALSE,
fix_new_exp (frag_now, where, 4, &(op1.exp), false,
BFD_RELOC_MSP430X_ABS20_ADR_SRC);
bfd_putl16 ((bfd_vma) bin, frag);
@ -3636,7 +3636,7 @@ msp430_operands (struct msp430_opcode_s * opcode, char * line)
}
case 9: /* MOVA, BRA, RETA. */
imm_op = FALSE;
imm_op = false;
bin = opcode->bin_opcode;
if (is_opcode ("reta"))
@ -3655,7 +3655,7 @@ msp430_operands (struct msp430_opcode_s * opcode, char * line)
{
line = extract_operand (line, l1, sizeof (l1));
res = msp430_srcoperand (&op1, l1, opcode->bin_opcode,
&imm_op, extended_op, FALSE);
&imm_op, extended_op, false);
if (is_opcode ("bra"))
{
@ -3668,7 +3668,7 @@ msp430_operands (struct msp430_opcode_s * opcode, char * line)
{
line = extract_operand (line, l2, sizeof (l2));
res += msp430_dstoperand (&op2, l2, opcode->bin_opcode,
extended_op, TRUE);
extended_op, true);
}
if (res)
@ -3747,8 +3747,8 @@ msp430_operands (struct msp430_opcode_s * opcode, char * line)
case 1: /* Format 1, double operand. */
line = extract_operand (line, l1, sizeof (l1));
line = extract_operand (line, l2, sizeof (l2));
res = msp430_srcoperand (&op1, l1, opcode->bin_opcode, &imm_op, extended_op, TRUE);
res += msp430_dstoperand (&op2, l2, opcode->bin_opcode, extended_op, TRUE);
res = msp430_srcoperand (&op1, l1, opcode->bin_opcode, &imm_op, extended_op, true);
res += msp430_dstoperand (&op2, l2, opcode->bin_opcode, extended_op, true);
if (res)
break; /* Error occurred. All warnings were done before. */
@ -3819,11 +3819,11 @@ msp430_operands (struct msp430_opcode_s * opcode, char * line)
{
/* The GIE bit is being set. */
warn_eint_nop (prev_insn_is_nop, prev_insn_is_dint);
this_insn_is_eint = TRUE;
this_insn_is_eint = true;
}
else
/* The GIE bit is being cleared. */
this_insn_is_dint = TRUE;
this_insn_is_dint = true;
}
/* If an immediate value which is covered by the constant generator
is the src, then op1 will have been changed to either R2 or R3 by
@ -3837,13 +3837,13 @@ msp430_operands (struct msp430_opcode_s * opcode, char * line)
&& (bin & 0x30) == 0x30)
{
warn_eint_nop (prev_insn_is_nop, prev_insn_is_dint);
this_insn_is_eint = TRUE;
this_insn_is_eint = true;
}
/* Any other use of the constant generator with destination R2, will
disable interrupts. */
else if (op1.mode == OP_REG
&& (op1.reg == 2 || op1.reg == 3))
this_insn_is_dint = TRUE;
this_insn_is_dint = true;
else if (do_unknown_interrupt_nops)
{
/* FIXME: Couldn't work out whether the insn is enabling or
@ -3891,10 +3891,10 @@ msp430_operands (struct msp430_opcode_s * opcode, char * line)
extended |= ((op1.exp.X_add_number >> 16) & 0xf) << 7;
else if (op1.reg || op1.am == 3) /* Not PC relative. */
fix_new_exp (frag_now, where, 6, &(op1.exp), FALSE,
fix_new_exp (frag_now, where, 6, &(op1.exp), false,
BFD_RELOC_MSP430X_ABS20_EXT_SRC);
else
fix_new_exp (frag_now, where, 6, &(op1.exp), FALSE,
fix_new_exp (frag_now, where, 6, &(op1.exp), false,
BFD_RELOC_MSP430X_PCR20_EXT_SRC);
}
@ -3904,12 +3904,12 @@ msp430_operands (struct msp430_opcode_s * opcode, char * line)
extended |= (op2.exp.X_add_number >> 16) & 0xf;
else if (op1.mode == OP_EXP)
fix_new_exp (frag_now, where, 8, &(op2.exp), FALSE,
fix_new_exp (frag_now, where, 8, &(op2.exp), false,
op2.reg ? BFD_RELOC_MSP430X_ABS20_EXT_ODST
: BFD_RELOC_MSP430X_PCR20_EXT_ODST);
else
fix_new_exp (frag_now, where, 6, &(op2.exp), FALSE,
fix_new_exp (frag_now, where, 6, &(op2.exp), false,
op2.reg ? BFD_RELOC_MSP430X_ABS20_EXT_DST
: BFD_RELOC_MSP430X_PCR20_EXT_DST);
}
@ -3938,10 +3938,10 @@ msp430_operands (struct msp430_opcode_s * opcode, char * line)
{
if (op1.reg || op1.am == 3) /* Not PC relative. */
fix_new_exp (frag_now, where, 2,
&(op1.exp), FALSE, CHECK_RELOC_MSP430 (op1));
&(op1.exp), false, CHECK_RELOC_MSP430 (op1));
else
fix_new_exp (frag_now, where, 2,
&(op1.exp), TRUE, CHECK_RELOC_MSP430_PCREL);
&(op1.exp), true, CHECK_RELOC_MSP430_PCREL);
}
}
@ -3963,10 +3963,10 @@ msp430_operands (struct msp430_opcode_s * opcode, char * line)
{
if (op2.reg) /* Not PC relative. */
fix_new_exp (frag_now, where, 2,
&(op2.exp), FALSE, CHECK_RELOC_MSP430 (op2));
&(op2.exp), false, CHECK_RELOC_MSP430 (op2));
else
fix_new_exp (frag_now, where, 2,
&(op2.exp), TRUE, CHECK_RELOC_MSP430_PCREL);
&(op2.exp), true, CHECK_RELOC_MSP430_PCREL);
}
}
}
@ -3993,7 +3993,7 @@ msp430_operands (struct msp430_opcode_s * opcode, char * line)
line = extract_operand (line, l1, sizeof (l1));
res = msp430_srcoperand (&op1, l1, opcode->bin_opcode,
&imm_op, extended_op, TRUE);
&imm_op, extended_op, true);
if (res)
break; /* Error in operand. */
@ -4059,10 +4059,10 @@ msp430_operands (struct msp430_opcode_s * opcode, char * line)
extended |= ((op1.exp.X_add_number >> 16) & 0xf) << 7;
else if (op1.reg || op1.am == 3) /* Not PC relative. */
fix_new_exp (frag_now, where, 6, &(op1.exp), FALSE,
fix_new_exp (frag_now, where, 6, &(op1.exp), false,
BFD_RELOC_MSP430X_ABS20_EXT_SRC);
else
fix_new_exp (frag_now, where, 6, &(op1.exp), FALSE,
fix_new_exp (frag_now, where, 6, &(op1.exp), false,
BFD_RELOC_MSP430X_PCR20_EXT_SRC);
}
@ -4091,10 +4091,10 @@ msp430_operands (struct msp430_opcode_s * opcode, char * line)
{
if (op1.reg || op1.am == 3) /* Not PC relative. */
fix_new_exp (frag_now, where, 2,
&(op1.exp), FALSE, CHECK_RELOC_MSP430 (op1));
&(op1.exp), false, CHECK_RELOC_MSP430 (op1));
else
fix_new_exp (frag_now, where, 2,
&(op1.exp), TRUE, CHECK_RELOC_MSP430_PCREL);
&(op1.exp), true, CHECK_RELOC_MSP430_PCREL);
}
}
}
@ -4174,7 +4174,7 @@ msp430_operands (struct msp430_opcode_s * opcode, char * line)
frag = frag_more (2); /* Instr size is 1 word. */
where = frag - frag_now->fr_literal;
fix_new_exp (frag_now, where, 2,
&exp, TRUE, BFD_RELOC_MSP430_10_PCREL);
&exp, true, BFD_RELOC_MSP430_10_PCREL);
bfd_putl16 ((bfd_vma) bin, frag);
}
@ -4301,30 +4301,30 @@ msp430_operands (struct msp430_opcode_s * opcode, char * line)
if (is_opcode ("nop"))
{
prev_insn_is_nop = TRUE;
prev_insn_is_dint = FALSE;
prev_insn_is_eint = FALSE;
prev_insn_is_nop = true;
prev_insn_is_dint = false;
prev_insn_is_eint = false;
}
else if (this_insn_is_dint || is_dint (opcode->name, bin))
{
prev_insn_is_dint = TRUE;
prev_insn_is_eint = FALSE;
prev_insn_is_nop = FALSE;
prev_insn_is_dint = true;
prev_insn_is_eint = false;
prev_insn_is_nop = false;
check_for_nop |= NOP_CHECK_INTERRUPT;
}
/* NOP is not needed after EINT for 430 ISA. */
else if (target_is_430x () && (this_insn_is_eint || is_eint (opcode->name, bin)))
{
prev_insn_is_eint = TRUE;
prev_insn_is_nop = FALSE;
prev_insn_is_dint = FALSE;
prev_insn_is_eint = true;
prev_insn_is_nop = false;
prev_insn_is_dint = false;
check_for_nop |= NOP_CHECK_INTERRUPT;
}
else
{
prev_insn_is_nop = FALSE;
prev_insn_is_dint = FALSE;
prev_insn_is_eint = FALSE;
prev_insn_is_nop = false;
prev_insn_is_dint = false;
prev_insn_is_eint = false;
}
input_line_pointer = line;
@ -4603,14 +4603,14 @@ md_apply_fix (fixS * fixp, valueT * valuep, segT seg)
}
}
static bfd_boolean
static bool
S_IS_GAS_LOCAL (symbolS * s)
{
const char * name;
unsigned int len;
if (s == NULL)
return FALSE;
return false;
name = S_GET_NAME (s);
len = strlen (name) - 1;
@ -4916,7 +4916,7 @@ md_convert_frag (bfd * abfd ATTRIBUTE_UNUSED,
another fix will be applied to the next word of insn anyway. */
if (hc->tlab == 2)
fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
fragP->fr_offset, TRUE, rela);
fragP->fr_offset, true, rela);
fragP->fr_fix += 2;
}
@ -4960,7 +4960,7 @@ md_convert_frag (bfd * abfd ATTRIBUTE_UNUSED,
/* Now apply fix. */
fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
fragP->fr_offset, TRUE, rela);
fragP->fr_offset, true, rela);
/* Just fixed 2 bytes. */
fragP->fr_fix += 2;
}
@ -5045,15 +5045,15 @@ msp430_relax_frag (segT seg ATTRIBUTE_UNUSED, fragS * fragP,
adjusted. We return FALSE here so that linker relaxation will
work. */
bfd_boolean
bool
msp430_fix_adjustable (struct fix *fixp ATTRIBUTE_UNUSED)
{
/* If the symbol is in a non-code section then it should be OK. */
if (fixp->fx_addsy
&& ((S_GET_SEGMENT (fixp->fx_addsy)->flags & SEC_CODE) == 0))
return TRUE;
return true;
return FALSE;
return false;
}
/* Scan uleb128 subtraction expressions and insert fixups for them.
@ -5152,23 +5152,23 @@ msp430_md_end (void)
subtraction of two same-section symbols cannot be computed by
the assembler. */
bfd_boolean
bool
msp430_allow_local_subtract (expressionS * left,
expressionS * right,
segT section)
{
/* If the symbols are not in a code section then they are OK. */
if ((section->flags & SEC_CODE) == 0)
return TRUE;
return true;
if (S_IS_GAS_LOCAL (left->X_add_symbol) || S_IS_GAS_LOCAL (right->X_add_symbol))
return TRUE;
return true;
if (left->X_add_symbol == right->X_add_symbol)
return TRUE;
return true;
/* We have to assume that there may be instructions between the
two symbols and that relaxation may increase the distance between
them. */
return FALSE;
return false;
}

4
gas/config/tc-msp430.h
View File

@ -127,7 +127,7 @@ extern int msp430_enable_relax;
extern int msp430_enable_polys;
#define tc_fix_adjustable(FIX) msp430_fix_adjustable (FIX)
extern bfd_boolean msp430_fix_adjustable (struct fix *);
extern bool msp430_fix_adjustable (struct fix *);
/* Allow hexadecimal numbers with 'h' suffix. Note that if the number
starts with a letter it will be interpreted as a symbol name not a
@ -146,7 +146,7 @@ extern void msp430_md_end (void);
/* The difference between same-section symbols may be affected by linker
relaxation, so do not resolve such expressions in the assembler. */
#define md_allow_local_subtract(l,r,s) msp430_allow_local_subtract (l, r, s)
extern bfd_boolean msp430_allow_local_subtract (expressionS *, expressionS *, segT);
extern bool msp430_allow_local_subtract (expressionS *, expressionS *, segT);
#define RELOC_EXPANSION_POSSIBLE
#define MAX_RELOC_EXPANSION 2

14
gas/config/tc-mt.c
View File

@ -179,7 +179,7 @@ md_begin (void)
/* Set the machine type. */
bfd_default_set_arch_mach (stdoutput, bfd_arch_mt, mt_mach);
literal_prefix_dollar_hex = TRUE;
literal_prefix_dollar_hex = true;
}
void
@ -438,7 +438,7 @@ md_number_to_chars (char * buf, valueT val, int n)
const char *
md_atof (int type, char * litP, int * sizeP)
{
return ieee_md_atof (type, litP, sizeP, FALSE);
return ieee_md_atof (type, litP, sizeP, false);
}
/* See whether we need to force a relocation into the output file. */
@ -458,7 +458,7 @@ mt_apply_fix (fixS *fixP, valueT *valueP, segT seg)
gas_cgen_md_apply_fix (fixP, valueP, seg);
}
bfd_boolean
bool
mt_fix_adjustable (fixS * fixP)
{
if ((int) fixP->fx_r_type >= (int) BFD_RELOC_UNUSED)
@ -472,14 +472,14 @@ mt_fix_adjustable (fixS * fixP)
}
if (fixP->fx_addsy == NULL)
return TRUE;
return true;
/* Prevent all adjustments to global symbols. */
if (S_IS_EXTERNAL (fixP->fx_addsy))
return FALSE;
return false;
if (S_IS_WEAK (fixP->fx_addsy))
return FALSE;
return false;
return 1;
return true;
}

2
gas/config/tc-mt.h
View File

@ -61,5 +61,5 @@ extern void gas_cgen_md_operand (expressionS *);
extern int mt_force_relocation (struct fix *);
#define tc_fix_adjustable(fixP) mt_fix_adjustable (fixP)
extern bfd_boolean mt_fix_adjustable (struct fix *);
extern bool mt_fix_adjustable (struct fix *);

550
gas/config/tc-nds32.c
View File

File diff suppressed because it is too large Load Diff

6
gas/config/tc-nds32.h
View File

@ -71,7 +71,7 @@ extern const char * nds32_target_format (void);
/* expr.c */
extern int nds32_parse_name (char const *, expressionS *, enum expr_mode, char *);
extern bfd_boolean nds32_allow_local_subtract (expressionS *, expressionS *, segT);
extern bool nds32_allow_local_subtract (expressionS *, expressionS *, segT);
#define md_parse_name(name, exprP, mode, nextcharP) \
nds32_parse_name (name, exprP, mode, nextcharP)
#define md_allow_local_subtract(lhs,rhs,sect) nds32_allow_local_subtract (lhs, rhs, sect)
@ -81,7 +81,7 @@ extern bfd_boolean nds32_allow_local_subtract (expressionS *, expressionS *, seg
/* write.c. */
extern long nds32_pcrel_from_section (struct fix *, segT);
extern bfd_boolean nds32_fix_adjustable (struct fix *);
extern bool nds32_fix_adjustable (struct fix *);
extern void nds32_frob_file (void);
extern void nds32_post_relax_hook (void);
extern void nds32_frob_file_before_fix (void);
@ -264,7 +264,7 @@ typedef struct nds32_cond_field
int offset;
int bitpos; /* Register position. */
int bitmask; /* Number of register bits. */
bfd_boolean signed_extend;
bool signed_extend;
} nds32_cond_field_t;
/* The max relaxation pattern is 20-bytes including the nop. */

60
gas/config/tc-nios2.c
View File

@ -103,12 +103,12 @@ static struct
and macro expansions generate a warning.
.set at -> noat = 0, assembly code using at warn but macro expansions
do not generate warnings. */
bfd_boolean noat;
bool noat;
/* .set nobreak -> nobreak = 1 allows assembly code to use ba,bt without
warning.
.set break -> nobreak = 0, assembly code using ba,bt warns. */
bfd_boolean nobreak;
bool nobreak;
/* .cmd line option -relax-all allows all branches and calls to be replaced
with longer versions.
@ -117,7 +117,7 @@ static struct
a section. */
relax_optionT relax;
} nios2_as_options = {FALSE, FALSE, relax_section};
} nios2_as_options = {false, false, relax_section};
typedef struct nios2_insn_reloc
@ -391,7 +391,7 @@ nios2_align (int log_size, const char *pfill, symbolS *label)
if (label != NULL && !switched_seg_p)
{
symbolS *sym;
int label_seen = FALSE;
int label_seen = false;
struct frag *old_frag;
valueT old_value;
valueT new_value;
@ -417,7 +417,7 @@ nios2_align (int log_size, const char *pfill, symbolS *label)
if (symbol_get_frag (sym) == old_frag
&& S_GET_VALUE (sym) == old_value)
{
label_seen = TRUE;
label_seen = true;
symbol_set_frag (sym, frag_now);
S_SET_VALUE (sym, new_value);
}
@ -579,17 +579,17 @@ s_nios2_set (int equiv)
SKIP_WHITESPACE ();
if (is_end_of_line[(unsigned char) *input_line_pointer])
{
bfd_boolean done = TRUE;
bool done = true;
*endline = 0;
if (!strcmp (directive, "noat"))
nios2_as_options.noat = TRUE;
nios2_as_options.noat = true;
else if (!strcmp (directive, "at"))
nios2_as_options.noat = FALSE;
nios2_as_options.noat = false;
else if (!strcmp (directive, "nobreak"))
nios2_as_options.nobreak = TRUE;
nios2_as_options.nobreak = true;
else if (!strcmp (directive, "break"))
nios2_as_options.nobreak = FALSE;
nios2_as_options.nobreak = false;
else if (!strcmp (directive, "norelax"))
nios2_as_options.relax = relax_none;
else if (!strcmp (directive, "relaxsection"))
@ -597,7 +597,7 @@ s_nios2_set (int equiv)
else if (!strcmp (directive, "relaxall"))
nios2_as_options.relax = relax_all;
else
done = FALSE;
done = false;
if (done)
{
@ -789,7 +789,7 @@ nios2_relax_frag (segT segment, fragS *fragp, long stretch)
fragS *sym_frag = symbol_get_frag (symbolp);
offsetT offset;
int n;
bfd_boolean is_cdx = FALSE;
bool is_cdx = false;
target += S_GET_VALUE (symbolp);
@ -809,11 +809,11 @@ nios2_relax_frag (segT segment, fragS *fragp, long stretch)
if (IS_CDXBRANCH (subtype) && IS_UBRANCH (subtype)
&& offset >= -1024 && offset < 1024)
/* PC-relative CDX branch with 11-bit offset. */
is_cdx = TRUE;
is_cdx = true;
else if (IS_CDXBRANCH (subtype) && IS_CBRANCH (subtype)
&& offset >= -128 && offset < 128)
/* PC-relative CDX branch with 8-bit offset. */
is_cdx = TRUE;
is_cdx = true;
else if (offset >= -32768 && offset < 32768)
/* Fits in PC-relative branch. */
n = 0;
@ -883,7 +883,7 @@ md_convert_frag (bfd *headers ATTRIBUTE_UNUSED, segT segment ATTRIBUTE_UNUSED,
unsigned int addend_mask, addi_mask, op;
offsetT addend, remainder;
int i;
bfd_boolean is_r2 = (bfd_get_mach (stdoutput) == bfd_mach_nios2r2);
bool is_r2 = (bfd_get_mach (stdoutput) == bfd_mach_nios2r2);
/* If this is a CDX branch we're not relaxing, just generate the fixup. */
if (IS_CDXBRANCH (subtype))
@ -1100,7 +1100,7 @@ md_convert_frag (bfd *headers ATTRIBUTE_UNUSED, segT segment ATTRIBUTE_UNUSED,
/** Fixups and overflow checking. */
/* Check a fixup for overflow. */
static bfd_boolean
static bool
nios2_check_overflow (valueT fixup, reloc_howto_type *howto)
{
/* If there is a rightshift, check that the low-order bits are
@ -1109,7 +1109,7 @@ nios2_check_overflow (valueT fixup, reloc_howto_type *howto)
{
if ((~(~((valueT) 0) << howto->rightshift) & fixup)
&& howto->complain_on_overflow != complain_overflow_dont)
return TRUE;
return true;
fixup = ((signed)fixup) >> howto->rightshift;
}
@ -1121,31 +1121,31 @@ nios2_check_overflow (valueT fixup, reloc_howto_type *howto)
case complain_overflow_bitfield:
if ((fixup >> howto->bitsize) != 0
&& ((signed) fixup >> howto->bitsize) != -1)
return TRUE;
return true;
break;
case complain_overflow_signed:
if ((fixup & 0x80000000) > 0)
{
/* Check for negative overflow. */
if ((signed) fixup < (signed) (~0U << (howto->bitsize - 1)))
return TRUE;
return true;
}
else
{
/* Check for positive overflow. */
if (fixup >= ((unsigned) 1 << (howto->bitsize - 1)))
return TRUE;
return true;
}
break;
case complain_overflow_unsigned:
if ((fixup >> howto->bitsize) != 0)
return TRUE;
return true;
break;
default:
as_bad (_("error checking for overflow - broken assembler"));
break;
}
return FALSE;
return false;
}
/* Emit diagnostic for fixup overflow. */
@ -3099,7 +3099,7 @@ nios2_parse_args (nios2_insn_infoS *insn, char *argstr,
int i;
p = argstr;
i = 0;
bfd_boolean terminate = FALSE;
bool terminate = false;
/* This rest of this function is it too fragile and it mostly works,
therefore special case this one. */
@ -3136,7 +3136,7 @@ nios2_parse_args (nios2_insn_infoS *insn, char *argstr,
}
if (*parsestr == '\0' || (p != NULL && *p == '\0'))
terminate = TRUE;
terminate = true;
++i;
}
@ -3350,7 +3350,7 @@ output_ubranch (nios2_insn_infoS *insn)
symbolS *symp = reloc->reloc_expression.X_add_symbol;
offsetT offset = reloc->reloc_expression.X_add_number;
char *f;
bfd_boolean is_cdx = (insn->insn_nios2_opcode->size == 2);
bool is_cdx = (insn->insn_nios2_opcode->size == 2);
/* Tag dwarf2 debug info to the address at the start of the insn.
We must do it before frag_var() below closes off the frag. */
@ -3382,7 +3382,7 @@ output_cbranch (nios2_insn_infoS *insn)
symbolS *symp = reloc->reloc_expression.X_add_symbol;
offsetT offset = reloc->reloc_expression.X_add_number;
char *f;
bfd_boolean is_cdx = (insn->insn_nios2_opcode->size == 2);
bool is_cdx = (insn->insn_nios2_opcode->size == 2);
/* Tag dwarf2 debug info to the address at the start of the insn.
We must do it before frag_var() below closes off the frag. */
@ -3640,8 +3640,8 @@ md_begin (void)
as_fatal (_("duplicate %s"), nios2_ps_insn_info_structs[i].pseudo_insn);
/* Assembler option defaults. */
nios2_as_options.noat = FALSE;
nios2_as_options.nobreak = FALSE;
nios2_as_options.noat = false;
nios2_as_options.nobreak = false;
/* Initialize the alignment data. */
nios2_current_align_seg = now_seg;
@ -3660,7 +3660,7 @@ md_assemble (char *op_str)
unsigned long saved_pinfo = 0;
nios2_insn_infoS thisinsn;
nios2_insn_infoS *insn = &thisinsn;
bfd_boolean ps_error = FALSE;
bool ps_error = false;
/* Make sure we are aligned on an appropriate boundary. */
if (nios2_current_align < nios2_min_align)
@ -3710,7 +3710,7 @@ md_assemble (char *op_str)
{
ps_insn = nios2_translate_pseudo_insn (insn);
if (!ps_insn)
ps_error = TRUE;
ps_error = true;
}
/* If we found invalid pseudo-instruction syntax, the error's already

2
gas/config/tc-ns32k.c
View File

@ -1917,7 +1917,7 @@ md_begin (void)
const char *
md_atof (int type, char *litP, int *sizeP)
{
return ieee_md_atof (type, litP, sizeP, FALSE);
return ieee_md_atof (type, litP, sizeP, false);
}
int

12
gas/config/tc-or1k.c
View File

@ -83,11 +83,11 @@ ignore_pseudo (int val ATTRIBUTE_UNUSED)
discard_rest_of_line ();
}
static bfd_boolean nodelay = FALSE;
static bool nodelay = false;
static void
s_nodelay (int val ATTRIBUTE_UNUSED)
{
nodelay = TRUE;
nodelay = true;
}
const char or1k_comment_chars [] = ";#";
@ -278,18 +278,18 @@ md_number_to_chars (char * buf, valueT val, int n)
const char *
md_atof (int type, char * litP, int * sizeP)
{
return ieee_md_atof (type, litP, sizeP, TRUE);
return ieee_md_atof (type, litP, sizeP, true);
}
bfd_boolean
bool
or1k_fix_adjustable (fixS * fixP)
{
/* We need the symbol name for the VTABLE entries. */
if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
|| fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
return FALSE;
return false;
return TRUE;
return true;
}
#define GOT_NAME "_GLOBAL_OFFSET_TABLE_"

2
gas/config/tc-or1k.h
View File

@ -46,7 +46,7 @@ extern const char or1k_comment_chars [];
#define md_apply_fix or1k_apply_fix
extern void or1k_apply_fix (struct fix *, valueT *, segT);
extern bfd_boolean or1k_fix_adjustable (struct fix *);
extern bool or1k_fix_adjustable (struct fix *);
#define tc_fix_adjustable(FIX) or1k_fix_adjustable (FIX)
/* Call md_pcrel_from_section(), not md_pcrel_from(). */

8
gas/config/tc-pdp11.c
View File

@ -484,7 +484,7 @@ parse_op_no_deferred (char *str, struct pdp11_code *operand)
str = parse_expression (str + 1, operand);
if (operand->error)
return str;
operand->additional = TRUE;
operand->additional = true;
operand->word = operand->reloc.exp.X_add_number;
switch (operand->reloc.exp.X_op)
{
@ -566,7 +566,7 @@ parse_op_no_deferred (char *str, struct pdp11_code *operand)
}
str++;
operand->additional = TRUE;
operand->additional = true;
operand->code |= 060;
switch (operand->reloc.exp.X_op)
{
@ -728,10 +728,10 @@ md_assemble (char *instruction_string)
insn.code = op->opcode;
insn.reloc.type = BFD_RELOC_NONE;
op1.error = NULL;
op1.additional = FALSE;
op1.additional = false;
op1.reloc.type = BFD_RELOC_NONE;
op2.error = NULL;
op2.additional = FALSE;
op2.additional = false;
op2.reloc.type = BFD_RELOC_NONE;
str = p;

118
gas/config/tc-ppc.c
View File

@ -46,7 +46,7 @@ static int set_target_endian = 0;
/* Whether to use user friendly register names. */
#ifndef TARGET_REG_NAMES_P
#define TARGET_REG_NAMES_P FALSE
#define TARGET_REG_NAMES_P false
#endif
/* Macros for calculating LO, HI, HA, HIGHER, HIGHERA, HIGHEST,
@ -83,7 +83,7 @@ static int set_target_endian = 0;
applied to constants. */
#define REPORT_OVERFLOW_HI 0
static bfd_boolean reg_names_p = TARGET_REG_NAMES_P;
static bool reg_names_p = TARGET_REG_NAMES_P;
static void ppc_macro (char *, const struct powerpc_macro *);
static void ppc_byte (int);
@ -816,7 +816,7 @@ reg_name_search (const struct pd_reg *regs, int regcount, const char *name)
* original state.
*/
static bfd_boolean
static bool
register_name (expressionS *expressionP)
{
const struct pd_reg *reg;
@ -830,7 +830,7 @@ register_name (expressionS *expressionP)
name = ++input_line_pointer;
else if (!reg_names_p || !ISALPHA (name[0]))
return FALSE;
return false;
c = get_symbol_name (&name);
reg = reg_name_search (pre_defined_registers, REG_NAME_CNT, name);
@ -848,12 +848,12 @@ register_name (expressionS *expressionP)
/* Make the rest nice. */
expressionP->X_add_symbol = NULL;
expressionP->X_op_symbol = NULL;
return TRUE;
return true;
}
/* Reset the line as if we had not done anything. */
input_line_pointer = start;
return FALSE;
return false;
}
/* This function is called for each symbol seen in an expression. It
@ -861,7 +861,7 @@ register_name (expressionS *expressionP)
to use for condition codes. */
/* Whether to do the special parsing. */
static bfd_boolean cr_operand;
static bool cr_operand;
/* Names to recognize in a condition code. This table is sorted. */
static const struct pd_reg cr_names[] =
@ -980,12 +980,12 @@ static flagword ppc_flags = 0;
/* Whether this is Solaris or not. */
#ifdef TARGET_SOLARIS_COMMENT
#define SOLARIS_P TRUE
#define SOLARIS_P true
#else
#define SOLARIS_P FALSE
#define SOLARIS_P false
#endif
static bfd_boolean msolaris = SOLARIS_P;
static bool msolaris = SOLARIS_P;
#endif
#ifdef OBJ_XCOFF
@ -1006,7 +1006,7 @@ struct ppc_xcoff_section ppc_xcoff_tbss_section;
/* Return true if the ppc_xcoff_section structure is already
initialized. */
static bfd_boolean
static bool
ppc_xcoff_section_is_initialized (struct ppc_xcoff_section *section)
{
return section->segment != NULL;
@ -1017,7 +1017,7 @@ ppc_xcoff_section_is_initialized (struct ppc_xcoff_section *section)
and .tdata. These symbols won't be output. */
static void
ppc_init_xcoff_section (struct ppc_xcoff_section *s, segT seg,
bfd_boolean need_dummy)
bool need_dummy)
{
s->segment = seg;
s->next_subsegment = 2;
@ -1194,10 +1194,10 @@ md_parse_option (int c, const char *arg)
}
else if (strcmp (arg, "regnames") == 0)
reg_names_p = TRUE;
reg_names_p = true;
else if (strcmp (arg, "no-regnames") == 0)
reg_names_p = FALSE;
reg_names_p = false;
#ifdef OBJ_ELF
/* -mrelocatable/-mrelocatable-lib -- warn about initializations
@ -1236,13 +1236,13 @@ md_parse_option (int c, const char *arg)
else if (strcmp (arg, "solaris") == 0)
{
msolaris = TRUE;
msolaris = true;
ppc_comment_chars = ppc_solaris_comment_chars;
}
else if (strcmp (arg, "no-solaris") == 0)
{
msolaris = FALSE;
msolaris = false;
ppc_comment_chars = ppc_eabi_comment_chars;
}
else if (strcmp (arg, "spe2") == 0)
@ -1545,7 +1545,7 @@ ppc_target_format (void)
/* Validate one entry in powerpc_opcodes[] or vle_opcodes[].
Return TRUE if there's a problem, otherwise FALSE. */
static bfd_boolean
static bool
insn_validate (const struct powerpc_opcode *op)
{
const unsigned char *o;
@ -1555,17 +1555,17 @@ insn_validate (const struct powerpc_opcode *op)
if ((op->opcode & omask) != op->opcode)
{
as_bad (_("mask trims opcode bits for %s"), op->name);
return TRUE;
return true;
}
/* The operands must not overlap the opcode or each other. */
for (o = op->operands; *o; ++o)
{
bfd_boolean optional = FALSE;
bool optional = false;
if (*o >= num_powerpc_operands)
{
as_bad (_("operand index error for %s"), op->name);
return TRUE;
return true;
}
else
{
@ -1592,20 +1592,20 @@ insn_validate (const struct powerpc_opcode *op)
{
as_bad (_("operand %d overlap in %s"),
(int) (o - op->operands), op->name);
return TRUE;
return true;
}
omask |= mask;
if ((operand->flags & PPC_OPERAND_OPTIONAL) != 0)
optional = TRUE;
optional = true;
else if (optional)
{
as_bad (_("non-optional operand %d follows optional operand in %s"),
(int) (o - op->operands), op->name);
return TRUE;
return true;
}
}
}
return FALSE;
return false;
}
/* Insert opcodes and macros into hash tables. Called at startup and
@ -1618,7 +1618,7 @@ ppc_setup_opcodes (void)
const struct powerpc_opcode *op_end;
const struct powerpc_macro *macro;
const struct powerpc_macro *macro_end;
bfd_boolean bad_insn = FALSE;
bool bad_insn = false;
if (ppc_hash != NULL)
htab_delete (ppc_hash);
@ -1650,7 +1650,7 @@ ppc_setup_opcodes (void)
if (mask != right_bit)
{
as_bad (_("powerpc_operands[%d].bitm invalid"), i);
bad_insn = TRUE;
bad_insn = true;
}
for (j = i + 1; j < num_powerpc_operands; ++j)
if (memcmp (&powerpc_operands[i], &powerpc_operands[j],
@ -1658,7 +1658,7 @@ ppc_setup_opcodes (void)
{
as_bad (_("powerpc_operands[%d] duplicates powerpc_operands[%d]"),
j, i);
bad_insn = TRUE;
bad_insn = true;
}
}
}
@ -1683,20 +1683,20 @@ ppc_setup_opcodes (void)
&& new_opcode < PPC_OP (op[-1].opcode))
{
as_bad (_("major opcode is not sorted for %s"), op->name);
bad_insn = TRUE;
bad_insn = true;
}
if ((op->flags & PPC_OPCODE_VLE) != 0)
{
as_bad (_("%s is enabled by vle flag"), op->name);
bad_insn = TRUE;
bad_insn = true;
}
if (PPC_OP (op->opcode) != 4
&& PPC_OP (op->opcode) != 31
&& (op->deprecated & PPC_OPCODE_VLE) == 0)
{
as_bad (_("%s not disabled by vle flag"), op->name);
bad_insn = TRUE;
bad_insn = true;
}
bad_insn |= insn_validate (op);
}
@ -1706,7 +1706,7 @@ ppc_setup_opcodes (void)
&& str_hash_insert (ppc_hash, op->name, op, 0) != NULL)
{
as_bad (_("duplicate %s"), op->name);
bad_insn = TRUE;
bad_insn = true;
}
}
@ -1734,7 +1734,7 @@ ppc_setup_opcodes (void)
&& new_opcode < PPC_PREFIX_SEG (op[-1].opcode))
{
as_bad (_("major opcode is not sorted for %s"), op->name);
bad_insn = TRUE;
bad_insn = true;
}
bad_insn |= insn_validate (op);
}
@ -1744,7 +1744,7 @@ ppc_setup_opcodes (void)
&& str_hash_insert (ppc_hash, op->name, op, 0) != NULL)
{
as_bad (_("duplicate %s"), op->name);
bad_insn = TRUE;
bad_insn = true;
}
}
@ -1772,7 +1772,7 @@ ppc_setup_opcodes (void)
&& new_seg < VLE_OP_TO_SEG (VLE_OP (op[-1].opcode, op[-1].mask)))
{
as_bad (_("major opcode is not sorted for %s"), op->name);
bad_insn = TRUE;
bad_insn = true;
}
bad_insn |= insn_validate (op);
@ -1783,7 +1783,7 @@ ppc_setup_opcodes (void)
&& str_hash_insert (ppc_hash, op->name, op, 0) != NULL)
{
as_bad (_("duplicate %s"), op->name);
bad_insn = TRUE;
bad_insn = true;
}
}
@ -1810,7 +1810,7 @@ ppc_setup_opcodes (void)
if (new_seg < old_seg)
{
as_bad (_("major opcode is not sorted for %s"), op->name);
bad_insn = TRUE;
bad_insn = true;
}
}
@ -1822,7 +1822,7 @@ ppc_setup_opcodes (void)
&& str_hash_insert (ppc_hash, op->name, op, 0) != NULL)
{
as_bad (_("duplicate %s"), op->name);
bad_insn = TRUE;
bad_insn = true;
}
}
@ -1840,7 +1840,7 @@ ppc_setup_opcodes (void)
&& str_hash_insert (ppc_macro_hash, macro->name, macro, 0) != NULL)
{
as_bad (_("duplicate %s"), macro->name);
bad_insn = TRUE;
bad_insn = true;
}
if (bad_insn)
@ -1881,9 +1881,9 @@ md_begin (void)
/* Create XCOFF sections with .text in first, as it's creating dummy symbols
to serve as initial csects. This forces the text csects to precede the
data csects. These symbols will not be output. */
ppc_init_xcoff_section (&ppc_xcoff_text_section, text_section, TRUE);
ppc_init_xcoff_section (&ppc_xcoff_data_section, data_section, TRUE);
ppc_init_xcoff_section (&ppc_xcoff_bss_section, bss_section, FALSE);
ppc_init_xcoff_section (&ppc_xcoff_text_section, text_section, true);
ppc_init_xcoff_section (&ppc_xcoff_data_section, data_section, true);
ppc_init_xcoff_section (&ppc_xcoff_bss_section, bss_section, false);
#endif
}
@ -2930,10 +2930,10 @@ struct ppc_fixup
pc-relative in PC_RELATIVE. */
static unsigned int
fixup_size (bfd_reloc_code_real_type reloc, bfd_boolean *pc_relative)
fixup_size (bfd_reloc_code_real_type reloc, bool *pc_relative)
{
unsigned int size = 0;
bfd_boolean pcrel = FALSE;
bool pcrel = false;
switch (reloc)
{
@ -3077,7 +3077,7 @@ fixup_size (bfd_reloc_code_real_type reloc, bfd_boolean *pc_relative)
#endif
case BFD_RELOC_PPC_VLE_REL8:
size = 2;
pcrel = TRUE;
pcrel = true;
break;
case BFD_RELOC_32:
@ -3137,7 +3137,7 @@ fixup_size (bfd_reloc_code_real_type reloc, bfd_boolean *pc_relative)
case BFD_RELOC_PPC_VLE_REL15:
case BFD_RELOC_PPC_VLE_REL24:
size = 4;
pcrel = TRUE;
pcrel = true;
break;
#ifndef OBJ_XCOFF
@ -3182,7 +3182,7 @@ fixup_size (bfd_reloc_code_real_type reloc, bfd_boolean *pc_relative)
case BFD_RELOC_PPC64_PCREL34:
case BFD_RELOC_PPC64_PLT_PCREL34:
size = 8;
pcrel = TRUE;
pcrel = true;
break;
default:
@ -3430,11 +3430,11 @@ md_assemble (char *str)
if (((operand->flags & PPC_OPERAND_CR_REG) != 0)
|| (operand->flags & PPC_OPERAND_CR_BIT) != 0)
{
cr_operand = TRUE;
cr_operand = true;
lex_type['%'] |= LEX_BEGIN_NAME;
}
expression (&ex);
cr_operand = FALSE;
cr_operand = false;
lex_type['%'] = save_lex;
}
@ -4071,7 +4071,7 @@ md_assemble (char *str)
fixS *fixP;
if (fixups[i].reloc != BFD_RELOC_NONE)
{
bfd_boolean pcrel;
bool pcrel;
unsigned int size = fixup_size (fixups[i].reloc, &pcrel);
int offset = target_big_endian ? (insn_length - size) : 0;
@ -4257,7 +4257,7 @@ ppc_byte (int ignore ATTRIBUTE_UNUSED)
/* This is set if we are creating a .stabx symbol, since we don't want
to handle symbol suffixes for such symbols. */
static bfd_boolean ppc_stab_symbol;
static bool ppc_stab_symbol;
/* The .comm and .lcomm pseudo-ops for XCOFF. XCOFF puts common
symbols in the .bss segment as though they were local common
@ -4379,7 +4379,7 @@ ppc_comm (int lcomm)
if (!ppc_xcoff_section_is_initialized (section))
{
ppc_init_xcoff_section (section,
subseg_new (".tbss", 0), FALSE);
subseg_new (".tbss", 0), false);
bfd_set_section_flags (section->segment,
SEC_ALLOC | SEC_THREAD_LOCAL);
seg_info (section->segment)->bss = 1;
@ -4537,7 +4537,7 @@ ppc_change_csect (symbolS *sym, offsetT align)
if (!ppc_xcoff_section_is_initialized (section))
{
ppc_init_xcoff_section (section, subseg_new (".tdata", 0),
TRUE);
true);
bfd_set_section_flags (section->segment, SEC_ALLOC
| SEC_LOAD | SEC_RELOC | SEC_DATA
| SEC_THREAD_LOCAL);
@ -4549,7 +4549,7 @@ ppc_change_csect (symbolS *sym, offsetT align)
if (!ppc_xcoff_section_is_initialized (section))
{
ppc_init_xcoff_section (section, subseg_new (".tbss", 0),
FALSE);
false);
bfd_set_section_flags (section->segment, SEC_ALLOC |
SEC_THREAD_LOCAL);
seg_info (section->segment)->bss = 1;
@ -4879,7 +4879,7 @@ ppc_ref (int ignore ATTRIBUTE_UNUSED)
c = get_symbol_name (&name);
fix_at_start (symbol_get_frag (ppc_current_csect), 0,
symbol_find_or_make (name), 0, FALSE, BFD_RELOC_NONE);
symbol_find_or_make (name), 0, false, BFD_RELOC_NONE);
*input_line_pointer = c;
SKIP_WHITESPACE_AFTER_NAME ();
@ -4955,9 +4955,9 @@ ppc_stabx (int ignore ATTRIBUTE_UNUSED)
}
++input_line_pointer;
ppc_stab_symbol = TRUE;
ppc_stab_symbol = true;
sym = symbol_make (name);
ppc_stab_symbol = FALSE;
ppc_stab_symbol = false;
symbol_get_tc (sym)->real_name = name;
@ -5836,7 +5836,7 @@ ppc_symbol_new_hook (symbolS *sym)
seen. It tells ppc_adjust_symtab whether it needs to look through
the symbols. */
static bfd_boolean ppc_saw_abs;
static bool ppc_saw_abs;
/* Change the name of a symbol just before writing it out. Set the
real name if the .rename pseudo-op was used. Otherwise, remove any
@ -5979,7 +5979,7 @@ ppc_frob_symbol (symbolS *sym)
{
/* This is an absolute symbol. The csect will be created by
ppc_adjust_symtab. */
ppc_saw_abs = TRUE;
ppc_saw_abs = true;
a->x_csect.x_smtyp = XTY_LD;
if (symbol_get_tc (sym)->symbol_class == -1)
symbol_get_tc (sym)->symbol_class = XMC_XO;
@ -6157,7 +6157,7 @@ ppc_adjust_symtab (void)
coffsymbol (symbol_get_bfdsym (sym))->native[i].fix_scnlen = 1;
}
ppc_saw_abs = FALSE;
ppc_saw_abs = false;
}
/* Set the VMA for a section. This is called on all the sections in

46
gas/config/tc-pru.c
View File

@ -66,14 +66,14 @@ struct pru_opt_s
{
/* -mno-link-relax / -mlink-relax: generate (or not)
relocations for linker relaxation. */
bfd_boolean link_relax;
bool link_relax;
/* -mno-warn-regname-label: do not output a warning that a label name
matches a register name. */
bfd_boolean warn_regname_label;
bool warn_regname_label;
};
static struct pru_opt_s pru_opt = { TRUE, TRUE };
static struct pru_opt_s pru_opt = { true, true };
const char *md_shortopts = "r";
@ -188,7 +188,7 @@ md_number_to_chars (char *buf, valueT val, int n)
const char *
md_atof (int type, char *litP, int *sizeP)
{
return ieee_md_atof (type, litP, sizeP, FALSE);
return ieee_md_atof (type, litP, sizeP, false);
}
/* Return true if STR starts with PREFIX, which should be a string literal. */
@ -246,7 +246,7 @@ pru_align (int log_size, const char *pfill, symbolS *label)
if (label != NULL && !switched_seg_p)
{
symbolS *sym;
int label_seen = FALSE;
int label_seen = false;
struct frag *old_frag;
valueT old_value;
valueT new_value;
@ -272,7 +272,7 @@ pru_align (int log_size, const char *pfill, symbolS *label)
if (symbol_get_frag (sym) == old_frag
&& S_GET_VALUE (sym) == old_value)
{
label_seen = TRUE;
label_seen = true;
symbol_set_frag (sym, frag_now);
S_SET_VALUE (sym, new_value);
}
@ -425,13 +425,13 @@ s_pru_set (int equiv)
SKIP_WHITESPACE ();
if (is_end_of_line[(unsigned char) *input_line_pointer])
{
bfd_boolean done = TRUE;
bool done = true;
*endline = 0;
if (!strcmp (directive, "no_warn_regname_label"))
pru_opt.warn_regname_label = FALSE;
pru_opt.warn_regname_label = false;
else
done = FALSE;
done = false;
if (done)
{
@ -491,7 +491,7 @@ md_convert_frag (bfd *headers ATTRIBUTE_UNUSED, segT segment ATTRIBUTE_UNUSED,
}
static bfd_boolean
static bool
relaxable_section (asection *sec)
{
return ((sec->flags & SEC_DEBUGGING) == 0
@ -1404,7 +1404,7 @@ pru_parse_args (pru_insn_infoS *insn ATTRIBUTE_UNUSED, char *argstr,
int i;
p = argstr;
i = 0;
bfd_boolean terminate = FALSE;
bool terminate = false;
/* This rest of this function is it too fragile and it mostly works,
therefore special case this one. */
@ -1439,7 +1439,7 @@ pru_parse_args (pru_insn_infoS *insn ATTRIBUTE_UNUSED, char *argstr,
}
if (*parsestr == '\0' || (p != NULL && *p == '\0'))
terminate = TRUE;
terminate = true;
++i;
}
@ -1516,13 +1516,13 @@ md_parse_option (int c, const char *arg ATTRIBUTE_UNUSED)
pru_mode = PRU_MODE_TEST;
break;
case OPTION_LINK_RELAX:
pru_opt.link_relax = TRUE;
pru_opt.link_relax = true;
break;
case OPTION_NO_LINK_RELAX:
pru_opt.link_relax = FALSE;
pru_opt.link_relax = false;
break;
case OPTION_NO_WARN_REGNAME_LABEL:
pru_opt.warn_regname_label = FALSE;
pru_opt.warn_regname_label = false;
break;
default:
return 0;
@ -1835,7 +1835,7 @@ skip_space (char *s)
int
pru_parse_cons_expression (expressionS *exp, int nbytes)
{
int is_pmem = FALSE;
int is_pmem = false;
char *tmp;
tmp = input_line_pointer = skip_space (input_line_pointer);
@ -1852,7 +1852,7 @@ pru_parse_cons_expression (expressionS *exp, int nbytes)
if (*input_line_pointer == '(')
{
input_line_pointer = skip_space (input_line_pointer + 1);
is_pmem = TRUE;
is_pmem = true;
expression (exp);
if (*input_line_pointer == ')')
@ -1860,7 +1860,7 @@ pru_parse_cons_expression (expressionS *exp, int nbytes)
else
{
as_bad (_("`)' required"));
is_pmem = FALSE;
is_pmem = false;
}
return is_pmem;
@ -1933,24 +1933,24 @@ pru_frame_initial_instructions (void)
cfi_add_CFA_def_cfa (fp_regno, 0);
}
bfd_boolean
bool
pru_allow_local_subtract (expressionS * left,
expressionS * right,
segT section)
{
/* If we are not in relaxation mode, subtraction is OK. */
if (!linkrelax)
return TRUE;
return true;
/* If the symbols are not in a code section then they are OK. */
if ((section->flags & SEC_CODE) == 0)
return TRUE;
return true;
if (left->X_add_symbol == right->X_add_symbol)
return TRUE;
return true;
/* We have to assume that there may be instructions between the
two symbols and that relaxation may increase the distance between
them. */
return FALSE;
return false;
}

3
gas/config/tc-pru.h
View File

@ -154,7 +154,6 @@ extern void pru_frame_initial_instructions (void);
/* The difference between same-section symbols may be affected by linker
relaxation, so do not resolve such expressions in the assembler. */
#define md_allow_local_subtract(l,r,s) pru_allow_local_subtract (l, r, s)
extern bfd_boolean pru_allow_local_subtract (expressionS *, expressionS *,
segT);
extern bool pru_allow_local_subtract (expressionS *, expressionS *, segT);
#endif /* __TC_PRU__ */

228
gas/config/tc-riscv.c
View File

@ -176,7 +176,7 @@ static enum riscv_spec_class default_priv_spec = PRIV_SPEC_CLASS_NONE;
static unsigned xlen = 0; /* The width of an x-register. */
static unsigned abi_xlen = 0; /* The width of a pointer in the ABI. */
static bfd_boolean rve_abi = FALSE;
static bool rve_abi = false;
enum float_abi
{
FLOAT_ABI_DEFAULT = -1,
@ -280,7 +280,7 @@ static struct riscv_set_options riscv_opts =
};
static void
riscv_set_rvc (bfd_boolean rvc_value)
riscv_set_rvc (bool rvc_value)
{
if (rvc_value)
elf_flags |= EF_RISCV_RVC;
@ -289,25 +289,25 @@ riscv_set_rvc (bfd_boolean rvc_value)
}
static void
riscv_set_rve (bfd_boolean rve_value)
riscv_set_rve (bool rve_value)
{
riscv_opts.rve = rve_value;
}
static riscv_subset_list_t riscv_subsets;
static bfd_boolean
static bool
riscv_subset_supports (const char *feature)
{
struct riscv_subset_t *subset;
if (riscv_opts.rvc && (strcasecmp (feature, "c") == 0))
return TRUE;
return true;
return riscv_lookup_subset (&riscv_subsets, feature, &subset);
}
static bfd_boolean
static bool
riscv_multi_subset_supports (enum riscv_insn_class insn_class)
{
switch (insn_class)
@ -345,7 +345,7 @@ riscv_multi_subset_supports (enum riscv_insn_class insn_class)
default:
as_fatal ("internal: unreachable");
return FALSE;
return false;
}
}
@ -419,10 +419,10 @@ riscv_set_arch (const char *s)
}
/* Indicate -mabi option is explictly set. */
static bfd_boolean explicit_mabi = FALSE;
static bool explicit_mabi = false;
static void
riscv_set_abi (unsigned new_xlen, enum float_abi new_float_abi, bfd_boolean rve)
riscv_set_abi (unsigned new_xlen, enum float_abi new_float_abi, bool rve)
{
abi_xlen = new_xlen;
float_abi = new_float_abi;
@ -438,11 +438,11 @@ riscv_set_abi_by_arch (void)
if (!explicit_mabi)
{
if (riscv_subset_supports ("q"))
riscv_set_abi (xlen, FLOAT_ABI_QUAD, FALSE);
riscv_set_abi (xlen, FLOAT_ABI_QUAD, false);
else if (riscv_subset_supports ("d"))
riscv_set_abi (xlen, FLOAT_ABI_DOUBLE, FALSE);
riscv_set_abi (xlen, FLOAT_ABI_DOUBLE, false);
else
riscv_set_abi (xlen, FLOAT_ABI_SOFT, FALSE);
riscv_set_abi (xlen, FLOAT_ABI_SOFT, false);
}
else
{
@ -493,13 +493,13 @@ const char EXP_CHARS[] = "eE";
const char FLT_CHARS[] = "rRsSfFdDxXpP";
/* Indicate we are already assemble any instructions or not. */
static bfd_boolean start_assemble = FALSE;
static bool start_assemble = false;
/* Indicate ELF attributes are explicitly set. */
static bfd_boolean explicit_attr = FALSE;
static bool explicit_attr = false;
/* Indicate CSR or priv instructions are explicitly used. */
static bfd_boolean explicit_priv_attr = FALSE;
static bool explicit_priv_attr = false;
/* Macros for encoding relaxation state for RVC branches and far jumps. */
#define RELAX_BRANCH_ENCODE(uncond, rvc, length) \
@ -795,7 +795,7 @@ riscv_init_csr_hash (const char *name,
enum riscv_spec_class abort_version)
{
struct riscv_csr_extra *entry, *pre_entry;
bfd_boolean need_enrty = TRUE;
bool need_enrty = true;
pre_entry = NULL;
entry = (struct riscv_csr_extra *) str_hash_find (csr_extra_hash, name);
@ -805,7 +805,7 @@ riscv_init_csr_hash (const char *name,
&& entry->address == address
&& entry->define_version == define_version
&& entry->abort_version == abort_version)
need_enrty = FALSE;
need_enrty = false;
pre_entry = entry;
entry = entry->next;
}
@ -843,8 +843,8 @@ riscv_csr_address (const char *csr_name,
{
struct riscv_csr_extra *saved_entry = entry;
enum riscv_csr_class csr_class = entry->csr_class;
bfd_boolean need_check_version = TRUE;
bfd_boolean result = TRUE;
bool need_check_version = true;
bool result = true;
switch (csr_class)
{
@ -856,10 +856,10 @@ riscv_csr_address (const char *csr_name,
break;
case CSR_CLASS_F:
result = riscv_subset_supports ("f");
need_check_version = FALSE;
need_check_version = false;
break;
case CSR_CLASS_DEBUG:
need_check_version = FALSE;
need_check_version = false;
break;
default:
as_bad (_("internal: bad RISC-V CSR class (0x%x)"), csr_class);
@ -927,7 +927,7 @@ reg_lookup_internal (const char *s, enum reg_class class)
return DECODE_REG_NUM (r);
}
static bfd_boolean
static bool
reg_lookup (char **s, enum reg_class class, unsigned int *regnop)
{
char *e;
@ -955,31 +955,31 @@ reg_lookup (char **s, enum reg_class class, unsigned int *regnop)
return reg >= 0;
}
static bfd_boolean
static bool
arg_lookup (char **s, const char *const *array, size_t size, unsigned *regnop)
{
const char *p = strchr (*s, ',');
size_t i, len = p ? (size_t)(p - *s) : strlen (*s);
if (len == 0)
return FALSE;
return false;
for (i = 0; i < size; i++)
if (array[i] != NULL && strncmp (array[i], *s, len) == 0)
{
*regnop = i;
*s += len;
return TRUE;
return true;
}
return FALSE;
return false;
}
/* For consistency checking, verify that all bits are specified either
by the match/mask part of the instruction definition, or by the
operand list. The `length` could be 0, 4 or 8, 0 for auto detection. */
static bfd_boolean
static bool
validate_riscv_insn (const struct riscv_opcode *opc, int length)
{
const char *p = opc->args;
@ -999,7 +999,7 @@ validate_riscv_insn (const struct riscv_opcode *opc, int length)
{
as_bad (_("internal: bad RISC-V opcode (mask error): %s %s"),
opc->name, opc->args);
return FALSE;
return false;
}
#define USE_BITS(mask,shift) (used_bits |= ((insn_t)(mask) << (shift)))
@ -1050,14 +1050,14 @@ validate_riscv_insn (const struct riscv_opcode *opc, int length)
as_bad (_("internal: bad RISC-V opcode "
"(unknown operand type `CF%c'): %s %s"),
c, opc->name, opc->args);
return FALSE;
return false;
}
break;
default:
as_bad (_("internal: bad RISC-V opcode "
"(unknown operand type `C%c'): %s %s"),
c, opc->name, opc->args);
return FALSE;
return false;
}
break;
case ',': break;
@ -1105,7 +1105,7 @@ validate_riscv_insn (const struct riscv_opcode *opc, int length)
as_bad (_("internal: bad RISC-V opcode "
"(unknown operand type `F%c'): %s %s"),
c, opc->name, opc->args);
return FALSE;
return false;
}
break;
case 'O': /* Opcode for .insn directive. */
@ -1117,14 +1117,14 @@ validate_riscv_insn (const struct riscv_opcode *opc, int length)
as_bad (_("internal: bad RISC-V opcode "
"(unknown operand type `F%c'): %s %s"),
c, opc->name, opc->args);
return FALSE;
return false;
}
break;
default:
as_bad (_("internal: bad RISC-V opcode "
"(unknown operand type `%c'): %s %s"),
c, opc->name, opc->args);
return FALSE;
return false;
}
#undef USE_BITS
if (used_bits != required_bits)
@ -1133,9 +1133,9 @@ validate_riscv_insn (const struct riscv_opcode *opc, int length)
"(bits 0x%lx undefined): %s %s"),
~(unsigned long)(used_bits & required_bits),
opc->name, opc->args);
return FALSE;
return false;
}
return TRUE;
return true;
}
struct percent_op_match
@ -1149,7 +1149,7 @@ struct percent_op_match
static htab_t
init_opcode_hash (const struct riscv_opcode *opcodes,
bfd_boolean insn_directive_p)
bool insn_directive_p)
{
int i = 0;
int length;
@ -1193,8 +1193,8 @@ md_begin (void)
if (! bfd_set_arch_mach (stdoutput, bfd_arch_riscv, mach))
as_warn (_("could not set architecture and machine"));
op_hash = init_opcode_hash (riscv_opcodes, FALSE);
insn_type_hash = init_opcode_hash (riscv_insn_types, TRUE);
op_hash = init_opcode_hash (riscv_opcodes, false);
insn_type_hash = init_opcode_hash (riscv_insn_types, true);
reg_names_hash = str_htab_create ();
hash_reg_names (RCLASS_GPR, riscv_gpr_names_numeric, NGPR);
@ -1285,7 +1285,7 @@ append_insn (struct riscv_cl_insn *ip, expressionS *address_expr,
ip->fixp = fix_new_exp (ip->frag, ip->where,
bfd_get_reloc_size (howto),
address_expr, FALSE, reloc_type);
address_expr, false, reloc_type);
ip->fixp->fx_tcbit = riscv_opts.relax;
}
@ -1414,7 +1414,7 @@ normalize_constant_expr (expressionS *ex)
static void
check_absolute_expr (struct riscv_cl_insn *ip, expressionS *ex,
bfd_boolean maybe_csr)
bool maybe_csr)
{
if (ex->X_op == O_big)
as_bad (_("unsupported large constant"));
@ -1536,7 +1536,7 @@ load_const (int reg, expressionS *ep)
/* Zero extend and sign extend byte/half-word/word. */
static void
riscv_ext (int destreg, int srcreg, unsigned shift, bfd_boolean sign)
riscv_ext (int destreg, int srcreg, unsigned shift, bool sign)
{
if (sign)
{
@ -1673,19 +1673,19 @@ macro (struct riscv_cl_insn *ip, expressionS *imm_expr,
break;
case M_ZEXTH:
riscv_ext (rd, rs1, xlen - 16, FALSE);
riscv_ext (rd, rs1, xlen - 16, false);
break;
case M_ZEXTW:
riscv_ext (rd, rs1, xlen - 32, FALSE);
riscv_ext (rd, rs1, xlen - 32, false);
break;
case M_SEXTB:
riscv_ext (rd, rs1, xlen - 8, TRUE);
riscv_ext (rd, rs1, xlen - 8, true);
break;
case M_SEXTH:
riscv_ext (rd, rs1, xlen - 16, TRUE);
riscv_ext (rd, rs1, xlen - 16, true);
break;
default:
@ -1736,7 +1736,7 @@ static const struct percent_op_match percent_op_null[] =
move *STR over the operator and store its relocation code in *RELOC.
Leave both *STR and *RELOC alone when returning false. */
static bfd_boolean
static bool
parse_relocation (char **str, bfd_reloc_code_real_type *reloc,
const struct percent_op_match *percent_op)
{
@ -1760,9 +1760,9 @@ parse_relocation (char **str, bfd_reloc_code_real_type *reloc,
"current ABI", percent_op->str);
*reloc = BFD_RELOC_UNUSED;
}
return TRUE;
return true;
}
return FALSE;
return false;
}
static void
@ -1863,7 +1863,7 @@ my_getOpcodeExpression (expressionS *ep, bfd_reloc_code_real_type *reloc,
"lw t0, (t1)" is shorthand for "lw t0, 0(t1)". Return TRUE iff such
an implicit offset was detected. */
static bfd_boolean
static bool
riscv_handle_implicit_zero_offset (expressionS *ep, const char *s)
{
/* Check whether there is only a single bracketed expression left.
@ -1872,10 +1872,10 @@ riscv_handle_implicit_zero_offset (expressionS *ep, const char *s)
{
ep->X_op = O_constant;
ep->X_add_number = 0;
return TRUE;
return true;
}
return FALSE;
return false;
}
/* All RISC-V CSR instructions belong to one of these classes. */
@ -1909,7 +1909,7 @@ riscv_csr_insn_type (insn_t insn)
CSR when RS1 isn't zero. The CSR is read only if the [11:10] bits of
CSR address is 0x3. */
static bfd_boolean
static bool
riscv_csr_read_only_check (insn_t insn)
{
int csr = (insn & (OP_MASK_CSR << OP_SH_CSR)) >> OP_SH_CSR;
@ -1922,9 +1922,9 @@ riscv_csr_read_only_check (insn_t insn)
|| csr_insn == INSN_CSRRC)
&& rs1 != 0)
|| csr_insn == INSN_CSRRW))
return FALSE;
return false;
return TRUE;
return true;
}
/* Return True if it is a privileged instruction. Otherwise, return FALSE.
@ -1940,7 +1940,7 @@ riscv_csr_read_only_check (insn_t insn)
dret is defined in the debug spec, so it should be checked in the future,
too. */
static bfd_boolean
static bool
riscv_is_priv_insn (insn_t insn)
{
return (((insn ^ MATCH_SRET) & MASK_SRET) == 0
@ -1971,7 +1971,7 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr,
const struct percent_op_match *p;
const char *error = "unrecognized opcode";
/* Indicate we are assembling instruction with CSR. */
bfd_boolean insn_with_csr = FALSE;
bool insn_with_csr = false;
/* Parse the name of the instruction. Terminate the string if whitespace
is found so that str_hash_find only sees the name part of the string. */
@ -2020,7 +2020,7 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr,
break;
if (riscv_is_priv_insn (ip->insn_opcode))
explicit_priv_attr = TRUE;
explicit_priv_attr = true;
/* Check if we write a read-only CSR by the CSR
instruction. */
@ -2033,14 +2033,14 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr,
if (save_c)
*(argsStart - 1) = save_c;
as_warn (_("read-only CSR is written `%s'"), str);
insn_with_csr = FALSE;
insn_with_csr = false;
}
}
if (*s != '\0')
break;
/* Successful assembly. */
error = NULL;
insn_with_csr = FALSE;
insn_with_csr = false;
goto out;
case 'C': /* RVC */
@ -2355,7 +2355,7 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr,
case '<': /* Shift amount, 0 - 31. */
my_getExpression (imm_expr, s);
check_absolute_expr (ip, imm_expr, FALSE);
check_absolute_expr (ip, imm_expr, false);
if ((unsigned long) imm_expr->X_add_number > 31)
as_bad (_("improper shift amount (%lu)"),
(unsigned long) imm_expr->X_add_number);
@ -2366,7 +2366,7 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr,
case '>': /* Shift amount, 0 - (XLEN-1). */
my_getExpression (imm_expr, s);
check_absolute_expr (ip, imm_expr, FALSE);
check_absolute_expr (ip, imm_expr, false);
if ((unsigned long) imm_expr->X_add_number >= xlen)
as_bad (_("improper shift amount (%lu)"),
(unsigned long) imm_expr->X_add_number);
@ -2377,7 +2377,7 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr,
case 'Z': /* CSRRxI immediate. */
my_getExpression (imm_expr, s);
check_absolute_expr (ip, imm_expr, FALSE);
check_absolute_expr (ip, imm_expr, false);
if ((unsigned long) imm_expr->X_add_number > 31)
as_bad (_("improper CSRxI immediate (%lu)"),
(unsigned long) imm_expr->X_add_number);
@ -2387,14 +2387,14 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr,
continue;
case 'E': /* Control register. */
insn_with_csr = TRUE;
explicit_priv_attr = TRUE;
insn_with_csr = true;
explicit_priv_attr = true;
if (reg_lookup (&s, RCLASS_CSR, &regno))
INSERT_OPERAND (CSR, *ip, regno);
else
{
my_getExpression (imm_expr, s);
check_absolute_expr (ip, imm_expr, TRUE);
check_absolute_expr (ip, imm_expr, true);
if ((unsigned long) imm_expr->X_add_number > 0xfff)
as_bad (_("improper CSR address (%lu)"),
(unsigned long) imm_expr->X_add_number);
@ -2712,7 +2712,7 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr,
}
s = argsStart;
error = _("illegal operands");
insn_with_csr = FALSE;
insn_with_csr = false;
}
out:
@ -2734,7 +2734,7 @@ md_assemble (char *str)
before assembling. */
if (!start_assemble)
{
start_assemble = TRUE;
start_assemble = true;
riscv_set_abi_by_arch ();
if (!riscv_set_default_priv_spec (NULL))
@ -2823,59 +2823,59 @@ md_parse_option (int c, const char *arg)
break;
case OPTION_NO_PIC:
riscv_opts.pic = FALSE;
riscv_opts.pic = false;
break;
case OPTION_PIC:
riscv_opts.pic = TRUE;
riscv_opts.pic = true;
break;
case OPTION_MABI:
if (strcmp (arg, "ilp32") == 0)
riscv_set_abi (32, FLOAT_ABI_SOFT, FALSE);
riscv_set_abi (32, FLOAT_ABI_SOFT, false);
else if (strcmp (arg, "ilp32e") == 0)
riscv_set_abi (32, FLOAT_ABI_SOFT, TRUE);
riscv_set_abi (32, FLOAT_ABI_SOFT, true);
else if (strcmp (arg, "ilp32f") == 0)
riscv_set_abi (32, FLOAT_ABI_SINGLE, FALSE);
riscv_set_abi (32, FLOAT_ABI_SINGLE, false);
else if (strcmp (arg, "ilp32d") == 0)
riscv_set_abi (32, FLOAT_ABI_DOUBLE, FALSE);
riscv_set_abi (32, FLOAT_ABI_DOUBLE, false);
else if (strcmp (arg, "ilp32q") == 0)
riscv_set_abi (32, FLOAT_ABI_QUAD, FALSE);
riscv_set_abi (32, FLOAT_ABI_QUAD, false);
else if (strcmp (arg, "lp64") == 0)
riscv_set_abi (64, FLOAT_ABI_SOFT, FALSE);
riscv_set_abi (64, FLOAT_ABI_SOFT, false);
else if (strcmp (arg, "lp64f") == 0)
riscv_set_abi (64, FLOAT_ABI_SINGLE, FALSE);
riscv_set_abi (64, FLOAT_ABI_SINGLE, false);
else if (strcmp (arg, "lp64d") == 0)
riscv_set_abi (64, FLOAT_ABI_DOUBLE, FALSE);
riscv_set_abi (64, FLOAT_ABI_DOUBLE, false);
else if (strcmp (arg, "lp64q") == 0)
riscv_set_abi (64, FLOAT_ABI_QUAD, FALSE);
riscv_set_abi (64, FLOAT_ABI_QUAD, false);
else
return 0;
explicit_mabi = TRUE;
explicit_mabi = true;
break;
case OPTION_RELAX:
riscv_opts.relax = TRUE;
riscv_opts.relax = true;
break;
case OPTION_NO_RELAX:
riscv_opts.relax = FALSE;
riscv_opts.relax = false;
break;
case OPTION_ARCH_ATTR:
riscv_opts.arch_attr = TRUE;
riscv_opts.arch_attr = true;
break;
case OPTION_NO_ARCH_ATTR:
riscv_opts.arch_attr = FALSE;
riscv_opts.arch_attr = false;
break;
case OPTION_CSR_CHECK:
riscv_opts.csr_check = TRUE;
riscv_opts.csr_check = true;
break;
case OPTION_NO_CSR_CHECK:
riscv_opts.csr_check = FALSE;
riscv_opts.csr_check = false;
break;
case OPTION_MISA_SPEC:
@ -2928,14 +2928,14 @@ riscv_after_parse_args (void)
riscv_set_arch (default_arch_with_ext);
/* Add the RVC extension, regardless of -march, to support .option rvc. */
riscv_set_rvc (FALSE);
riscv_set_rvc (false);
if (riscv_subset_supports ("c"))
riscv_set_rvc (TRUE);
riscv_set_rvc (true);
/* Enable RVE if specified by the -march option. */
riscv_set_rve (FALSE);
riscv_set_rve (false);
if (riscv_subset_supports ("e"))
riscv_set_rve (TRUE);
riscv_set_rve (true);
/* If the CIE to be produced has not been overridden on the command line,
then produce version 3 by default. This allows us to use the full
@ -2957,7 +2957,7 @@ md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
{
unsigned int subtype;
bfd_byte *buf = (bfd_byte *) (fixP->fx_frag->fr_literal + fixP->fx_where);
bfd_boolean relaxable = FALSE;
bool relaxable = false;
offsetT loc;
segT sub_segment;
@ -2972,8 +2972,8 @@ md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
bfd_putl32 (riscv_apply_const_reloc (fixP->fx_r_type, *valP)
| bfd_getl32 (buf), buf);
if (fixP->fx_addsy == NULL)
fixP->fx_done = TRUE;
relaxable = TRUE;
fixP->fx_done = true;
relaxable = true;
break;
case BFD_RELOC_RISCV_GOT_HI20:
@ -2993,7 +2993,7 @@ md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
case BFD_RELOC_RISCV_TPREL_LO12_I:
case BFD_RELOC_RISCV_TPREL_LO12_S:
case BFD_RELOC_RISCV_TPREL_ADD:
relaxable = TRUE;
relaxable = true;
/* Fall through. */
case BFD_RELOC_RISCV_TLS_GOT_HI20:
@ -3166,7 +3166,7 @@ md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
case BFD_RELOC_RISCV_CALL:
case BFD_RELOC_RISCV_CALL_PLT:
relaxable = TRUE;
relaxable = true;
break;
case BFD_RELOC_RISCV_PCREL_HI20:
@ -3265,21 +3265,21 @@ s_riscv_option (int x ATTRIBUTE_UNUSED)
*input_line_pointer = '\0';
if (strcmp (name, "rvc") == 0)
riscv_set_rvc (TRUE);
riscv_set_rvc (true);
else if (strcmp (name, "norvc") == 0)
riscv_set_rvc (FALSE);
riscv_set_rvc (false);
else if (strcmp (name, "pic") == 0)
riscv_opts.pic = TRUE;
riscv_opts.pic = true;
else if (strcmp (name, "nopic") == 0)
riscv_opts.pic = FALSE;
riscv_opts.pic = false;
else if (strcmp (name, "relax") == 0)
riscv_opts.relax = TRUE;
riscv_opts.relax = true;
else if (strcmp (name, "norelax") == 0)
riscv_opts.relax = FALSE;
riscv_opts.relax = false;
else if (strcmp (name, "csr-check") == 0)
riscv_opts.csr_check = TRUE;
riscv_opts.csr_check = true;
else if (strcmp (name, "no-csr-check") == 0)
riscv_opts.csr_check = FALSE;
riscv_opts.csr_check = false;
else if (strcmp (name, "push") == 0)
{
struct riscv_option_stack *s;
@ -3333,7 +3333,7 @@ s_dtprel (int bytes)
p = frag_more (bytes);
md_number_to_chars (p, 0, bytes);
fix_new_exp (frag_now, p - frag_now->fr_literal, bytes, &ex, FALSE,
fix_new_exp (frag_now, p - frag_now->fr_literal, bytes, &ex, false,
(bytes == 8
? BFD_RELOC_RISCV_TLS_DTPREL64
: BFD_RELOC_RISCV_TLS_DTPREL32));
@ -3378,7 +3378,7 @@ riscv_make_nops (char *buf, bfd_vma bytes)
will later relax to the correct number of NOPs. We can't compute
the correct alignment now because of other linker relaxations. */
bfd_boolean
bool
riscv_frag_align_code (int n)
{
bfd_vma bytes = (bfd_vma) 1 << n;
@ -3390,11 +3390,11 @@ riscv_frag_align_code (int n)
/* If we are moving to a smaller alignment than the instruction size, then no
alignment is required. */
if (bytes <= insn_alignment)
return TRUE;
return true;
/* When not relaxing, riscv_handle_align handles code alignment. */
if (!riscv_opts.relax)
return FALSE;
return false;
nops = frag_more (worst_case_bytes);
@ -3404,9 +3404,9 @@ riscv_frag_align_code (int n)
riscv_make_nops (nops, worst_case_bytes);
fix_new_exp (frag_now, nops - frag_now->fr_literal, 0,
&ex, FALSE, BFD_RELOC_RISCV_ALIGN);
&ex, false, BFD_RELOC_RISCV_ALIGN);
return TRUE;
return true;
}
/* Implement HANDLE_ALIGN. */
@ -3452,7 +3452,7 @@ riscv_handle_align (fragS *fragP)
int
md_estimate_size_before_relax (fragS *fragp, asection *segtype)
{
return (fragp->fr_var = relaxed_branch_length (fragp, segtype, FALSE));
return (fragp->fr_var = relaxed_branch_length (fragp, segtype, false));
}
/* Translate internal representation of relocation info to BFD target
@ -3494,7 +3494,7 @@ riscv_relax_frag (asection *sec, fragS *fragp, long stretch ATTRIBUTE_UNUSED)
if (RELAX_BRANCH_P (fragp->fr_subtype))
{
offsetT old_var = fragp->fr_var;
fragp->fr_var = relaxed_branch_length (fragp, sec, TRUE);
fragp->fr_var = relaxed_branch_length (fragp, sec, true);
return fragp->fr_var - old_var;
}
@ -3556,7 +3556,7 @@ md_convert_frag_branch (fragS *fragp)
reloc = RELAX_BRANCH_UNCOND (fragp->fr_subtype)
? BFD_RELOC_RISCV_RVC_JUMP : BFD_RELOC_RISCV_RVC_BRANCH;
fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
2, &exp, FALSE, reloc);
2, &exp, false, reloc);
buf += 2;
goto done;
@ -3580,7 +3580,7 @@ md_convert_frag_branch (fragS *fragp)
jump:
/* Jump to the target. */
fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
4, &exp, FALSE, BFD_RELOC_RISCV_JMP);
4, &exp, false, BFD_RELOC_RISCV_JMP);
bfd_putl32 (MATCH_JAL, buf);
buf += 4;
break;
@ -3589,7 +3589,7 @@ md_convert_frag_branch (fragS *fragp)
reloc = RELAX_BRANCH_UNCOND (fragp->fr_subtype)
? BFD_RELOC_RISCV_JMP : BFD_RELOC_12_PCREL;
fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
4, &exp, FALSE, reloc);
4, &exp, false, reloc);
buf += 4;
break;
@ -3840,7 +3840,7 @@ s_riscv_attribute (int ignored ATTRIBUTE_UNUSED)
unsigned old_xlen;
obj_attribute *attr;
explicit_attr = TRUE;
explicit_attr = true;
switch (tag)
{
case Tag_RISCV_arch:

2
gas/config/tc-riscv.h
View File

@ -53,7 +53,7 @@ extern int riscv_relax_frag (asection *, struct frag *, long);
#define md_undefined_symbol(name) (0)
#define md_operand(x)
extern bfd_boolean riscv_frag_align_code (int);
extern bool riscv_frag_align_code (int);
#define md_do_align(N, FILL, LEN, MAX, LABEL) \
if ((N) != 0 && !(FILL) && !need_pass_2 && subseg_text_p (now_seg)) \
{ \

38
gas/config/tc-rx.c
View File

@ -42,15 +42,15 @@ const char EXP_CHARS[] = "eE";
const char FLT_CHARS[] = "dD";
#ifndef TE_LINUX
bfd_boolean rx_use_conventional_section_names = FALSE;
bool rx_use_conventional_section_names = false;
static int elf_flags = E_FLAG_RX_ABI;
#else
bfd_boolean rx_use_conventional_section_names = TRUE;
bool rx_use_conventional_section_names = true;
static int elf_flags;
#endif
static bfd_boolean rx_use_small_data_limit = FALSE;
static bfd_boolean rx_pid_mode = FALSE;
static bool rx_use_small_data_limit = false;
static bool rx_pid_mode = false;
static int rx_num_int_regs = 0;
int rx_pid_register;
int rx_gp_register;
@ -147,15 +147,15 @@ md_parse_option (int c ATTRIBUTE_UNUSED, const char * arg ATTRIBUTE_UNUSED)
return 1;
case OPTION_CONVENTIONAL_SECTION_NAMES:
rx_use_conventional_section_names = TRUE;
rx_use_conventional_section_names = true;
return 1;
case OPTION_RENESAS_SECTION_NAMES:
rx_use_conventional_section_names = FALSE;
rx_use_conventional_section_names = false;
return 1;
case OPTION_SMALL_DATA_LIMIT:
rx_use_small_data_limit = TRUE;
rx_use_small_data_limit = true;
return 1;
case OPTION_RELAX:
@ -163,7 +163,7 @@ md_parse_option (int c ATTRIBUTE_UNUSED, const char * arg ATTRIBUTE_UNUSED)
return 1;
case OPTION_PID:
rx_pid_mode = TRUE;
rx_pid_mode = true;
elf_flags |= E_FLAG_RX_PID;
return 1;
@ -289,7 +289,7 @@ rx_include (int ignore)
/* Get the filename. Spaces are allowed, NUL characters are not. */
filename = input_line_pointer;
last_char = find_end_of_line (filename, FALSE);
last_char = find_end_of_line (filename, false);
input_line_pointer = last_char;
while (last_char >= filename && (* last_char == ' ' || * last_char == '\n'))
@ -490,7 +490,7 @@ parse_rx_section (char * name)
else
type = SHT_NOBITS;
obj_elf_change_section (name, type, attr, 0, NULL, FALSE, FALSE);
obj_elf_change_section (name, type, attr, 0, NULL, false, false);
}
else /* Try not to redefine a section, especially B_1. */
{
@ -505,7 +505,7 @@ parse_rx_section (char * name)
| ((flags & SEC_STRINGS) ? SHF_STRINGS : 0)
| ((flags & SEC_THREAD_LOCAL) ? SHF_TLS : 0);
obj_elf_change_section (name, type, attr, 0, NULL, FALSE, FALSE);
obj_elf_change_section (name, type, attr, 0, NULL, false, false);
}
bfd_set_section_alignment (now_seg, align);
@ -1096,7 +1096,7 @@ rx_equ (char * name, char * expression)
rather than at the start of a line. (eg .EQU or .DEFINE). If one
is found, process it and return TRUE otherwise return FALSE. */
static bfd_boolean
static bool
scan_for_infix_rx_pseudo_ops (char * str)
{
char * p;
@ -1104,16 +1104,16 @@ scan_for_infix_rx_pseudo_ops (char * str)
char * dot = strchr (str, '.');
if (dot == NULL || dot == str)
return FALSE;
return false;
/* A real pseudo-op must be preceded by whitespace. */
if (dot[-1] != ' ' && dot[-1] != '\t')
return FALSE;
return false;
pseudo_op = dot + 1;
if (!ISALNUM (* pseudo_op))
return FALSE;
return false;
for (p = pseudo_op + 1; ISALNUM (* p); p++)
;
@ -1127,9 +1127,9 @@ scan_for_infix_rx_pseudo_ops (char * str)
else if (strncasecmp ("BTEQU", pseudo_op, p - pseudo_op) == 0)
as_warn (_("The .BTEQU pseudo-op is not implemented."));
else
return FALSE;
return false;
return TRUE;
return true;
}
void
@ -2464,7 +2464,7 @@ arelent **
tc_gen_reloc (asection * sec ATTRIBUTE_UNUSED, fixS * fixp)
{
static arelent * reloc[5];
bfd_boolean is_opcode = FALSE;
bool is_opcode = false;
if (fixp->fx_r_type == BFD_RELOC_NONE)
{
@ -2489,7 +2489,7 @@ tc_gen_reloc (asection * sec ATTRIBUTE_UNUSED, fixS * fixp)
&& fixp->fx_subsy)
{
fixp->fx_r_type = BFD_RELOC_RX_DIFF;
is_opcode = TRUE;
is_opcode = true;
}
else if (sec)
is_opcode = sec->flags & SEC_CODE;

2
gas/config/tc-rx.h
View File

@ -106,7 +106,7 @@ extern void rx_handle_align (fragS *);
#define elf_tc_final_processing rx_elf_final_processing
extern void rx_elf_final_processing (void);
extern bfd_boolean rx_use_conventional_section_names;
extern bool rx_use_conventional_section_names;
#define TEXT_SECTION_NAME (rx_use_conventional_section_names ? ".text" : "P")
#define DATA_SECTION_NAME (rx_use_conventional_section_names ? ".data" : "D_1")
#define BSS_SECTION_NAME (rx_use_conventional_section_names ? ".bss" : "B_1")

172
gas/config/tc-s12z.c
View File

@ -23,9 +23,7 @@
#include "subsegs.h"
#include "dwarf2dbg.h"
#include "opcode/s12z.h"
#include <stdint.h>
#include <limits.h>
#include <stdbool.h>
const char comment_chars[] = ";";
@ -164,7 +162,7 @@ md_parse_option (int c, const char *arg)
register_prefix = xstrdup (arg);
break;
case OPTION_DOLLAR_HEX:
literal_prefix_dollar_hex = TRUE;
literal_prefix_dollar_hex = true;
break;
default:
return 0;
@ -181,7 +179,7 @@ md_undefined_symbol (char *name ATTRIBUTE_UNUSED)
const char *
md_atof (int type, char *litP, int *sizeP)
{
return ieee_md_atof (type, litP, sizeP, TRUE);
return ieee_md_atof (type, litP, sizeP, true);
}
valueT
@ -200,7 +198,7 @@ void
s12z_init_after_args (void)
{
if (flag_traditional_format)
literal_prefix_dollar_hex = TRUE;
literal_prefix_dollar_hex = true;
}
/* Builtin help. */
@ -231,9 +229,9 @@ s12z_new_insn (int size)
static bfd_boolean lex_reg_name (uint16_t which, int *reg);
static bool lex_reg_name (uint16_t which, int *reg);
static bfd_boolean
static bool
lex_constant (long *v)
{
char *end = NULL;
@ -259,7 +257,7 @@ lex_constant (long *v)
return false;
}
static bfd_boolean
static bool
lex_match (char x)
{
char *p = input_line_pointer;
@ -271,7 +269,7 @@ lex_match (char x)
}
static bfd_boolean
static bool
lex_expression (expressionS *exp)
{
char *ilp = input_line_pointer;
@ -298,7 +296,7 @@ lex_expression (expressionS *exp)
If EXP_O is non-null, then a symbolic expression is permitted,
in which case, EXP_O will be populated with the parsed expression.
*/
static bfd_boolean
static bool
lex_imm (long *v, expressionS *exp_o)
{
char *ilp = input_line_pointer;
@ -329,7 +327,7 @@ lex_imm (long *v, expressionS *exp_o)
}
/* Short mmediate operand */
static bfd_boolean
static bool
lex_imm_e4 (long *val)
{
char *ilp = input_line_pointer;
@ -345,7 +343,7 @@ lex_imm_e4 (long *val)
return false;
}
static bfd_boolean
static bool
lex_match_string (const char *s)
{
char *p = input_line_pointer;
@ -373,7 +371,7 @@ lex_match_string (const char *s)
On success, REG will be filled with the index of the register which
was successfully scanned.
*/
static bfd_boolean
static bool
lex_reg_name (uint16_t which, int *reg)
{
char *p = input_line_pointer;
@ -425,7 +423,7 @@ lex_reg_name (uint16_t which, int *reg)
return false;
}
static bfd_boolean
static bool
lex_force_match (char x)
{
char *p = input_line_pointer;
@ -439,7 +437,7 @@ lex_force_match (char x)
return true;
}
static bfd_boolean
static bool
lex_opr (uint8_t *buffer, int *n_bytes, expressionS *exp,
bool immediate_ok)
{
@ -751,7 +749,7 @@ lex_opr (uint8_t *buffer, int *n_bytes, expressionS *exp,
return false;
}
static bfd_boolean
static bool
lex_offset (long *val)
{
char *end = NULL;
@ -783,7 +781,7 @@ lex_offset (long *val)
struct instruction;
typedef bfd_boolean (*parse_operand_func) (const struct instruction *);
typedef bool (*parse_operand_func) (const struct instruction *);
struct instruction
{
@ -805,7 +803,7 @@ struct instruction
uint8_t alt_opc;
};
static bfd_boolean
static bool
no_operands (const struct instruction *insn)
{
if (*input_line_pointer != '\0')
@ -833,7 +831,7 @@ emit_reloc (expressionS *exp, char *f, int size, enum bfd_reloc_code_real reloc)
f - frag_now->fr_literal,
size,
exp,
FALSE,
false,
reloc);
/* Some third party tools seem to use the lower bits
of this addend for flags. They don't get added
@ -867,7 +865,7 @@ emit_ext24 (char *f, long v)
return f + 3;
}
static bfd_boolean
static bool
opr (const struct instruction *insn)
{
uint8_t buffer[4];
@ -906,7 +904,7 @@ opr (const struct instruction *insn)
/* Parse a 15 bit offset, as an expression.
LONG_DISPLACEMENT will be set to true if the offset is wider than 7 bits.
*/
static bfd_boolean
static bool
lex_15_bit_offset (bool *long_displacement, expressionS *exp)
{
char *ilp = input_line_pointer;
@ -964,7 +962,7 @@ emit_15_bit_offset (char *f, int where, expressionS *exp)
f - frag_now->fr_literal,
2,
exp,
TRUE,
true,
BFD_RELOC_16_PCREL);
fix->fx_addnumber = where - 2;
}
@ -981,7 +979,7 @@ emit_15_bit_offset (char *f, int where, expressionS *exp)
}
}
static bfd_boolean
static bool
rel (const struct instruction *insn)
{
bool long_displacement;
@ -996,7 +994,7 @@ rel (const struct instruction *insn)
return true;
}
static bfd_boolean
static bool
reg_inh (const struct instruction *insn)
{
int reg;
@ -1015,7 +1013,7 @@ reg_inh (const struct instruction *insn)
/* Special case for CLR X and CLR Y */
static bfd_boolean
static bool
clr_xy (const struct instruction *insn ATTRIBUTE_UNUSED)
{
int reg;
@ -1061,7 +1059,7 @@ size_from_suffix (const struct instruction *insn, int idx)
return size;
}
static bfd_boolean
static bool
mul_reg_reg_reg (const struct instruction *insn)
{
char *ilp = input_line_pointer;
@ -1118,7 +1116,7 @@ mul_reg_reg_reg (const struct instruction *insn)
}
static bfd_boolean
static bool
mul_reg_reg_imm (const struct instruction *insn)
{
char *ilp = input_line_pointer;
@ -1179,7 +1177,7 @@ mul_reg_reg_imm (const struct instruction *insn)
}
static bfd_boolean
static bool
mul_reg_reg_opr (const struct instruction *insn)
{
char *ilp = input_line_pointer;
@ -1241,7 +1239,7 @@ mul_reg_reg_opr (const struct instruction *insn)
return false;
}
static bfd_boolean
static bool
mul_reg_opr_opr (const struct instruction *insn)
{
char *ilp = input_line_pointer;
@ -1342,7 +1340,7 @@ static const uint8_t reg_map [] =
0x00
};
static bfd_boolean
static bool
lex_reg_list (uint16_t grp, uint16_t *reg_bits)
{
if (lex_match (','))
@ -1358,7 +1356,7 @@ lex_reg_list (uint16_t grp, uint16_t *reg_bits)
return true;
}
static bfd_boolean
static bool
psh_pull (const struct instruction *insn)
{
uint8_t pb =
@ -1410,7 +1408,7 @@ psh_pull (const struct instruction *insn)
}
static bfd_boolean
static bool
tfr (const struct instruction *insn)
{
int reg1;
@ -1446,7 +1444,7 @@ tfr (const struct instruction *insn)
return false;
}
static bfd_boolean
static bool
imm8 (const struct instruction *insn)
{
long imm;
@ -1465,7 +1463,7 @@ imm8 (const struct instruction *insn)
return true;
}
static bfd_boolean
static bool
reg_imm (const struct instruction *insn, int allowed_reg)
{
char *ilp = input_line_pointer;
@ -1495,26 +1493,26 @@ reg_imm (const struct instruction *insn, int allowed_reg)
}
static bfd_boolean
static bool
regd_imm (const struct instruction *insn)
{
return reg_imm (insn, REG_BIT_Dn);
}
static bfd_boolean
static bool
regdxy_imm (const struct instruction *insn)
{
return reg_imm (insn, REG_BIT_Dn | REG_BIT_XY);
}
static bfd_boolean
static bool
regs_imm (const struct instruction *insn)
{
return reg_imm (insn, 0x1U << REG_S);
}
static bfd_boolean
static bool
trap_imm (const struct instruction *insn ATTRIBUTE_UNUSED)
{
long imm = -1;
@ -1546,7 +1544,7 @@ trap_imm (const struct instruction *insn ATTRIBUTE_UNUSED)
/* Special one byte instruction CMP X, Y */
static bfd_boolean
static bool
regx_regy (const struct instruction *insn)
{
int reg;
@ -1566,7 +1564,7 @@ regx_regy (const struct instruction *insn)
}
/* Special one byte instruction SUB D6, X, Y */
static bfd_boolean
static bool
regd6_regx_regy (const struct instruction *insn)
{
char *ilp = input_line_pointer;
@ -1597,7 +1595,7 @@ regd6_regx_regy (const struct instruction *insn)
}
/* Special one byte instruction SUB D6, Y, X */
static bfd_boolean
static bool
regd6_regy_regx (const struct instruction *insn)
{
char *ilp = input_line_pointer;
@ -1627,7 +1625,7 @@ regd6_regy_regx (const struct instruction *insn)
return false;
}
static bfd_boolean
static bool
reg_opr (const struct instruction *insn, int allowed_regs,
bool immediate_ok)
{
@ -1681,20 +1679,20 @@ reg_opr (const struct instruction *insn, int allowed_regs,
}
static bfd_boolean
static bool
regdxy_opr_dest (const struct instruction *insn)
{
return reg_opr (insn, REG_BIT_Dn | REG_BIT_XY, false);
}
static bfd_boolean
static bool
regdxy_opr_src (const struct instruction *insn)
{
return reg_opr (insn, REG_BIT_Dn | REG_BIT_XY, true);
}
static bfd_boolean
static bool
regd_opr (const struct instruction *insn)
{
return reg_opr (insn, REG_BIT_Dn, true);
@ -1702,20 +1700,20 @@ regd_opr (const struct instruction *insn)
/* OP0: S; OP1: destination OPR */
static bfd_boolean
static bool
regs_opr_dest (const struct instruction *insn)
{
return reg_opr (insn, 0x1U << REG_S, false);
}
/* OP0: S; OP1: source OPR */
static bfd_boolean
static bool
regs_opr_src (const struct instruction *insn)
{
return reg_opr (insn, 0x1U << REG_S, true);
}
static bfd_boolean
static bool
imm_opr (const struct instruction *insn)
{
char *ilp = input_line_pointer;
@ -1763,7 +1761,7 @@ imm_opr (const struct instruction *insn)
return false;
}
static bfd_boolean
static bool
opr_opr (const struct instruction *insn)
{
char *ilp = input_line_pointer;
@ -1798,7 +1796,7 @@ opr_opr (const struct instruction *insn)
return false;
}
static bfd_boolean
static bool
reg67sxy_opr (const struct instruction *insn)
{
int reg;
@ -1821,7 +1819,7 @@ reg67sxy_opr (const struct instruction *insn)
return true;
}
static bfd_boolean
static bool
rotate (const struct instruction *insn, short dir)
{
uint8_t buffer[4];
@ -1847,13 +1845,13 @@ rotate (const struct instruction *insn, short dir)
return false;
}
static bfd_boolean
static bool
rol (const struct instruction *insn)
{
return rotate (insn, 1);
}
static bfd_boolean
static bool
ror (const struct instruction *insn)
{
return rotate (insn, 0);
@ -1864,7 +1862,7 @@ ror (const struct instruction *insn)
left = 1; right = 0;
logical = 0; arithmetic = 1;
*/
static bfd_boolean
static bool
lex_shift_reg_imm1 (const struct instruction *insn, short type, short dir)
{
/*
@ -1925,7 +1923,7 @@ lex_shift_reg_imm1 (const struct instruction *insn, short type, short dir)
/* Shift instruction with a register operand.
left = 1; right = 0;
logical = 0; arithmetic = 1; */
static bfd_boolean
static bool
lex_shift_reg (const struct instruction *insn, short type, short dir)
{
int Dd, Ds, Dn;
@ -2031,7 +2029,7 @@ impute_shift_dir_and_type (const struct instruction *insn, short *type, short *d
}
/* Shift instruction with a OPR operand */
static bfd_boolean
static bool
shift_two_operand (const struct instruction *insn)
{
uint8_t sb = 0x34;
@ -2079,7 +2077,7 @@ shift_two_operand (const struct instruction *insn)
}
/* Shift instruction with a OPR operand */
static bfd_boolean
static bool
shift_opr_imm (const struct instruction *insn)
{
char *ilp = input_line_pointer;
@ -2176,7 +2174,7 @@ shift_opr_imm (const struct instruction *insn)
}
/* Shift instruction with a register operand */
static bfd_boolean
static bool
shift_reg (const struct instruction *insn)
{
short dir = -1;
@ -2189,7 +2187,7 @@ shift_reg (const struct instruction *insn)
return lex_shift_reg (insn, type, dir);
}
static bfd_boolean
static bool
bm_regd_imm (const struct instruction *insn)
{
char *ilp = input_line_pointer;
@ -2220,7 +2218,7 @@ bm_regd_imm (const struct instruction *insn)
return false;
}
static bfd_boolean
static bool
bm_opr_reg (const struct instruction *insn)
{
char *ilp = input_line_pointer;
@ -2259,7 +2257,7 @@ bm_opr_reg (const struct instruction *insn)
}
static bfd_boolean
static bool
bm_opr_imm (const struct instruction *insn)
{
char *ilp = input_line_pointer;
@ -2310,7 +2308,7 @@ bm_opr_imm (const struct instruction *insn)
}
static bfd_boolean
static bool
bm_regd_reg (const struct instruction *insn)
{
char *ilp = input_line_pointer;
@ -2347,7 +2345,7 @@ bm_regd_reg (const struct instruction *insn)
static bfd_boolean
static bool
bf_reg_opr_imm (const struct instruction *insn, short ie)
{
char *ilp = input_line_pointer;
@ -2417,7 +2415,7 @@ bf_reg_opr_imm (const struct instruction *insn, short ie)
}
static bfd_boolean
static bool
bf_opr_reg_imm (const struct instruction *insn, short ie)
{
char *ilp = input_line_pointer;
@ -2487,7 +2485,7 @@ bf_opr_reg_imm (const struct instruction *insn, short ie)
static bfd_boolean
static bool
bf_reg_reg_imm (const struct instruction *insn, short ie)
{
char *ilp = input_line_pointer;
@ -2550,7 +2548,7 @@ bf_reg_reg_imm (const struct instruction *insn, short ie)
return false;
}
static bfd_boolean
static bool
bf_reg_reg_reg (const struct instruction *insn ATTRIBUTE_UNUSED, short ie)
{
char *ilp = input_line_pointer;
@ -2593,7 +2591,7 @@ bf_reg_reg_reg (const struct instruction *insn ATTRIBUTE_UNUSED, short ie)
return false;
}
static bfd_boolean
static bool
bf_opr_reg_reg (const struct instruction *insn, short ie)
{
char *ilp = input_line_pointer;
@ -2646,7 +2644,7 @@ bf_opr_reg_reg (const struct instruction *insn, short ie)
}
static bfd_boolean
static bool
bf_reg_opr_reg (const struct instruction *insn, short ie)
{
char *ilp = input_line_pointer;
@ -2698,75 +2696,75 @@ bf_reg_opr_reg (const struct instruction *insn, short ie)
static bfd_boolean
static bool
bfe_reg_reg_reg (const struct instruction *insn)
{
return bf_reg_reg_reg (insn, 0);
}
static bfd_boolean
static bool
bfi_reg_reg_reg (const struct instruction *insn)
{
return bf_reg_reg_reg (insn, 1);
}
static bfd_boolean
static bool
bfe_reg_reg_imm (const struct instruction *insn)
{
return bf_reg_reg_imm (insn, 0);
}
static bfd_boolean
static bool
bfi_reg_reg_imm (const struct instruction *insn)
{
return bf_reg_reg_imm (insn, 1);
}
static bfd_boolean
static bool
bfe_reg_opr_reg (const struct instruction *insn)
{
return bf_reg_opr_reg (insn, 0);
}
static bfd_boolean
static bool
bfi_reg_opr_reg (const struct instruction *insn)
{
return bf_reg_opr_reg (insn, 1);
}
static bfd_boolean
static bool
bfe_opr_reg_reg (const struct instruction *insn)
{
return bf_opr_reg_reg (insn, 0);
}
static bfd_boolean
static bool
bfi_opr_reg_reg (const struct instruction *insn)
{
return bf_opr_reg_reg (insn, 1);
}
static bfd_boolean
static bool
bfe_reg_opr_imm (const struct instruction *insn)
{
return bf_reg_opr_imm (insn, 0);
}
static bfd_boolean
static bool
bfi_reg_opr_imm (const struct instruction *insn)
{
return bf_reg_opr_imm (insn, 1);
}
static bfd_boolean
static bool
bfe_opr_reg_imm (const struct instruction *insn)
{
return bf_opr_reg_imm (insn, 0);
}
static bfd_boolean
static bool
bfi_opr_reg_imm (const struct instruction *insn)
{
return bf_opr_reg_imm (insn, 1);
@ -2775,7 +2773,7 @@ bfi_opr_reg_imm (const struct instruction *insn)
static bfd_boolean
static bool
tb_reg_rel (const struct instruction *insn)
{
char *ilp = input_line_pointer;
@ -2844,7 +2842,7 @@ tb_reg_rel (const struct instruction *insn)
}
static bfd_boolean
static bool
tb_opr_rel (const struct instruction *insn)
{
char *ilp = input_line_pointer;
@ -2912,7 +2910,7 @@ tb_opr_rel (const struct instruction *insn)
static bfd_boolean
static bool
test_br_reg_reg_rel (const struct instruction *insn)
{
char *ilp = input_line_pointer;
@ -2959,7 +2957,7 @@ test_br_reg_reg_rel (const struct instruction *insn)
return false;
}
static bfd_boolean
static bool
test_br_opr_reg_rel (const struct instruction *insn)
{
char *ilp = input_line_pointer;
@ -3008,7 +3006,7 @@ test_br_opr_reg_rel (const struct instruction *insn)
}
static bfd_boolean
static bool
test_br_opr_imm_rel (const struct instruction *insn)
{
char *ilp = input_line_pointer;
@ -3063,7 +3061,7 @@ test_br_opr_imm_rel (const struct instruction *insn)
}
static bfd_boolean
static bool
test_br_reg_imm_rel (const struct instruction *insn)
{
char *ilp = input_line_pointer;
@ -3919,7 +3917,7 @@ tc_s12z_force_relocation (fixS *fixP)
we need to make sure that the linker relaxation is done
correctly, so in some cases we force the original symbol to be
used. */
bfd_boolean
bool
tc_s12z_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED)
{
return true;

2
gas/config/tc-s12z.h
View File

@ -91,7 +91,7 @@ extern long s12z_relax_frag (segT, fragS*, long);
extern int tc_s12z_force_relocation (struct fix *);
#define tc_fix_adjustable(X) tc_s12z_fix_adjustable(X)
extern bfd_boolean tc_s12z_fix_adjustable (struct fix *);
extern bool tc_s12z_fix_adjustable (struct fix *);
#define md_operand(x)

64
gas/config/tc-s390.c
View File

@ -48,17 +48,17 @@ static unsigned int current_mode_mask = 0;
/* Set to TRUE if the highgprs flag in the ELF header needs to be set
for the output file. */
static bfd_boolean set_highgprs_p = FALSE;
static bool set_highgprs_p = false;
/* Whether to use user friendly register names. Default is TRUE. */
#ifndef TARGET_REG_NAMES_P
#define TARGET_REG_NAMES_P TRUE
#define TARGET_REG_NAMES_P true
#endif
static bfd_boolean reg_names_p = TARGET_REG_NAMES_P;
static bool reg_names_p = TARGET_REG_NAMES_P;
/* Set to TRUE if we want to warn about zero base/index registers. */
static bfd_boolean warn_areg_zero = FALSE;
static bool warn_areg_zero = false;
/* Generic assembler global variables which must be defined by all
targets. */
@ -156,7 +156,7 @@ reg_name_search (const char *name)
* original state.
*/
static bfd_boolean
static bool
register_name (expressionS *expressionP)
{
int reg_number;
@ -169,7 +169,7 @@ register_name (expressionS *expressionP)
if (name[0] == '%' && ISALPHA (name[1]))
name = ++input_line_pointer;
else
return FALSE;
return false;
c = get_symbol_name (&name);
reg_number = reg_name_search (name);
@ -186,12 +186,12 @@ register_name (expressionS *expressionP)
/* Make the rest nice. */
expressionP->X_add_symbol = NULL;
expressionP->X_op_symbol = NULL;
return TRUE;
return true;
}
/* Reset the line as if we had not done anything. */
input_line_pointer = start;
return FALSE;
return false;
}
/* Local variables. */
@ -264,9 +264,9 @@ s390_target_format (void)
In case of an error, S390_OPCODE_MAXCPU is returned. */
static unsigned int
s390_parse_cpu (const char * arg,
unsigned int * ret_flags,
bfd_boolean allow_extensions)
s390_parse_cpu (const char *arg,
unsigned int *ret_flags,
bool allow_extensions)
{
static struct
{
@ -298,15 +298,15 @@ s390_parse_cpu (const char * arg,
};
static struct
{
const char * name;
const char *name;
unsigned int mask;
bfd_boolean on;
bool on;
} cpu_flags[] =
{
{ "htm", S390_INSTR_FLAG_HTM, TRUE },
{ "nohtm", S390_INSTR_FLAG_HTM, FALSE },
{ "vx", S390_INSTR_FLAG_VX, TRUE },
{ "novx", S390_INSTR_FLAG_VX, FALSE }
{ "htm", S390_INSTR_FLAG_HTM, true },
{ "nohtm", S390_INSTR_FLAG_HTM, false },
{ "vx", S390_INSTR_FLAG_VX, true },
{ "novx", S390_INSTR_FLAG_VX, false }
};
unsigned int icpu;
char *ilp_bak;
@ -403,13 +403,13 @@ md_parse_option (int c, const char *arg)
break;
case 'm':
if (arg != NULL && strcmp (arg, "regnames") == 0)
reg_names_p = TRUE;
reg_names_p = true;
else if (arg != NULL && strcmp (arg, "no-regnames") == 0)
reg_names_p = FALSE;
reg_names_p = false;
else if (arg != NULL && strcmp (arg, "warn-areg-zero") == 0)
warn_areg_zero = TRUE;
warn_areg_zero = true;
else if (arg != NULL && strcmp (arg, "31") == 0)
s390_arch_size = 32;
@ -423,13 +423,13 @@ md_parse_option (int c, const char *arg)
else if (arg != NULL && strcmp (arg, "zarch") == 0)
{
if (s390_arch_size == 32)
set_highgprs_p = TRUE;
set_highgprs_p = true;
current_mode_mask = 1 << S390_OPCODE_ZARCH;
}
else if (arg != NULL && strncmp (arg, "arch=", 5) == 0)
{
current_cpu = s390_parse_cpu (arg + 5, &current_flags, FALSE);
current_cpu = s390_parse_cpu (arg + 5, &current_flags, false);
if (current_cpu == S390_OPCODE_MAXCPU)
{
as_bad (_("invalid switch -m%s"), arg);
@ -495,7 +495,7 @@ s390_setup_opcodes (void)
{
const struct s390_opcode *op;
const struct s390_opcode *op_end;
bfd_boolean dup_insn = FALSE;
bool dup_insn = false;
if (s390_opcode_hash != NULL)
htab_delete (s390_opcode_hash);
@ -536,7 +536,7 @@ s390_setup_opcodes (void)
&& str_hash_insert (s390_opcode_hash, op->name, op, 0) != NULL)
{
as_bad (_("duplicate %s"), op->name);
dup_insn = TRUE;
dup_insn = true;
}
while (op < op_end - 1 && strcmp (op->name, op[1].name) == 0)
@ -1208,7 +1208,7 @@ s390_elf_cons (int nbytes /* 1=.byte, 2=.word, 4=.long */)
/* To make fixup_segment do the pc relative conversion the
pcrel parameter on the fix_new_exp call needs to be FALSE. */
fix_new_exp (frag_now, where - frag_now->fr_literal,
size, &exp, FALSE, reloc);
size, &exp, false, reloc);
}
else
as_bad (_("relocation not applicable"));
@ -1224,20 +1224,20 @@ s390_elf_cons (int nbytes /* 1=.byte, 2=.word, 4=.long */)
/* Return true if all remaining operands in the opcode with
OPCODE_FLAGS can be skipped. */
static bfd_boolean
static bool
skip_optargs_p (unsigned int opcode_flags, const unsigned char *opindex_ptr)
{
if ((opcode_flags & (S390_INSTR_FLAG_OPTPARM | S390_INSTR_FLAG_OPTPARM2))
&& opindex_ptr[0] != '\0'
&& opindex_ptr[1] == '\0')
return TRUE;
return true;
if ((opcode_flags & S390_INSTR_FLAG_OPTPARM2)
&& opindex_ptr[0] != '\0'
&& opindex_ptr[1] != '\0'
&& opindex_ptr[2] == '\0')
return TRUE;
return FALSE;
return true;
return false;
}
/* We need to keep a list of fixups. We can't simply generate them as
@ -1977,7 +1977,7 @@ s390_machine (int ignore ATTRIBUTE_UNUSED)
}
}
else
new_cpu = s390_parse_cpu (cpu_string, &new_flags, TRUE);
new_cpu = s390_parse_cpu (cpu_string, &new_flags, true);
if (new_cpu == S390_OPCODE_MAXCPU)
as_bad (_("invalid machine `%s'"), cpu_string);
@ -2047,7 +2047,7 @@ s390_machinemode (int ignore ATTRIBUTE_UNUSED)
else if (strcmp (mode_string, "zarch") == 0)
{
if (s390_arch_size == 32)
set_highgprs_p = TRUE;
set_highgprs_p = true;
current_mode_mask = 1 << S390_OPCODE_ZARCH;
}
else if (strcmp (mode_string, "zarch_nohighgprs") == 0)
@ -2068,7 +2068,7 @@ s390_machinemode (int ignore ATTRIBUTE_UNUSED)
const char *
md_atof (int type, char *litp, int *sizep)
{
return ieee_md_atof (type, litp, sizep, TRUE);
return ieee_md_atof (type, litp, sizep, true);
}
/* Align a section (I don't know why this is machine dependent). */

110
gas/config/tc-score.c
View File

@ -65,7 +65,7 @@ static const char *s3_atof (int type, char *litP, int *sizeP);
static void s3_frag_check (fragS * fragp ATTRIBUTE_UNUSED);
static void s3_validate_fix (fixS *fixP);
static int s3_force_relocation (struct fix *fixp);
static bfd_boolean s3_fix_adjustable (fixS * fixP);
static bool s3_fix_adjustable (fixS * fixP);
static void s3_elf_final_processing (void);
static int s3_estimate_size_before_relax (fragS * fragp, asection * sec ATTRIBUTE_UNUSED);
static int s3_relax_frag (asection * sec ATTRIBUTE_UNUSED, fragS * fragp, long stretch ATTRIBUTE_UNUSED);
@ -2544,7 +2544,7 @@ static void
s3_gen_insn_frag (struct s3_score_it *part_1, struct s3_score_it *part_2)
{
char *p;
bfd_boolean pce_p = FALSE;
bool pce_p = false;
int relaxable_p = s3_g_opt;
int relax_size = 0;
struct s3_score_it *inst1 = part_1;
@ -2643,7 +2643,7 @@ s3_gen_insn_frag (struct s3_score_it *part_1, struct s3_score_it *part_2)
}
static void
s3_parse_16_32_inst (char *insnstr, bfd_boolean gen_frag_p)
s3_parse_16_32_inst (char *insnstr, bool gen_frag_p)
{
char c;
char *p;
@ -2693,7 +2693,7 @@ s3_parse_16_32_inst (char *insnstr, bfd_boolean gen_frag_p)
}
static void
s3_parse_48_inst (char *insnstr, bfd_boolean gen_frag_p)
s3_parse_48_inst (char *insnstr, bool gen_frag_p)
{
char c;
char *p;
@ -2740,7 +2740,7 @@ s3_parse_48_inst (char *insnstr, bfd_boolean gen_frag_p)
}
static int
s3_append_insn (char *str, bfd_boolean gen_frag_p)
s3_append_insn (char *str, bool gen_frag_p)
{
int retval = s3_SUCCESS;
@ -4099,7 +4099,7 @@ s3_build_la_pic (int reg_rd, expressionS exp)
For an external symbol: lw rD, <sym>($gp)
(BFD_RELOC_SCORE_GOT15 or BFD_RELOC_SCORE_CALL15) */
sprintf (tmp, "lw_pic r%d, %s", reg_rd, S_GET_NAME (add_symbol));
if (s3_append_insn (tmp, FALSE) == (int) s3_FAIL)
if (s3_append_insn (tmp, false) == (int) s3_FAIL)
return;
if (reg_rd == s3_PIC_CALL_REG)
@ -4113,7 +4113,7 @@ s3_build_la_pic (int reg_rd, expressionS exp)
s3_inst.reloc.type = BFD_RELOC_SCORE_GOT15;
memcpy (&var_insts[0], &s3_inst, sizeof (struct s3_score_it));
sprintf (tmp, "addi_s_pic r%d, %s", reg_rd, S_GET_NAME (add_symbol));
if (s3_append_insn (tmp, FALSE) == (int) s3_FAIL)
if (s3_append_insn (tmp, false) == (int) s3_FAIL)
return;
memcpy (&var_insts[1], &s3_inst, sizeof (struct s3_score_it));
@ -4123,7 +4123,7 @@ s3_build_la_pic (int reg_rd, expressionS exp)
{
/* Insn 1: lw rD, <sym>($gp) (BFD_RELOC_SCORE_GOT15) */
sprintf (tmp, "lw_pic r%d, %s", reg_rd, S_GET_NAME (add_symbol));
if (s3_append_insn (tmp, TRUE) == (int) s3_FAIL)
if (s3_append_insn (tmp, true) == (int) s3_FAIL)
return;
/* Insn 2 */
@ -4132,7 +4132,7 @@ s3_build_la_pic (int reg_rd, expressionS exp)
/* Fix part
For an external symbol: addi rD, <constant> */
sprintf (tmp, "addi r%d, %d", reg_rd, (int)add_number);
if (s3_append_insn (tmp, FALSE) == (int) s3_FAIL)
if (s3_append_insn (tmp, false) == (int) s3_FAIL)
return;
memcpy (&fix_insts[0], &s3_inst, sizeof (struct s3_score_it));
@ -4141,7 +4141,7 @@ s3_build_la_pic (int reg_rd, expressionS exp)
For a local symbol: addi rD, <sym>+<constant> (BFD_RELOC_GOT_LO16) */
sprintf (tmp, "addi_s_pic r%d, %s + %d", reg_rd,
S_GET_NAME (add_symbol), (int) add_number);
if (s3_append_insn (tmp, FALSE) == (int) s3_FAIL)
if (s3_append_insn (tmp, false) == (int) s3_FAIL)
return;
memcpy (&var_insts[0], &s3_inst, sizeof (struct s3_score_it));
@ -4154,7 +4154,7 @@ s3_build_la_pic (int reg_rd, expressionS exp)
/* Insn 1: lw rD, <sym>($gp) (BFD_RELOC_SCORE_GOT15) */
sprintf (tmp, "lw_pic r%d, %s", reg_rd, S_GET_NAME (add_symbol));
if (s3_append_insn (tmp, TRUE) == (int) s3_FAIL)
if (s3_append_insn (tmp, true) == (int) s3_FAIL)
return;
/* Insn 2 */
@ -4163,7 +4163,7 @@ s3_build_la_pic (int reg_rd, expressionS exp)
/* Fix part
For an external symbol: ldis r1, HI%<constant> */
sprintf (tmp, "ldis r1, %d", hi);
if (s3_append_insn (tmp, FALSE) == (int) s3_FAIL)
if (s3_append_insn (tmp, false) == (int) s3_FAIL)
return;
memcpy (&fix_insts[0], &s3_inst, sizeof (struct s3_score_it));
@ -4176,7 +4176,7 @@ s3_build_la_pic (int reg_rd, expressionS exp)
hi += 1;
}
sprintf (tmp, "ldis_pic r1, %d", hi);
if (s3_append_insn (tmp, FALSE) == (int) s3_FAIL)
if (s3_append_insn (tmp, false) == (int) s3_FAIL)
return;
memcpy (&var_insts[0], &s3_inst, sizeof (struct s3_score_it));
@ -4188,7 +4188,7 @@ s3_build_la_pic (int reg_rd, expressionS exp)
/* Fix part
For an external symbol: ori r1, LO%<constant> */
sprintf (tmp, "ori r1, %d", lo);
if (s3_append_insn (tmp, FALSE) == (int) s3_FAIL)
if (s3_append_insn (tmp, false) == (int) s3_FAIL)
return;
memcpy (&fix_insts[0], &s3_inst, sizeof (struct s3_score_it));
@ -4196,7 +4196,7 @@ s3_build_la_pic (int reg_rd, expressionS exp)
/* Var part
For a local symbol: addi r1, <sym>+LO%<constant> (BFD_RELOC_GOT_LO16) */
sprintf (tmp, "addi_u_pic r1, %s + %d", S_GET_NAME (add_symbol), lo);
if (s3_append_insn (tmp, FALSE) == (int) s3_FAIL)
if (s3_append_insn (tmp, false) == (int) s3_FAIL)
return;
memcpy (&var_insts[0], &s3_inst, sizeof (struct s3_score_it));
@ -4204,7 +4204,7 @@ s3_build_la_pic (int reg_rd, expressionS exp)
/* Insn 4: add rD, rD, r1 */
sprintf (tmp, "add r%d, r%d, r1", reg_rd, reg_rd);
if (s3_append_insn (tmp, TRUE) == (int) s3_FAIL)
if (s3_append_insn (tmp, true) == (int) s3_FAIL)
return;
/* Set bwarn as -1, so macro instruction itself will not be generated frag. */
@ -4270,11 +4270,11 @@ s3_do_macro_la_rdi32 (char *str)
if ((s3_score_pic == s3_NO_PIC) || (!s3_inst.reloc.exp.X_add_symbol))
{
sprintf (append_str, "ld_i32hi r%d, %s", reg_rd, keep_data);
if (s3_append_insn (append_str, TRUE) == (int) s3_FAIL)
if (s3_append_insn (append_str, true) == (int) s3_FAIL)
return;
sprintf (append_str, "ld_i32lo r%d, %s", reg_rd, keep_data);
if (s3_append_insn (append_str, TRUE) == (int) s3_FAIL)
if (s3_append_insn (append_str, true) == (int) s3_FAIL)
return;
}
else
@ -4352,12 +4352,12 @@ s3_do_macro_li_rdi32 (char *str)
{
sprintf (append_str, "ld_i32hi r%d, %s", reg_rd, keep_data);
if (s3_append_insn (append_str, TRUE) == (int) s3_FAIL)
if (s3_append_insn (append_str, true) == (int) s3_FAIL)
return;
else
{
sprintf (append_str, "ld_i32lo r%d, %s", reg_rd, keep_data);
if (s3_append_insn (append_str, TRUE) == (int) s3_FAIL)
if (s3_append_insn (append_str, true) == (int) s3_FAIL)
return;
/* Set bwarn as -1, so macro instruction itself will not be generated frag. */
@ -4435,11 +4435,11 @@ s3_do_macro_mul_rdrsrs (char *str)
}
/* Output mul/mulu or div/divu or rem/remu. */
if (s3_append_insn (append_str, TRUE) == (int) s3_FAIL)
if (s3_append_insn (append_str, true) == (int) s3_FAIL)
return;
/* Output mfcel or mfceh. */
if (s3_append_insn (append_str1, TRUE) == (int) s3_FAIL)
if (s3_append_insn (append_str1, true) == (int) s3_FAIL)
return;
/* Set bwarn as -1, so macro instruction itself will not be generated frag. */
@ -4474,7 +4474,7 @@ s3_exp_macro_ldst_abs (char *str)
backupstr = tmp;
sprintf (append_str, "li r1 %s", backupstr);
s3_append_insn (append_str, TRUE);
s3_append_insn (append_str, true);
memcpy (&s3_inst, &inst_backup, sizeof (struct s3_score_it));
sprintf (append_str, " r%d, [r1,0]", reg_rd);
@ -4537,14 +4537,14 @@ s3_do_macro_bcmp (char *str)
if (s3_score_pic == s3_NO_PIC)
{
sprintf (append_str, "cmp! r%d, r%d", reg_a, reg_b);
if (s3_append_insn (append_str, TRUE) == (int) s3_FAIL)
if (s3_append_insn (append_str, true) == (int) s3_FAIL)
goto out;
if ((inst_main.instruction & 0x3e00007e) == 0x0000004c)
memcpy (append_str, "beq ", 4);
else
memcpy (append_str, "bne ", 4);
memmove (append_str + 4, keep_data, strlen (keep_data) + 1);
if (s3_append_insn (append_str, TRUE) == (int) s3_FAIL)
if (s3_append_insn (append_str, true) == (int) s3_FAIL)
goto out;
}
else
@ -4569,7 +4569,7 @@ s3_do_macro_bcmp (char *str)
if (s3_score_pic == s3_NO_PIC)
{
sprintf (append_str, "cmp! r%d, r%d", reg_a, reg_b);
if (s3_append_insn (append_str, FALSE) == (int) s3_FAIL)
if (s3_append_insn (append_str, false) == (int) s3_FAIL)
goto out;
memcpy (&inst_expand[0], &s3_inst, sizeof (struct s3_score_it));
@ -4578,7 +4578,7 @@ s3_do_macro_bcmp (char *str)
else
memcpy (append_str, "bne ", 4);
memmove (append_str + 4, keep_data, strlen (keep_data) + 1);
if (s3_append_insn (append_str, FALSE) == (int) s3_FAIL)
if (s3_append_insn (append_str, false) == (int) s3_FAIL)
goto out;
memcpy (&inst_expand[1], &s3_inst, sizeof (struct s3_score_it));
}
@ -4687,14 +4687,14 @@ s3_do_macro_bcmpz (char *str)
if (s3_score_pic == s3_NO_PIC)
{
sprintf (append_str, "cmpi! r%d, 0", reg_a);
if (s3_append_insn (append_str, TRUE) == (int) s3_FAIL)
if (s3_append_insn (append_str, true) == (int) s3_FAIL)
goto out;
if ((inst_main.instruction & 0x3e00007e) == 0x0000004c)
memcpy (append_str, "beq ", 4);
else
memcpy (append_str, "bne ", 4);
memmove (append_str + 4, keep_data, strlen (keep_data) + 1);
if (s3_append_insn (append_str, TRUE) == (int) s3_FAIL)
if (s3_append_insn (append_str, true) == (int) s3_FAIL)
goto out;
}
else
@ -4719,7 +4719,7 @@ s3_do_macro_bcmpz (char *str)
if (s3_score_pic == s3_NO_PIC)
{
sprintf (append_str, "cmpi! r%d, 0", reg_a);
if (s3_append_insn (append_str, FALSE) == (int) s3_FAIL)
if (s3_append_insn (append_str, false) == (int) s3_FAIL)
goto out;
memcpy (&inst_expand[0], &s3_inst, sizeof (struct s3_score_it));
if ((inst_main.instruction & 0x3e00007e) == 0x0000004c)
@ -4727,7 +4727,7 @@ s3_do_macro_bcmpz (char *str)
else
memcpy (append_str, "bne ", 4);
memmove (append_str + 4, keep_data, strlen (keep_data) + 1);
if (s3_append_insn (append_str, FALSE) == (int) s3_FAIL)
if (s3_append_insn (append_str, false) == (int) s3_FAIL)
goto out;
memcpy (&inst_expand[1], &s3_inst, sizeof (struct s3_score_it));
}
@ -4868,7 +4868,7 @@ s3_build_lwst_pic (int reg_rd, expressionS exp, const char *insn_name)
For an external symbol: lw rD, <sym>($gp)
(BFD_RELOC_SCORE_GOT15) */
sprintf (tmp, "lw_pic r1, %s", S_GET_NAME (add_symbol));
if (s3_append_insn (tmp, FALSE) == (int) s3_FAIL)
if (s3_append_insn (tmp, false) == (int) s3_FAIL)
return;
memcpy (&fix_insts[0], &s3_inst, sizeof (struct s3_score_it));
@ -4880,7 +4880,7 @@ s3_build_lwst_pic (int reg_rd, expressionS exp, const char *insn_name)
s3_inst.reloc.type = BFD_RELOC_SCORE_GOT15;
memcpy (&var_insts[0], &s3_inst, sizeof (struct s3_score_it));
sprintf (tmp, "addi_s_pic r1, %s", S_GET_NAME (add_symbol));
if (s3_append_insn (tmp, FALSE) == (int) s3_FAIL)
if (s3_append_insn (tmp, false) == (int) s3_FAIL)
return;
memcpy (&var_insts[1], &s3_inst, sizeof (struct s3_score_it));
@ -4888,7 +4888,7 @@ s3_build_lwst_pic (int reg_rd, expressionS exp, const char *insn_name)
/* Insn 2 or Insn 3: lw/st rD, [r1, constant] */
sprintf (tmp, "%s r%d, [r1, %d]", insn_name, reg_rd, add_number);
if (s3_append_insn (tmp, TRUE) == (int) s3_FAIL)
if (s3_append_insn (tmp, true) == (int) s3_FAIL)
return;
/* Set bwarn as -1, so macro instruction itself will not be generated frag. */
@ -5032,7 +5032,7 @@ s3_do_macro_ldst_label (char *str)
ld/st rd, [r1, 0] */
for (i = 0; i < 3; i++)
{
if (s3_append_insn (append_str[i], FALSE) == (int) s3_FAIL)
if (s3_append_insn (append_str[i], false) == (int) s3_FAIL)
return;
memcpy (&inst_expand[i], &s3_inst, sizeof (struct s3_score_it));
@ -5282,11 +5282,11 @@ s3_do16_branch (char *str)
}
/* Return true if the given symbol should be considered local for s3_PIC. */
static bfd_boolean
static bool
s3_pic_need_relax (symbolS *sym, asection *segtype)
{
asection *symsec;
bfd_boolean linkonce;
bool linkonce;
/* Handle the case of a symbol equated to another symbol. */
while (symbol_equated_reloc_p (sym))
@ -5304,18 +5304,18 @@ s3_pic_need_relax (symbolS *sym, asection *segtype)
symsec = S_GET_SEGMENT (sym);
/* duplicate the test for LINK_ONCE sections as in adjust_reloc_syms */
linkonce = FALSE;
linkonce = false;
if (symsec != segtype && ! S_IS_LOCAL (sym))
{
if ((bfd_section_flags (symsec) & SEC_LINK_ONCE) != 0)
linkonce = TRUE;
linkonce = true;
/* The GNU toolchain uses an extension for ELF: a section
beginning with the magic string .gnu.linkonce is a linkonce
section. */
if (strncmp (segment_name (symsec), ".gnu.linkonce",
sizeof ".gnu.linkonce" - 1) == 0)
linkonce = TRUE;
linkonce = true;
}
/* This must duplicate the test in adjust_reloc_syms. */
@ -5351,13 +5351,13 @@ s3_parse_pce_inst (char *insnstr)
p += 2;
sprintf (second, "%s", p);
s3_parse_16_32_inst (first, FALSE);
s3_parse_16_32_inst (first, false);
if (s3_inst.error)
return;
memcpy (&pec_part_1, &s3_inst, sizeof (s3_inst));
s3_parse_16_32_inst (second, FALSE);
s3_parse_16_32_inst (second, false);
if (s3_inst.error)
return;
@ -5933,15 +5933,15 @@ s3_s_score_cpload (int ignore ATTRIBUTE_UNUSED)
demand_empty_rest_of_line ();
sprintf (insn_str, "ld_i32hi r%d, %s", s3_GP, GP_DISP_LABEL);
if (s3_append_insn (insn_str, TRUE) == (int) s3_FAIL)
if (s3_append_insn (insn_str, true) == (int) s3_FAIL)
return;
sprintf (insn_str, "ld_i32lo r%d, %s", s3_GP, GP_DISP_LABEL);
if (s3_append_insn (insn_str, TRUE) == (int) s3_FAIL)
if (s3_append_insn (insn_str, true) == (int) s3_FAIL)
return;
sprintf (insn_str, "add r%d, r%d, r%d", s3_GP, s3_GP, reg);
if (s3_append_insn (insn_str, TRUE) == (int) s3_FAIL)
if (s3_append_insn (insn_str, true) == (int) s3_FAIL)
return;
}
@ -5973,7 +5973,7 @@ s3_s_score_cprestore (int ignore ATTRIBUTE_UNUSED)
if (cprestore_offset <= 0x3fff)
{
sprintf (insn_str, "sw r%d, [r%d, %d]", s3_GP, reg, cprestore_offset);
if (s3_append_insn (insn_str, TRUE) == (int) s3_FAIL)
if (s3_append_insn (insn_str, true) == (int) s3_FAIL)
return;
}
else
@ -5984,15 +5984,15 @@ s3_s_score_cprestore (int ignore ATTRIBUTE_UNUSED)
s3_nor1 = 0;
sprintf (insn_str, "li r1, %d", cprestore_offset);
if (s3_append_insn (insn_str, TRUE) == (int) s3_FAIL)
if (s3_append_insn (insn_str, true) == (int) s3_FAIL)
return;
sprintf (insn_str, "add r1, r1, r%d", reg);
if (s3_append_insn (insn_str, TRUE) == (int) s3_FAIL)
if (s3_append_insn (insn_str, true) == (int) s3_FAIL)
return;
sprintf (insn_str, "sw r%d, [r1]", s3_GP);
if (s3_append_insn (insn_str, TRUE) == (int) s3_FAIL)
if (s3_append_insn (insn_str, true) == (int) s3_FAIL)
return;
s3_nor1 = r1_bak;
@ -6023,7 +6023,7 @@ s3_s_score_gpword (int ignore ATTRIBUTE_UNUSED)
}
p = frag_more (4);
s3_md_number_to_chars (p, (valueT) 0, 4);
fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE, BFD_RELOC_GPREL32);
fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, false, BFD_RELOC_GPREL32);
demand_empty_rest_of_line ();
}
@ -6050,7 +6050,7 @@ s3_s_score_cpadd (int ignore ATTRIBUTE_UNUSED)
/* Add $gp to the register named as an argument. */
sprintf (insn_str, "add r%d, r%d, r%d", reg, reg, s3_GP);
if (s3_append_insn (insn_str, TRUE) == (int) s3_FAIL)
if (s3_append_insn (insn_str, true) == (int) s3_FAIL)
return;
}
@ -6474,9 +6474,9 @@ s3_assemble (char *str)
if (s3_INSN_IS_PCE_P (str))
s3_parse_pce_inst (str);
else if (s3_INSN_IS_48_P (str))
s3_parse_48_inst (str, TRUE);
s3_parse_48_inst (str, true);
else
s3_parse_16_32_inst (str, TRUE);
s3_parse_16_32_inst (str, true);
if (s3_inst.error)
as_bad (_("%s -- `%s'"), s3_inst.error, s3_inst.str);
@ -6723,7 +6723,7 @@ s3_force_relocation (struct fix *fixp)
return retval;
}
static bfd_boolean
static bool
s3_fix_adjustable (fixS * fixP)
{
if (fixP->fx_addsy == NULL)
@ -7552,7 +7552,7 @@ score_force_relocation (struct fix *fixp)
/* Implementation of md_frag_check.
Called after md_convert_frag(). */
bfd_boolean
bool
score_fix_adjustable (fixS * fixP)
{
if (score3)

2
gas/config/tc-score.h
View File

@ -49,7 +49,7 @@ extern void score_validate_fix (struct fix *);
extern int score_force_relocation (struct fix *);
#define tc_fix_adjustable(fixp) score_fix_adjustable (fixp)
extern bfd_boolean score_fix_adjustable (struct fix *);
extern bool score_fix_adjustable (struct fix *);
#define elf_tc_final_processing score_elf_final_processing
extern void score_elf_final_processing (void);

92
gas/config/tc-score7.c
View File

@ -2665,7 +2665,7 @@ static void
s7_gen_insn_frag (struct s7_score_it *part_1, struct s7_score_it *part_2)
{
char *p;
bfd_boolean pce_p = FALSE;
bool pce_p = false;
int relaxable_p = s7_g_opt;
int relax_size = 0;
struct s7_score_it *inst1 = part_1;
@ -2770,7 +2770,7 @@ s7_gen_insn_frag (struct s7_score_it *part_1, struct s7_score_it *part_2)
}
static void
s7_parse_16_32_inst (char *insnstr, bfd_boolean gen_frag_p)
s7_parse_16_32_inst (char *insnstr, bool gen_frag_p)
{
char c;
char *p;
@ -2820,7 +2820,7 @@ s7_parse_16_32_inst (char *insnstr, bfd_boolean gen_frag_p)
}
static int
s7_append_insn (char *str, bfd_boolean gen_frag_p)
s7_append_insn (char *str, bool gen_frag_p)
{
int retval = s7_SUCCESS;
@ -2872,7 +2872,7 @@ s7_do16_mv_rdrs (char *str)
char append_str[s7_MAX_LITERAL_POOL_SIZE];
sprintf (append_str, "mlfh! %s", backupstr);
if (s7_append_insn (append_str, TRUE) == (int) s7_FAIL)
if (s7_append_insn (append_str, true) == (int) s7_FAIL)
return;
/* Set bwarn as -1, so macro instruction itself will not be generated frag. */
s7_inst.bwarn = -1;
@ -2891,7 +2891,7 @@ s7_do16_mv_rdrs (char *str)
char append_str[s7_MAX_LITERAL_POOL_SIZE];
sprintf (append_str, "mhfl! %s", backupstr);
if (s7_append_insn (append_str, TRUE) == (int) s7_FAIL)
if (s7_append_insn (append_str, true) == (int) s7_FAIL)
return;
/* Set bwarn as -1, so macro instruction itself will not be generated frag. */
@ -4201,7 +4201,7 @@ s7_build_la_pic (int reg_rd, expressionS exp)
For an external symbol: lw rD, <sym>($gp)
(BFD_RELOC_SCORE_GOT15 or BFD_RELOC_SCORE_CALL15) */
sprintf (tmp, "lw_pic r%d, %s", reg_rd, S_GET_NAME (add_symbol));
if (s7_append_insn (tmp, FALSE) == (int) s7_FAIL)
if (s7_append_insn (tmp, false) == (int) s7_FAIL)
return;
if (reg_rd == s7_PIC_CALL_REG)
@ -4215,7 +4215,7 @@ s7_build_la_pic (int reg_rd, expressionS exp)
s7_inst.reloc.type = BFD_RELOC_SCORE_GOT15;
memcpy (&var_insts[0], &s7_inst, sizeof (struct s7_score_it));
sprintf (tmp, "addi_s_pic r%d, %s", reg_rd, S_GET_NAME (add_symbol));
if (s7_append_insn (tmp, FALSE) == (int) s7_FAIL)
if (s7_append_insn (tmp, false) == (int) s7_FAIL)
return;
memcpy (&var_insts[1], &s7_inst, sizeof (struct s7_score_it));
@ -4225,7 +4225,7 @@ s7_build_la_pic (int reg_rd, expressionS exp)
{
/* Insn 1: lw rD, <sym>($gp) (BFD_RELOC_SCORE_GOT15) */
sprintf (tmp, "lw_pic r%d, %s", reg_rd, S_GET_NAME (add_symbol));
if (s7_append_insn (tmp, TRUE) == (int) s7_FAIL)
if (s7_append_insn (tmp, true) == (int) s7_FAIL)
return;
/* Insn 2 */
@ -4234,7 +4234,7 @@ s7_build_la_pic (int reg_rd, expressionS exp)
/* Fix part
For an external symbol: addi rD, <constant> */
sprintf (tmp, "addi r%d, %d", reg_rd, (int) add_number);
if (s7_append_insn (tmp, FALSE) == (int) s7_FAIL)
if (s7_append_insn (tmp, false) == (int) s7_FAIL)
return;
memcpy (&fix_insts[0], &s7_inst, sizeof (struct s7_score_it));
@ -4243,7 +4243,7 @@ s7_build_la_pic (int reg_rd, expressionS exp)
For a local symbol: addi rD, <sym>+<constant> (BFD_RELOC_GOT_LO16) */
sprintf (tmp, "addi_s_pic r%d, %s + %d", reg_rd,
S_GET_NAME (add_symbol), (int) add_number);
if (s7_append_insn (tmp, FALSE) == (int) s7_FAIL)
if (s7_append_insn (tmp, false) == (int) s7_FAIL)
return;
memcpy (&var_insts[0], &s7_inst, sizeof (struct s7_score_it));
@ -4256,7 +4256,7 @@ s7_build_la_pic (int reg_rd, expressionS exp)
/* Insn 1: lw rD, <sym>($gp) (BFD_RELOC_SCORE_GOT15) */
sprintf (tmp, "lw_pic r%d, %s", reg_rd, S_GET_NAME (add_symbol));
if (s7_append_insn (tmp, TRUE) == (int) s7_FAIL)
if (s7_append_insn (tmp, true) == (int) s7_FAIL)
return;
/* Insn 2 */
@ -4265,7 +4265,7 @@ s7_build_la_pic (int reg_rd, expressionS exp)
/* Fix part
For an external symbol: ldis r1, HI%<constant> */
sprintf (tmp, "ldis r1, %d", hi);
if (s7_append_insn (tmp, FALSE) == (int) s7_FAIL)
if (s7_append_insn (tmp, false) == (int) s7_FAIL)
return;
memcpy (&fix_insts[0], &s7_inst, sizeof (struct s7_score_it));
@ -4278,7 +4278,7 @@ s7_build_la_pic (int reg_rd, expressionS exp)
hi += 1;
}
sprintf (tmp, "ldis_pic r1, %d", hi);
if (s7_append_insn (tmp, FALSE) == (int) s7_FAIL)
if (s7_append_insn (tmp, false) == (int) s7_FAIL)
return;
memcpy (&var_insts[0], &s7_inst, sizeof (struct s7_score_it));
@ -4290,7 +4290,7 @@ s7_build_la_pic (int reg_rd, expressionS exp)
/* Fix part
For an external symbol: ori r1, LO%<constant> */
sprintf (tmp, "ori r1, %d", lo);
if (s7_append_insn (tmp, FALSE) == (int) s7_FAIL)
if (s7_append_insn (tmp, false) == (int) s7_FAIL)
return;
memcpy (&fix_insts[0], &s7_inst, sizeof (struct s7_score_it));
@ -4298,7 +4298,7 @@ s7_build_la_pic (int reg_rd, expressionS exp)
/* Var part
For a local symbol: addi r1, <sym>+LO%<constant> (BFD_RELOC_GOT_LO16) */
sprintf (tmp, "addi_u_pic r1, %s + %d", S_GET_NAME (add_symbol), lo);
if (s7_append_insn (tmp, FALSE) == (int) s7_FAIL)
if (s7_append_insn (tmp, false) == (int) s7_FAIL)
return;
memcpy (&var_insts[0], &s7_inst, sizeof (struct s7_score_it));
@ -4306,7 +4306,7 @@ s7_build_la_pic (int reg_rd, expressionS exp)
/* Insn 4: add rD, rD, r1 */
sprintf (tmp, "add r%d, r%d, r1", reg_rd, reg_rd);
if (s7_append_insn (tmp, TRUE) == (int) s7_FAIL)
if (s7_append_insn (tmp, true) == (int) s7_FAIL)
return;
/* Set bwarn as -1, so macro instruction itself will not be generated frag. */
@ -4371,11 +4371,11 @@ s7_do_macro_la_rdi32 (char *str)
if ((s7_score_pic == s7_NO_PIC) || (!s7_inst.reloc.exp.X_add_symbol))
{
sprintf (append_str, "ld_i32hi r%d, %s", reg_rd, keep_data);
if (s7_append_insn (append_str, TRUE) == (int) s7_FAIL)
if (s7_append_insn (append_str, true) == (int) s7_FAIL)
return;
sprintf (append_str, "ld_i32lo r%d, %s", reg_rd, keep_data);
if (s7_append_insn (append_str, TRUE) == (int) s7_FAIL)
if (s7_append_insn (append_str, true) == (int) s7_FAIL)
return;
}
else
@ -4451,12 +4451,12 @@ s7_do_macro_li_rdi32 (char *str)
{
sprintf (append_str, "ld_i32hi r%d, %s", reg_rd, keep_data);
if (s7_append_insn (append_str, TRUE) == (int) s7_FAIL)
if (s7_append_insn (append_str, true) == (int) s7_FAIL)
return;
else
{
sprintf (append_str, "ld_i32lo r%d, %s", reg_rd, keep_data);
if (s7_append_insn (append_str, TRUE) == (int) s7_FAIL)
if (s7_append_insn (append_str, true) == (int) s7_FAIL)
return;
/* Set bwarn as -1, so macro instruction itself will not be generated frag. */
@ -4535,11 +4535,11 @@ s7_do_macro_mul_rdrsrs (char *str)
}
/* Output mul/mulu or div/divu or rem/remu. */
if (s7_append_insn (append_str, TRUE) == (int) s7_FAIL)
if (s7_append_insn (append_str, true) == (int) s7_FAIL)
return;
/* Output mfcel or mfceh. */
if (s7_append_insn (append_str1, TRUE) == (int) s7_FAIL)
if (s7_append_insn (append_str1, true) == (int) s7_FAIL)
return;
/* Set bwarn as -1, so macro instruction itself will not be generated frag. */
@ -4574,7 +4574,7 @@ s7_exp_macro_ldst_abs (char *str)
backupstr = tmp;
sprintf (append_str, "li r1 %s", backupstr);
s7_append_insn (append_str, TRUE);
s7_append_insn (append_str, true);
memcpy (&s7_inst, &inst_backup, sizeof (struct s7_score_it));
sprintf (append_str, " r%d, [r1,0]", reg_rd);
@ -4663,7 +4663,7 @@ s7_build_lwst_pic (int reg_rd, expressionS exp, const char *insn_name)
For an external symbol: lw rD, <sym>($gp)
(BFD_RELOC_SCORE_GOT15) */
sprintf (tmp, "lw_pic r1, %s", S_GET_NAME (add_symbol));
if (s7_append_insn (tmp, FALSE) == (int) s7_FAIL)
if (s7_append_insn (tmp, false) == (int) s7_FAIL)
return;
memcpy (&fix_insts[0], &s7_inst, sizeof (struct s7_score_it));
@ -4675,7 +4675,7 @@ s7_build_lwst_pic (int reg_rd, expressionS exp, const char *insn_name)
s7_inst.reloc.type = BFD_RELOC_SCORE_GOT15;
memcpy (&var_insts[0], &s7_inst, sizeof (struct s7_score_it));
sprintf (tmp, "addi_s_pic r1, %s", S_GET_NAME (add_symbol));
if (s7_append_insn (tmp, FALSE) == (int) s7_FAIL)
if (s7_append_insn (tmp, false) == (int) s7_FAIL)
return;
memcpy (&var_insts[1], &s7_inst, sizeof (struct s7_score_it));
@ -4683,7 +4683,7 @@ s7_build_lwst_pic (int reg_rd, expressionS exp, const char *insn_name)
/* Insn 2 or Insn 3: lw/st rD, [r1, constant] */
sprintf (tmp, "%s r%d, [r1, %d]", insn_name, reg_rd, add_number);
if (s7_append_insn (tmp, TRUE) == (int) s7_FAIL)
if (s7_append_insn (tmp, true) == (int) s7_FAIL)
return;
/* Set bwarn as -1, so macro instruction itself will not be generated frag. */
@ -4827,7 +4827,7 @@ s7_do_macro_ldst_label (char *str)
ld/st rd, [r1, 0] */
for (i = 0; i < 3; i++)
{
if (s7_append_insn (append_str[i], FALSE) == (int) s7_FAIL)
if (s7_append_insn (append_str[i], false) == (int) s7_FAIL)
return;
memcpy (&inst_expand[i], &s7_inst, sizeof (struct s7_score_it));
@ -5164,11 +5164,11 @@ s7_md_chars_to_number (char *buf, int n)
/* Return true if the given symbol should be considered local for s7_PIC. */
static bfd_boolean
static bool
s7_pic_need_relax (symbolS *sym, asection *segtype)
{
asection *symsec;
bfd_boolean linkonce;
bool linkonce;
/* Handle the case of a symbol equated to another symbol. */
while (symbol_equated_reloc_p (sym))
@ -5186,18 +5186,18 @@ s7_pic_need_relax (symbolS *sym, asection *segtype)
symsec = S_GET_SEGMENT (sym);
/* Duplicate the test for LINK_ONCE sections as in adjust_reloc_syms */
linkonce = FALSE;
linkonce = false;
if (symsec != segtype && ! S_IS_LOCAL (sym))
{
if ((bfd_section_flags (symsec) & SEC_LINK_ONCE) != 0)
linkonce = TRUE;
linkonce = true;
/* The GNU toolchain uses an extension for ELF: a section
beginning with the magic string .gnu.linkonce is a linkonce
section. */
if (strncmp (segment_name (symsec), ".gnu.linkonce",
sizeof ".gnu.linkonce" - 1) == 0)
linkonce = TRUE;
linkonce = true;
}
/* This must duplicate the test in adjust_reloc_syms. */
@ -5313,7 +5313,7 @@ s7_parse_pce_inst (char *insnstr)
p += 2;
strcpy (second, p);
s7_parse_16_32_inst (first, FALSE);
s7_parse_16_32_inst (first, false);
if (s7_inst.error)
return;
@ -5326,7 +5326,7 @@ s7_parse_pce_inst (char *insnstr)
q++;
}
s7_parse_16_32_inst (second, FALSE);
s7_parse_16_32_inst (second, false);
if (s7_inst.error)
return;
@ -5779,15 +5779,15 @@ s7_s_score_cpload (int ignore ATTRIBUTE_UNUSED)
demand_empty_rest_of_line ();
sprintf (insn_str, "ld_i32hi r%d, %s", s7_GP, GP_DISP_LABEL);
if (s7_append_insn (insn_str, TRUE) == (int) s7_FAIL)
if (s7_append_insn (insn_str, true) == (int) s7_FAIL)
return;
sprintf (insn_str, "ld_i32lo r%d, %s", s7_GP, GP_DISP_LABEL);
if (s7_append_insn (insn_str, TRUE) == (int) s7_FAIL)
if (s7_append_insn (insn_str, true) == (int) s7_FAIL)
return;
sprintf (insn_str, "add r%d, r%d, r%d", s7_GP, s7_GP, reg);
if (s7_append_insn (insn_str, TRUE) == (int) s7_FAIL)
if (s7_append_insn (insn_str, true) == (int) s7_FAIL)
return;
}
@ -5820,7 +5820,7 @@ s7_s_score_cprestore (int ignore ATTRIBUTE_UNUSED)
if (cprestore_offset <= 0x3fff)
{
sprintf (insn_str, "sw r%d, [r%d, %d]", s7_GP, reg, cprestore_offset);
if (s7_append_insn (insn_str, TRUE) == (int) s7_FAIL)
if (s7_append_insn (insn_str, true) == (int) s7_FAIL)
return;
}
else
@ -5831,15 +5831,15 @@ s7_s_score_cprestore (int ignore ATTRIBUTE_UNUSED)
s7_nor1 = 0;
sprintf (insn_str, "li r1, %d", cprestore_offset);
if (s7_append_insn (insn_str, TRUE) == (int) s7_FAIL)
if (s7_append_insn (insn_str, true) == (int) s7_FAIL)
return;
sprintf (insn_str, "add r1, r1, r%d", reg);
if (s7_append_insn (insn_str, TRUE) == (int) s7_FAIL)
if (s7_append_insn (insn_str, true) == (int) s7_FAIL)
return;
sprintf (insn_str, "sw r%d, [r1]", s7_GP);
if (s7_append_insn (insn_str, TRUE) == (int) s7_FAIL)
if (s7_append_insn (insn_str, true) == (int) s7_FAIL)
return;
s7_nor1 = r1_bak;
@ -5871,7 +5871,7 @@ s7_s_score_gpword (int ignore ATTRIBUTE_UNUSED)
}
p = frag_more (4);
s7_number_to_chars (p, (valueT) 0, 4);
fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE, BFD_RELOC_GPREL32);
fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, false, BFD_RELOC_GPREL32);
demand_empty_rest_of_line ();
}
@ -5899,7 +5899,7 @@ s7_s_score_cpadd (int ignore ATTRIBUTE_UNUSED)
/* Add $gp to the register named as an argument. */
sprintf (insn_str, "add r%d, r%d, r%d", reg, reg, s7_GP);
if (s7_append_insn (insn_str, TRUE) == (int) s7_FAIL)
if (s7_append_insn (insn_str, true) == (int) s7_FAIL)
return;
}
@ -6147,7 +6147,7 @@ s7_assemble (char *str)
if (s7_INSN_IS_PCE_P (str))
s7_parse_pce_inst (str);
else
s7_parse_16_32_inst (str, TRUE);
s7_parse_16_32_inst (str, true);
if (s7_inst.error)
as_bad (_("%s -- `%s'"), s7_inst.error, s7_inst.str);
@ -6276,7 +6276,7 @@ s7_force_relocation (struct fix *fixp)
return retval;
}
static bfd_boolean
static bool
s7_fix_adjustable (fixS * fixP)
{
if (fixP->fx_addsy == NULL)
@ -6342,7 +6342,7 @@ s7_relax_frag (asection * sec ATTRIBUTE_UNUSED,
int insn_size;
int do_relax_p = 0; /* Indicate doing relaxation for this frag. */
int relaxable_p = 0;
bfd_boolean word_align_p = FALSE;
bool word_align_p = false;
fragS *next_fragp;
/* If the instruction address is odd, make it half word align first. */

20
gas/config/tc-sh.c
View File

@ -461,7 +461,7 @@ sh_elf_cons (int nbytes)
/* The regular frag_offset_fixed_p doesn't work for rs_align_test
frags. */
static bfd_boolean
static bool
align_test_frag_offset_fixed_p (const fragS *frag1, const fragS *frag2,
bfd_vma *offset)
{
@ -474,7 +474,7 @@ align_test_frag_offset_fixed_p (const fragS *frag1, const fragS *frag2,
if (frag1 == frag2)
{
*offset = off;
return TRUE;
return true;
}
/* Maybe frag2 is after frag1. */
@ -492,7 +492,7 @@ align_test_frag_offset_fixed_p (const fragS *frag1, const fragS *frag2,
if (frag == frag2)
{
*offset = off;
return TRUE;
return true;
}
}
@ -512,11 +512,11 @@ align_test_frag_offset_fixed_p (const fragS *frag1, const fragS *frag2,
if (frag == frag1)
{
*offset = off;
return TRUE;
return true;
}
}
return FALSE;
return false;
}
/* Optimize a difference of symbols which have rs_align_test frag if
@ -2526,7 +2526,7 @@ md_assemble (char *str)
char *name = initial_str;
int name_length = 0;
const sh_opcode_info *op;
bfd_boolean found = FALSE;
bool found = false;
/* Identify opcode in string. */
while (ISSPACE (*name))
@ -2541,7 +2541,7 @@ md_assemble (char *str)
if (strncasecmp (op->name, name, name_length) == 0
&& op->name[name_length] == '\0')
{
found = TRUE;
found = true;
break;
}
}
@ -2824,7 +2824,7 @@ md_parse_option (int c, const char *arg ATTRIBUTE_UNUSED)
#ifdef OBJ_ELF
case OPTION_FDPIC:
sh_fdpic = TRUE;
sh_fdpic = true;
break;
#endif /* OBJ_ELF */
@ -3278,7 +3278,7 @@ sh_handle_align (fragS *frag)
/* See whether the relocation should be resolved locally. */
static bfd_boolean
static bool
sh_local_pcrel (fixS *fix)
{
return (! sh_relax
@ -3327,7 +3327,7 @@ sh_force_relocation (fixS *fix)
}
#ifdef OBJ_ELF
bfd_boolean
bool
sh_fix_adjustable (fixS *fixP)
{
if (fixP->fx_r_type == BFD_RELOC_32_PLT_PCREL

2
gas/config/tc-sh.h
View File

@ -185,7 +185,7 @@ extern void sh_elf_final_processing (void);
#define TC_RELOC_GLOBAL_OFFSET_TABLE BFD_RELOC_SH_GOTPC
#define tc_fix_adjustable(FIX) sh_fix_adjustable(FIX)
extern bfd_boolean sh_fix_adjustable (struct fix *);
extern bool sh_fix_adjustable (struct fix *);
/* Values passed to md_apply_fix don't include symbol values. */
#define MD_APPLY_SYM_VALUE(FIX) 0

2
gas/config/tc-spu.c
View File

@ -707,7 +707,7 @@ get_imm (const char *param, struct spu_insn *insn, int arg)
const char *
md_atof (int type, char *litP, int *sizeP)
{
return ieee_md_atof (type, litP, sizeP, TRUE);
return ieee_md_atof (type, litP, sizeP, true);
}
#ifndef WORKING_DOT_WORD

4
gas/config/tc-tic54x.c
View File

@ -3986,7 +3986,7 @@ emit_insn (tic54x_insn *insn)
if (insn->opcode[i].unresolved)
fix_new_exp (frag_now, p - frag_now->fr_literal,
insn->opcode[i].r_nchars, &insn->opcode[i].addr_expr,
FALSE, insn->opcode[i].r_type);
false, insn->opcode[i].r_type);
}
}
@ -5037,7 +5037,7 @@ md_atof (int type, char *literalP, int *sizeP)
{
/* Target data is little-endian, but floats are stored
big-"word"ian. ugh. */
return ieee_md_atof (type, literalP, sizeP, TRUE);
return ieee_md_atof (type, literalP, sizeP, true);
}
arelent *

359
gas/config/tc-tic6x.c
View File

File diff suppressed because it is too large Load Diff

16
gas/config/tc-tic6x.h
View File

@ -62,14 +62,14 @@ typedef struct tic6x_unwind_info {
int data_bytes;
offsetT reg_offset[TIC6X_NUM_UNWIND_REGS];
bfd_boolean reg_saved[TIC6X_NUM_UNWIND_REGS];
bool reg_saved[TIC6X_NUM_UNWIND_REGS];
int cfa_reg;
int return_reg;
unsigned safe_mask;
unsigned compact_mask;
unsigned reg_saved_mask;
offsetT cfa_offset;
bfd_boolean pop_rts;
bool pop_rts;
/* Only valid for UNWIND_OP_POP_REG */
int saved_reg_count;
} tic6x_unwind_info;
@ -82,7 +82,7 @@ typedef struct
tic6x_label_list *label_list;
/* Whether compact instructions are forbidden here. */
bfd_boolean nocmp;
bool nocmp;
/* If there is a current execute packet, the frag being used for
that execute packet. */
@ -123,11 +123,11 @@ typedef struct
{
/* Whether this machine-dependent frag is used for instructions (as
opposed to code alignment). */
bfd_boolean is_insns;
bool is_insns;
/* For a frag used for instructions, whether it is may cross a fetch
packet boundary (subject to alignment requirements). */
bfd_boolean can_cross_fp_boundary;
bool can_cross_fp_boundary;
} tic6x_frag_info;
#define TC_FRAG_TYPE tic6x_frag_info
#define TC_FRAG_INIT(fragP, max_bytes) tic6x_frag_init (fragP)
@ -140,7 +140,7 @@ typedef struct
left (it represents a value to be encoded literally in the
instruction, whereas a non-constant represents a DP-relative
value counting in the appropriate units). */
bfd_boolean fix_adda;
bool fix_adda;
/* The symbol to be subtracted in case of a PCR_H16 or PCR_L16
reloc. */
symbolS *fix_subsy;
@ -164,7 +164,7 @@ extern void tic6x_cons_align (int n);
if (tic6x_do_align (n, fill, len, max)) \
goto label; \
} while (0)
extern bfd_boolean tic6x_do_align (int n, char *fill, int len, int max);
extern bool tic6x_do_align (int n, char *fill, int len, int max);
#define CONVERT_SYMBOLIC_ATTRIBUTE(name) \
tic6x_convert_symbolic_attribute (name)
@ -190,7 +190,7 @@ extern void tic6x_cons_fix_new (fragS *, int, int, expressionS *,
bfd_reloc_code_real_type);
#define tc_fix_adjustable(FIX) tic6x_fix_adjustable (FIX)
extern bfd_boolean tic6x_fix_adjustable (struct fix *);
extern bool tic6x_fix_adjustable (struct fix *);
#define tc_frob_label(sym) tic6x_frob_label (sym)
extern void tic6x_frob_label (symbolS *sym);

4
gas/config/tc-tilegx.c
View File

@ -891,7 +891,7 @@ tilegx_flush_bundle (void)
/* Make sure all instructions can be bundled with other
instructions. */
const struct tilegx_opcode *cannot_bundle = NULL;
bfd_boolean seen_non_nop = FALSE;
bool seen_non_nop = false;
for (j = 0; j < current_bundle_index; j++)
{
@ -902,7 +902,7 @@ tilegx_flush_bundle (void)
else if (op->mnemonic != TILEGX_OPC_NOP
&& op->mnemonic != TILEGX_OPC_INFO
&& op->mnemonic != TILEGX_OPC_INFOL)
seen_non_nop = TRUE;
seen_non_nop = true;
}
if (cannot_bundle != NULL && seen_non_nop)

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