RISC-V: Better support for long instructions (assembler)
Commit bb996692bd96 ("RISC-V/gas: allow generating up to 176-bit instructions with .insn") tried to start supporting long instructions but it was insufficient. 1. It heavily depended on the bignum internals (radix of 2^16), 2. It generates "value conflicts with instruction length" even if a big number instruction encoding does not exceed its expected length and 3. Because long opcode was handled separately (from struct riscv_cl_insn), some information like DWARF line number correspondence was missing. To resolve these problems, this commit: 1. Handles bignum (and its encodings) precisely and 2. Incorporates long opcode handling into regular instruction handling. This commit will be tested on the separate commit. gas/ChangeLog: * config/tc-riscv.c (struct riscv_cl_insn): Add long opcode field. (create_insn) Clear long opcode marker. (install_insn) Install longer opcode as well. (s_riscv_insn) Likewise. (riscv_ip_hardcode): Make big number handling stricter. Length and the value conflicts only if the bignum size exceeds the expected maximum length.
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@ -42,9 +42,13 @@ struct riscv_cl_insn
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/* The opcode's entry in riscv_opcodes. */
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const struct riscv_opcode *insn_mo;
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/* The encoded instruction bits. */
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/* The encoded instruction bits
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(first bits enough to extract instruction length on a long opcode). */
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insn_t insn_opcode;
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/* The long encoded instruction bits ([0] is non-zero on a long opcode). */
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char insn_long_opcode[RISCV_MAX_INSN_LEN];
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/* The frag that contains the instruction. */
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struct frag *frag;
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@ -720,6 +724,7 @@ create_insn (struct riscv_cl_insn *insn, const struct riscv_opcode *mo)
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{
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insn->insn_mo = mo;
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insn->insn_opcode = mo->match;
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insn->insn_long_opcode[0] = 0;
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insn->frag = NULL;
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insn->where = 0;
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insn->fixp = NULL;
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@ -731,7 +736,10 @@ static void
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install_insn (const struct riscv_cl_insn *insn)
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{
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char *f = insn->frag->fr_literal + insn->where;
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number_to_chars_littleendian (f, insn->insn_opcode, insn_length (insn));
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if (insn->insn_long_opcode[0] != 0)
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memcpy (f, insn->insn_long_opcode, insn_length (insn));
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else
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number_to_chars_littleendian (f, insn->insn_opcode, insn_length (insn));
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}
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/* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly
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@ -3503,7 +3511,9 @@ riscv_ip_hardcode (char *str,
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values[num++] = (insn_t) imm_expr->X_add_number;
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break;
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case O_big:
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values[num++] = generic_bignum[0];
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/* Extract lower 32-bits of a big number.
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Assume that generic_bignum_to_int32 work on such number. */
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values[num++] = (insn_t) generic_bignum_to_int32 ();
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break;
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default:
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/* The first value isn't constant, so it should be
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@ -3530,12 +3540,25 @@ riscv_ip_hardcode (char *str,
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if (imm_expr->X_op == O_big)
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{
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if (bytes != imm_expr->X_add_number * CHARS_PER_LITTLENUM)
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unsigned int llen = 0;
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for (LITTLENUM_TYPE lval = generic_bignum[imm_expr->X_add_number - 1];
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lval != 0; llen++)
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lval >>= BITS_PER_CHAR;
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unsigned int repr_bytes
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= (imm_expr->X_add_number - 1) * CHARS_PER_LITTLENUM + llen;
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if (bytes < repr_bytes)
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return _("value conflicts with instruction length");
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char *f = frag_more (bytes);
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for (num = 0; num < imm_expr->X_add_number; ++num)
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number_to_chars_littleendian (f + num * CHARS_PER_LITTLENUM,
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generic_bignum[num], CHARS_PER_LITTLENUM);
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for (num = 0; num < imm_expr->X_add_number - 1; ++num)
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number_to_chars_littleendian (
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ip->insn_long_opcode + num * CHARS_PER_LITTLENUM,
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generic_bignum[num],
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CHARS_PER_LITTLENUM);
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if (llen != 0)
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number_to_chars_littleendian (
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ip->insn_long_opcode + num * CHARS_PER_LITTLENUM,
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generic_bignum[num],
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llen);
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memset(ip->insn_long_opcode + repr_bytes, 0, bytes - repr_bytes);
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return NULL;
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}
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@ -4612,7 +4635,7 @@ s_riscv_insn (int x ATTRIBUTE_UNUSED)
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else
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as_bad ("%s `%s'", error.msg, error.statement);
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}
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else if (imm_expr.X_op != O_big)
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else
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{
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gas_assert (insn.insn_mo->pinfo != INSN_MACRO);
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append_insn (&insn, &imm_expr, imm_reloc);
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