opcodes: microblaze: Add new bit-field instructions
This patches adds new bsefi and bsifi instructions. BSEFI- The instruction shall extract a bit field from a register and place it right-adjusted in the destination register. The other bits in the destination register shall be set to zero. BSIFI- The instruction shall insert a right-adjusted bit field from a register at another position in the destination register. The rest of the bits in the destination register shall be unchanged. Further documentation of these instructions can be found here: https://docs.xilinx.com/v/u/en-US/ug984-vivado-microblaze-ref This patch has been tested for years of AMD Xilinx Yocto releases as part of the following patch set: https://github.com/Xilinx/meta-xilinx/tree/master/meta-microblaze/recipes-devtools/binutils/binutils Signed-off-by: nagaraju <nagaraju.mekala@amd.com> Signed-off-by: Ibai Erkiaga <ibai.erkiaga-elorza@amd.com> Signed-off-by: Neal Frager <neal.frager@amd.com> Signed-off-by: Michael J. Eager <eager@eagercon.com>
This commit is contained in:
Neal Frager
Michael J. Eager
parent
9a896be332
commit
6bbf249557
@ -6461,6 +6461,11 @@ value relative to the read-write small data area anchor */
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expressions of the form "Symbol Op Symbol" */
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BFD_RELOC_MICROBLAZE_32_SYM_OP_SYM,
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/* This is a 32 bit reloc that stores the 32 bit pc relative
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value in two words (with an imm instruction).No relocation is
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done here - only used for relaxing */
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BFD_RELOC_MICROBLAZE_32_NONE,
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/* This is a 64 bit reloc that stores the 32 bit pc relative
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value in two words (with an imm instruction). No relocation is
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done here - only used for relaxing */
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@ -174,6 +174,21 @@ static reloc_howto_type microblaze_elf_howto_raw[] =
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0x0000ffff, /* Dest Mask. */
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false), /* PC relative offset? */
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/* This reloc does nothing. Used for relaxation. */
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HOWTO (R_MICROBLAZE_32_NONE, /* Type. */
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0, /* Rightshift. */
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2, /* Size (0 = byte, 1 = short, 2 = long). */
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32, /* Bitsize. */
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true, /* PC_relative. */
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0, /* Bitpos. */
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complain_overflow_bitfield, /* Complain on overflow. */
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NULL, /* Special Function. */
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"R_MICROBLAZE_32_NONE",/* Name. */
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false, /* Partial Inplace. */
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0, /* Source Mask. */
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0, /* Dest Mask. */
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false), /* PC relative offset? */
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/* This reloc does nothing. Used for relaxation. */
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HOWTO (R_MICROBLAZE_64_NONE, /* Type. */
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0, /* Rightshift. */
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@ -560,6 +575,9 @@ microblaze_elf_reloc_type_lookup (bfd * abfd ATTRIBUTE_UNUSED,
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case BFD_RELOC_NONE:
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microblaze_reloc = R_MICROBLAZE_NONE;
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break;
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case BFD_RELOC_MICROBLAZE_32_NONE:
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microblaze_reloc = R_MICROBLAZE_32_NONE;
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break;
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case BFD_RELOC_MICROBLAZE_64_NONE:
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microblaze_reloc = R_MICROBLAZE_64_NONE;
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break;
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@ -1954,14 +1972,22 @@ microblaze_elf_relax_section (bfd *abfd,
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}
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break;
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case R_MICROBLAZE_NONE:
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case R_MICROBLAZE_32_NONE:
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{
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/* This was a PC-relative instruction that was
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completely resolved. */
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size_t sfix, efix;
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unsigned int val;
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bfd_vma target_address;
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target_address = irel->r_addend + irel->r_offset;
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sfix = calc_fixup (irel->r_offset, 0, sec);
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efix = calc_fixup (target_address, 0, sec);
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/* Validate the in-band val. */
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val = bfd_get_32 (abfd, contents + irel->r_offset);
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if (val != irel->r_addend && ELF32_R_TYPE (irel->r_info) == R_MICROBLAZE_32_NONE) {
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fprintf(stderr, "%d: CORRUPT relax reloc %x %lx\n", __LINE__, val, irel->r_addend);
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}
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irel->r_addend -= (efix - sfix);
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/* Should use HOWTO. */
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microblaze_bfd_write_imm_value_32 (abfd, contents + irel->r_offset,
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@ -2009,6 +2035,49 @@ microblaze_elf_relax_section (bfd *abfd,
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irelscanend = irelocs + o->reloc_count;
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for (irelscan = irelocs; irelscan < irelscanend; irelscan++)
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{
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if (ELF32_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_32_NONE)
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{
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unsigned int val;
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isym = isymbuf + ELF32_R_SYM (irelscan->r_info);
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/* hax: We only do the following fixup for debug location lists. */
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if (strcmp(".debug_loc", o->name))
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continue;
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/* This was a PC-relative instruction that was completely resolved. */
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if (ocontents == NULL)
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{
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if (elf_section_data (o)->this_hdr.contents != NULL)
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ocontents = elf_section_data (o)->this_hdr.contents;
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else
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{
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/* We always cache the section contents.
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Perhaps, if info->keep_memory is FALSE, we
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should free them, if we are permitted to. */
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if (o->rawsize == 0)
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o->rawsize = o->size;
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ocontents = (bfd_byte *) bfd_malloc (o->rawsize);
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if (ocontents == NULL)
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goto error_return;
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if (!bfd_get_section_contents (abfd, o, ocontents,
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(file_ptr) 0,
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o->rawsize))
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goto error_return;
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elf_section_data (o)->this_hdr.contents = ocontents;
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}
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}
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val = bfd_get_32 (abfd, ocontents + irelscan->r_offset);
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if (val != irelscan->r_addend) {
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fprintf(stderr, "%d: CORRUPT relax reloc! %x %lx\n", __LINE__, val, irelscan->r_addend);
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}
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irelscan->r_addend -= calc_fixup (irelscan->r_addend, 0, sec);
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microblaze_bfd_write_imm_value_32 (abfd, ocontents + irelscan->r_offset,
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irelscan->r_addend);
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}
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if (ELF32_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_32)
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{
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isym = isymbuf + ELF32_R_SYM (irelscan->r_info);
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@ -2033,7 +2102,7 @@ microblaze_elf_relax_section (bfd *abfd,
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goto error_return;
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if (!bfd_get_section_contents (abfd, o, ocontents,
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(file_ptr) 0,
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o->rawsize))
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o->rawsize))
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goto error_return;
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elf_section_data (o)->this_hdr.contents = ocontents;
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}
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@ -2068,7 +2137,7 @@ microblaze_elf_relax_section (bfd *abfd,
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elf_section_data (o)->this_hdr.contents = ocontents;
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}
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}
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irelscan->r_addend -= calc_fixup (irel->r_addend
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irelscan->r_addend -= calc_fixup (irelscan->r_addend
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+ isym->st_value,
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0,
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sec);
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@ -3010,6 +3010,7 @@ static const char *const bfd_reloc_code_real_names[] = { "@@uninitialized@@",
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"BFD_RELOC_MICROBLAZE_32_ROSDA",
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"BFD_RELOC_MICROBLAZE_32_RWSDA",
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"BFD_RELOC_MICROBLAZE_32_SYM_OP_SYM",
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"BFD_RELOC_MICROBLAZE_32_NONE",
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"BFD_RELOC_MICROBLAZE_64_NONE",
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"BFD_RELOC_MICROBLAZE_64_GOTPC",
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"BFD_RELOC_MICROBLAZE_64_GOT",
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@ -6694,6 +6694,12 @@ ENUM
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ENUMDOC
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This is a 32 bit reloc for the microblaze to handle
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expressions of the form "Symbol Op Symbol"
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ENUM
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BFD_RELOC_MICROBLAZE_32_NONE
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ENUMDOC
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This is a 32 bit reloc that stores the 32 bit pc relative
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value in two words (with an imm instruction). No relocation is
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done here - only used for relaxing
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ENUM
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BFD_RELOC_MICROBLAZE_64_NONE
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ENUMDOC
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@ -15279,6 +15279,10 @@ is_8bit_abs_reloc (Filedata * filedata, unsigned int reloc_type)
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return reloc_type == 54; /* R_RISCV_SET8. */
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case EM_Z80:
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return reloc_type == 1; /* R_Z80_8. */
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case EM_MICROBLAZE:
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return reloc_type == 33 /* R_MICROBLAZE_32_NONE. */
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|| reloc_type == 0 /* R_MICROBLAZE_NONE. */
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|| reloc_type == 9; /* R_MICROBLAZE_64_NONE. */
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default:
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return false;
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}
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@ -915,7 +915,7 @@ md_assemble (char * str)
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unsigned reg2;
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unsigned reg3;
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unsigned isize;
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unsigned int immed = 0, temp;
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unsigned int immed = 0, immed2 = 0, temp;
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expressionS exp;
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char name[20];
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@ -1177,6 +1177,77 @@ md_assemble (char * str)
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inst |= (immed << IMM_LOW) & IMM5_MASK;
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break;
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case INST_TYPE_RD_R1_IMM5_IMM5:
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if (strcmp (op_end, ""))
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op_end = parse_reg (op_end + 1, ®1); /* Get rd. */
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else
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{
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as_fatal (_("Error in statement syntax"));
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reg1 = 0;
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}
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if (strcmp (op_end, ""))
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op_end = parse_reg (op_end + 1, ®2); /* Get r1. */
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else
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{
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as_fatal (_("Error in statement syntax"));
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reg2 = 0;
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}
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/* Check for spl registers. */
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if (check_spl_reg (®1))
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as_fatal (_("Cannot use special register with this instruction"));
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if (check_spl_reg (®2))
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as_fatal (_("Cannot use special register with this instruction"));
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/* Width immediate value. */
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if (strcmp (op_end, ""))
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op_end = parse_imm (op_end + 1, &exp, MIN_IMM_WIDTH, MAX_IMM_WIDTH);
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else
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as_fatal (_("Error in statement syntax"));
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if (exp.X_op != O_constant)
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{
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as_warn (_("Symbol used as immediate width value for bit field instruction"));
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immed = 1;
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}
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else
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immed = exp.X_add_number;
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if (opcode->instr == bsefi && immed > 31)
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as_fatal (_("Width value must be less than 32"));
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/* Shift immediate value. */
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if (strcmp (op_end, ""))
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op_end = parse_imm (op_end + 1, &exp, MIN_IMM, MAX_IMM);
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else
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as_fatal (_("Error in statement syntax"));
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if (exp.X_op != O_constant)
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{
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as_warn (_("Symbol used as immediate shift value for bit field instruction"));
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immed2 = 0;
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}
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else
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{
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output = frag_more (isize);
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immed2 = exp.X_add_number;
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}
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if (immed2 != (immed2 % 32))
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{
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as_warn (_("Shift value greater than 32. using <value %% 32>"));
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immed2 = immed2 % 32;
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}
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/* Check combined value. */
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if (immed + immed2 > 32)
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as_fatal (_("Width value + shift value must not be greater than 32"));
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inst |= (reg1 << RD_LOW) & RD_MASK;
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inst |= (reg2 << RA_LOW) & RA_MASK;
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if (opcode->instr == bsefi)
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inst |= (immed & IMM5_MASK) << IMM_WIDTH_LOW; /* bsefi */
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else
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inst |= ((immed + immed2 - 1) & IMM5_MASK) << IMM_WIDTH_LOW; /* bsifi */
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inst |= (immed2 << IMM_LOW) & IMM5_MASK;
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break;
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case INST_TYPE_R1_R2:
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if (strcmp (op_end, ""))
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op_end = parse_reg (op_end + 1, ®1); /* Get r1. */
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@ -2209,9 +2280,12 @@ md_apply_fix (fixS * fixP,
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moves code around due to relaxing. */
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if (fixP->fx_r_type == BFD_RELOC_64_PCREL)
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fixP->fx_r_type = BFD_RELOC_MICROBLAZE_64_NONE;
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else if (fixP->fx_r_type == BFD_RELOC_32)
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fixP->fx_r_type = BFD_RELOC_MICROBLAZE_32_NONE;
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else
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fixP->fx_r_type = BFD_RELOC_NONE;
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fixP->fx_addsy = section_symbol (absolute_section);
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fixP->fx_done = 0;
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}
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return;
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}
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@ -2432,6 +2506,7 @@ tc_gen_reloc (asection * section ATTRIBUTE_UNUSED, fixS * fixp)
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switch (fixp->fx_r_type)
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{
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case BFD_RELOC_NONE:
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case BFD_RELOC_MICROBLAZE_32_NONE:
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case BFD_RELOC_MICROBLAZE_64_NONE:
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case BFD_RELOC_32:
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case BFD_RELOC_MICROBLAZE_32_LO:
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@ -61,6 +61,7 @@ START_RELOC_NUMBERS (elf_microblaze_reloc_type)
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RELOC_NUMBER (R_MICROBLAZE_TEXTPCREL_64, 30) /* PC-relative TEXT offset. */
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RELOC_NUMBER (R_MICROBLAZE_TEXTREL_64, 31) /* TEXT Entry offset 64-bit. */
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RELOC_NUMBER (R_MICROBLAZE_TEXTREL_32_LO, 32) /* TEXT Entry offset 32-bit. */
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RELOC_NUMBER (R_MICROBLAZE_32_NONE, 33)
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END_RELOC_NUMBERS (R_MICROBLAZE_max)
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/* Global base address names. */
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@ -90,6 +90,18 @@ get_field_imm5_mbar (struct string_buf *buf, long instr)
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return p;
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}
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static char *
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get_field_imm5width (struct string_buf *buf, long instr)
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{
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char *p = strbuf (buf);
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if (instr & 0x00004000)
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sprintf (p, "%d", (short)(((instr & IMM5_WIDTH_MASK) >> IMM_WIDTH_LOW))); /* bsefi */
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else
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sprintf (p, "%d", (short)(((instr & IMM5_WIDTH_MASK) >> IMM_WIDTH_LOW) - ((instr & IMM5_MASK) >> IMM_LOW) + 1)); /* bsifi */
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return p;
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}
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static char *
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get_field_rfsl (struct string_buf *buf, long instr)
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{
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@ -427,6 +439,10 @@ print_insn_microblaze (bfd_vma memaddr, struct disassemble_info * info)
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/* For mbar 16 or sleep insn. */
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case INST_TYPE_NONE:
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break;
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/* For bit field insns. */
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case INST_TYPE_RD_R1_IMM5_IMM5:
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print_func (stream, "\t%s, %s, %s, %s", get_field_rd (&buf, inst),get_field_r1(&buf, inst),get_field_imm5width (&buf, inst), get_field_imm5 (&buf, inst));
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break;
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/* For tuqula instruction */
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case INST_TYPE_RD:
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print_func (stream, "\t%s", get_field_rd (&buf, inst));
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@ -59,6 +59,9 @@
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/* For mbar. */
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#define INST_TYPE_IMM5 20
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/* For bsefi and bsifi */
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#define INST_TYPE_RD_R1_IMM5_IMM5 21
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#define INST_TYPE_NONE 25
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@ -89,7 +92,9 @@
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#define OPCODE_MASK_H124 0xFFFF07FF /* High 16, and low 11 bits. */
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#define OPCODE_MASK_H1234 0xFFFFFFFF /* All 32 bits. */
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#define OPCODE_MASK_H3 0xFC000600 /* High 6 bits and bits 21, 22. */
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#define OPCODE_MASK_H3B 0xFC00C600 /* High 6 bits and bits 16, 17, 21, 22. */
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#define OPCODE_MASK_H32 0xFC00FC00 /* High 6 bits and bit 16-21. */
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#define OPCODE_MASK_H32B 0xFC00C000 /* High 6 bits and bit 16, 17. */
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#define OPCODE_MASK_H34B 0xFC0000FF /* High 6 bits and low 8 bits. */
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#define OPCODE_MASK_H35B 0xFC0004FF /* High 6 bits and low 9 bits. */
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#define OPCODE_MASK_H34C 0xFC0007E0 /* High 6 bits and bits 21-26. */
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@ -102,7 +107,7 @@
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#define DELAY_SLOT 1
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#define NO_DELAY_SLOT 0
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#define MAX_OPCODES 300
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#define MAX_OPCODES 301
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const struct op_code_struct
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{
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@ -159,6 +164,8 @@ const struct op_code_struct
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{"bslli", INST_TYPE_RD_R1_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64000400, OPCODE_MASK_H3, bslli, barrel_shift_inst },
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{"bsrai", INST_TYPE_RD_R1_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64000200, OPCODE_MASK_H3, bsrai, barrel_shift_inst },
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{"bsrli", INST_TYPE_RD_R1_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64000000, OPCODE_MASK_H3, bsrli, barrel_shift_inst },
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{"bsefi", INST_TYPE_RD_R1_IMM5_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64004000, OPCODE_MASK_H32B, bsefi, barrel_shift_inst },
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{"bsifi", INST_TYPE_RD_R1_IMM5_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64008000, OPCODE_MASK_H32B, bsifi, barrel_shift_inst },
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{"or", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x80000000, OPCODE_MASK_H4, microblaze_or, logical_inst },
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{"and", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x84000000, OPCODE_MASK_H4, microblaze_and, logical_inst },
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{"xor", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x88000000, OPCODE_MASK_H4, microblaze_xor, logical_inst },
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@ -438,5 +445,8 @@ char pvr_register_prefix[] = "rpvr";
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#define MIN_IMM5 ((int) 0x00000000)
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#define MAX_IMM5 ((int) 0x0000001f)
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#define MIN_IMM_WIDTH ((int) 0x00000001)
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#define MAX_IMM_WIDTH ((int) 0x00000020)
|
||||
|
||||
#endif /* MICROBLAZE_OPC */
|
||||
|
||||
|
||||
@ -29,7 +29,7 @@ enum microblaze_instr
|
||||
addi, rsubi, addic, rsubic, addik, rsubik, addikc, rsubikc, mul,
|
||||
mulh, mulhu, mulhsu, swapb, swaph,
|
||||
idiv, idivu, bsll, bsra, bsrl, get, put, nget, nput, cget, cput,
|
||||
ncget, ncput, muli, bslli, bsrai, bsrli, mului,
|
||||
ncget, ncput, muli, bslli, bsrai, bsrli, bsefi, bsifi, mului,
|
||||
/* 'or/and/xor' are C++ keywords. */
|
||||
microblaze_or, microblaze_and, microblaze_xor,
|
||||
andn, pcmpbf, pcmpbc, pcmpeq, pcmpne, sra, src, srl, sext8, sext16,
|
||||
@ -130,6 +130,7 @@ enum microblaze_instr_type
|
||||
#define RB_LOW 11 /* Low bit for RB. */
|
||||
#define IMM_LOW 0 /* Low bit for immediate. */
|
||||
#define IMM_MBAR 21 /* low bit for mbar instruction. */
|
||||
#define IMM_WIDTH_LOW 6 /* Low bit for immediate width */
|
||||
|
||||
#define RD_MASK 0x03E00000
|
||||
#define RA_MASK 0x001F0000
|
||||
@ -142,6 +143,9 @@ enum microblaze_instr_type
|
||||
/* Imm mask for mbar. */
|
||||
#define IMM5_MBAR_MASK 0x03E00000
|
||||
|
||||
/* Imm mask for extract/insert width. */
|
||||
#define IMM5_WIDTH_MASK 0x000007C0
|
||||
|
||||
/* FSL imm mask for get, put instructions. */
|
||||
#define RFSL_MASK 0x000000F
|
||||
|
||||
|
||||
Loading…
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Reference in New Issue
Block a user