2008-11-04 Sterling Augustine <sterling@tensilica.com>
* config/tc-xtensa.c (tinsn_check_arguments): Check for multiple writes to the same register.
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@ -1,3 +1,8 @@
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2008-11-04 Sterling Augustine <sterling@tensilica.com>
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* config/tc-xtensa.c (tinsn_check_arguments): Check for multiple
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writes to the same register.
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2008-11-04 Sterling Augustine <sterling@tensilica.com>
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* config/tc-xtensa.c (xtensa_j_opcode): New.
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@ -11457,6 +11457,12 @@ tinsn_check_arguments (const TInsn *insn)
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{
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xtensa_isa isa = xtensa_default_isa;
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xtensa_opcode opcode = insn->opcode;
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xtensa_regfile t1_regfile, t2_regfile;
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int t1_reg, t2_reg;
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int t1_base_reg, t1_last_reg;
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int t2_base_reg, t2_last_reg;
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char t1_inout, t2_inout;
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int i, j;
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if (opcode == XTENSA_UNDEFINED)
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{
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@ -11475,6 +11481,54 @@ tinsn_check_arguments (const TInsn *insn)
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as_bad (_("too many operands"));
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return TRUE;
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}
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/* Check registers. */
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for (j = 0; j < insn->ntok; j++)
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{
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if (xtensa_operand_is_register (isa, insn->opcode, j) != 1)
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continue;
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t2_regfile = xtensa_operand_regfile (isa, insn->opcode, j);
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t2_base_reg = insn->tok[j].X_add_number;
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t2_last_reg
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= t2_base_reg + xtensa_operand_num_regs (isa, insn->opcode, j);
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for (i = 0; i < insn->ntok; i++)
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{
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if (i == j)
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continue;
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if (xtensa_operand_is_register (isa, insn->opcode, i) != 1)
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continue;
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t1_regfile = xtensa_operand_regfile (isa, insn->opcode, i);
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if (t1_regfile != t2_regfile)
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continue;
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t1_inout = xtensa_operand_inout (isa, insn->opcode, i);
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t2_inout = xtensa_operand_inout (isa, insn->opcode, j);
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t1_base_reg = insn->tok[i].X_add_number;
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t1_last_reg = (t1_base_reg
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+ xtensa_operand_num_regs (isa, insn->opcode, i));
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for (t1_reg = t1_base_reg; t1_reg < t1_last_reg; t1_reg++)
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{
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for (t2_reg = t2_base_reg; t2_reg < t2_last_reg; t2_reg++)
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{
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if (t1_reg != t2_reg)
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continue;
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if (t1_inout != 'i' && t2_inout != 'i')
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{
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as_bad (_("multiple writes to the same register"));
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return TRUE;
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}
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}
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}
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}
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}
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return FALSE;
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}
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