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Fix tic54x testsuite failures and Lmem disassembly bugs.

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This commit is contained in:
Timothy Wall 2001-11-13 14:22:53 +00:00
parent 1a78a35acf
commit 6e91790347
25 changed files with 808 additions and 821 deletions
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8
binutils/ChangeLog
View File

@ -1,5 +1,9 @@
2001-11-12 * Steven J. Hill <sjhill@realitydiluted.com>
2001-11-13 Timothy Wall <twall@alum.mit.edu>
* MAINTAINERS: Add self as tic54x maintainer. This target
includes the IBM C54XDSP clone.
2001-11-12 * Steven J. Hill <sjhill@realitydiluted.com>
* bucomm.c (make_tempname): Use mkstemp in place of mktemp.
2001-11-09 Jeffrey A Law (law@cygnus.com)
@ -923,7 +927,7 @@
2000-11-28 Hans-Peter Nilsson <hp@bitrange.com>
* MAINTAINERS: Add Jörn Rennecke and self as SH maintainers.
* MAINTAINERS: Add J<EFBFBD>örn Rennecke and self as SH maintainers.
Change sourceware.cygnus.com to sources.redhat.com.
Fix typo for "amongst".

3
binutils/MAINTAINERS
View File

@ -72,9 +72,10 @@ responsibility among the other maintainers.
PPC Geoff Keating <geoffk@redhat.com>
PPC XCOFF Tom Rix <trix@redhat.com>
s390, s390x Martin Schwidefsky <schwidefsky@de.ibm.com>
SH Jörn Rennecke <amylaar@onetel.net.uk>
SH J<EFBFBD>örn Rennecke <amylaar@onetel.net.uk>
SH Hans-Peter Nilsson <hp@bitrange.com>
SPARC Jakub Jelinek <jakub@redhat.com>
TIC54X Timothy Wall <twall@alum.mit.edu>
z8k Christian Groessler <cpg@aladdin.de>
--------- CGEN Maintainers -------------

8
gas/ChangeLog
View File

@ -1,3 +1,11 @@
2001-11-11 Timothy Wall <twall@alum.mit.edu>
* write.c (relax_segment): Convert symbol address into an octet
offset prior to adding to the frag address, which is an octet
offset. Add comments to that effect.
* config/tc-tic54x.c: Fix bugs causing tests to fail.
* config/tc-tic54x.h: Ditch PARAMS macro.
2001-11-13 Alan Modra <amodra@bigpond.net.au>
* config/obj-elf.c (obj_elf_version): Ensure terminating NUL is

339
gas/config/tc-tic54x.c
View File

@ -39,7 +39,11 @@
We don't convert '' to '\0'
We don't allow strings with .byte/.half/.short/.long
Probably details of the subsym stuff are different
TI sets labels to be data type 4 (T_INT); GAS uses T_NULL. */
TI sets labels to be data type 4 (T_INT); GAS uses T_NULL.
COFF1 limits section names to 8 characters.
Some of the default behavior changed from COFF1 to COFF2.
*/
#include <stdlib.h>
#include <limits.h>
@ -235,8 +239,7 @@ static subsegT stag_saved_subseg;
/* Output a single character (upper octect is zero). */
static void
tic54x_emit_char (c)
char c;
tic54x_emit_char (char c)
{
expressionS exp;
@ -248,9 +251,7 @@ tic54x_emit_char (c)
/* Walk backwards in the frag chain. */
static fragS *
frag_prev (frag, seg)
fragS *frag;
segT seg;
frag_prev (fragS *frag, segT seg)
{
segment_info_type *seginfo = seg_info (seg);
fragS *fragp;
@ -263,9 +264,7 @@ frag_prev (frag, seg)
}
static fragS *
bit_offset_frag (frag, seg)
fragS *frag;
segT seg;
bit_offset_frag (fragS *frag, segT seg)
{
while (frag != NULL)
{
@ -283,9 +282,7 @@ bit_offset_frag (frag, seg)
none. .field/.space/.bes may leave words partially allocated. */
static int
frag_bit_offset (frag, seg)
fragS *frag;
segT seg;
frag_bit_offset (fragS *frag, segT seg)
{
frag = bit_offset_frag (frag, seg);
@ -319,8 +316,7 @@ parse_expression (char *str, expressionS * exp)
unsupported. */
static void
tic54x_asg (x)
int x ATTRIBUTE_UNUSED;
tic54x_asg (int x ATTRIBUTE_UNUSED)
{
int c;
char *name;
@ -381,8 +377,7 @@ tic54x_asg (x)
table, since that's what works best. */
static void
tic54x_eval (x)
int x ATTRIBUTE_UNUSED;
tic54x_eval (int x ATTRIBUTE_UNUSED)
{
char c;
int value;
@ -458,8 +453,7 @@ tic54x_eval (x)
(not yet implemented). */
static void
tic54x_bss (x)
int x ATTRIBUTE_UNUSED;
tic54x_bss (int x ATTRIBUTE_UNUSED)
{
char c;
char *name;
@ -522,7 +516,7 @@ tic54x_bss (x)
symbol_set_frag (symbolP, frag_now);
p = frag_var (rs_org, 1, 1, (relax_substateT) 0, symbolP,
(offsetT) (words << 1), (char *) 0);
(offsetT) (words * OCTETS_PER_BYTE), (char *) 0);
*p = 0; /* Fill char. */
S_SET_SEGMENT (symbolP, bss_section);
@ -548,12 +542,11 @@ tic54x_bss (x)
}
static void
stag_add_field_symbols (stag, path, base_offset, rootsym, root_stag_name)
struct stag *stag;
const char *path;
bfd_vma base_offset;
symbolS *rootsym;
const char *root_stag_name;
stag_add_field_symbols (struct stag *stag,
const char *path,
bfd_vma base_offset,
symbolS *rootsym,
const char *root_stag_name)
{
char prefix[strlen (path) + 2];
struct stag_field *field = stag->field;
@ -606,11 +599,10 @@ stag_add_field_symbols (stag, path, base_offset, rootsym, root_stag_name)
complete dereferencing symbols to the symbol table. */
static void
stag_add_field (parent, name, offset, stag)
struct stag *parent;
const char *name;
bfd_vma offset;
struct stag *stag;
stag_add_field (struct stag *parent,
const char *name,
bfd_vma offset,
struct stag *stag)
{
struct stag_field *sfield = xmalloc (sizeof (struct stag_field));
@ -787,8 +779,7 @@ tic54x_endstruct (int is_union)
format on the existing allocated space. */
static void
tic54x_tag (ignore)
int ignore ATTRIBUTE_UNUSED;
tic54x_tag (int ignore ATTRIBUTE_UNUSED)
{
char *name = input_line_pointer;
int c = get_symbol_end ();
@ -1104,8 +1095,7 @@ tic54x_cons (int type)
these, so we ignore the type here. */
void
tic54x_global (type)
int type;
tic54x_global (int type)
{
char *name;
int c;
@ -1139,9 +1129,8 @@ tic54x_global (type)
/* Remove the symbol from the local label hash lookup. */
static void
tic54x_remove_local_label (key, value)
const char *key;
PTR value ATTRIBUTE_UNUSED;
tic54x_remove_local_label (const char *key,
PTR value ATTRIBUTE_UNUSED)
{
PTR *elem = hash_delete (local_label_hash[macro_level], key);
free (elem);
@ -1150,8 +1139,7 @@ tic54x_remove_local_label (key, value)
/* Reset all local labels. */
static void
tic54x_clear_local_labels (ignored)
int ignored ATTRIBUTE_UNUSED;
tic54x_clear_local_labels (int ignored ATTRIBUTE_UNUSED)
{
hash_traverse (local_label_hash[macro_level], tic54x_remove_local_label);
}
@ -1165,7 +1153,9 @@ tic54x_clear_local_labels (ignored)
ARG is 't' for text, 'd' for data, or '*' for a named section
For compatibility, '*' sections have SEC_DATA set instead of SEC_CODE. */
For compatibility, '*' sections are SEC_CODE if instructions are
encountered, or SEC_DATA if not.
*/
static void
tic54x_sect (int arg)
@ -1195,11 +1185,13 @@ tic54x_sect (int arg)
int c;
name = input_line_pointer;
c = get_symbol_end ();
len = strlen(name);
name = strcpy (xmalloc (len + 10), name);
*input_line_pointer = c;
demand_empty_rest_of_line ();
}
/* Make sure all named initialized sections are SEC_DATA. */
/* Make sure all named initialized sections flagged properly. If we
encounter instructions, we'll flag it with SEC_CODE as well. */
strcat (name, ",\"w\"\n");
input_scrub_insert_line (name);
obj_coff_section (0);
@ -1356,8 +1348,7 @@ tic54x_space (int arg)
Has no effect on the current section. */
static void
tic54x_usect (x)
int x ATTRIBUTE_UNUSED;
tic54x_usect (int x ATTRIBUTE_UNUSED)
{
char c;
char *name;
@ -1453,8 +1444,7 @@ tic54x_usect (x)
}
static enum cpu_version
lookup_version (ver)
const char *ver;
lookup_version (const char *ver)
{
enum cpu_version version = VNONE;
@ -1475,8 +1465,7 @@ lookup_version (ver)
}
static void
set_cpu (version)
enum cpu_version version;
set_cpu (enum cpu_version version)
{
cpu = version;
if (version == V545LP || version == V546LP)
@ -1503,8 +1492,7 @@ set_cpu (version)
static int cpu_needs_set = 1;
static void
tic54x_version (x)
int x ATTRIBUTE_UNUSED;
tic54x_version (int x ATTRIBUTE_UNUSED)
{
enum cpu_version version = VNONE;
enum cpu_version old_version = cpu;
@ -1573,12 +1561,11 @@ tic54x_float_cons (int type)
/* The argument is capitalized if it should be zero-terminated
's' is normal string with upper 8-bits zero-filled, 'p' is packed.
Code copied from read.c, and slightly modified so that strings are packed
Code copied from stringer, and slightly modified so that strings are packed
and encoded into the correct octets. */
static void
tic54x_stringer (type)
int type;
tic54x_stringer (int type)
{
register unsigned int c;
char *start;
@ -1665,15 +1652,13 @@ tic54x_stringer (type)
}
static void
tic54x_p2align (arg)
int arg ATTRIBUTE_UNUSED;
tic54x_p2align (int arg ATTRIBUTE_UNUSED)
{
as_bad (_("p2align not supported on this target"));
}
static void
tic54x_align_words (arg)
int arg;
tic54x_align_words (int arg)
{
/* Only ".align" with no argument is allowed within .struct/.union. */
int count = arg;
@ -1705,8 +1690,7 @@ tic54x_align_words (arg)
/* Initialize multiple-bit fields withing a single word of memory. */
static void
tic54x_field (ignore)
int ignore ATTRIBUTE_UNUSED;
tic54x_field (int ignore ATTRIBUTE_UNUSED)
{
expressionS exp;
int size = 16;
@ -1826,8 +1810,7 @@ tic54x_field (ignore)
available yet. seg_info ()->bss is the next best thing. */
static int
tic54x_initialized_section (seg)
segT seg;
tic54x_initialized_section (segT seg)
{
return !seg_info (seg)->bss;
}
@ -1840,8 +1823,7 @@ tic54x_initialized_section (seg)
Name is required for uninitialized sections. */
static void
tic54x_clink (ignored)
int ignored ATTRIBUTE_UNUSED;
tic54x_clink (int ignored ATTRIBUTE_UNUSED)
{
segT seg = now_seg;
@ -1887,8 +1869,7 @@ tic54x_clink (ignored)
set to "." instead. */
static void
tic54x_set_default_include (dot)
int dot;
tic54x_set_default_include (int dot)
{
char *dir = ".";
char *tmp = NULL;
@ -1932,8 +1913,7 @@ tic54x_set_default_include (dot)
Entering/exiting included/copied file clears all local labels. */
static void
tic54x_include (ignored)
int ignored ATTRIBUTE_UNUSED;
tic54x_include (int ignored ATTRIBUTE_UNUSED)
{
char newblock[] = " .newblock\n";
char *filename;
@ -1976,8 +1956,7 @@ tic54x_include (ignored)
}
static void
tic54x_message (type)
int type;
tic54x_message (int type)
{
char *msg;
char c;
@ -2023,8 +2002,7 @@ tic54x_message (type)
run address (vma). */
static void
tic54x_label (ignored)
int ignored ATTRIBUTE_UNUSED;
tic54x_label (int ignored ATTRIBUTE_UNUSED)
{
char *name = input_line_pointer;
symbolS *symbolP;
@ -2045,8 +2023,7 @@ tic54x_label (ignored)
absolute local symbols. */
static void
tic54x_mmregs (ignored)
int ignored ATTRIBUTE_UNUSED;
tic54x_mmregs (int ignored ATTRIBUTE_UNUSED)
{
symbol *sym;
@ -2079,8 +2056,7 @@ tic54x_loop (int count)
/* Normally, endloop gets eaten by the preceding loop. */
static void
tic54x_endloop (ignore)
int ignore ATTRIBUTE_UNUSED;
tic54x_endloop (int ignore ATTRIBUTE_UNUSED)
{
as_bad (_("ENDLOOP without corresponding LOOP"));
ignore_rest_of_line ();
@ -2089,8 +2065,7 @@ tic54x_endloop (ignore)
/* .break [condition]. */
static void
tic54x_break (ignore)
int ignore ATTRIBUTE_UNUSED;
tic54x_break (int ignore ATTRIBUTE_UNUSED)
{
int cond = 1;
@ -2105,8 +2080,7 @@ tic54x_break (ignore)
}
static void
set_address_mode (mode)
int mode;
set_address_mode (int mode)
{
amode = mode;
if (mode == far_mode)
@ -2120,8 +2094,7 @@ set_address_mode (mode)
static int address_mode_needs_set = 1;
static void
tic54x_address_mode (mode)
int mode;
tic54x_address_mode (int mode)
{
if (assembly_begun && amode != (unsigned) mode)
{
@ -2144,8 +2117,7 @@ tic54x_address_mode (mode)
Designate initialized sections for blocking. */
static void
tic54x_sblock (ignore)
int ignore ATTRIBUTE_UNUSED;
tic54x_sblock (int ignore ATTRIBUTE_UNUSED)
{
int c = ',';
@ -2200,8 +2172,7 @@ tic54x_sblock (ignore)
symbols assigned with .set/.equ may not be redefined. */
static void
tic54x_set (ignore)
int ignore ATTRIBUTE_UNUSED;
tic54x_set (int ignore ATTRIBUTE_UNUSED)
{
symbolS *symbolP;
char *name;
@ -2256,8 +2227,7 @@ tic54x_sslist (int show)
Define a substitution string to be local to a macro. */
static void
tic54x_var (ignore)
int ignore ATTRIBUTE_UNUSED;
tic54x_var (int ignore ATTRIBUTE_UNUSED)
{
static char empty[] = "";
char *name;
@ -2305,8 +2275,7 @@ tic54x_var (ignore)
FIXME need to try the source file directory as well. */
static void
tic54x_mlib (ignore)
int ignore ATTRIBUTE_UNUSED;
tic54x_mlib (int ignore ATTRIBUTE_UNUSED)
{
char *filename;
char *path;
@ -2408,6 +2377,8 @@ const pseudo_typeS md_pseudo_table[] =
{
{ "algebraic", s_ignore , 0 },
{ "align" , tic54x_align_words , 128 },
{ "ascii" , tic54x_stringer , 'p' },
{ "asciz" , tic54x_stringer , 'P' },
{ "even" , tic54x_align_words , 2 },
{ "asg" , tic54x_asg , 0 },
{ "eval" , tic54x_eval , 0 },
@ -2626,9 +2597,7 @@ tic54x_macro_end ()
}
static int
subsym_symlen (a, ignore)
char *a;
char *ignore ATTRIBUTE_UNUSED;
subsym_symlen (char *a, char *ignore ATTRIBUTE_UNUSED)
{
return strlen (a);
}
@ -2636,9 +2605,7 @@ subsym_symlen (a, ignore)
/* Compare symbol A to string B. */
static int
subsym_symcmp (a, b)
char *a;
char *b;
subsym_symcmp (char *a, char *b)
{
return strcmp (a, b);
}
@ -2647,9 +2614,7 @@ subsym_symcmp (a, b)
assumes b is an integer char value as a string. Index is one-based. */
static int
subsym_firstch (a, b)
char *a;
char *b;
subsym_firstch (char *a, char *b)
{
int val = atoi (b);
char *tmp = strchr (a, val);
@ -2660,9 +2625,7 @@ subsym_firstch (a, b)
/* Similar to firstch, but returns index of last occurrence of B in A. */
static int
subsym_lastch (a, b)
char *a;
char *b;
subsym_lastch (char *a, char *b)
{
int val = atoi (b);
char *tmp = strrchr (a, val);
@ -2674,9 +2637,7 @@ subsym_lastch (a, b)
symbol table). */
static int
subsym_isdefed (a, ignore)
char *a;
char *ignore ATTRIBUTE_UNUSED;
subsym_isdefed (char *a, char *ignore ATTRIBUTE_UNUSED)
{
symbolS *symbolP = symbol_find (a);
@ -2688,9 +2649,7 @@ subsym_isdefed (a, ignore)
symbols, unsubstituted. */
static int
subsym_ismember (sym, list)
char *sym;
char *list;
subsym_ismember (char *sym, char *list)
{
char *elem, *ptr, *listv;
@ -2728,9 +2687,7 @@ subsym_ismember (sym, list)
5 if decimal. */
static int
subsym_iscons (a, ignore)
char *a;
char *ignore ATTRIBUTE_UNUSED;
subsym_iscons (char *a, char *ignore ATTRIBUTE_UNUSED)
{
expressionS exp;
@ -2769,9 +2726,7 @@ subsym_iscons (a, ignore)
/* Return 1 if A is a valid symbol name. Expects string input. */
static int
subsym_isname (a, ignore)
char *a;
char *ignore ATTRIBUTE_UNUSED;
subsym_isname (char *a, char *ignore ATTRIBUTE_UNUSED)
{
if (!is_name_beginner (*a))
return 0;
@ -2789,9 +2744,7 @@ subsym_isname (a, ignore)
Note this does not recognize "A" or "B" accumulators. */
static int
subsym_isreg (a, ignore)
char *a;
char *ignore ATTRIBUTE_UNUSED;
subsym_isreg (char *a, char *ignore ATTRIBUTE_UNUSED)
{
if (hash_find (reg_hash, a))
return 1;
@ -2803,9 +2756,7 @@ subsym_isreg (a, ignore)
/* Return the structrure size, given the stag. */
static int
subsym_structsz (name, ignore)
char *name;
char *ignore ATTRIBUTE_UNUSED;
subsym_structsz (char *name, char *ignore ATTRIBUTE_UNUSED)
{
struct stag *stag = (struct stag *) hash_find (stag_hash, name);
if (stag)
@ -2822,9 +2773,8 @@ subsym_structsz (name, ignore)
return zero, we punt and return zero. */
static int
subsym_structacc (stag_name, ignore)
char *stag_name ATTRIBUTE_UNUSED;
char *ignore ATTRIBUTE_UNUSED;
subsym_structacc (char *stag_name ATTRIBUTE_UNUSED,
char *ignore ATTRIBUTE_UNUSED)
{
return 0;
}
@ -3115,8 +3065,7 @@ static const math_proc_entry math_procs[] =
void
md_begin ()
{
template *opcode;
partemplate *paropcode;
template *tm;
symbol *sym;
const subsym_proc_entry *subsym_proc;
const math_proc_entry *math_proc;
@ -3143,26 +3092,24 @@ md_begin ()
}
op_hash = hash_new ();
for (opcode = (template *) tic54x_optab; opcode->name; opcode++)
for (tm = (template *) tic54x_optab; tm->name; tm++)
{
if (hash_find (op_hash, opcode->name))
if (hash_find (op_hash, tm->name))
continue;
hash_err = hash_insert (op_hash, opcode->name, (char *) opcode);
hash_err = hash_insert (op_hash, tm->name, (char *) tm);
if (hash_err)
as_fatal ("Internal Error: Can't hash %s: %s",
opcode->name, hash_err);
tm->name, hash_err);
}
parop_hash = hash_new ();
for (paropcode = (partemplate *) tic54x_paroptab;
paropcode->name;
paropcode++)
for (tm = (template *) tic54x_paroptab; tm->name; tm++)
{
if (hash_find (parop_hash, paropcode->name))
if (hash_find (parop_hash, tm->name))
continue;
hash_err = hash_insert (parop_hash, paropcode->name, (char *) paropcode);
hash_err = hash_insert (parop_hash, tm->name, (char *) tm);
if (hash_err)
as_fatal ("Internal Error: Can't hash %s: %s",
paropcode->name, hash_err);
tm->name, hash_err);
}
reg_hash = hash_new ();
for (sym = (symbol *) regs; sym->name; sym++)
@ -3232,7 +3179,6 @@ md_begin ()
typedef struct _tic54x_insn
{
const template *tm; /* Opcode template. */
const partemplate *ptm; /* Parallel opcode template. */
char mnemonic[MAX_LINE]; /* Opcode name/mnemonic. */
char parmnemonic[MAX_LINE]; /* 2nd mnemonic of parallel insn. */
@ -3268,10 +3214,10 @@ static int encode_dmad (tic54x_insn *, struct opstruct *, int);
static int operands_match (tic54x_insn *, struct opstruct *, int,
const enum optype *, int, int);
static int encode_address (tic54x_insn *, struct opstruct *);
static int is_accumulator (struct opstruct *);
static int
is_accumulator (operand)
struct opstruct *operand;
is_accumulator (struct opstruct *operand)
{
return strcasecmp (operand->buf, "a") == 0
|| strcasecmp (operand->buf, "b") == 0;
@ -3282,9 +3228,7 @@ is_accumulator (operand)
the next array. */
static int
get_operands (operands, line)
struct opstruct operands[];
char *line;
get_operands (struct opstruct operands[], char *line)
{
char *lptr = line;
int numexp = 0;
@ -3409,8 +3353,7 @@ get_operands (operands, line)
/* Predicates for different operand types. */
static int
is_immediate (operand)
struct opstruct *operand;
is_immediate (struct opstruct *operand)
{
return *operand->buf == '#';
}
@ -3419,8 +3362,7 @@ is_immediate (operand)
and must *not* have the '#' prefix. */
static int
is_absolute (operand)
struct opstruct *operand;
is_absolute (struct opstruct *operand)
{
return operand->exp.X_op == O_constant && !is_immediate (operand);
}
@ -3428,8 +3370,7 @@ is_absolute (operand)
/* Is this an indirect operand? */
static int
is_indirect (operand)
struct opstruct *operand;
is_indirect (struct opstruct *operand)
{
return operand->buf[0] == '*';
}
@ -3437,8 +3378,7 @@ is_indirect (operand)
/* Is this a valid dual-memory operand? */
static int
is_dual (operand)
struct opstruct *operand;
is_dual (struct opstruct *operand)
{
if (is_indirect (operand) && strncasecmp (operand->buf, "*ar", 3) == 0)
{
@ -3458,8 +3398,7 @@ is_dual (operand)
}
static int
is_mmreg (operand)
struct opstruct *operand;
is_mmreg (struct opstruct *operand)
{
return (is_absolute (operand)
|| is_immediate (operand)
@ -3467,9 +3406,7 @@ is_mmreg (operand)
}
static int
is_type (operand, type)
struct opstruct *operand;
enum optype type;
is_type (struct opstruct *operand, enum optype type)
{
switch (type)
{
@ -3727,9 +3664,7 @@ encode_address (insn, operand)
}
static int
encode_indirect (insn, operand)
tic54x_insn *insn;
struct opstruct *operand;
encode_indirect (tic54x_insn *insn, struct opstruct *operand)
{
int arf;
int mod;
@ -3801,11 +3736,9 @@ encode_indirect (insn, operand)
}
static int
encode_integer (insn, operand, which, min, max, mask)
tic54x_insn *insn;
struct opstruct *operand;
int which, min, max;
unsigned short mask;
encode_integer (tic54x_insn *insn,
struct opstruct *operand,
int which, int min, int max, unsigned short mask)
{
long parse, integer;
@ -3860,9 +3793,7 @@ encode_integer (insn, operand, which, min, max, mask)
}
static int
encode_condition (insn, operand)
tic54x_insn *insn;
struct opstruct *operand;
encode_condition (tic54x_insn *insn, struct opstruct *operand)
{
symbol *cc = (symbol *) hash_find (cc_hash, operand->buf);
if (!cc)
@ -3922,9 +3853,7 @@ encode_condition (insn, operand)
}
static int
encode_cc3 (insn, operand)
tic54x_insn *insn;
struct opstruct *operand;
encode_cc3 (tic54x_insn *insn, struct opstruct *operand)
{
symbol *cc3 = (symbol *) hash_find (cc3_hash, operand->buf);
int value = cc3 ? cc3->value : operand->exp.X_add_number << 8;
@ -3939,9 +3868,7 @@ encode_cc3 (insn, operand)
}
static int
encode_arx (insn, operand)
tic54x_insn *insn;
struct opstruct *operand;
encode_arx (tic54x_insn *insn, struct opstruct *operand)
{
int arf = strlen (operand->buf) >= 3 ? operand->buf[2] - '0' : -1;
if (strncasecmp ("ar", operand->buf, 2) || arf < 0 || arf > 7)
@ -3954,9 +3881,7 @@ encode_arx (insn, operand)
}
static int
encode_cc2 (insn, operand)
tic54x_insn *insn;
struct opstruct *operand;
encode_cc2 (tic54x_insn *insn, struct opstruct *operand)
{
symbol *cc2 = (symbol *) hash_find (cc2_hash, operand->buf);
if (!cc2)
@ -3974,7 +3899,7 @@ encode_operand (insn, type, operand)
enum optype type;
struct opstruct *operand;
{
int ext = insn->tm && ((insn->tm->flags & FL_EXT) != 0);
int ext = (insn->tm->flags & FL_EXT) != 0;
if (type == OP_MMR && operand->exp.X_op != O_constant)
{
@ -4195,10 +4120,16 @@ encode_operand (insn, type, operand)
}
static void
emit_insn (insn)
tic54x_insn *insn;
emit_insn (tic54x_insn *insn)
{
int i;
flagword oldflags = bfd_get_section_flags (stdoutput, now_seg);
flagword flags = oldflags | SEC_CODE;
if (! bfd_set_section_flags (stdoutput, now_seg, flags))
as_warn (_("error setting flags for \"%s\": %s"),
bfd_section_name (stdoutput, now_seg),
bfd_errmsg (bfd_get_error ()));
for (i = 0; i < insn->words; i++)
{
@ -4222,13 +4153,12 @@ emit_insn (insn)
return the total number of words used by the instruction. */
static int
build_insn (insn)
tic54x_insn *insn;
build_insn (tic54x_insn *insn)
{
int i;
/* Only non-parallel instructions support lk addressing. */
if (insn->tm)
if (!(insn->tm->flags & FL_PAR))
{
for (i = 0; i < insn->opcount; i++)
{
@ -4245,11 +4175,10 @@ build_insn (insn)
}
}
}
insn->words =
(insn->tm ? insn->tm->words : insn->ptm->words) + insn->is_lkaddr;
insn->words = insn->tm->words + insn->is_lkaddr;
insn->opcode[0].word = insn->tm ? insn->tm->opcode : insn->ptm->opcode;
if (insn->tm && (insn->tm->flags & FL_EXT))
insn->opcode[0].word = insn->tm->opcode;
if (insn->tm->flags & FL_EXT)
insn->opcode[1 + insn->is_lkaddr].word = insn->tm->opcode2;
for (i = 0; i < insn->opcount; i++)
@ -4258,7 +4187,7 @@ build_insn (insn)
if (!encode_operand (insn, type, &insn->operands[i]))
return 0;
}
if (insn->ptm)
if (insn->tm->flags & FL_PAR)
for (i = 0; i < insn->paropcount; i++)
{
enum optype partype = insn->paroperands[i].type;
@ -4272,8 +4201,7 @@ build_insn (insn)
}
static int
optimize_insn (insn)
tic54x_insn *insn;
optimize_insn (tic54x_insn *insn)
{
/* Optimize some instructions, helping out the brain-dead programmer. */
#define is_zero(op) ((op).exp.X_op == O_constant && (op).exp.X_add_number == 0)
@ -4366,9 +4294,7 @@ optimize_insn (insn)
/* Find a matching template if possible, and get the operand strings. */
static int
tic54x_parse_insn (insn, line)
tic54x_insn *insn;
char *line;
tic54x_parse_insn (tic54x_insn *insn, char *line)
{
insn->tm = (template *) hash_find (op_hash, insn->mnemonic);
if (!insn->tm)
@ -4415,8 +4341,7 @@ static int parallel_on_next_line_hint = 0;
Look for a subsequent line starting with "||". */
static int
next_line_shows_parallel (next_line)
char *next_line;
next_line_shows_parallel (char *next_line)
{
/* Look for the second half. */
while (ISSPACE (*next_line))
@ -4427,31 +4352,29 @@ next_line_shows_parallel (next_line)
}
static int
tic54x_parse_parallel_insn_firstline (insn, line)
tic54x_insn *insn;
char *line;
tic54x_parse_parallel_insn_firstline (tic54x_insn *insn, char *line)
{
insn->ptm = (partemplate *) hash_find (parop_hash, insn->mnemonic);
if (!insn->ptm)
insn->tm = (template *) hash_find (parop_hash, insn->mnemonic);
if (!insn->tm)
{
as_bad (_("Unrecognized parallel instruction \"%s\""),
insn->mnemonic);
return 0;
}
while (insn->ptm->name && strcasecmp (insn->ptm->name,
insn->mnemonic) == 0)
while (insn->tm->name && strcasecmp (insn->tm->name,
insn->mnemonic) == 0)
{
insn->opcount = get_operands (insn->operands, line);
if (insn->opcount < 0)
return 0;
if (insn->opcount == 2
&& operands_match (insn, &insn->operands[0], insn->opcount,
insn->ptm->operand_types, 2, 2))
insn->tm->operand_types, 2, 2))
{
return 1;
}
++(insn->ptm);
++(insn->tm);
}
/* Didn't find a matching parallel; try for a normal insn. */
return 0;
@ -4460,30 +4383,28 @@ tic54x_parse_parallel_insn_firstline (insn, line)
/* Parse the second line of a two-line parallel instruction. */
static int
tic54x_parse_parallel_insn_lastline (insn, line)
tic54x_insn *insn;
char *line;
tic54x_parse_parallel_insn_lastline (tic54x_insn *insn, char *line)
{
int valid_mnemonic = 0;
insn->paropcount = get_operands (insn->paroperands, line);
while (insn->ptm->name && strcasecmp (insn->ptm->name,
while (insn->tm->name && strcasecmp (insn->tm->name,
insn->mnemonic) == 0)
{
if (strcasecmp (insn->ptm->parname, insn->parmnemonic) == 0)
if (strcasecmp (insn->tm->parname, insn->parmnemonic) == 0)
{
valid_mnemonic = 1;
if (insn->paropcount >= insn->ptm->minops
&& insn->paropcount <= insn->ptm->maxops
if (insn->paropcount >= insn->tm->minops
&& insn->paropcount <= insn->tm->maxops
&& operands_match (insn, insn->paroperands,
insn->paropcount,
insn->ptm->paroperand_types,
insn->ptm->minops, insn->ptm->maxops))
insn->tm->paroperand_types,
insn->tm->minops, insn->tm->maxops))
{
return 1;
}
}
++(insn->ptm);
++(insn->tm);
}
if (valid_mnemonic)
as_bad (_("Invalid operand (s) for parallel instruction \"%s\""),

18
gas/config/tc-tic54x.h
View File

@ -83,26 +83,26 @@ extern void tic54x_cons_fix_new PARAMS((fragS *,int,int,expressionS *));
*/
#define md_number_to_chars tic54x_number_to_chars
extern void tic54x_number_to_chars PARAMS((char *, valueT, int));
extern void tic54x_number_to_chars (char *, valueT, int);
#define tc_adjust_symtab() tic54x_adjust_symtab()
extern void tic54x_adjust_symtab PARAMS(());
extern void tic54x_adjust_symtab (void);
#define tc_unrecognized_line(ch) tic54x_unrecognized_line(ch)
extern int tic54x_unrecognized_line PARAMS((int ch));
extern int tic54x_unrecognized_line (int ch);
#define md_parse_name(s,e,c) tic54x_parse_name(s,e)
extern int tic54x_parse_name PARAMS((char *name, expressionS *e));
extern int tic54x_parse_name (char *name, expressionS *e);
#define md_undefined_symbol(s) tic54x_undefined_symbol(s)
extern symbolS *tic54x_undefined_symbol PARAMS((char *name));
extern symbolS *tic54x_undefined_symbol (char *name);
#define md_macro_start() tic54x_macro_start()
extern void tic54x_macro_start ();
extern void tic54x_macro_start (void);
#define md_macro_end() tic54x_macro_end()
extern void tic54x_macro_end ();
extern void tic54x_macro_end (void);
#define md_macro_info(args) tic54x_macro_info(args)
extern void tic54x_macro_info PARAMS((void *macro));
#define tc_frob_label(sym) tic54x_define_label (sym)
extern void tic54x_define_label PARAMS((symbolS *));
#define md_start_line_hook() tic54x_start_line_hook()
extern void tic54x_start_line_hook ();
extern void tic54x_start_line_hook (void);
#define md_estimate_size_before_relax(f,s) \
tic54x_estimate_size_before_relax(f,s)
@ -125,4 +125,6 @@ extern void tic54x_convert_frag(bfd *, segT, fragS *);
/* spruce up the listing output */
#define LISTING_WORD_SIZE 2
extern void tic54x_global (int);
#endif

16
gas/testsuite/ChangeLog
View File

@ -1,3 +1,18 @@
2001-11-11 Timothy Wall <twall@alum.mit.edu>
* gas/tic54x/sections.[sd]: Check for named, initialized sections
defaulting to CODE and DATA.
* gas/tic54x/align.[sd]: While breaking compatibility with TI's
assembler, the difference is not worth the effort to fix. We'd
prefer the assembler *not* fill the section alignment.
* gas/tic54x/all-opcodes.d: Verify Lmem opcodes have proper
length.
* gas/tic54x/labels.s: Document differences from TI tools.
* gas/tic54x/extaddr.d: Match output.
* gas/all/gas.exp: On c54x targets, don't do any tests that use
p2align.
* gas/macros/macros.exp: Expect failure matching use of .ascii.
2001-11-12 Thiemo Seufer <seufer@csv.ica.uni-stuttgart.de>
* gas/mips/mips.exp: Change naming of some conditionals to reflect
@ -60,6 +75,7 @@
* gas/mmix: New testsuite directory.
>>>>>>> 1.244
2001-10-24 Chris Demetriou <cgd@broadcom.com>
* gas/mips/ld-empic.d: Remove extra whitespace at beginning of

3
gas/testsuite/gas/all/gas.exp
View File

@ -155,10 +155,9 @@ proc test_cond {} {
# again, p2align doesn't work on c54x target
if ![istarget *c54x*-*-*] then {
test_cond
run_dump_test incbin
}
run_dump_test incbin
# FIXME: this is here cause of a bug in DejaGnu 1.1.1. When it is no longer
# in use, then this can be removed.
if [info exists errorInfo] then {

2
gas/testsuite/gas/macros/macros.exp
View File

@ -33,5 +33,7 @@ if { ![istarget hppa*-*-*] || [istarget *-*-linux*]} {
setup_xfail sh*-*-*
setup_xfail z8k*-*-*
setup_xfail h8300*-*-*
# FIXME: Due to difference in what "consecutive octets" means.
setup_xfail *c54x*-*-*
run_dump_test strings
}

8
gas/testsuite/gas/tic54x/align.d
View File

@ -1,12 +1,12 @@
#objdump: -d --headers
#name: c54x align (NOTE: .even is broken on TI tools)
#name: c54x align
.*: +file format .*c54x.*
Sections:
Idx Name Size VMA LMA File off Algn
0 .text 00000089 00000000 00000000 0000.... 2..7
CONTENTS, ALLOC, LOAD, CODE
0 .text 000000c0 00000000 00000000 0000.... 2..7
CONTENTS, ALLOC, LOAD, ....
1 .data 00000005 00000000 00000000 0000.... 2..1
CONTENTS, ALLOC, LOAD, DATA
2 .bss 00000000 00000000 00000000 0000.... 2..0
@ -53,4 +53,4 @@ Disassembly of section .text:
86: 0005.*
87: 0006.*
88: 0007.*
...

5
gas/testsuite/gas/tic54x/align.s
View File

@ -1,6 +1,10 @@
* alignment directives
* .even == .align 1, .even 2 == longword boundary
* .align [size] ; size is number of words (value must be a power of 2)
* NOTE: .even is broken on TI tools, so theirs won't align .data
* NOTE: TI defaults text section to DATA until opcodes are seen
* NOTE: GAS will fill a section to its alignment; it should probably not
* in this case.
.global even, align2, align8, align128
.field 2, 3
.field 11, 8
@ -15,6 +19,7 @@ align8 .word 8
.align
align128 .byte 4
.word 0,1,2,3,4,5,6,7
* TI .text section total size is 0x89 words; GAS fills to 0xc0
.data
.field 2, 3
.field 11, 8

142
gas/testsuite/gas/tic54x/all-opcodes.d
View File

@ -61593,17 +61593,17 @@ Disassembly of section .text:
f08f: 53f0.*
f090: 1ead.*
f091: 50f8.*
f092: 1eae.*
f092: 1eae
f093: 51f8.*
f094: 1eaf.*
f094: 1eaf
f095: 50f8.*
f096: 1eb0.*
f096: 1eb0
f097: 52f8.*
f098: 1eb1.*
f098: 1eb1
f099: 53f8.*
f09a: 1eb2.*
f09a: 1eb2
f09b: 53f8.*
f09c: 1eb3.*
f09c: 1eb3
f09d: 5081.*
f09e: 5181.*
f09f: 5081.*
@ -61707,17 +61707,17 @@ Disassembly of section .text:
f101: 53f1.*
f102: 1ec5.*
f103: 50f8.*
f104: 1ec6.*
f104: 1ec6
f105: 51f8.*
f106: 1ec7.*
f106: 1ec7
f107: 50f8.*
f108: 1ec8.*
f108: 1ec8
f109: 52f8.*
f10a: 1ec9.*
f10a: 1ec9
f10b: 53f8.*
f10c: 1eca.*
f10c: 1eca
f10d: 53f8.*
f10e: 1ecb.*
f10e: 1ecb
f10f: 5082.*
f110: 5182.*
f111: 5082.*
@ -61821,17 +61821,17 @@ Disassembly of section .text:
f173: 53f2.*
f174: 1edd.*
f175: 50f8.*
f176: 1ede.*
f176: 1ede
f177: 51f8.*
f178: 1edf.*
f178: 1edf
f179: 50f8.*
f17a: 1ee0.*
f17a: 1ee0
f17b: 52f8.*
f17c: 1ee1.*
f17c: 1ee1
f17d: 53f8.*
f17e: 1ee2.*
f17e: 1ee2
f17f: 53f8.*
f180: 1ee3.*
f180: 1ee3
f181: 5083.*
f182: 5183.*
f183: 5083.*
@ -61935,17 +61935,17 @@ Disassembly of section .text:
f1e5: 53f3.*
f1e6: 1ef5.*
f1e7: 50f8.*
f1e8: 1ef6.*
f1e8: 1ef6
f1e9: 51f8.*
f1ea: 1ef7.*
f1ea: 1ef7
f1eb: 50f8.*
f1ec: 1ef8.*
f1ec: 1ef8
f1ed: 52f8.*
f1ee: 1ef9.*
f1ee: 1ef9
f1ef: 53f8.*
f1f0: 1efa.*
f1f0: 1efa
f1f1: 53f8.*
f1f2: 1efb.*
f1f2: 1efb
f1f3: 5084.*
f1f4: 5184.*
f1f5: 5084.*
@ -62049,17 +62049,17 @@ Disassembly of section .text:
f257: 53f4.*
f258: 1f0d.*
f259: 50f8.*
f25a: 1f0e.*
f25a: 1f0e
f25b: 51f8.*
f25c: 1f0f.*
f25c: 1f0f
f25d: 50f8.*
f25e: 1f10.*
f25e: 1f10
f25f: 52f8.*
f260: 1f11.*
f260: 1f11
f261: 53f8.*
f262: 1f12.*
f262: 1f12
f263: 53f8.*
f264: 1f13.*
f264: 1f13
f265: 5085.*
f266: 5185.*
f267: 5085.*
@ -62163,17 +62163,17 @@ Disassembly of section .text:
f2c9: 53f5.*
f2ca: 1f25.*
f2cb: 50f8.*
f2cc: 1f26.*
f2cc: 1f26
f2cd: 51f8.*
f2ce: 1f27.*
f2ce: 1f27
f2cf: 50f8.*
f2d0: 1f28.*
f2d0: 1f28
f2d1: 52f8.*
f2d2: 1f29.*
f2d2: 1f29
f2d3: 53f8.*
f2d4: 1f2a.*
f2d4: 1f2a
f2d5: 53f8.*
f2d6: 1f2b.*
f2d6: 1f2b
f2d7: 5086.*
f2d8: 5186.*
f2d9: 5086.*
@ -62277,17 +62277,17 @@ Disassembly of section .text:
f33b: 53f6.*
f33c: 1f3d.*
f33d: 50f8.*
f33e: 1f3e.*
f33e: 1f3e
f33f: 51f8.*
f340: 1f3f.*
f340: 1f3f
f341: 50f8.*
f342: 1f40.*
f342: 1f40
f343: 52f8.*
f344: 1f41.*
f344: 1f41
f345: 53f8.*
f346: 1f42.*
f346: 1f42
f347: 53f8.*
f348: 1f43.*
f348: 1f43
f349: 5087.*
f34a: 5187.*
f34b: 5087.*
@ -62391,17 +62391,17 @@ Disassembly of section .text:
f3ad: 53f7.*
f3ae: 1f55.*
f3af: 50f8.*
f3b0: 1f56.*
f3b0: 1f56
f3b1: 51f8.*
f3b2: 1f57.*
f3b2: 1f57
f3b3: 50f8.*
f3b4: 1f58.*
f3b4: 1f58
f3b5: 52f8.*
f3b6: 1f59.*
f3b6: 1f59
f3b7: 53f8.*
f3b8: 1f5a.*
f3b8: 1f5a
f3b9: 53f8.*
f3ba: 1f5b.*
f3ba: 1f5b
f3bb: 5a63.*
f3bc: 5b64.*
f3bd: 5a80.*
@ -62439,9 +62439,9 @@ Disassembly of section .text:
f3dd: 5bf0.*
f3de: 1f61.*
f3df: 5af8.*
f3e0: 1f62.*
f3e0: 1f62
f3e1: 5bf8.*
f3e2: 1f63.*
f3e2: 1f63
f3e3: 5a81.*
f3e4: 5b81.*
f3e5: 5a89.*
@ -62477,9 +62477,9 @@ Disassembly of section .text:
f403: 5bf1.*
f404: 1f69.*
f405: 5af8.*
f406: 1f6a.*
f406: 1f6a
f407: 5bf8.*
f408: 1f6b.*
f408: 1f6b
f409: 5a82.*
f40a: 5b82.*
f40b: 5a8a.*
@ -62515,9 +62515,9 @@ Disassembly of section .text:
f429: 5bf2.*
f42a: 1f71.*
f42b: 5af8.*
f42c: 1f72.*
f42c: 1f72
f42d: 5bf8.*
f42e: 1f73.*
f42e: 1f73
f42f: 5a83.*
f430: 5b83.*
f431: 5a8b.*
@ -62553,9 +62553,9 @@ Disassembly of section .text:
f44f: 5bf3.*
f450: 1f79.*
f451: 5af8.*
f452: 1f7a.*
f452: 1f7a
f453: 5bf8.*
f454: 1f7b.*
f454: 1f7b
f455: 5a84.*
f456: 5b84.*
f457: 5a8c.*
@ -62591,9 +62591,9 @@ Disassembly of section .text:
f475: 5bf4.*
f476: 1f81.*
f477: 5af8.*
f478: 1f82.*
f478: 1f82
f479: 5bf8.*
f47a: 1f83.*
f47a: 1f83
f47b: 5a85.*
f47c: 5b85.*
f47d: 5a8d.*
@ -62629,9 +62629,9 @@ Disassembly of section .text:
f49b: 5bf5.*
f49c: 1f89.*
f49d: 5af8.*
f49e: 1f8a.*
f49e: 1f8a
f49f: 5bf8.*
f4a0: 1f8b.*
f4a0: 1f8b
f4a1: 5a86.*
f4a2: 5b86.*
f4a3: 5a8e.*
@ -62667,9 +62667,9 @@ Disassembly of section .text:
f4c1: 5bf6.*
f4c2: 1f91.*
f4c3: 5af8.*
f4c4: 1f92.*
f4c4: 1f92
f4c5: 5bf8.*
f4c6: 1f93.*
f4c6: 1f93
f4c7: 5a87.*
f4c8: 5b87.*
f4c9: 5a8f.*
@ -62705,9 +62705,9 @@ Disassembly of section .text:
f4e7: 5bf7.*
f4e8: 1f99.*
f4e9: 5af8.*
f4ea: 1f9a.*
f4ea: 1f9a
f4eb: 5bf8.*
f4ec: 1f9b.*
f4ec: 1f9b
f4ed: 4d65.*
f4ee: 4d80.*
f4ef: 4d88.*
@ -62727,7 +62727,7 @@ Disassembly of section .text:
f4fd: 4df0.*
f4fe: 1f9e.*
f4ff: 4df8.*
f500: 1f9f.*
f500: 1f9f
f501: 4d81.*
f502: 4d89.*
f503: 4d91.*
@ -62746,7 +62746,7 @@ Disassembly of section .text:
f510: 4df1.*
f511: 1fa2.*
f512: 4df8.*
f513: 1fa3.*
f513: 1fa3
f514: 4d82.*
f515: 4d8a.*
f516: 4d92.*
@ -63794,13 +63794,13 @@ Disassembly of section .text:
f928: 4ed0.*
f929: 4ed8.*
f92a: 4ee0.*
f92b: 207c.*
f92b: 207c
f92c: 4ee8.*
f92d: 207d.*
f92d: 207d
f92e: 4ef0.*
f92f: 207e.*
f930: 4ef8.*
f931: 207f.*
f92f: 207e
f930: 4ef8 dst a,\*(.*)
f931: 207f
f932: 4e81.*
f933: 4e89.*
f934: 4e91.*

1
gas/testsuite/gas/tic54x/extaddr.d
View File

@ -53,4 +53,5 @@ Disassembly of section .text:
10080: f881.*
10081: 0080.*
.*10080: ARELEXT.*
...

90
gas/testsuite/gas/tic54x/extaddr.s
View File

@ -1,45 +1,45 @@
*
* Extended addressing support
*
.version 548
.far_mode
.global F1, start, end
; LDX pseudo-op
ldx #F1,16,a ; load upper 8 bits of extended address
or #F1,a,a ; load remaining bits
bacc a
; extended addressing functions
start:
fb end
fbd end
nop
nop
fbacc a
fbaccd a
nop
nop
fcala a
fcalad b
nop
nop
fcall end
fcalld end
nop
nop
fret
fretd
nop
nop
frete
freted
nop
nop
.space 16*0xFFFF
.align 0x80
end:
fb end
.end
*
* Extended addressing support
*
.version 548
.far_mode
.global F1, start, end
; LDX pseudo-op
ldx #F1,16,a ; load upper 8 bits of extended address
or #F1,a,a ; load remaining bits
bacc a
; extended addressing functions
start:
fb end
fbd end
nop
nop
fbacc a
fbaccd a
nop
nop
fcala a
fcalad b
nop
nop
fcall end
fcalld end
nop
nop
fret
fretd
nop
nop
frete
freted
nop
nop
.space 16*0xFFFF
.align 0x80
end:
fb end
.end

110
gas/testsuite/gas/tic54x/labels.s
View File

@ -1,55 +1,55 @@
* local labels
* two forms, $[0-9] and label? are allowed
* Local labels are undefined/reset in one of four ways:
* .newblock
* changing sections
* entering an include file
* leaving an include file
.global addra, addrb, addrc
label1: ld addra,a
sub addrb,a
bc $1, alt ; generates frag!
ld addrb, a
b $2
$1: ld addra,a
$2 add addrc,a
.newblock
bc $1,alt
stl a, addrc
$1 nop
* #1, First definition of local label 'lab'
nop
lab? add #1,a ; reports as line 17?
b lab?
* #2, Included file also defines local label 'lab'
.copy labels.inc
* #3, Next definition; exit from .copy clears all locals
lab? add #3,a ; reports as line 22?
b lab?
* #4, Next definition is within macro; supersedes previous definition while
* within the macro
mac .macro
lab? add #4,a ; line 31?
b lab?
.endm
* Macro invocation
mac
* This reference should resolve to definition #3
after_macro:
b lab?
* Section change clears all definitions
.sect new_section
nop
lab? add #5,a
nop
nop
b lab?
* Newblock directive clears local labels
.newblock
lab? add #6,a
nop
nop
b lab?
.end
* local labels
* two forms, $[0-9] and label? are allowed
* Local labels are undefined/reset in one of four ways:
* .newblock
* changing sections
* entering an include file
* leaving an include file
.global addra, addrb, addrc
label1: ld addra,a
sub addrb,a
bc $1, alt ; generates frag!
ld addrb, a
b $2
$1: ld addra,a
$2 add addrc,a
.newblock
bc $1,alt
stl a, addrc
$1 nop
* #1, First definition of local label 'lab'
nop
lab? add #1,a ; reports as line 17?
b lab?
* #2, Included file also defines local label 'lab'
.copy labels.inc
* #3, Next definition; exit from .copy clears all locals
lab? add #3,a ; reports as line 22?
b lab?
* #4, Next definition is within macro; supersedes previous definition while
* within the macro
mac .macro
lab? add #4,a ; line 31?
b lab?
.endm
* Macro invocation
mac
* This reference should resolve to definition #3
after_macro:
b lab?
* Section change clears all definitions; TI defaults to CODE section w/o name
.sect new_section
nop
lab? add #5,a
nop
nop
b lab?
* Newblock directive clears local labels
.newblock
lab? add #6,a
nop
nop
b lab?
.end

18
gas/testsuite/gas/tic54x/sections.d
View File

@ -16,9 +16,9 @@ Idx Name Size VMA LMA File off Algn
4 vectors 00000002 00000000 00000000 0000.... 2..0
CONTENTS, ALLOC, LOAD, CODE, BLOCK
5 clink 00000002 00000000 00000000 0000.... 2..0
CONTENTS, ALLOC, LOAD, CODE, CLINK
CONTENTS, ALLOC, LOAD, DATA, CLINK
6 blksect 00000002 00000000 00000000 0000.... 2..0
CONTENTS, ALLOC, LOAD, CODE, BLOCK
CONTENTS, ALLOC, LOAD, DATA, BLOCK
Disassembly of section .text:
00000000 <.text>:
@ -72,15 +72,5 @@ Disassembly of section .text:
Disassembly of section vectors:
00000000 <vectors>:
0: 0011.*
1: 0033.*
Disassembly of section clink:
00000000 <clink>:
0: 0022.*
1: 0044.*
Disassembly of section blksect:
00000000 <blksect>:
0: 1234.*
1: 4321.*
0: f495.*
1: f495.*

145
gas/testsuite/gas/tic54x/sections.s
View File

@ -1,72 +1,73 @@
*
* Various sections directives
* .bss, .data, .sect, .text, .usect
* .align, .space, .bes
*
; default section (should be .text)
.word 0x1234 ; this should be put in .text
; initialized data
.data
.global coeff
coeff .word 011h,022h,033h
; uninitialized data
.global B1, buffer
.bss buffer, 10
B1: .usect ".bss", 10 ; alocate 10 words
; more initialized data in .data
.global ptr
ptr .word 0123h
; .text section
.text
.global add, aloop
add: ld 0fh,a
aloop: sub #1,a
bc aloop,ageq
; more initialized data into .data
.data
.global ivals
ivals .word 0aah, 0bbh, 0cch
; define another section for more variables
.global var2, inbuf, align2
var2 .usect "newvars", 1 ; with quotes
inbuf .usect newvars, 7, 1 ; w/o quotes, block 7 words
align2 .usect newvars, 15, ,1 ; 15 words aligned
; more code
.text
.global mpy, mloop
mpy: ld 0ah,b
mloop: mpy #0ah,b
bc mloop,bnov
.global space, bes, spacep, besp
space: .space 64 ; points to first word of block
bes: .bes 64 ; points to last word of block
spacep: .word space
besp: .word bes
.global pk1, pk2, pk3, endpk1, endpk2, endpk3
pk1: .space 20
endpk1: .space 12
pk2: .bes 20
endpk2 .bes 12
pk3: .space 20
endpk3: .bes 12
; named initialized section (TI assembler marks this as DATA, not CODE)
.sect "vectors"
.word 011h, 033h
; named, initialized section, no quotes (TI assembler marks as DATA)
.sect clink
.clink ; mark section clink as STYP_CLINK
.word 022h, 044h
.sect "blksect" ; (TI assembler marks this as DATA)
.word 0x1234,0x4321
.sblock "blksect", vectors ; set block flag on blksect and vectors
.end
*
* Various sections directives
* .bss, .data, .sect, .text, .usect
* .align, .space, .bes
*
; default section (should be .text)
.word 0x1234 ; this should be put in .text
; initialized data
.data
.global coeff
coeff .word 011h,022h,033h
; uninitialized data
.global B1, buffer
.bss buffer, 10
B1: .usect ".bss", 10 ; alocate 10 words
; more initialized data in .data
.global ptr
ptr .word 0123h
; .text section
.text
.global add, aloop
add: ld 0fh,a
aloop: sub #1,a
bc aloop,ageq
; more initialized data into .data
.data
.global ivals
ivals .word 0aah, 0bbh, 0cch
; define another section for more variables
.global var2, inbuf, align2
var2 .usect "newvars", 1 ; with quotes
inbuf .usect newvars, 7, 1 ; w/o quotes, block 7 words
align2 .usect newvars, 15, ,1 ; 15 words aligned
; more code
.text
.global mpy, mloop
mpy: ld 0ah,b
mloop: mpy #0ah,b
bc mloop,bnov
.global space, bes, spacep, besp
space: .space 64 ; points to first word of block
bes: .bes 64 ; points to last word of block
spacep: .word space
besp: .word bes
.global pk1, pk2, pk3, endpk1, endpk2, endpk3
pk1: .space 20
endpk1: .space 12
pk2: .bes 20
endpk2 .bes 12
pk3: .space 20
endpk3: .bes 12
; named initialized section (CODE)
.sect "vectors"
nop
nop
; named, initialized section, no quotes (DATA)
.sect clink
.clink ; mark section clink as STYP_CLINK
.word 022h, 044h
.sect "blksect" ; (DATA)
.word 0x1234,0x4321
.sblock "blksect", vectors ; set block flag on blksect and vectors
.end

7
gas/write.c
View File

@ -2430,7 +2430,12 @@ relax_segment (segment_frag_root, segment)
know (!(S_GET_SEGMENT (symbolP) == SEG_ABSOLUTE)
|| (symbolP->sy_frag == &zero_address_frag));
#endif
target += S_GET_VALUE (symbolP);
/* Convert from an actual address to an octet offset
into the section. Here it is assumed that the
section's VMA is zero, and can omit subtracting it
from the symbol's value to get the address offset. */
know (S_GET_SECTION (symbolP)->vma == 0);
target += S_GET_VALUE (symbolP) * OCTETS_PER_BYTE;
}
know (fragP->fr_next);

7
include/coff/ChangeLog
View File

@ -1,3 +1,10 @@
2001-11-11 Timothy Wall <twall@alum.mit.edu>
* ti.h: Move arch-specific stuff from here...
(COFF_ADJUST_SYM_IN/OUT): Optionally put page flag into symbol
value.
* tic54x.h: ...to here.
2001-10-26 Christian Groessler <cpg@aladdin.de>
* external.h (GET_LINENO_LNNO): Fix usage of H_GET_32/16.

38
include/coff/ti.h
View File

@ -95,7 +95,7 @@ struct external_filehdr
do \
{ \
((struct internal_filehdr *)(dst))->f_target_id = \
H_GET_16 (abfd, ((FILHDR *)(src))->f_target_id); \
H_GET_16 (abfd, ((FILHDR *)(src))->f_target_id); \
} \
while (0)
#endif
@ -260,27 +260,6 @@ struct external_scnhdr {
} \
while (0)
/* Page macros
The first GDB port requires flags in its remote memory access commands to
distinguish between data/prog space. Hopefully we can make this go away
eventually. Stuff the page in the upper bits of a 32-bit address, since
the c5x family only uses 16 or 23 bits.
c2x, c5x and most c54x devices have 16-bit addresses, but the c548 has
23-bit program addresses. Make sure the page flags don't interfere.
These flags are used by GDB to identify the destination page for
addresses.
*/
/* recognized load pages */
#define PG_PROG 0x0 /* PROG page */
#define PG_DATA 0x1 /* DATA page */
#define ADDR_MASK 0x00FFFFFF
#define PG_TO_FLAG(p) (((unsigned long)(p) & 0xFF) << 24)
#define FLAG_TO_PG(f) (((f) >> 24) & 0xFF)
/*
* names of "special" sections
*/
@ -411,13 +390,23 @@ union external_auxent {
H_PUT_16 (abfd, ((class != C_FIELD) ? (in) * 8 : (in)), \
ext->x_sym.x_misc.x_lnsz.x_size)
/* TI COFF stores offsets for MOS and MOU in bits; BFD expects bytes */
/* TI COFF stores offsets for MOS and MOU in bits; BFD expects bytes
Also put the load page flag of the section into the symbol value if it's an
address. */
#ifndef NEEDS_PAGE
#define NEEDS_PAGE(X) 0
#define PAGE_MASK 0
#endif
#define COFF_ADJUST_SYM_IN_POST(ABFD, EXT, INT) \
do \
{ \
struct internal_syment *dst = (struct internal_syment *)(INT); \
if (dst->n_sclass == C_MOS || dst->n_sclass == C_MOU) \
dst->n_value /= 8; \
else if (NEEDS_PAGE (dst->n_sclass)) { \
asection *scn = coff_section_from_bfd_index (abfd, dst->n_scnum); \
dst->n_value |= (scn->lma & PAGE_MASK); \
} \
} \
while (0)
@ -428,6 +417,9 @@ union external_auxent {
SYMENT *dst = (SYMENT *)(EXT); \
if (src->n_sclass == C_MOU || src->n_sclass == C_MOS) \
H_PUT_32 (abfd, src->n_value * 8, dst->e_value); \
else if (NEEDS_PAGE (src->n_sclass)) { \
H_PUT_32 (abfd, src->n_value &= ~PAGE_MASK, dst->e_value); \
} \
} \
while (0)

27
include/coff/tic54x.h
View File

@ -18,8 +18,8 @@
Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
#ifndef COFF_TIC54X_H
#define COFF_TIC54X_H
#define TIC54X_TARGET_ID 0x98
#define TIC54XALGMAGIC 0x009B /* c54x algebraic assembler output */
#define TIC5X_TARGET_ID 0x92
@ -29,6 +29,31 @@
#define TICOFF_TARGET_ARCH bfd_arch_tic54x
#define TICOFF_DEFAULT_MAGIC TICOFF1MAGIC /* we use COFF1 for compatibility */
/* Page macros
The first GDB port requires flags in its remote memory access commands to
distinguish between data/prog space. Hopefully we can make this go away
eventually. Stuff the page in the upper bits of a 32-bit address, since
the c5x family only uses 16 or 23 bits.
c2x, c5x and most c54x devices have 16-bit addresses, but the c548 has
23-bit program addresses. Make sure the page flags don't interfere.
These flags are used by GDB to identify the destination page for
addresses.
*/
/* Recognized load pages (by common convention). */
#define PG_PROG 0x0 /* PROG page */
#define PG_DATA 0x1 /* DATA page */
#define PG_IO 0x2 /* I/O page */
/** Indicate whether the given storage class requires a page flag. */
#define NEEDS_PAGE(X) ((X)==C_EXT)
#define PAGE_MASK 0xFF000000
#define ADDR_MASK 0x00FFFFFF
#define PG_TO_FLAG(p) (((unsigned long)(p) & 0xFF) << 24)
#define FLAG_TO_PG(f) (((f) >> 24) & 0xFF)
#include "coff/ti.h"
#endif /* COFF_TIC54X_H */

5
include/opcode/ChangeLog
View File

@ -1,3 +1,8 @@
2001-11-11 Timothy Wall <twall@alum.mit.edu>
* tic54x.h: Revise opcode layout; don't really need a separate
structure for parallel opcodes.
2001-11-13 Zack Weinberg <zack@codesourcery.com>
Alan Modra <amodra@bigpond.net.au>

28
include/opcode/tic54x.h
View File

@ -19,8 +19,8 @@ along with this file; see the file COPYING. If not, write to the Free
Software Foundation, 59 Temple Place - Suite 330, Boston, MA
02111-1307, USA. */
#ifndef _TIC54X_H_
#define _TIC54X_H_
#ifndef _opcode_tic54x_h_
#define _opcode_tic54x_h_
typedef struct _symbol
{
@ -86,7 +86,6 @@ typedef struct _template
{
/* The opcode mnemonic */
const char *name;
unsigned int words; /* insn size in words */
int minops, maxops; /* min/max operand count */
/* The significant bits in the opcode. Other bits are zero.
@ -141,27 +140,24 @@ typedef struct _template
#define FL_NR 0x100 /* no repeat allowed */
#define FL_SMR 0x200 /* Smem read (for flagging write-only *+ARx */
#define FL_PAR 0x400 /* Parallel instruction. */
unsigned short opcode2, mask2; /* some insns have an extended opcode */
const char* parname;
enum optype paroperand_types[MAX_OPERANDS];
} template;
typedef struct _partemplate {
char *name;
char *parname;
unsigned int words; /* length in words */
int minops, maxops; /* min/max operand count for 2nd part of insn */
unsigned short opcode;
unsigned short mask;
enum optype operand_types[MAX_OPERANDS];
enum optype paroperand_types[MAX_OPERANDS];
} partemplate;
extern const template tic54x_unknown_opcode;
extern const template tic54x_optab[];
extern const partemplate tic54x_paroptab[];
extern const template tic54x_paroptab[];
extern const symbol mmregs[], regs[];
extern const symbol condition_codes[], cc2_codes[], status_bits[];
extern const symbol cc3_codes[];
extern const char *misc_symbols[];
struct disassemble_info;
extern const template* tic54x_get_insn (struct disassemble_info *,
bfd_vma, unsigned short, int *);
#endif /* TIC54X_H */
#endif /* _opcode_tic54x_h_ */

8
opcodes/ChangeLog
View File

@ -1,3 +1,11 @@
2001-11-11 Timothy Wall <twall@alum.mit.edu>
* tic54x-dis.c: Use revised opcode structure. Export opcode
template lookup.
(has_lkaddr): Don't forget about Lmem insns.
* tic54x-opc.c: Add emulation trap. Parallel table now uses
standard opcode templates.
2001-11-13 Zack Weinberg <zack@codesourcery.com>
* i386-dis.c (grps): Change "sldt", "str", and "smsw" entries

117
opcodes/tic54x-dis.c
View File

@ -25,22 +25,14 @@
#include "opcode/tic54x.h"
#include "coff/tic54x.h"
typedef struct _instruction {
int parallel;
template *tm;
partemplate *ptm;
} instruction;
static int has_lkaddr PARAMS ((unsigned short, template *));
static int get_insn_size PARAMS ((unsigned short, instruction *));
static int get_instruction PARAMS ((disassemble_info *, bfd_vma,
unsigned short, instruction *));
static int print_instruction PARAMS ((disassemble_info *, bfd_vma,
unsigned short, char *,
enum optype [], int, int));
static int print_parallel_instruction PARAMS ((disassemble_info *, bfd_vma,
unsigned short, partemplate *,
int));
static int has_lkaddr (unsigned short, const template *);
static int get_insn_size (unsigned short, const template *);
static int print_instruction (disassemble_info *, bfd_vma,
unsigned short, const char *,
const enum optype [], int, int);
static int print_parallel_instruction (disassemble_info *, bfd_vma,
unsigned short,
const template *, int);
static int sprint_dual_address (disassemble_info *,char [],
unsigned short);
static int sprint_indirect_address (disassemble_info *,char [],
@ -52,14 +44,12 @@ static int sprint_condition (disassemble_info *,char *,unsigned short);
static int sprint_cc2 (disassemble_info *,char *,unsigned short);
int
print_insn_tic54x (memaddr, info)
bfd_vma memaddr;
disassemble_info *info;
print_insn_tic54x (bfd_vma memaddr, disassemble_info *info)
{
bfd_byte opbuf[2];
unsigned short opcode;
int status, size;
instruction insn;
const template* tm;
status = (*info->read_memory_func) (memaddr, opbuf, 2, info);
if (status != 0)
@ -69,26 +59,24 @@ print_insn_tic54x (memaddr, info)
}
opcode = bfd_getl16 (opbuf);
if (!get_instruction (info, memaddr, opcode, &insn))
return -1;
tm = tic54x_get_insn (info, memaddr, opcode, &size);
size = get_insn_size (opcode, &insn);
info->bytes_per_line = 2;
info->bytes_per_chunk = 2;
info->octets_per_byte = 2;
info->display_endian = BFD_ENDIAN_LITTLE;
if (insn.parallel)
if (tm->flags & FL_PAR)
{
if (!print_parallel_instruction (info, memaddr, opcode, insn.ptm, size))
if (!print_parallel_instruction (info, memaddr, opcode, tm, size))
return -1;
}
else
{
if (!print_instruction (info, memaddr, opcode,
(char *) insn.tm->name,
insn.tm->operand_types,
size, (insn.tm->flags & FL_EXT)))
(char *) tm->name,
tm->operand_types,
size, (tm->flags & FL_EXT)))
return -1;
}
@ -96,33 +84,28 @@ print_insn_tic54x (memaddr, info)
}
static int
has_lkaddr (opcode, tm)
unsigned short opcode;
template *tm;
has_lkaddr (unsigned short memdata, const template *tm)
{
return (IS_LKADDR (opcode)
return (IS_LKADDR (memdata)
&& (OPTYPE (tm->operand_types[0]) == OP_Smem
|| OPTYPE (tm->operand_types[1]) == OP_Smem
|| OPTYPE (tm->operand_types[2]) == OP_Smem
|| OPTYPE (tm->operand_types[1]) == OP_Sind));
|| OPTYPE (tm->operand_types[1]) == OP_Sind
|| OPTYPE (tm->operand_types[0]) == OP_Lmem
|| OPTYPE (tm->operand_types[1]) == OP_Lmem));
}
/* always returns 1 (whether an insn template was found) since we provide an
"unknown instruction" template */
static int
get_instruction (info, addr, opcode, insn)
disassemble_info *info;
bfd_vma addr;
unsigned short opcode;
instruction *insn;
const template*
tic54x_get_insn (disassemble_info *info, bfd_vma addr,
unsigned short memdata, int *size)
{
template * tm;
partemplate * ptm;
const template *tm = NULL;
insn->parallel = 0;
for (tm = (template *) tic54x_optab; tm->name; tm++)
for (tm = tic54x_optab; tm->name; tm++)
{
if (tm->opcode == (opcode & tm->mask))
if (tm->opcode == (memdata & tm->mask))
{
/* a few opcodes span two words */
if (tm->flags & FL_EXT)
@ -130,54 +113,52 @@ get_instruction (info, addr, opcode, insn)
/* if lk addressing is used, the second half of the opcode gets
pushed one word later */
bfd_byte opbuf[2];
bfd_vma addr2 = addr + 1 + has_lkaddr (opcode, tm);
bfd_vma addr2 = addr + 1 + has_lkaddr (memdata, tm);
int status = (*info->read_memory_func) (addr2, opbuf, 2, info);
// FIXME handle errors
if (status == 0)
{
unsigned short opcode2 = bfd_getl16 (opbuf);
if (tm->opcode2 == (opcode2 & tm->mask2))
unsigned short data2 = bfd_getl16 (opbuf);
if (tm->opcode2 == (data2 & tm->mask2))
{
insn->tm = tm;
return 1;
if (size) *size = get_insn_size (memdata, tm);
return tm;
}
}
}
else
{
insn->tm = tm;
return 1;
if (size) *size = get_insn_size (memdata, tm);
return tm;
}
}
}
for (ptm = (partemplate *) tic54x_paroptab; ptm->name; ptm++)
for (tm = (template *) tic54x_paroptab; tm->name; tm++)
{
if (ptm->opcode == (opcode & ptm->mask))
if (tm->opcode == (memdata & tm->mask))
{
insn->parallel = 1;
insn->ptm = ptm;
return 1;
if (size) *size = get_insn_size (memdata, tm);
return tm;
}
}
insn->tm = (template *) &tic54x_unknown_opcode;
return 1;
if (size) *size = 1;
return &tic54x_unknown_opcode;
}
static int
get_insn_size (opcode, insn)
unsigned short opcode;
instruction *insn;
get_insn_size (unsigned short memdata, const template *insn)
{
int size;
if (insn->parallel)
if (insn->flags & FL_PAR)
{
/* only non-parallel instructions support lk addressing */
size = insn->ptm->words;
size = insn->words;
}
else
{
size = insn->tm->words + has_lkaddr (opcode, insn->tm);
size = insn->words + has_lkaddr (memdata, insn);
}
return size;
@ -188,8 +169,8 @@ print_instruction (info, memaddr, opcode, tm_name, tm_operands, size, ext)
disassemble_info *info;
bfd_vma memaddr;
unsigned short opcode;
char *tm_name;
enum optype tm_operands[];
const char *tm_name;
const enum optype tm_operands[];
int size;
int ext;
{
@ -486,7 +467,7 @@ print_parallel_instruction (info, memaddr, opcode, ptm, size)
disassemble_info *info;
bfd_vma memaddr;
unsigned short opcode;
partemplate *ptm;
const template *ptm;
int size;
{
print_instruction (info, memaddr, opcode,
@ -541,7 +522,7 @@ sprint_direct_address (info, buf, opcode)
unsigned short opcode;
{
/* FIXME -- look up relocation if available */
return sprintf (buf, "0x??%02x", (int) (opcode & 0x7F));
return sprintf (buf, "DP+0x%02x", (int) (opcode & 0x7F));
}
static int

476
opcodes/tic54x-opc.c
View File

@ -18,6 +18,7 @@
02111-1307, USA. */
#include "sysdep.h"
#include "dis-asm.h"
#include "opcode/tic54x.h"
/* these are the only register names not found in mmregs */
@ -225,252 +226,269 @@ const char *misc_symbols[] = {
as an argument are arranged so that the more restrictive (predefined
symbol) version is checked first (marked "SRC").
*/
#define ZPAR 0,{OP_None}
#define REST 0,0,ZPAR
#define XREST ZPAR
const template tic54x_unknown_opcode =
{ "???", 1,0,0,0x0000, 0x0000, {0}, 0, 0, 0};
{ "???", 1,0,0,0x0000, 0x0000, {0}, 0, REST};
const template tic54x_optab[] = {
/* these must precede bc/bcd, cc/ccd to avoid misinterpretation */
{ "fb", 2,1,1,0xF880, 0xFF80, {OP_xpmad}, B_BRANCH|FL_FAR|FL_NR, 0, 0 },
{ "fbd", 2,1,1,0xFA80, 0xFF80, {OP_xpmad}, B_BRANCH|FL_FAR|FL_DELAY|FL_NR, 0, 0 },
{ "fcall", 2,1,1,0xF980, 0xFF80, {OP_xpmad}, B_BRANCH|FL_FAR|FL_NR, 0, 0 },
{ "fcalld",2,1,1,0xFB80, 0xFF80, {OP_xpmad}, B_BRANCH|FL_FAR|FL_DELAY|FL_NR, 0, 0 },
{ "fb", 2,1,1,0xF880, 0xFF80, {OP_xpmad}, B_BRANCH|FL_FAR|FL_NR, REST},
{ "fbd", 2,1,1,0xFA80, 0xFF80, {OP_xpmad}, B_BRANCH|FL_FAR|FL_DELAY|FL_NR, REST},
{ "fcall", 2,1,1,0xF980, 0xFF80, {OP_xpmad}, B_BRANCH|FL_FAR|FL_NR, REST},
{ "fcalld",2,1,1,0xFB80, 0xFF80, {OP_xpmad}, B_BRANCH|FL_FAR|FL_DELAY|FL_NR, REST},
{ "abdst", 1,2,2,0xE300, 0xFF00, {OP_Xmem,OP_Ymem}, 0, 0, 0 },
{ "abs", 1,1,2,0xF485, 0xFCFF, {OP_SRC,OPT|OP_DST}, 0, 0, 0 },
{ "add", 1,1,3,0xF400, 0xFCE0, {OP_SRC,OPT|OP_SHIFT,OPT|OP_DST}, 0, 0, 0 },/*SRC*/
{ "add", 1,2,3,0xF480, 0xFCFF, {OP_SRC,OP_ASM,OPT|OP_DST}, 0, 0, 0},/*SRC*/
{ "add", 1,2,2,0x0000, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR, 0, 0 },
{ "add", 1,3,3,0x0400, 0xFE00, {OP_Smem,OP_TS,OP_SRC1}, FL_SMR, 0, 0 },
{ "add", 1,3,4,0x3C00, 0xFC00, {OP_Smem,OP_16,OP_SRC,OPT|OP_DST}, FL_SMR, 0, 0 },
{ "add", 1,3,3,0x9000, 0xFE00, {OP_Xmem,OP_SHFT,OP_SRC1}, 0, 0, 0 },/*PREFER*/
{ "abdst", 1,2,2,0xE300, 0xFF00, {OP_Xmem,OP_Ymem}, 0, REST},
{ "abs", 1,1,2,0xF485, 0xFCFF, {OP_SRC,OPT|OP_DST}, 0, REST},
{ "add", 1,1,3,0xF400, 0xFCE0, {OP_SRC,OPT|OP_SHIFT,OPT|OP_DST}, 0, REST},/*SRC*/
{ "add", 1,2,3,0xF480, 0xFCFF, {OP_SRC,OP_ASM,OPT|OP_DST}, 0, REST},/*SRC*/
{ "add", 1,2,2,0x0000, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR, REST},
{ "add", 1,3,3,0x0400, 0xFE00, {OP_Smem,OP_TS,OP_SRC1}, FL_SMR, REST},
{ "add", 1,3,4,0x3C00, 0xFC00, {OP_Smem,OP_16,OP_SRC,OPT|OP_DST}, FL_SMR, REST},
{ "add", 1,3,3,0x9000, 0xFE00, {OP_Xmem,OP_SHFT,OP_SRC1}, 0, REST},/*PREFER*/
{ "add", 2,2,4,0x6F00, 0xFF00, {OP_Smem,OPT|OP_SHIFT,OP_SRC,OPT|OP_DST},
FL_EXT|FL_SMR, 0x0C00, 0xFCE0},
{ "add", 1,3,3,0xA000, 0xFE00, {OP_Xmem,OP_Ymem,OP_DST}, 0, 0, 0},
{ "add", 2,2,4,0xF000, 0xFCF0, {OP_lk,OPT|OP_SHIFT,OP_SRC,OPT|OP_DST}, 0, 0, 0 },
{ "add", 2,3,4,0xF060, 0xFCFF, {OP_lk,OP_16,OP_SRC,OPT|OP_DST}, 0, 0, 0 },
{ "addc", 1,2,2,0x0600, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR, 0, 0 },
{ "addm", 2,2,2,0x6B00, 0xFF00, {OP_lk,OP_Smem}, FL_NR|FL_SMR, 0, 0 },
{ "adds", 1,2,2,0x0200, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR, 0, 0 },
{ "and", 1,1,3,0xF080, 0xFCE0, {OP_SRC,OPT|OP_SHIFT,OPT|OP_DST}, 0, 0, 0 },
{ "and", 1,2,2,0x1800, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR, 0, 0 },
{ "and", 2,2,4,0xF030, 0xFCF0, {OP_lk,OPT|OP_SHFT,OP_SRC,OPT|OP_DST}, 0, 0, 0 },
{ "and", 2,3,4,0xF063, 0xFCFF, {OP_lk,OP_16,OP_SRC,OPT|OP_DST}, 0, 0, 0 },
{ "andm", 2,2,2,0x6800, 0xFF00, {OP_lk,OP_Smem}, FL_NR, 0, 0 },
{ "b", 2,1,1,0xF073, 0xFFFF, {OP_pmad}, B_BRANCH|FL_NR, 0, 0 },
{ "bd", 2,1,1,0xF273, 0xFFFF, {OP_pmad}, B_BRANCH|FL_DELAY|FL_NR, 0, 0 },
{ "bacc", 1,1,1,0xF4E2, 0xFEFF, {OP_SRC1}, B_BACC|FL_NR, 0, 0 },
{ "baccd", 1,1,1,0xF6E2, 0xFEFF, {OP_SRC1}, B_BACC|FL_DELAY|FL_NR, 0, 0 },
{ "banz", 2,2,2,0x6C00, 0xFF00, {OP_pmad,OP_Sind}, B_BRANCH|FL_NR, 0, 0 },
{ "banzd", 2,2,2,0x6E00, 0xFF00, {OP_pmad,OP_Sind}, B_BRANCH|FL_DELAY|FL_NR, 0, 0 },
FL_EXT|FL_SMR, 0x0C00, 0xFCE0, XREST},
{ "add", 1,3,3,0xA000, 0xFE00, {OP_Xmem,OP_Ymem,OP_DST}, 0, REST},
{ "add", 2,2,4,0xF000, 0xFCF0, {OP_lk,OPT|OP_SHIFT,OP_SRC,OPT|OP_DST}, 0, REST},
{ "add", 2,3,4,0xF060, 0xFCFF, {OP_lk,OP_16,OP_SRC,OPT|OP_DST}, 0, REST},
{ "addc", 1,2,2,0x0600, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR, REST},
{ "addm", 2,2,2,0x6B00, 0xFF00, {OP_lk,OP_Smem}, FL_NR|FL_SMR, REST},
{ "adds", 1,2,2,0x0200, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR, REST},
{ "and", 1,1,3,0xF080, 0xFCE0, {OP_SRC,OPT|OP_SHIFT,OPT|OP_DST}, 0, REST},
{ "and", 1,2,2,0x1800, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR, REST },
{ "and", 2,2,4,0xF030, 0xFCF0, {OP_lk,OPT|OP_SHFT,OP_SRC,OPT|OP_DST}, 0, REST},
{ "and", 2,3,4,0xF063, 0xFCFF, {OP_lk,OP_16,OP_SRC,OPT|OP_DST}, 0, REST},
{ "andm", 2,2,2,0x6800, 0xFF00, {OP_lk,OP_Smem}, FL_NR, REST},
{ "b", 2,1,1,0xF073, 0xFFFF, {OP_pmad}, B_BRANCH|FL_NR, REST},
{ "bd", 2,1,1,0xF273, 0xFFFF, {OP_pmad}, B_BRANCH|FL_DELAY|FL_NR, REST},
{ "bacc", 1,1,1,0xF4E2, 0xFEFF, {OP_SRC1}, B_BACC|FL_NR, REST},
{ "baccd", 1,1,1,0xF6E2, 0xFEFF, {OP_SRC1}, B_BACC|FL_DELAY|FL_NR, REST},
{ "banz", 2,2,2,0x6C00, 0xFF00, {OP_pmad,OP_Sind}, B_BRANCH|FL_NR, REST},
{ "banzd", 2,2,2,0x6E00, 0xFF00, {OP_pmad,OP_Sind}, B_BRANCH|FL_DELAY|FL_NR, REST},
{ "bc", 2,2,4,0xF800, 0xFF00, {OP_pmad,OP_CC,OPT|OP_CC,OPT|OP_CC},
B_BRANCH|FL_NR, 0, 0 },
B_BRANCH|FL_NR, REST},
{ "bcd", 2,2,4,0xFA00, 0xFF00, {OP_pmad,OP_CC,OPT|OP_CC,OPT|OP_CC},
B_BRANCH|FL_DELAY|FL_NR, 0, 0 },
{ "bit", 1,2,2,0x9600, 0xFF00, {OP_Xmem,OP_BITC}, 0, 0, 0 },
{ "bitf", 2,2,2,0x6100, 0xFF00, {OP_Smem,OP_lk}, FL_SMR, 0, 0 },
{ "bitt", 1,1,1,0x3400, 0xFF00, {OP_Smem}, FL_SMR, 0, 0 },
{ "cala", 1,1,1,0xF4E3, 0xFEFF, {OP_SRC1}, B_BACC|FL_NR, 0, 0 },
{ "calad", 1,1,1,0xF6E3, 0xFEFF, {OP_SRC1}, B_BACC|FL_DELAY|FL_NR, 0, 0 },
{ "call", 2,1,1,0xF074, 0xFFFF, {OP_pmad}, B_BRANCH|FL_NR, 0, 0 },
{ "calld", 2,1,1,0xF274, 0xFFFF, {OP_pmad}, B_BRANCH|FL_DELAY|FL_NR, 0, 0 },
B_BRANCH|FL_DELAY|FL_NR, REST},
{ "bit", 1,2,2,0x9600, 0xFF00, {OP_Xmem,OP_BITC}, 0, REST},
{ "bitf", 2,2,2,0x6100, 0xFF00, {OP_Smem,OP_lk}, FL_SMR, REST},
{ "bitt", 1,1,1,0x3400, 0xFF00, {OP_Smem}, FL_SMR, REST},
{ "cala", 1,1,1,0xF4E3, 0xFEFF, {OP_SRC1}, B_BACC|FL_NR, REST},
{ "calad", 1,1,1,0xF6E3, 0xFEFF, {OP_SRC1}, B_BACC|FL_DELAY|FL_NR, REST},
{ "call", 2,1,1,0xF074, 0xFFFF, {OP_pmad}, B_BRANCH|FL_NR, REST},
{ "calld", 2,1,1,0xF274, 0xFFFF, {OP_pmad}, B_BRANCH|FL_DELAY|FL_NR, REST},
{ "cc", 2,2,4,0xF900, 0xFF00, {OP_pmad,OP_CC,OPT|OP_CC,OPT|OP_CC},
B_BRANCH|FL_NR, 0, 0 },
B_BRANCH|FL_NR, REST},
{ "ccd", 2,2,4,0xFB00, 0xFF00, {OP_pmad,OP_CC,OPT|OP_CC,OPT|OP_CC},
B_BRANCH|FL_DELAY|FL_NR, 0, 0 },
{ "cmpl", 1,1,2,0xF493, 0xFCFF, {OP_SRC,OPT|OP_DST}, 0, 0, 0 },
{ "cmpm", 2,2,2,0x6000, 0xFF00, {OP_Smem,OP_lk}, FL_SMR, 0, 0 },
{ "cmpr", 1,2,2,0xF4A8, 0xFCF8, {OP_CC3,OP_ARX}, FL_NR, 0, 0 },
{ "cmps", 1,2,2,0x8E00, 0xFE00, {OP_SRC1,OP_Smem}, 0, 0, 0 },
{ "dadd", 1,2,3,0x5000, 0xFC00, {OP_Lmem,OP_SRC,OPT|OP_DST}, 0, 0, 0 },
{ "dadst", 1,2,2,0x5A00, 0xFE00, {OP_Lmem,OP_DST}, 0, 0, 0 },
{ "delay", 1,1,1,0x4D00, 0xFF00, {OP_Smem}, FL_SMR, 0, 0 },
{ "dld", 1,2,2,0x5600, 0xFE00, {OP_Lmem,OP_DST}, 0, 0, 0 },
{ "drsub", 1,2,2,0x5800, 0xFE00, {OP_Lmem,OP_SRC1}, 0, 0, 0 },
{ "dsadt", 1,2,2,0x5E00, 0xFE00, {OP_Lmem,OP_DST}, 0, 0, 0 },
{ "dst", 1,2,2,0x4E00, 0xFE00, {OP_SRC1,OP_Lmem}, FL_NR, 0, 0 },
{ "dsub", 1,2,2,0x5400, 0xFE00, {OP_Lmem,OP_SRC1}, 0, 0, 0 },
{ "dsubt", 1,2,2,0x5C00, 0xFE00, {OP_Lmem,OP_DST}, 0, 0, 0 },
{ "exp", 1,1,1,0xF48E, 0xFEFF, {OP_SRC1}, 0, 0, 0 },
{ "fbacc", 1,1,1,0xF4E6, 0xFEFF, {OP_SRC1}, B_BACC|FL_FAR|FL_NR, 0, 0 },
{ "fbaccd",1,1,1,0xF6E6, 0xFEFF, {OP_SRC1}, B_BACC|FL_FAR|FL_DELAY|FL_NR, 0, 0 },
{ "fcala", 1,1,1,0xF4E7, 0xFEFF, {OP_SRC1}, B_BACC|FL_FAR|FL_NR, 0, 0 },
{ "fcalad",1,1,1,0xF6E7, 0xFEFF, {OP_SRC1}, B_BACC|FL_FAR|FL_DELAY|FL_NR, 0, 0 },
{ "firs", 2,3,3,0xE000, 0xFF00, {OP_Xmem,OP_Ymem,OP_pmad}, 0, 0, 0 },
{ "frame", 1,1,1,0xEE00, 0xFF00, {OP_k8}, 0, 0, 0 },
{ "fret", 1,0,0,0xF4E4, 0xFFFF, {OP_None}, B_RET|FL_FAR|FL_NR, 0, 0 },
{ "fretd", 1,0,0,0xF6E4, 0xFFFF, {OP_None}, B_RET|FL_FAR|FL_DELAY|FL_NR, 0, 0 },
{ "frete", 1,0,0,0xF4E5, 0xFFFF, {OP_None}, B_RET|FL_FAR|FL_NR, 0, 0 },
{ "freted",1,0,0,0xF6E5, 0xFFFF, {OP_None}, B_RET|FL_FAR|FL_DELAY|FL_NR, 0, 0 },
{ "idle", 1,1,1,0xF4E1, 0xFCFF, {OP_123}, FL_NR, 0, 0 },
{ "intr", 1,1,1,0xF7C0, 0xFFE0, {OP_031}, B_BRANCH|FL_NR, 0, 0 },
{ "ld", 1,2,3,0xF482, 0xFCFF, {OP_SRC,OP_ASM,OPT|OP_DST}, 0, 0, 0 },/*SRC*/
{ "ld", 1,2,3,0xF440, 0xFCE0, {OP_SRC,OPT|OP_SHIFT,OP_DST}, 0, 0, 0 },/*SRC*/
B_BRANCH|FL_DELAY|FL_NR, REST},
{ "cmpl", 1,1,2,0xF493, 0xFCFF, {OP_SRC,OPT|OP_DST}, 0, REST},
{ "cmpm", 2,2,2,0x6000, 0xFF00, {OP_Smem,OP_lk}, FL_SMR, REST},
{ "cmpr", 1,2,2,0xF4A8, 0xFCF8, {OP_CC3,OP_ARX}, FL_NR, REST},
{ "cmps", 1,2,2,0x8E00, 0xFE00, {OP_SRC1,OP_Smem}, 0, REST},
{ "dadd", 1,2,3,0x5000, 0xFC00, {OP_Lmem,OP_SRC,OPT|OP_DST}, 0, REST},
{ "dadst", 1,2,2,0x5A00, 0xFE00, {OP_Lmem,OP_DST}, 0, REST},
{ "delay", 1,1,1,0x4D00, 0xFF00, {OP_Smem}, FL_SMR, REST},
{ "dld", 1,2,2,0x5600, 0xFE00, {OP_Lmem,OP_DST}, 0, REST},
{ "drsub", 1,2,2,0x5800, 0xFE00, {OP_Lmem,OP_SRC1}, 0, REST},
{ "dsadt", 1,2,2,0x5E00, 0xFE00, {OP_Lmem,OP_DST}, 0, REST},
{ "dst", 1,2,2,0x4E00, 0xFE00, {OP_SRC1,OP_Lmem}, FL_NR, REST},
{ "dsub", 1,2,2,0x5400, 0xFE00, {OP_Lmem,OP_SRC1}, 0, REST},
{ "dsubt", 1,2,2,0x5C00, 0xFE00, {OP_Lmem,OP_DST}, 0, REST},
{ "estop", 1,0,0,0xF4F0, 0xFFFF, {OP_None}, 0, REST}, /* undocumented */
{ "exp", 1,1,1,0xF48E, 0xFEFF, {OP_SRC1}, 0, REST},
{ "fbacc", 1,1,1,0xF4E6, 0xFEFF, {OP_SRC1}, B_BACC|FL_FAR|FL_NR, REST},
{ "fbaccd",1,1,1,0xF6E6, 0xFEFF, {OP_SRC1}, B_BACC|FL_FAR|FL_DELAY|FL_NR, REST},
{ "fcala", 1,1,1,0xF4E7, 0xFEFF, {OP_SRC1}, B_BACC|FL_FAR|FL_NR, REST},
{ "fcalad",1,1,1,0xF6E7, 0xFEFF, {OP_SRC1}, B_BACC|FL_FAR|FL_DELAY|FL_NR, REST},
{ "firs", 2,3,3,0xE000, 0xFF00, {OP_Xmem,OP_Ymem,OP_pmad}, 0, REST},
{ "frame", 1,1,1,0xEE00, 0xFF00, {OP_k8}, 0, REST},
{ "fret", 1,0,0,0xF4E4, 0xFFFF, {OP_None}, B_RET|FL_FAR|FL_NR, REST},
{ "fretd", 1,0,0,0xF6E4, 0xFFFF, {OP_None}, B_RET|FL_FAR|FL_DELAY|FL_NR, REST},
{ "frete", 1,0,0,0xF4E5, 0xFFFF, {OP_None}, B_RET|FL_FAR|FL_NR, REST},
{ "freted",1,0,0,0xF6E5, 0xFFFF, {OP_None}, B_RET|FL_FAR|FL_DELAY|FL_NR, REST},
{ "idle", 1,1,1,0xF4E1, 0xFCFF, {OP_123}, FL_NR, REST},
{ "intr", 1,1,1,0xF7C0, 0xFFE0, {OP_031}, B_BRANCH|FL_NR, REST},
{ "ld", 1,2,3,0xF482, 0xFCFF, {OP_SRC,OP_ASM,OPT|OP_DST}, 0, REST},/*SRC*/
{ "ld", 1,2,3,0xF440, 0xFCE0, {OP_SRC,OPT|OP_SHIFT,OP_DST}, 0, REST},/*SRC*/
/* alternate syntax */
{ "ld", 1,2,3,0xF440, 0xFCE0, {OP_SRC,OP_SHIFT,OPT|OP_DST}, 0, 0, 0 },/*SRC*/
{ "ld", 1,2,2,0xE800, 0xFE00, {OP_k8u,OP_DST}, 0, 0, 0 },/*SRC*/
{ "ld", 1,2,2,0xED00, 0xFFE0, {OP_k5,OP_ASM}, 0, 0, 0 },/*SRC*/
{ "ld", 1,2,2,0xF4A0, 0xFFF8, {OP_k3,OP_ARP}, FL_NR, 0, 0 },/*SRC*/
{ "ld", 1,2,2,0xEA00, 0xFE00, {OP_k9,OP_DP}, FL_NR, 0, 0 },/*PREFER */
{ "ld", 1,2,2,0x3000, 0xFF00, {OP_Smem,OP_T}, FL_SMR, 0, 0 },/*SRC*/
{ "ld", 1,2,2,0x4600, 0xFF00, {OP_Smem,OP_DP}, FL_SMR, 0, 0 },/*SRC*/
{ "ld", 1,2,2,0x3200, 0xFF00, {OP_Smem,OP_ASM}, FL_SMR, 0, 0 },/*SRC*/
{ "ld", 1,2,2,0x1000, 0xFE00, {OP_Smem,OP_DST}, FL_SMR, 0, 0 },
{ "ld", 1,3,3,0x1400, 0xFE00, {OP_Smem,OP_TS,OP_DST}, FL_SMR, 0, 0 },
{ "ld", 1,3,3,0x4400, 0xFE00, {OP_Smem,OP_16,OP_DST}, FL_SMR, 0, 0 },
{ "ld", 1,3,3,0x9400, 0xFE00, {OP_Xmem,OP_SHFT,OP_DST}, 0, 0, 0 },/*PREFER*/
{ "ld", 1,2,3,0xF440, 0xFCE0, {OP_SRC,OP_SHIFT,OPT|OP_DST}, 0, REST},/*SRC*/
{ "ld", 1,2,2,0xE800, 0xFE00, {OP_k8u,OP_DST}, 0, REST},/*SRC*/
{ "ld", 1,2,2,0xED00, 0xFFE0, {OP_k5,OP_ASM}, 0, REST},/*SRC*/
{ "ld", 1,2,2,0xF4A0, 0xFFF8, {OP_k3,OP_ARP}, FL_NR, REST},/*SRC*/
{ "ld", 1,2,2,0xEA00, 0xFE00, {OP_k9,OP_DP}, FL_NR, REST},/*PREFER */
{ "ld", 1,2,2,0x3000, 0xFF00, {OP_Smem,OP_T}, FL_SMR, REST},/*SRC*/
{ "ld", 1,2,2,0x4600, 0xFF00, {OP_Smem,OP_DP}, FL_SMR, REST},/*SRC*/
{ "ld", 1,2,2,0x3200, 0xFF00, {OP_Smem,OP_ASM}, FL_SMR, REST},/*SRC*/
{ "ld", 1,2,2,0x1000, 0xFE00, {OP_Smem,OP_DST}, FL_SMR, REST},
{ "ld", 1,3,3,0x1400, 0xFE00, {OP_Smem,OP_TS,OP_DST}, FL_SMR, REST},
{ "ld", 1,3,3,0x4400, 0xFE00, {OP_Smem,OP_16,OP_DST}, FL_SMR, REST},
{ "ld", 1,3,3,0x9400, 0xFE00, {OP_Xmem,OP_SHFT,OP_DST}, 0, REST},/*PREFER*/
{ "ld", 2,2,3,0x6F00, 0xFF00, {OP_Smem,OPT|OP_SHIFT,OP_DST},
FL_EXT|FL_SMR, 0x0C40, 0xFEE0 },
{ "ld", 2,2,3,0xF020, 0xFEF0, {OP_lk,OPT|OP_SHFT,OP_DST}, 0, 0, 0 },
{ "ld", 2,3,3,0xF062, 0xFEFF, {OP_lk,OP_16,OP_DST}, 0, 0, 0 },
{ "ldm", 1,2,2,0x4800, 0xFE00, {OP_MMR,OP_DST}, 0, 0, 0 },
{ "ldr", 1,2,2,0x1600, 0xFE00, {OP_Smem,OP_DST}, FL_SMR, 0, 0 },
{ "ldu", 1,2,2,0x1200, 0xFE00, {OP_Smem,OP_DST}, FL_SMR, 0, 0 },
{ "ldx", 2,3,3,0xF062, 0xFEFF, {OP_xpmad_ms7,OP_16,OP_DST}, FL_FAR, 0, 0},/*pseudo-op*/
{ "lms", 1,2,2,0xE100, 0xFF00, {OP_Xmem,OP_Ymem}, 0, 0, 0 },
{ "ltd", 1,1,1,0x4C00, 0xFF00, {OP_Smem}, FL_SMR, 0, 0 },
{ "mac", 1,2,2,0x2800, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR, 0, 0 },
{ "mac", 1,3,4,0xB000, 0xFC00, {OP_Xmem,OP_Ymem,OP_SRC,OPT|OP_DST}, 0, 0, 0 },
{ "mac", 2,2,3,0xF067, 0xFCFF, {OP_lk,OP_SRC,OPT|OP_DST}, 0, 0, 0 },
{ "mac", 2,3,4,0x6400, 0xFC00, {OP_Smem,OP_lk,OP_SRC,OPT|OP_DST}, FL_SMR, 0, 0 },
{ "macr", 1,2,2,0x2A00, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR, 0, 0 },
{ "macr", 1,3,4,0xB400, 0xFC00, {OP_Xmem,OP_Ymem,OP_SRC,OPT|OP_DST},FL_SMR, 0, 0 },
{ "maca", 1,2,3,0xF488, 0xFCFF, {OP_T,OP_SRC,OPT|OP_DST}, FL_SMR, 0, 0 },/*SRC*/
{ "maca", 1,1,2,0x3500, 0xFF00, {OP_Smem,OPT|OP_B}, FL_SMR, 0, 0 },
{ "macar", 1,2,3,0xF489, 0xFCFF, {OP_T,OP_SRC,OPT|OP_DST}, FL_SMR, 0, 0 },/*SRC*/
{ "macar", 1,1,2,0x3700, 0xFF00, {OP_Smem,OPT|OP_B}, FL_SMR, 0, 0 },
{ "macd", 2,3,3,0x7A00, 0xFE00, {OP_Smem,OP_pmad,OP_SRC1}, FL_SMR, 0, 0 },
{ "macp", 2,3,3,0x7800, 0xFE00, {OP_Smem,OP_pmad,OP_SRC1}, FL_SMR, 0, 0 },
{ "macsu", 1,3,3,0xA600, 0xFE00, {OP_Xmem,OP_Ymem,OP_SRC1}, 0, 0, 0 },
{ "mar", 1,1,1,0x6D00, 0xFF00, {OP_Smem}, 0, 0, 0 },
{ "mas", 1,2,2,0x2C00, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR, 0, 0 },
{ "mas", 1,3,4,0xB800, 0xFC00, {OP_Xmem,OP_Ymem,OP_SRC,OPT|OP_DST}, 0, 0, 0 },
{ "masr", 1,2,2,0x2E00, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR, 0, 0 },
{ "masr", 1,3,4,0xBC00, 0xFC00, {OP_Xmem,OP_Ymem,OP_SRC,OPT|OP_DST}, 0, 0, 0 },
{ "masa", 1,2,3,0xF48A, 0xFCFF, {OP_T,OP_SRC,OPT|OP_DST}, 0, 0, 0 },/*SRC*/
{ "masa", 1,1,2,0x3300, 0xFF00, {OP_Smem,OPT|OP_B}, FL_SMR, 0, 0 },
{ "masar", 1,2,3,0xF48B, 0xFCFF, {OP_T,OP_SRC,OPT|OP_DST}, 0, 0, 0 },
{ "max", 1,1,1,0xF486, 0xFEFF, {OP_DST}, 0, 0, 0 },
{ "min", 1,1,1,0xF487, 0xFEFF, {OP_DST}, 0, 0, 0 },
{ "mpy", 1,2,2,0x2000, 0xFE00, {OP_Smem,OP_DST}, FL_SMR, 0, 0 },
{ "mpy", 1,3,3,0xA400, 0xFE00, {OP_Xmem,OP_Ymem,OP_DST}, 0, 0, 0 },
{ "mpy", 2,3,3,0x6200, 0xFE00, {OP_Smem,OP_lk,OP_DST}, FL_SMR, 0, 0 },
{ "mpy", 2,2,2,0xF066, 0xFEFF, {OP_lk,OP_DST}, 0, 0, 0 },
{ "mpyr", 1,2,2,0x2200, 0xFE00, {OP_Smem,OP_DST}, FL_SMR, 0, 0 },
{ "mpya", 1,1,1,0xF48C, 0xFEFF, {OP_DST}, 0, 0, 0 }, /*SRC*/
{ "mpya", 1,1,1,0x3100, 0xFF00, {OP_Smem}, FL_SMR, 0, 0 },
{ "mpyu", 1,2,2,0x2400, 0xFE00, {OP_Smem,OP_DST}, FL_SMR, 0, 0 },
{ "mvdd", 1,2,2,0xE500, 0xFF00, {OP_Xmem,OP_Ymem}, 0, 0, 0 },
{ "mvdk", 2,2,2,0x7100, 0xFF00, {OP_Smem,OP_dmad}, FL_SMR, 0, 0 },
{ "mvdm", 2,2,2,0x7200, 0xFF00, {OP_dmad,OP_MMR}, 0, 0, 0 },
{ "mvdp", 2,2,2,0x7D00, 0xFF00, {OP_Smem,OP_pmad}, FL_SMR, 0, 0 },
{ "mvkd", 2,2,2,0x7000, 0xFF00, {OP_dmad,OP_Smem}, 0, 0, 0 },
{ "mvmd", 2,2,2,0x7300, 0xFF00, {OP_MMR,OP_dmad}, 0, 0, 0 },
{ "mvmm", 1,2,2,0xE700, 0xFF00, {OP_MMRX,OP_MMRY}, FL_NR, 0, 0 },
{ "mvpd", 2,2,2,0x7C00, 0xFF00, {OP_pmad,OP_Smem}, 0, 0, 0 },
{ "neg", 1,1,2,0xF484, 0xFCFF, {OP_SRC,OPT|OP_DST}, 0, 0, 0 },
{ "nop", 1,0,0,0xF495, 0xFFFF, {OP_None}, 0, 0, 0 },
{ "norm", 1,1,2,0xF48F, 0xFCFF, {OP_SRC,OPT|OP_DST}, 0, 0, 0 },
{ "or", 1,1,3,0xF0A0, 0xFCE0, {OP_SRC,OPT|OP_SHIFT,OPT|OP_DST}, 0, 0, 0 },/*SRC*/
{ "or", 1,2,2,0x1A00, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR, 0, 0 },
{ "or", 2,2,4,0xF040, 0xFCF0, {OP_lk,OPT|OP_SHFT,OP_SRC,OPT|OP_DST}, 0, 0, 0 },
{ "or", 2,3,4,0xF064, 0xFCFF, {OP_lk,OP_16,OP_SRC,OPT|OP_DST}, 0, 0, 0 },
{ "orm", 2,2,2,0x6900, 0xFF00, {OP_lk,OP_Smem}, FL_NR|FL_SMR, 0, 0 },
{ "poly", 1,1,1,0x3600, 0xFF00, {OP_Smem}, FL_SMR, 0, 0 },
{ "popd", 1,1,1,0x8B00, 0xFF00, {OP_Smem}, 0, 0, 0 },
{ "popm", 1,1,1,0x8A00, 0xFF00, {OP_MMR}, 0, 0, 0 },
{ "portr", 2,2,2,0x7400, 0xFF00, {OP_PA,OP_Smem}, 0, 0, 0 },
{ "portw", 2,2,2,0x7500, 0xFF00, {OP_Smem,OP_PA}, FL_SMR, 0, 0 },
{ "pshd", 1,1,1,0x4B00, 0xFF00, {OP_Smem}, FL_SMR, 0, 0 },
{ "pshm", 1,1,1,0x4A00, 0xFF00, {OP_MMR}, 0, 0, 0 },
{ "ret", 1,0,0,0xFC00, 0xFFFF, {OP_None}, B_RET|FL_NR, 0, 0 },
{ "retd", 1,0,0,0xFE00, 0xFFFF, {OP_None}, B_RET|FL_DELAY|FL_NR, 0, 0 },
FL_EXT|FL_SMR, 0x0C40, 0xFEE0, XREST},
{ "ld", 2,2,3,0xF020, 0xFEF0, {OP_lk,OPT|OP_SHFT,OP_DST}, 0, REST},
{ "ld", 2,3,3,0xF062, 0xFEFF, {OP_lk,OP_16,OP_DST}, 0, REST},
{ "ldm", 1,2,2,0x4800, 0xFE00, {OP_MMR,OP_DST}, 0, REST},
{ "ldr", 1,2,2,0x1600, 0xFE00, {OP_Smem,OP_DST}, FL_SMR, REST},
{ "ldu", 1,2,2,0x1200, 0xFE00, {OP_Smem,OP_DST}, FL_SMR, REST},
{ "ldx", 2,3,3,0xF062, 0xFEFF, {OP_xpmad_ms7,OP_16,OP_DST}, FL_FAR, REST},/*pseudo-op*/
{ "lms", 1,2,2,0xE100, 0xFF00, {OP_Xmem,OP_Ymem}, 0, REST},
{ "ltd", 1,1,1,0x4C00, 0xFF00, {OP_Smem}, FL_SMR, REST},
{ "mac", 1,2,2,0x2800, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR, REST},
{ "mac", 1,3,4,0xB000, 0xFC00, {OP_Xmem,OP_Ymem,OP_SRC,OPT|OP_DST}, 0, REST},
{ "mac", 2,2,3,0xF067, 0xFCFF, {OP_lk,OP_SRC,OPT|OP_DST}, 0, REST},
{ "mac", 2,3,4,0x6400, 0xFC00, {OP_Smem,OP_lk,OP_SRC,OPT|OP_DST}, FL_SMR, REST},
{ "macr", 1,2,2,0x2A00, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR, REST},
{ "macr", 1,3,4,0xB400, 0xFC00, {OP_Xmem,OP_Ymem,OP_SRC,OPT|OP_DST},FL_SMR, REST},
{ "maca", 1,2,3,0xF488, 0xFCFF, {OP_T,OP_SRC,OPT|OP_DST}, FL_SMR, REST},/*SRC*/
{ "maca", 1,1,2,0x3500, 0xFF00, {OP_Smem,OPT|OP_B}, FL_SMR, REST},
{ "macar", 1,2,3,0xF489, 0xFCFF, {OP_T,OP_SRC,OPT|OP_DST}, FL_SMR, REST},/*SRC*/
{ "macar", 1,1,2,0x3700, 0xFF00, {OP_Smem,OPT|OP_B}, FL_SMR, REST},
{ "macd", 2,3,3,0x7A00, 0xFE00, {OP_Smem,OP_pmad,OP_SRC1}, FL_SMR, REST},
{ "macp", 2,3,3,0x7800, 0xFE00, {OP_Smem,OP_pmad,OP_SRC1}, FL_SMR, REST},
{ "macsu", 1,3,3,0xA600, 0xFE00, {OP_Xmem,OP_Ymem,OP_SRC1}, 0, REST},
{ "mar", 1,1,1,0x6D00, 0xFF00, {OP_Smem}, 0, REST},
{ "mas", 1,2,2,0x2C00, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR, REST},
{ "mas", 1,3,4,0xB800, 0xFC00, {OP_Xmem,OP_Ymem,OP_SRC,OPT|OP_DST}, 0, REST},
{ "masr", 1,2,2,0x2E00, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR, REST},
{ "masr", 1,3,4,0xBC00, 0xFC00, {OP_Xmem,OP_Ymem,OP_SRC,OPT|OP_DST}, 0, REST},
{ "masa", 1,2,3,0xF48A, 0xFCFF, {OP_T,OP_SRC,OPT|OP_DST}, 0, REST},/*SRC*/
{ "masa", 1,1,2,0x3300, 0xFF00, {OP_Smem,OPT|OP_B}, FL_SMR, REST},
{ "masar", 1,2,3,0xF48B, 0xFCFF, {OP_T,OP_SRC,OPT|OP_DST}, 0, REST},
{ "max", 1,1,1,0xF486, 0xFEFF, {OP_DST}, 0, REST},
{ "min", 1,1,1,0xF487, 0xFEFF, {OP_DST}, 0, REST},
{ "mpy", 1,2,2,0x2000, 0xFE00, {OP_Smem,OP_DST}, FL_SMR, REST},
{ "mpy", 1,3,3,0xA400, 0xFE00, {OP_Xmem,OP_Ymem,OP_DST}, 0, REST},
{ "mpy", 2,3,3,0x6200, 0xFE00, {OP_Smem,OP_lk,OP_DST}, FL_SMR, REST},
{ "mpy", 2,2,2,0xF066, 0xFEFF, {OP_lk,OP_DST}, 0, REST},
{ "mpyr", 1,2,2,0x2200, 0xFE00, {OP_Smem,OP_DST}, FL_SMR, REST},
{ "mpya", 1,1,1,0xF48C, 0xFEFF, {OP_DST}, 0, REST}, /*SRC*/
{ "mpya", 1,1,1,0x3100, 0xFF00, {OP_Smem}, FL_SMR, REST},
{ "mpyu", 1,2,2,0x2400, 0xFE00, {OP_Smem,OP_DST}, FL_SMR, REST},
{ "mvdd", 1,2,2,0xE500, 0xFF00, {OP_Xmem,OP_Ymem}, 0, REST},
{ "mvdk", 2,2,2,0x7100, 0xFF00, {OP_Smem,OP_dmad}, FL_SMR, REST},
{ "mvdm", 2,2,2,0x7200, 0xFF00, {OP_dmad,OP_MMR}, 0, REST},
{ "mvdp", 2,2,2,0x7D00, 0xFF00, {OP_Smem,OP_pmad}, FL_SMR, REST},
{ "mvkd", 2,2,2,0x7000, 0xFF00, {OP_dmad,OP_Smem}, 0, REST},
{ "mvmd", 2,2,2,0x7300, 0xFF00, {OP_MMR,OP_dmad}, 0, REST},
{ "mvmm", 1,2,2,0xE700, 0xFF00, {OP_MMRX,OP_MMRY}, FL_NR, REST},
{ "mvpd", 2,2,2,0x7C00, 0xFF00, {OP_pmad,OP_Smem}, 0, REST},
{ "neg", 1,1,2,0xF484, 0xFCFF, {OP_SRC,OPT|OP_DST}, 0, REST},
{ "nop", 1,0,0,0xF495, 0xFFFF, {OP_None}, 0, REST},
{ "norm", 1,1,2,0xF48F, 0xFCFF, {OP_SRC,OPT|OP_DST}, 0, REST},
{ "or", 1,1,3,0xF0A0, 0xFCE0, {OP_SRC,OPT|OP_SHIFT,OPT|OP_DST}, 0, REST},/*SRC*/
{ "or", 1,2,2,0x1A00, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR, REST},
{ "or", 2,2,4,0xF040, 0xFCF0, {OP_lk,OPT|OP_SHFT,OP_SRC,OPT|OP_DST}, 0, REST},
{ "or", 2,3,4,0xF064, 0xFCFF, {OP_lk,OP_16,OP_SRC,OPT|OP_DST}, 0, REST},
{ "orm", 2,2,2,0x6900, 0xFF00, {OP_lk,OP_Smem}, FL_NR|FL_SMR, REST},
{ "poly", 1,1,1,0x3600, 0xFF00, {OP_Smem}, FL_SMR, REST},
{ "popd", 1,1,1,0x8B00, 0xFF00, {OP_Smem}, 0, REST},
{ "popm", 1,1,1,0x8A00, 0xFF00, {OP_MMR}, 0, REST},
{ "portr", 2,2,2,0x7400, 0xFF00, {OP_PA,OP_Smem}, 0, REST},
{ "portw", 2,2,2,0x7500, 0xFF00, {OP_Smem,OP_PA}, FL_SMR, REST},
{ "pshd", 1,1,1,0x4B00, 0xFF00, {OP_Smem}, FL_SMR, REST},
{ "pshm", 1,1,1,0x4A00, 0xFF00, {OP_MMR}, 0, REST},
{ "ret", 1,0,0,0xFC00, 0xFFFF, {OP_None}, B_RET|FL_NR, REST},
{ "retd", 1,0,0,0xFE00, 0xFFFF, {OP_None}, B_RET|FL_DELAY|FL_NR, REST},
{ "rc", 1,1,3,0xFC00, 0xFF00, {OP_CC,OPT|OP_CC,OPT|OP_CC},
B_RET|FL_NR, 0, 0 },
B_RET|FL_NR, REST},
{ "rcd", 1,1,3,0xFE00, 0xFF00, {OP_CC,OPT|OP_CC,OPT|OP_CC},
B_RET|FL_DELAY|FL_NR, 0, 0 },
{ "reada", 1,1,1,0x7E00, 0xFF00, {OP_Smem}, 0, 0, 0 },
{ "reset", 1,0,0,0xF7E0, 0xFFFF, {OP_None}, FL_NR, 0, 0 },
{ "rete", 1,0,0,0xF4EB, 0xFFFF, {OP_None}, B_RET|FL_NR, 0, 0 },
{ "reted", 1,0,0,0xF6EB, 0xFFFF, {OP_None}, B_RET|FL_DELAY|FL_NR, 0, 0 },
{ "retf", 1,0,0,0xF49B, 0xFFFF, {OP_None}, B_RET|FL_NR, 0, 0 },
{ "retfd", 1,0,0,0xF69B, 0xFFFF, {OP_None}, B_RET|FL_DELAY|FL_NR, 0, 0 },
{ "rnd", 1,1,2,0xF49F, 0xFCFF, {OP_SRC,OPT|OP_DST}, FL_LP|FL_NR, 0, 0 },
{ "rol", 1,1,1,0xF491, 0xFEFF, {OP_SRC1}, 0, 0, 0 },
{ "roltc", 1,1,1,0xF492, 0xFEFF, {OP_SRC1}, 0, 0, 0 },
{ "ror", 1,1,1,0xF490, 0xFEFF, {OP_SRC1}, 0, 0, 0 },
{ "rpt", 1,1,1,0x4700, 0xFF00, {OP_Smem}, B_REPEAT|FL_NR|FL_SMR, 0, 0 },
{ "rpt", 1,1,1,0xEC00, 0xFF00, {OP_k8u}, B_REPEAT|FL_NR, 0, 0 },
{ "rpt", 2,1,1,0xF070, 0xFFFF, {OP_lku}, B_REPEAT|FL_NR, 0, 0 },
{ "rptb", 2,1,1,0xF072, 0xFFFF, {OP_pmad}, FL_NR, 0, 0 },
{ "rptbd", 2,1,1,0xF272, 0xFFFF, {OP_pmad}, FL_DELAY|FL_NR, 0, 0 },
{ "rptz", 2,2,2,0xF071, 0xFEFF, {OP_DST,OP_lku}, B_REPEAT|FL_NR, 0, 0 },
{ "rsbx", 1,1,2,0xF4B0, 0xFDF0, {OPT|OP_N,OP_SBIT}, FL_NR, 0, 0 },
{ "saccd", 1,3,3,0x9E00, 0xFE00, {OP_SRC1,OP_Xmem,OP_CC2}, 0, 0, 0 },
{ "sat", 1,1,1,0xF483, 0xFEFF, {OP_SRC1}, 0, 0, 0 },
{ "sfta", 1,2,3,0xF460, 0xFCE0, {OP_SRC,OP_SHIFT,OPT|OP_DST}, 0, 0, 0 },
{ "sftc", 1,1,1,0xF494, 0xFEFF, {OP_SRC1}, 0, 0, 0 },
{ "sftl", 1,2,3,0xF0E0, 0xFCE0, {OP_SRC,OP_SHIFT,OPT|OP_DST}, 0, 0, 0 },
{ "sqdst", 1,2,2,0xE200, 0xFF00, {OP_Xmem,OP_Ymem}, 0, 0, 0 },
{ "squr", 1,2,2,0xF48D, 0xFEFF, {OP_A,OP_DST}, 0, 0, 0 },/*SRC*/
{ "squr", 1,2,2,0x2600, 0xFE00, {OP_Smem,OP_DST}, FL_SMR, 0, 0 },
{ "squra", 1,2,2,0x3800, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR, 0, 0 },
{ "squrs", 1,2,2,0x3A00, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR, 0, 0 },
{ "srccd", 1,2,2,0x9D00, 0xFF00, {OP_Xmem,OP_CC2}, 0, 0, 0 },
{ "ssbx", 1,1,2,0xF5B0, 0xFDF0, {OPT|OP_N,OP_SBIT}, FL_NR, 0, 0 },
{ "st", 1,2,2,0x8C00, 0xFF00, {OP_T,OP_Smem}, 0, 0, 0 },
{ "st", 1,2,2,0x8D00, 0xFF00, {OP_TRN,OP_Smem}, 0, 0, 0 },
{ "st", 2,2,2,0x7600, 0xFF00, {OP_lk,OP_Smem}, 0, 0, 0 },
{ "sth", 1,2,2,0x8200, 0xFE00, {OP_SRC1,OP_Smem}, 0, 0, 0 },
{ "sth", 1,3,3,0x8600, 0xFE00, {OP_SRC1,OP_ASM,OP_Smem}, 0, 0, 0 },
{ "sth", 1,3,3,0x9A00, 0xFE00, {OP_SRC1,OP_SHFT,OP_Xmem}, 0, 0, 0 },
B_RET|FL_DELAY|FL_NR, REST},
{ "reada", 1,1,1,0x7E00, 0xFF00, {OP_Smem}, 0, REST},
{ "reset", 1,0,0,0xF7E0, 0xFFFF, {OP_None}, FL_NR, REST},
{ "rete", 1,0,0,0xF4EB, 0xFFFF, {OP_None}, B_RET|FL_NR, REST},
{ "reted", 1,0,0,0xF6EB, 0xFFFF, {OP_None}, B_RET|FL_DELAY|FL_NR, REST},
{ "retf", 1,0,0,0xF49B, 0xFFFF, {OP_None}, B_RET|FL_NR, REST},
{ "retfd", 1,0,0,0xF69B, 0xFFFF, {OP_None}, B_RET|FL_DELAY|FL_NR, REST},
{ "rnd", 1,1,2,0xF49F, 0xFCFF, {OP_SRC,OPT|OP_DST}, FL_LP|FL_NR, REST},
{ "rol", 1,1,1,0xF491, 0xFEFF, {OP_SRC1}, 0, REST},
{ "roltc", 1,1,1,0xF492, 0xFEFF, {OP_SRC1}, 0, REST},
{ "ror", 1,1,1,0xF490, 0xFEFF, {OP_SRC1}, 0, REST},
{ "rpt", 1,1,1,0x4700, 0xFF00, {OP_Smem}, B_REPEAT|FL_NR|FL_SMR, REST},
{ "rpt", 1,1,1,0xEC00, 0xFF00, {OP_k8u}, B_REPEAT|FL_NR, REST},
{ "rpt", 2,1,1,0xF070, 0xFFFF, {OP_lku}, B_REPEAT|FL_NR, REST},
{ "rptb", 2,1,1,0xF072, 0xFFFF, {OP_pmad}, FL_NR, REST},
{ "rptbd", 2,1,1,0xF272, 0xFFFF, {OP_pmad}, FL_DELAY|FL_NR, REST},
{ "rptz", 2,2,2,0xF071, 0xFEFF, {OP_DST,OP_lku}, B_REPEAT|FL_NR, REST},
{ "rsbx", 1,1,2,0xF4B0, 0xFDF0, {OPT|OP_N,OP_SBIT}, FL_NR, REST},
{ "saccd", 1,3,3,0x9E00, 0xFE00, {OP_SRC1,OP_Xmem,OP_CC2}, 0, REST},
{ "sat", 1,1,1,0xF483, 0xFEFF, {OP_SRC1}, 0, REST},
{ "sfta", 1,2,3,0xF460, 0xFCE0, {OP_SRC,OP_SHIFT,OPT|OP_DST}, 0, REST},
{ "sftc", 1,1,1,0xF494, 0xFEFF, {OP_SRC1}, 0, REST},
{ "sftl", 1,2,3,0xF0E0, 0xFCE0, {OP_SRC,OP_SHIFT,OPT|OP_DST}, 0, REST},
{ "sqdst", 1,2,2,0xE200, 0xFF00, {OP_Xmem,OP_Ymem}, 0, REST},
{ "squr", 1,2,2,0xF48D, 0xFEFF, {OP_A,OP_DST}, 0, REST},/*SRC*/
{ "squr", 1,2,2,0x2600, 0xFE00, {OP_Smem,OP_DST}, FL_SMR, REST},
{ "squra", 1,2,2,0x3800, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR, REST},
{ "squrs", 1,2,2,0x3A00, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR, REST},
{ "srccd", 1,2,2,0x9D00, 0xFF00, {OP_Xmem,OP_CC2}, 0, REST},
{ "ssbx", 1,1,2,0xF5B0, 0xFDF0, {OPT|OP_N,OP_SBIT}, FL_NR, REST},
{ "st", 1,2,2,0x8C00, 0xFF00, {OP_T,OP_Smem}, 0, REST},
{ "st", 1,2,2,0x8D00, 0xFF00, {OP_TRN,OP_Smem}, 0, REST},
{ "st", 2,2,2,0x7600, 0xFF00, {OP_lk,OP_Smem}, 0, REST},
{ "sth", 1,2,2,0x8200, 0xFE00, {OP_SRC1,OP_Smem}, 0, REST},
{ "sth", 1,3,3,0x8600, 0xFE00, {OP_SRC1,OP_ASM,OP_Smem}, 0, REST},
{ "sth", 1,3,3,0x9A00, 0xFE00, {OP_SRC1,OP_SHFT,OP_Xmem}, 0, REST},
{ "sth", 2,2,3,0x6F00, 0xFF00, {OP_SRC1,OPT|OP_SHIFT,OP_Smem},
FL_EXT, 0x0C60, 0xFEE0 },
{ "stl", 1,2,2,0x8000, 0xFE00, {OP_SRC1,OP_Smem}, 0, 0, 0 },
{ "stl", 1,3,3,0x8400, 0xFE00, {OP_SRC1,OP_ASM,OP_Smem}, 0, 0, 0 },
{ "stl", 1,3,3,0x9800, 0xFE00, {OP_SRC1,OP_SHFT,OP_Xmem}, 0, 0, 0 },
FL_EXT, 0x0C60, 0xFEE0, XREST},
{ "stl", 1,2,2,0x8000, 0xFE00, {OP_SRC1,OP_Smem}, 0, REST},
{ "stl", 1,3,3,0x8400, 0xFE00, {OP_SRC1,OP_ASM,OP_Smem}, 0, REST},
{ "stl", 1,3,3,0x9800, 0xFE00, {OP_SRC1,OP_SHFT,OP_Xmem}, 0, REST},
{ "stl", 2,2,3,0x6F00, 0xFF00, {OP_SRC1,OPT|OP_SHIFT,OP_Smem},
FL_EXT, 0x0C80, 0xFEE0 },
{ "stlm", 1,2,2,0x8800, 0xFE00, {OP_SRC1,OP_MMR}, 0, 0, 0 },
{ "stm", 2,2,2,0x7700, 0xFF00, {OP_lk,OP_MMR}, 0, 0, 0 },
{ "strcd", 1,2,2,0x9C00, 0xFF00, {OP_Xmem,OP_CC2}, 0, 0, 0 },
{ "sub", 1,1,3,0xF420, 0xFCE0, {OP_SRC,OPT|OP_SHIFT,OPT|OP_DST}, 0, 0, 0 },/*SRC*/
{ "sub", 1,2,3,0xF481, 0xFCFF, {OP_SRC,OP_ASM,OPT|OP_DST}, 0, 0, 0 },/*SRC*/
{ "sub", 1,2,2,0x0800, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR, 0, 0 },
{ "sub", 1,3,3,0x0C00, 0xFE00, {OP_Smem,OP_TS,OP_SRC1}, FL_SMR, 0, 0 },
{ "sub", 1,3,4,0x4000, 0xFC00, {OP_Smem,OP_16,OP_SRC,OPT|OP_DST}, FL_SMR, 0, 0 },
{ "sub", 1,3,3,0x9200, 0xFE00, {OP_Xmem,OP_SHFT,OP_SRC1}, 0, 0, 0 }, /*PREFER*/
FL_EXT, 0x0C80, 0xFEE0, XREST },
{ "stlm", 1,2,2,0x8800, 0xFE00, {OP_SRC1,OP_MMR}, 0, REST},
{ "stm", 2,2,2,0x7700, 0xFF00, {OP_lk,OP_MMR}, 0, REST},
{ "strcd", 1,2,2,0x9C00, 0xFF00, {OP_Xmem,OP_CC2}, 0, REST},
{ "sub", 1,1,3,0xF420, 0xFCE0, {OP_SRC,OPT|OP_SHIFT,OPT|OP_DST}, 0, REST},/*SRC*/
{ "sub", 1,2,3,0xF481, 0xFCFF, {OP_SRC,OP_ASM,OPT|OP_DST}, 0, REST},/*SRC*/
{ "sub", 1,2,2,0x0800, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR, REST},
{ "sub", 1,3,3,0x0C00, 0xFE00, {OP_Smem,OP_TS,OP_SRC1}, FL_SMR, REST},
{ "sub", 1,3,4,0x4000, 0xFC00, {OP_Smem,OP_16,OP_SRC,OPT|OP_DST}, FL_SMR, REST},
{ "sub", 1,3,3,0x9200, 0xFE00, {OP_Xmem,OP_SHFT,OP_SRC1}, 0, REST}, /*PREFER*/
{ "sub", 2,2,4,0x6F00, 0xFF00, {OP_Smem,OPT|OP_SHIFT,OP_SRC,OPT|OP_DST},
FL_EXT|FL_SMR, 0x0C20, 0xFCE0 },
{ "sub", 1,3,3,0xA200, 0xFE00, {OP_Xmem,OP_Ymem,OP_DST}, 0, 0, 0 },
{ "sub", 2,2,4,0xF010, 0xFCF0, {OP_lk,OPT|OP_SHFT,OP_SRC,OPT|OP_DST}, 0, 0, 0 },
{ "sub", 2,3,4,0xF061, 0xFCFF, {OP_lk,OP_16,OP_SRC,OPT|OP_DST}, 0, 0, 0 },
{ "subb", 1,2,2,0x0E00, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR, 0, 0 },
{ "subc", 1,2,2,0x1E00, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR, 0, 0 },
{ "subs", 1,2,2,0x0A00, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR, 0, 0 },
{ "trap", 1,1,1,0xF4C0, 0xFFE0, {OP_031}, B_BRANCH|FL_NR, 0, 0 },
{ "writa", 1,1,1,0x7F00, 0xFF00, {OP_Smem}, FL_SMR, 0, 0 },
{ "xc", 1,2,4,0xFD00, 0xFD00, {OP_12,OP_CC,OPT|OP_CC,OPT|OP_CC}, FL_NR, 0, 0 },
{ "xor", 1,1,3,0xF0C0, 0xFCE0, {OP_SRC,OPT|OP_SHIFT,OPT|OP_DST}, 0, 0, 0 },/*SRC*/
{ "xor", 1,2,2,0x1C00, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR, 0, 0 },
{ "xor", 2,2,4,0xF050, 0xFCF0, {OP_lku,OPT|OP_SHFT,OP_SRC,OPT|OP_DST}, 0, 0, 0 },
{ "xor", 2,3,4,0xF065, 0xFCFF, {OP_lku,OP_16,OP_SRC,OPT|OP_DST}, 0, 0, 0 },
{ "xorm", 2,2,2,0x6A00, 0xFF00, {OP_lku,OP_Smem}, FL_NR|FL_SMR, 0, 0 },
{ NULL, 0,0,0,0,0, {}, 0, 0, 0 },
FL_EXT|FL_SMR, 0x0C20, 0xFCE0, XREST},
{ "sub", 1,3,3,0xA200, 0xFE00, {OP_Xmem,OP_Ymem,OP_DST}, 0, REST},
{ "sub", 2,2,4,0xF010, 0xFCF0, {OP_lk,OPT|OP_SHFT,OP_SRC,OPT|OP_DST}, 0, REST},
{ "sub", 2,3,4,0xF061, 0xFCFF, {OP_lk,OP_16,OP_SRC,OPT|OP_DST}, 0, REST},
{ "subb", 1,2,2,0x0E00, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR, REST},
{ "subc", 1,2,2,0x1E00, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR, REST},
{ "subs", 1,2,2,0x0A00, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR, REST},
{ "trap", 1,1,1,0xF4C0, 0xFFE0, {OP_031}, B_BRANCH|FL_NR, REST},
{ "writa", 1,1,1,0x7F00, 0xFF00, {OP_Smem}, FL_SMR, REST},
{ "xc", 1,2,4,0xFD00, 0xFD00, {OP_12,OP_CC,OPT|OP_CC,OPT|OP_CC}, FL_NR, REST},
{ "xor", 1,1,3,0xF0C0, 0xFCE0, {OP_SRC,OPT|OP_SHIFT,OPT|OP_DST}, 0, REST},/*SRC*/
{ "xor", 1,2,2,0x1C00, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR, REST},
{ "xor", 2,2,4,0xF050, 0xFCF0, {OP_lku,OPT|OP_SHFT,OP_SRC,OPT|OP_DST}, 0, REST},
{ "xor", 2,3,4,0xF065, 0xFCFF, {OP_lku,OP_16,OP_SRC,OPT|OP_DST}, 0, REST},
{ "xorm", 2,2,2,0x6A00, 0xFF00, {OP_lku,OP_Smem}, FL_NR|FL_SMR, REST},
{ NULL, 0,0,0,0,0, {}, 0, REST},
};
/* assume all parallel instructions have at least three operands */
const partemplate tic54x_paroptab[] = {
{ "ld","mac", 1,1,2,0xA800, 0xFE00, {OP_Xmem,OP_DST},{OP_Ymem,OPT|OP_RND},},
{ "ld","macr",1,1,2,0xAA00, 0xFE00, {OP_Xmem,OP_DST},{OP_Ymem,OPT|OP_RND},},
{ "ld","mas", 1,1,2,0xAC00, 0xFE00, {OP_Xmem,OP_DST},{OP_Ymem,OPT|OP_RND},},
{ "ld","masr",1,1,2,0xAE00, 0xFE00, {OP_Xmem,OP_DST},{OP_Ymem,OPT|OP_RND},},
{ "st","add", 1,2,2,0xC000, 0xFC00, {OP_SRC,OP_Ymem},{OP_Xmem,OP_DST}, },
{ "st","ld", 1,2,2,0xC800, 0xFC00, {OP_SRC,OP_Ymem},{OP_Xmem,OP_DST}, },
{ "st","ld", 1,2,2,0xE400, 0xFC00, {OP_SRC,OP_Ymem},{OP_Xmem,OP_T}, },
{ "st","mac", 1,2,2,0xD000, 0xFC00, {OP_SRC,OP_Ymem},{OP_Xmem,OP_DST}, },
{ "st","macr",1,2,2,0xD400, 0xFC00, {OP_SRC,OP_Ymem},{OP_Xmem,OP_DST}, },
{ "st","mas", 1,2,2,0xD800, 0xFC00, {OP_SRC,OP_Ymem},{OP_Xmem,OP_DST}, },
{ "st","masr",1,2,2,0xDC00, 0xFC00, {OP_SRC,OP_Ymem},{OP_Xmem,OP_DST}, },
{ "st","mpy", 1,2,2,0xCC00, 0xFC00, {OP_SRC,OP_Ymem},{OP_Xmem,OP_DST}, },
{ "st","sub", 1,2,2,0xC400, 0xFC00, {OP_SRC,OP_Ymem},{OP_Xmem,OP_DST}, },
{ NULL,NULL, 0, 0, 0, 0, 0, {}, {}, },
const template tic54x_paroptab[] = {
{ "ld",1,1,2,0xA800, 0xFE00, {OP_Xmem,OP_DST}, FL_PAR,0,0,
"mac", {OP_Ymem,OPT|OP_RND},},
{ "ld",1,1,2,0xAA00, 0xFE00, {OP_Xmem,OP_DST}, FL_PAR,0,0,
"macr", {OP_Ymem,OPT|OP_RND},},
{ "ld",1,1,2,0xAC00, 0xFE00, {OP_Xmem,OP_DST}, FL_PAR,0,0,
"mas", {OP_Ymem,OPT|OP_RND},},
{ "ld",1,1,2,0xAE00, 0xFE00, {OP_Xmem,OP_DST}, FL_PAR,0,0,
"masr", {OP_Ymem,OPT|OP_RND},},
{ "st",1,2,2,0xC000, 0xFC00, {OP_SRC,OP_Ymem}, FL_PAR,0,0,
"add", {OP_Xmem,OP_DST}, },
{ "st",1,2,2,0xC800, 0xFC00, {OP_SRC,OP_Ymem}, FL_PAR,0,0,
"ld", {OP_Xmem,OP_DST}, },
{ "st",1,2,2,0xE400, 0xFC00, {OP_SRC,OP_Ymem}, FL_PAR,0,0,
"ld", {OP_Xmem,OP_T}, },
{ "st",1,2,2,0xD000, 0xFC00, {OP_SRC,OP_Ymem}, FL_PAR,0,0,
"mac", {OP_Xmem,OP_DST}, },
{ "st",1,2,2,0xD400, 0xFC00, {OP_SRC,OP_Ymem}, FL_PAR,0,0,
"macr", {OP_Xmem,OP_DST}, },
{ "st",1,2,2,0xD800, 0xFC00, {OP_SRC,OP_Ymem}, FL_PAR,0,0,
"mas", {OP_Xmem,OP_DST}, },
{ "st",1,2,2,0xDC00, 0xFC00, {OP_SRC,OP_Ymem}, FL_PAR,0,0,
"masr", {OP_Xmem,OP_DST}, },
{ "st",1,2,2,0xCC00, 0xFC00, {OP_SRC,OP_Ymem}, FL_PAR,0,0,
"mpy", {OP_Xmem,OP_DST}, },
{ "st",1,2,2,0xC400, 0xFC00, {OP_SRC,OP_Ymem}, FL_PAR,0,0,
"sub", {OP_Xmem,OP_DST}, },
{ NULL, 0, 0, 0, 0, 0, {0,0,0,0}, 0, REST },
};