* config/tc-mips.c (MAX_NOPS): New macro.
(history): Resize to 1 + MAX_NOPS. (fix_vr4120_class): New enumeration. (vr4120_conflicts): New variable. (init_vr4120_conflicts): New function. (md_begin): Call it. (insn_uses_reg): Constify first argument. (classify_vr4120_insn, insns_between, nops_for_insn, nops_for_sequence) (nops_for_insn_or_target): New functions. (append_insn): Use the new nops_for_* functions instead of inline delay checks. Generalize prev_nop_frag handling to handle an arbitrary history length. Insert nops into the history buffer once the number of nops in prev_nop_frag is fixed. (emit_delays): Use nops_for_insn instead of inline delay checks.
This commit is contained in:
Richard Sandiford
parent
9b91f5445f
commit
71400594f2
@ -1,3 +1,20 @@
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2005-03-09 Richard Sandiford <rsandifo@redhat.com>
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* config/tc-mips.c (MAX_NOPS): New macro.
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(history): Resize to 1 + MAX_NOPS.
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(fix_vr4120_class): New enumeration.
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(vr4120_conflicts): New variable.
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(init_vr4120_conflicts): New function.
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(md_begin): Call it.
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(insn_uses_reg): Constify first argument.
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(classify_vr4120_insn, insns_between, nops_for_insn, nops_for_sequence)
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(nops_for_insn_or_target): New functions.
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(append_insn): Use the new nops_for_* functions instead of inline
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delay checks. Generalize prev_nop_frag handling to handle an
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arbitrary history length. Insert nops into the history buffer
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once the number of nops in prev_nop_frag is fixed.
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(emit_delays): Use nops_for_insn instead of inline delay checks.
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2005-03-09 Richard Sandiford <rsandifo@redhat.com>
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* config/tc-mips.c (append_insn): Remove now-redundant nops != 0
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@ -557,8 +557,16 @@ static int mips_optimize = 2;
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equivalent to seeing no -g option at all. */
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static int mips_debug = 0;
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/* A list of previous instructions, with index 0 being the most recent. */
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static struct mips_cl_insn history[2];
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/* The maximum number of NOPs needed to satisfy a hardware hazard
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or processor errata. */
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#define MAX_NOPS 2
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/* A list of previous instructions, with index 0 being the most recent.
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We need to look back MAX_NOPS instructions when filling delay slots
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or working around processor errata. We need to look back one
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instruction further if we're thinking about using history[0] to
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fill a branch delay slot. */
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static struct mips_cl_insn history[1 + MAX_NOPS];
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/* Nop instructions used by emit_nop. */
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static struct mips_cl_insn nop_insn, mips16_nop_insn;
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@ -631,6 +639,24 @@ static const unsigned int mips16_to_32_reg_map[] =
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16, 17, 2, 3, 4, 5, 6, 7
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};
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/* Classifies the kind of instructions we're interested in when
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implementing -mfix-vr4120. */
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enum fix_vr4120_class {
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FIX_VR4120_MACC,
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FIX_VR4120_DMACC,
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FIX_VR4120_MULT,
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FIX_VR4120_DMULT,
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FIX_VR4120_DIV,
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FIX_VR4120_MTHILO,
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NUM_FIX_VR4120_CLASSES
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};
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/* Given two FIX_VR4120_* values X and Y, bit Y of element X is set if
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there must be at least one other instruction between an instruction
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of type X and an instruction of type Y. */
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static unsigned int vr4120_conflicts[NUM_FIX_VR4120_CLASSES];
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/* True if -mfix-vr4120 is in force. */
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static int mips_fix_vr4120;
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/* We don't relax branches by default, since this causes us to expand
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@ -1285,6 +1311,50 @@ emit_nop (void)
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insert_into_history (0, 1, NOP_INSN);
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}
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/* Initialize vr4120_conflicts. There is a bit of duplication here:
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the idea is to make it obvious at a glance that each errata is
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included. */
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static void
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init_vr4120_conflicts (void)
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{
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#define CONFLICT(FIRST, SECOND) \
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vr4120_conflicts[FIX_VR4120_##FIRST] |= 1 << FIX_VR4120_##SECOND
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/* Errata 21 - [D]DIV[U] after [D]MACC */
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CONFLICT (MACC, DIV);
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CONFLICT (DMACC, DIV);
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/* Errata 23 - Continuous DMULT[U]/DMACC instructions. */
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CONFLICT (DMULT, DMULT);
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CONFLICT (DMULT, DMACC);
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CONFLICT (DMACC, DMULT);
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CONFLICT (DMACC, DMACC);
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/* Errata 24 - MT{LO,HI} after [D]MACC */
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CONFLICT (MACC, MTHILO);
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CONFLICT (DMACC, MTHILO);
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/* VR4181A errata MD(1): "If a MULT, MULTU, DMULT or DMULTU
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instruction is executed immediately after a MACC or DMACC
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instruction, the result of [either instruction] is incorrect." */
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CONFLICT (MACC, MULT);
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CONFLICT (MACC, DMULT);
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CONFLICT (DMACC, MULT);
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CONFLICT (DMACC, DMULT);
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/* VR4181A errata MD(4): "If a MACC or DMACC instruction is
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executed immediately after a DMULT, DMULTU, DIV, DIVU,
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DDIV or DDIVU instruction, the result of the MACC or
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DMACC instruction is incorrect.". */
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CONFLICT (DMULT, MACC);
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CONFLICT (DMULT, DMACC);
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CONFLICT (DIV, MACC);
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CONFLICT (DIV, DMACC);
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#undef CONFLICT
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}
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/* This function is called once, at assembler startup time. It should
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set up all the tables, etc. that the MD part of the assembler will need. */
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@ -1513,6 +1583,9 @@ md_begin (void)
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if (! ECOFF_DEBUGGING)
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md_obj_begin ();
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if (mips_fix_vr4120)
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init_vr4120_conflicts ();
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}
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void
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@ -1604,7 +1677,7 @@ fixup_has_matching_lo_p (fixS *fixp)
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of register. */
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static int
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insn_uses_reg (struct mips_cl_insn *ip, unsigned int reg,
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insn_uses_reg (const struct mips_cl_insn *ip, unsigned int reg,
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enum mips_regclass class)
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{
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if (class == MIPS16_REG)
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@ -1773,6 +1846,223 @@ relax_end (void)
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mips_relax.sequence = 0;
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}
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/* Classify an instruction according to the FIX_VR4120_* enumeration.
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Return NUM_FIX_VR4120_CLASSES if the instruction isn't affected
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by VR4120 errata. */
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static unsigned int
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classify_vr4120_insn (const char *name)
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{
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if (strncmp (name, "macc", 4) == 0)
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return FIX_VR4120_MACC;
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if (strncmp (name, "dmacc", 5) == 0)
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return FIX_VR4120_DMACC;
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if (strncmp (name, "mult", 4) == 0)
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return FIX_VR4120_MULT;
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if (strncmp (name, "dmult", 5) == 0)
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return FIX_VR4120_DMULT;
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if (strstr (name, "div"))
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return FIX_VR4120_DIV;
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if (strcmp (name, "mtlo") == 0 || strcmp (name, "mthi") == 0)
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return FIX_VR4120_MTHILO;
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return NUM_FIX_VR4120_CLASSES;
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}
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/* Return the number of instructions that must separate INSN1 and INSN2,
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where INSN1 is the earlier instruction. Return the worst-case value
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for any INSN2 if INSN2 is null. */
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static unsigned int
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insns_between (const struct mips_cl_insn *insn1,
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const struct mips_cl_insn *insn2)
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{
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unsigned long pinfo1, pinfo2;
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/* This function needs to know which pinfo flags are set for INSN2
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and which registers INSN2 uses. The former is stored in PINFO2 and
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the latter is tested via INSN2_USES_REG. If INSN2 is null, PINFO2
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will have every flag set and INSN2_USES_REG will always return true. */
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pinfo1 = insn1->insn_mo->pinfo;
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pinfo2 = insn2 ? insn2->insn_mo->pinfo : ~0U;
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#define INSN2_USES_REG(REG, CLASS) \
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(insn2 == NULL || insn_uses_reg (insn2, REG, CLASS))
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/* For most targets, write-after-read dependencies on the HI and LO
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registers must be separated by at least two instructions. */
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if (!hilo_interlocks)
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{
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if ((pinfo1 & INSN_READ_LO) && (pinfo2 & INSN_WRITE_LO))
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return 2;
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if ((pinfo1 & INSN_READ_HI) && (pinfo2 & INSN_WRITE_HI))
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return 2;
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}
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/* If we're working around r7000 errata, there must be two instructions
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between an mfhi or mflo and any instruction that uses the result. */
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if (mips_7000_hilo_fix
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&& MF_HILO_INSN (pinfo1)
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&& INSN2_USES_REG (EXTRACT_OPERAND (RD, *insn1), MIPS_GR_REG))
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return 2;
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/* If working around VR4120 errata, check for combinations that need
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a single intervening instruction. */
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if (mips_fix_vr4120)
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{
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unsigned int class1, class2;
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class1 = classify_vr4120_insn (insn1->insn_mo->name);
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if (class1 != NUM_FIX_VR4120_CLASSES && vr4120_conflicts[class1] != 0)
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{
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if (insn2 == NULL)
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return 1;
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class2 = classify_vr4120_insn (insn2->insn_mo->name);
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if (vr4120_conflicts[class1] & (1 << class2))
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return 1;
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}
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}
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if (!mips_opts.mips16)
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{
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/* Check for GPR or coprocessor load delays. All such delays
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are on the RT register. */
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/* Itbl support may require additional care here. */
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if ((!gpr_interlocks && (pinfo1 & INSN_LOAD_MEMORY_DELAY))
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|| (!cop_interlocks && (pinfo1 & INSN_LOAD_COPROC_DELAY)))
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{
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know (pinfo1 & INSN_WRITE_GPR_T);
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if (INSN2_USES_REG (EXTRACT_OPERAND (RT, *insn1), MIPS_GR_REG))
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return 1;
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}
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/* Check for generic coprocessor hazards.
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This case is not handled very well. There is no special
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knowledge of CP0 handling, and the coprocessors other than
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the floating point unit are not distinguished at all. */
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/* Itbl support may require additional care here. FIXME!
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Need to modify this to include knowledge about
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user specified delays! */
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else if ((!cop_interlocks && (pinfo1 & INSN_COPROC_MOVE_DELAY))
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|| (!cop_mem_interlocks && (pinfo1 & INSN_COPROC_MEMORY_DELAY)))
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{
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/* Handle cases where INSN1 writes to a known general coprocessor
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register. There must be a one instruction delay before INSN2
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if INSN2 reads that register, otherwise no delay is needed. */
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if (pinfo1 & INSN_WRITE_FPR_T)
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{
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if (INSN2_USES_REG (EXTRACT_OPERAND (FT, *insn1), MIPS_FP_REG))
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return 1;
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}
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else if (pinfo1 & INSN_WRITE_FPR_S)
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{
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if (INSN2_USES_REG (EXTRACT_OPERAND (FS, *insn1), MIPS_FP_REG))
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return 1;
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}
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else
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{
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/* Read-after-write dependencies on the control registers
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require a two-instruction gap. */
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if ((pinfo1 & INSN_WRITE_COND_CODE)
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&& (pinfo2 & INSN_READ_COND_CODE))
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return 2;
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/* We don't know exactly what INSN1 does. If INSN2 is
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also a coprocessor instruction, assume there must be
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a one instruction gap. */
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if (pinfo2 & INSN_COP)
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return 1;
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}
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}
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/* Check for read-after-write dependencies on the coprocessor
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control registers in cases where INSN1 does not need a general
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coprocessor delay. This means that INSN1 is a floating point
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comparison instruction. */
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/* Itbl support may require additional care here. */
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else if (!cop_interlocks
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&& (pinfo1 & INSN_WRITE_COND_CODE)
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&& (pinfo2 & INSN_READ_COND_CODE))
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return 1;
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}
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#undef INSN2_USES_REG
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return 0;
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}
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/* Return the number of nops that would be needed if instruction INSN
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immediately followed the MAX_NOPS instructions given by HISTORY,
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where HISTORY[0] is the most recent instruction. If INSN is null,
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return the worse-case number of nops for any instruction. */
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static int
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nops_for_insn (const struct mips_cl_insn *history,
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const struct mips_cl_insn *insn)
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{
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int i, nops, tmp_nops;
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nops = 0;
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for (i = 0; i < MAX_NOPS; i++)
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if (!history[i].noreorder_p)
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{
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tmp_nops = insns_between (history + i, insn) - i;
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if (tmp_nops > nops)
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nops = tmp_nops;
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}
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return nops;
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}
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/* The variable arguments provide NUM_INSNS extra instructions that
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might be added to HISTORY. Return the largest number of nops that
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would be needed after the extended sequence. */
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static int
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nops_for_sequence (int num_insns, const struct mips_cl_insn *history, ...)
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{
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va_list args;
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struct mips_cl_insn buffer[MAX_NOPS];
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struct mips_cl_insn *cursor;
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int nops;
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va_start (args, history);
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cursor = buffer + num_insns;
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memcpy (cursor, history, (MAX_NOPS - num_insns) * sizeof (*cursor));
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while (cursor > buffer)
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*--cursor = *va_arg (args, const struct mips_cl_insn *);
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nops = nops_for_insn (buffer, NULL);
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va_end (args);
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return nops;
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}
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/* Like nops_for_insn, but if INSN is a branch, take into account the
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worst-case delay for the branch target. */
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static int
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nops_for_insn_or_target (const struct mips_cl_insn *history,
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const struct mips_cl_insn *insn)
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{
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int nops, tmp_nops;
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nops = nops_for_insn (history, insn);
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if (insn->insn_mo->pinfo & (INSN_UNCOND_BRANCH_DELAY
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| INSN_COND_BRANCH_DELAY
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| INSN_COND_BRANCH_LIKELY))
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{
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tmp_nops = nops_for_sequence (2, history, insn, NOP_INSN);
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if (tmp_nops > nops)
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nops = tmp_nops;
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}
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else if (mips_opts.mips16 && (insn->insn_mo->pinfo & MIPS16_INSN_BRANCH))
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{
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tmp_nops = nops_for_sequence (1, history, insn);
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if (tmp_nops > nops)
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nops = tmp_nops;
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}
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return nops;
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}
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/* Output an instruction. IP is the instruction information.
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ADDRESS_EXPR is an operand of the instruction to be used with
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RELOC_TYPE. */
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@ -1782,7 +2072,6 @@ append_insn (struct mips_cl_insn *ip, expressionS *address_expr,
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bfd_reloc_code_real_type *reloc_type)
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{
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register unsigned long prev_pinfo, pinfo;
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int nops = 0;
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relax_stateT prev_insn_frag_type = 0;
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bfd_boolean relaxed_branch = FALSE;
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@ -1792,293 +2081,19 @@ append_insn (struct mips_cl_insn *ip, expressionS *address_expr,
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prev_pinfo = history[0].insn_mo->pinfo;
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pinfo = ip->insn_mo->pinfo;
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if (mips_relax.sequence != 2
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&& (!mips_opts.noreorder || prev_nop_frag != NULL))
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if (mips_relax.sequence != 2 && !mips_opts.noreorder)
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{
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int prev_prev_nop;
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/* If the previous insn required any delay slots, see if we need
|
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to insert a NOP or two. There are eight kinds of possible
|
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hazards, of which an instruction can have at most one type.
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(1) a load from memory delay
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(2) a load from a coprocessor delay
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(3) an unconditional branch delay
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(4) a conditional branch delay
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(5) a move to coprocessor register delay
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(6) a load coprocessor register from memory delay
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(7) a coprocessor condition code delay
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(8) a HI/LO special register delay
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There are a lot of optimizations we could do that we don't.
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/* There are a lot of optimizations we could do that we don't.
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In particular, we do not, in general, reorder instructions.
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If you use gcc with optimization, it will reorder
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instructions and generally do much more optimization then we
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do here; repeating all that work in the assembler would only
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benefit hand written assembly code, and does not seem worth
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it. */
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/* The previous insn might require a delay slot, depending upon
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the contents of the current insn. */
|
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if (! mips_opts.mips16
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&& (((prev_pinfo & INSN_LOAD_MEMORY_DELAY)
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&& ! gpr_interlocks)
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|| ((prev_pinfo & INSN_LOAD_COPROC_DELAY)
|
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&& ! cop_interlocks)))
|
||||
{
|
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/* A load from a coprocessor or from memory. All load
|
||||
delays delay the use of general register rt for one
|
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instruction. */
|
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/* Itbl support may require additional care here. */
|
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know (prev_pinfo & INSN_WRITE_GPR_T);
|
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if (mips_optimize == 0
|
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|| insn_uses_reg (ip, EXTRACT_OPERAND (RT, history[0]),
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MIPS_GR_REG))
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++nops;
|
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}
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else if (! mips_opts.mips16
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&& (((prev_pinfo & INSN_COPROC_MOVE_DELAY)
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&& ! cop_interlocks)
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|| ((prev_pinfo & INSN_COPROC_MEMORY_DELAY)
|
||||
&& ! cop_mem_interlocks)))
|
||||
{
|
||||
/* A generic coprocessor delay. The previous instruction
|
||||
modified a coprocessor general or control register. If
|
||||
it modified a control register, we need to avoid any
|
||||
coprocessor instruction (this is probably not always
|
||||
required, but it sometimes is). If it modified a general
|
||||
register, we avoid using that register.
|
||||
|
||||
This case is not handled very well. There is no special
|
||||
knowledge of CP0 handling, and the coprocessors other
|
||||
than the floating point unit are not distinguished at
|
||||
all. */
|
||||
/* Itbl support may require additional care here. FIXME!
|
||||
Need to modify this to include knowledge about
|
||||
user specified delays! */
|
||||
if (prev_pinfo & INSN_WRITE_FPR_T)
|
||||
{
|
||||
if (mips_optimize == 0
|
||||
|| insn_uses_reg (ip, EXTRACT_OPERAND (FT, history[0]),
|
||||
MIPS_FP_REG))
|
||||
++nops;
|
||||
}
|
||||
else if (prev_pinfo & INSN_WRITE_FPR_S)
|
||||
{
|
||||
if (mips_optimize == 0
|
||||
|| insn_uses_reg (ip, EXTRACT_OPERAND (FS, history[0]),
|
||||
MIPS_FP_REG))
|
||||
++nops;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* We don't know exactly what the previous instruction
|
||||
does. If the current instruction uses a coprocessor
|
||||
register, we must insert a NOP. If previous
|
||||
instruction may set the condition codes, and the
|
||||
current instruction uses them, we must insert two
|
||||
NOPS. */
|
||||
/* Itbl support may require additional care here. */
|
||||
if (mips_optimize == 0
|
||||
|| ((prev_pinfo & INSN_WRITE_COND_CODE)
|
||||
&& (pinfo & INSN_READ_COND_CODE)))
|
||||
nops += 2;
|
||||
else if (pinfo & INSN_COP)
|
||||
++nops;
|
||||
}
|
||||
}
|
||||
else if (! mips_opts.mips16
|
||||
&& (prev_pinfo & INSN_WRITE_COND_CODE)
|
||||
&& ! cop_interlocks)
|
||||
{
|
||||
/* The previous instruction sets the coprocessor condition
|
||||
codes, but does not require a general coprocessor delay
|
||||
(this means it is a floating point comparison
|
||||
instruction). If this instruction uses the condition
|
||||
codes, we need to insert a single NOP. */
|
||||
/* Itbl support may require additional care here. */
|
||||
if (mips_optimize == 0
|
||||
|| (pinfo & INSN_READ_COND_CODE))
|
||||
++nops;
|
||||
}
|
||||
|
||||
/* If we're fixing up mfhi/mflo for the r7000 and the
|
||||
previous insn was an mfhi/mflo and the current insn
|
||||
reads the register that the mfhi/mflo wrote to, then
|
||||
insert two nops. */
|
||||
|
||||
else if (mips_7000_hilo_fix
|
||||
&& MF_HILO_INSN (prev_pinfo)
|
||||
&& insn_uses_reg (ip, EXTRACT_OPERAND (RD, history[0]),
|
||||
MIPS_GR_REG))
|
||||
{
|
||||
nops += 2;
|
||||
}
|
||||
|
||||
/* If we're fixing up mfhi/mflo for the r7000 and the
|
||||
2nd previous insn was an mfhi/mflo and the current insn
|
||||
reads the register that the mfhi/mflo wrote to, then
|
||||
insert one nop. */
|
||||
|
||||
else if (mips_7000_hilo_fix
|
||||
&& MF_HILO_INSN (history[1].insn_opcode)
|
||||
&& insn_uses_reg (ip, EXTRACT_OPERAND (RD, history[1]),
|
||||
MIPS_GR_REG))
|
||||
|
||||
{
|
||||
++nops;
|
||||
}
|
||||
|
||||
else if (prev_pinfo & INSN_READ_LO)
|
||||
{
|
||||
/* The previous instruction reads the LO register; if the
|
||||
current instruction writes to the LO register, we must
|
||||
insert two NOPS. Some newer processors have interlocks.
|
||||
Also the tx39's multiply instructions can be executed
|
||||
immediately after a read from HI/LO (without the delay),
|
||||
though the tx39's divide insns still do require the
|
||||
delay. */
|
||||
if (! (hilo_interlocks
|
||||
|| (mips_opts.arch == CPU_R3900 && (pinfo & INSN_MULT)))
|
||||
&& (mips_optimize == 0
|
||||
|| (pinfo & INSN_WRITE_LO)))
|
||||
nops += 2;
|
||||
/* Most mips16 branch insns don't have a delay slot.
|
||||
If a read from LO is immediately followed by a branch
|
||||
to a write to LO we have a read followed by a write
|
||||
less than 2 insns away. We assume the target of
|
||||
a branch might be a write to LO, and insert a nop
|
||||
between a read and an immediately following branch. */
|
||||
else if (mips_opts.mips16
|
||||
&& (mips_optimize == 0
|
||||
|| (pinfo & MIPS16_INSN_BRANCH)))
|
||||
++nops;
|
||||
}
|
||||
else if (history[0].insn_mo->pinfo & INSN_READ_HI)
|
||||
{
|
||||
/* The previous instruction reads the HI register; if the
|
||||
current instruction writes to the HI register, we must
|
||||
insert a NOP. Some newer processors have interlocks.
|
||||
Also the note tx39's multiply above. */
|
||||
if (! (hilo_interlocks
|
||||
|| (mips_opts.arch == CPU_R3900 && (pinfo & INSN_MULT)))
|
||||
&& (mips_optimize == 0
|
||||
|| (pinfo & INSN_WRITE_HI)))
|
||||
nops += 2;
|
||||
/* Most mips16 branch insns don't have a delay slot.
|
||||
If a read from HI is immediately followed by a branch
|
||||
to a write to HI we have a read followed by a write
|
||||
less than 2 insns away. We assume the target of
|
||||
a branch might be a write to HI, and insert a nop
|
||||
between a read and an immediately following branch. */
|
||||
else if (mips_opts.mips16
|
||||
&& (mips_optimize == 0
|
||||
|| (pinfo & MIPS16_INSN_BRANCH)))
|
||||
++nops;
|
||||
}
|
||||
|
||||
/* If the previous instruction was in a noreorder section, then
|
||||
we don't want to insert the nop after all. */
|
||||
/* Itbl support may require additional care here. */
|
||||
if (history[0].noreorder_p)
|
||||
nops = 0;
|
||||
|
||||
/* There are two cases which require two intervening
|
||||
instructions: 1) setting the condition codes using a move to
|
||||
coprocessor instruction which requires a general coprocessor
|
||||
delay and then reading the condition codes 2) reading the HI
|
||||
or LO register and then writing to it (except on processors
|
||||
which have interlocks). If we are not already emitting a NOP
|
||||
instruction, we must check for these cases compared to the
|
||||
instruction previous to the previous instruction. */
|
||||
if ((! mips_opts.mips16
|
||||
&& (history[1].insn_mo->pinfo & INSN_COPROC_MOVE_DELAY)
|
||||
&& (history[1].insn_mo->pinfo & INSN_WRITE_COND_CODE)
|
||||
&& (pinfo & INSN_READ_COND_CODE)
|
||||
&& ! cop_interlocks)
|
||||
|| ((history[1].insn_mo->pinfo & INSN_READ_LO)
|
||||
&& (pinfo & INSN_WRITE_LO)
|
||||
&& ! (hilo_interlocks
|
||||
|| (mips_opts.arch == CPU_R3900 && (pinfo & INSN_MULT))))
|
||||
|| ((history[1].insn_mo->pinfo & INSN_READ_HI)
|
||||
&& (pinfo & INSN_WRITE_HI)
|
||||
&& ! (hilo_interlocks
|
||||
|| (mips_opts.arch == CPU_R3900 && (pinfo & INSN_MULT)))))
|
||||
prev_prev_nop = 1;
|
||||
else
|
||||
prev_prev_nop = 0;
|
||||
|
||||
if (history[1].noreorder_p)
|
||||
prev_prev_nop = 0;
|
||||
|
||||
if (prev_prev_nop && nops == 0)
|
||||
++nops;
|
||||
|
||||
if (mips_fix_vr4120 && history[0].insn_mo->name)
|
||||
{
|
||||
/* We're out of bits in pinfo, so we must resort to string
|
||||
ops here. Shortcuts are selected based on opcodes being
|
||||
limited to the VR4120 instruction set. */
|
||||
int min_nops = 0;
|
||||
const char *pn = history[0].insn_mo->name;
|
||||
const char *tn = ip->insn_mo->name;
|
||||
if (strncmp (pn, "macc", 4) == 0
|
||||
|| strncmp (pn, "dmacc", 5) == 0)
|
||||
{
|
||||
/* Errata 21 - [D]DIV[U] after [D]MACC */
|
||||
if (strstr (tn, "div"))
|
||||
min_nops = 1;
|
||||
|
||||
/* VR4181A errata MD(1): "If a MULT, MULTU, DMULT or DMULTU
|
||||
instruction is executed immediately after a MACC or
|
||||
DMACC instruction, the result of [either instruction]
|
||||
is incorrect." */
|
||||
if (strncmp (tn, "mult", 4) == 0
|
||||
|| strncmp (tn, "dmult", 5) == 0)
|
||||
min_nops = 1;
|
||||
|
||||
/* Errata 23 - Continuous DMULT[U]/DMACC instructions.
|
||||
Applies on top of VR4181A MD(1) errata. */
|
||||
if (pn[0] == 'd' && strncmp (tn, "dmacc", 5) == 0)
|
||||
min_nops = 1;
|
||||
|
||||
/* Errata 24 - MT{LO,HI} after [D]MACC */
|
||||
if (strcmp (tn, "mtlo") == 0
|
||||
|| strcmp (tn, "mthi") == 0)
|
||||
min_nops = 1;
|
||||
}
|
||||
else if (strncmp (pn, "dmult", 5) == 0
|
||||
&& (strncmp (tn, "dmult", 5) == 0
|
||||
|| strncmp (tn, "dmacc", 5) == 0))
|
||||
{
|
||||
/* Here is the rest of errata 23. */
|
||||
min_nops = 1;
|
||||
}
|
||||
else if ((strncmp (pn, "dmult", 5) == 0 || strstr (pn, "div"))
|
||||
&& (strncmp (tn, "macc", 4) == 0
|
||||
|| strncmp (tn, "dmacc", 5) == 0))
|
||||
{
|
||||
/* VR4181A errata MD(4): "If a MACC or DMACC instruction is
|
||||
executed immediately after a DMULT, DMULTU, DIV, DIVU,
|
||||
DDIV or DDIVU instruction, the result of the MACC or
|
||||
DMACC instruction is incorrect.". This partly overlaps
|
||||
the workaround for errata 23. */
|
||||
min_nops = 1;
|
||||
}
|
||||
if (nops < min_nops)
|
||||
nops = min_nops;
|
||||
}
|
||||
|
||||
/* If we are being given a nop instruction, don't bother with
|
||||
one of the nops we would otherwise output. This will only
|
||||
happen when a nop instruction is used with mips_optimize set
|
||||
to 0. */
|
||||
if (nops > 0
|
||||
&& ! mips_opts.noreorder
|
||||
&& ip->insn_opcode == (unsigned) (mips_opts.mips16 ? 0x6500 : 0))
|
||||
--nops;
|
||||
|
||||
/* Now emit the right number of NOP instructions. */
|
||||
if (nops > 0 && ! mips_opts.noreorder)
|
||||
int nops = (mips_optimize == 0
|
||||
? nops_for_insn (history, NULL)
|
||||
: nops_for_insn_or_target (history, ip));
|
||||
if (nops > 0)
|
||||
{
|
||||
fragS *old_frag;
|
||||
unsigned long old_frag_offset;
|
||||
@ -2123,42 +2138,32 @@ append_insn (struct mips_cl_insn *ip, expressionS *address_expr,
|
||||
ecoff_fix_loc (old_frag, old_frag_offset);
|
||||
#endif
|
||||
}
|
||||
else if (prev_nop_frag != NULL)
|
||||
{
|
||||
/* We have a frag holding nops we may be able to remove. If
|
||||
we don't need any nops, we can decrease the size of
|
||||
prev_nop_frag by the size of one instruction. If we do
|
||||
need some nops, we count them in prev_nops_required. */
|
||||
if (prev_nop_frag_since == 0)
|
||||
{
|
||||
if (nops == 0)
|
||||
{
|
||||
prev_nop_frag->fr_fix -= mips_opts.mips16 ? 2 : 4;
|
||||
--prev_nop_frag_holds;
|
||||
}
|
||||
else
|
||||
prev_nop_frag_required += nops;
|
||||
}
|
||||
else
|
||||
else if (mips_relax.sequence != 2 && prev_nop_frag != NULL)
|
||||
{
|
||||
if (prev_prev_nop == 0)
|
||||
{
|
||||
prev_nop_frag->fr_fix -= mips_opts.mips16 ? 2 : 4;
|
||||
--prev_nop_frag_holds;
|
||||
}
|
||||
else
|
||||
++prev_nop_frag_required;
|
||||
}
|
||||
/* Work out how many nops in prev_nop_frag are needed by IP. */
|
||||
int nops = nops_for_insn_or_target (history, ip);
|
||||
assert (nops <= prev_nop_frag_holds);
|
||||
|
||||
if (prev_nop_frag_holds <= prev_nop_frag_required)
|
||||
/* Enforce NOPS as a minimum. */
|
||||
if (nops > prev_nop_frag_required)
|
||||
prev_nop_frag_required = nops;
|
||||
|
||||
if (prev_nop_frag_holds == prev_nop_frag_required)
|
||||
{
|
||||
/* Settle for the current number of nops. Update the history
|
||||
accordingly (for the benefit of any future .set reorder code). */
|
||||
prev_nop_frag = NULL;
|
||||
|
||||
++prev_nop_frag_since;
|
||||
|
||||
/* Sanity check: by the time we reach the second instruction
|
||||
after prev_nop_frag, we should have used up all the nops
|
||||
one way or another. */
|
||||
assert (prev_nop_frag_since <= 1 || prev_nop_frag == NULL);
|
||||
insert_into_history (prev_nop_frag_since,
|
||||
prev_nop_frag_holds, NOP_INSN);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Allow this instruction to replace one of the nops that was
|
||||
tentatively added to prev_nop_frag. */
|
||||
prev_nop_frag->fr_fix -= mips_opts.mips16 ? 2 : 4;
|
||||
prev_nop_frag_holds--;
|
||||
prev_nop_frag_since++;
|
||||
}
|
||||
}
|
||||
|
||||
@ -2511,28 +2516,12 @@ append_insn (struct mips_cl_insn *ip, expressionS *address_expr,
|
||||
|| (! mips_opts.mips16
|
||||
&& (pinfo & INSN_READ_COND_CODE)
|
||||
&& ! cop_interlocks)
|
||||
/* We can not swap with an instruction that requires a
|
||||
delay slot, because the target of the branch might
|
||||
interfere with that instruction. */
|
||||
|| (! mips_opts.mips16
|
||||
&& (prev_pinfo
|
||||
/* Itbl support may require additional care here. */
|
||||
& (INSN_LOAD_COPROC_DELAY
|
||||
| INSN_COPROC_MOVE_DELAY
|
||||
| INSN_WRITE_COND_CODE))
|
||||
&& ! cop_interlocks)
|
||||
|| (! (hilo_interlocks
|
||||
|| (mips_opts.arch == CPU_R3900 && (pinfo & INSN_MULT)))
|
||||
&& (prev_pinfo
|
||||
& (INSN_READ_LO
|
||||
| INSN_READ_HI)))
|
||||
|| (! mips_opts.mips16
|
||||
&& (prev_pinfo & INSN_LOAD_MEMORY_DELAY)
|
||||
&& ! gpr_interlocks)
|
||||
|| (! mips_opts.mips16
|
||||
/* Itbl support may require additional care here. */
|
||||
&& (prev_pinfo & INSN_COPROC_MEMORY_DELAY)
|
||||
&& ! cop_mem_interlocks)
|
||||
/* Check for conflicts between the branch and the instructions
|
||||
before the candidate delay slot. */
|
||||
|| nops_for_insn (history + 1, ip) > 0
|
||||
/* Check for conflicts between the swapped sequence and the
|
||||
target of the branch. */
|
||||
|| nops_for_sequence (2, history + 1, ip, history) > 0
|
||||
/* We do not swap with a trap instruction, since it
|
||||
complicates trap handlers to have the trap
|
||||
instruction be in a delay slot. */
|
||||
@ -2606,18 +2595,6 @@ append_insn (struct mips_cl_insn *ip, expressionS *address_expr,
|
||||
|| (mips_opts.mips16
|
||||
&& (pinfo & MIPS16_INSN_WRITE_31)
|
||||
&& insn_uses_reg (&history[0], RA, MIPS_GR_REG))
|
||||
/* If the previous previous instruction has a load
|
||||
delay, and sets a register that the branch reads, we
|
||||
can not swap. */
|
||||
|| (! mips_opts.mips16
|
||||
/* Itbl support may require additional care here. */
|
||||
&& (((history[1].insn_mo->pinfo & INSN_LOAD_COPROC_DELAY)
|
||||
&& ! cop_interlocks)
|
||||
|| ((history[1].insn_mo->pinfo
|
||||
& INSN_LOAD_MEMORY_DELAY)
|
||||
&& ! gpr_interlocks))
|
||||
&& insn_uses_reg (ip, EXTRACT_OPERAND (RT, history[1]),
|
||||
MIPS_GR_REG))
|
||||
/* If one instruction sets a condition code and the
|
||||
other one uses a condition code, we can not swap. */
|
||||
|| ((pinfo & INSN_READ_COND_CODE)
|
||||
@ -2739,69 +2716,12 @@ mips_emit_delays (bfd_boolean insns)
|
||||
{
|
||||
if (! mips_opts.noreorder)
|
||||
{
|
||||
int nops;
|
||||
|
||||
nops = 0;
|
||||
if ((! mips_opts.mips16
|
||||
&& ((history[0].insn_mo->pinfo
|
||||
& (INSN_LOAD_COPROC_DELAY
|
||||
| INSN_COPROC_MOVE_DELAY
|
||||
| INSN_WRITE_COND_CODE))
|
||||
&& ! cop_interlocks))
|
||||
|| (! hilo_interlocks
|
||||
&& (history[0].insn_mo->pinfo
|
||||
& (INSN_READ_LO
|
||||
| INSN_READ_HI)))
|
||||
|| (! mips_opts.mips16
|
||||
&& (history[0].insn_mo->pinfo & INSN_LOAD_MEMORY_DELAY)
|
||||
&& ! gpr_interlocks)
|
||||
|| (! mips_opts.mips16
|
||||
&& (history[0].insn_mo->pinfo & INSN_COPROC_MEMORY_DELAY)
|
||||
&& ! cop_mem_interlocks))
|
||||
{
|
||||
/* Itbl support may require additional care here. */
|
||||
++nops;
|
||||
if ((! mips_opts.mips16
|
||||
&& ((history[0].insn_mo->pinfo & INSN_WRITE_COND_CODE)
|
||||
&& ! cop_interlocks))
|
||||
|| (! hilo_interlocks
|
||||
&& ((history[0].insn_mo->pinfo & INSN_READ_HI)
|
||||
|| (history[0].insn_mo->pinfo & INSN_READ_LO))))
|
||||
++nops;
|
||||
|
||||
if (history[0].noreorder_p)
|
||||
nops = 0;
|
||||
}
|
||||
else if ((! mips_opts.mips16
|
||||
&& ((history[1].insn_mo->pinfo & INSN_WRITE_COND_CODE)
|
||||
&& ! cop_interlocks))
|
||||
|| (! hilo_interlocks
|
||||
&& ((history[1].insn_mo->pinfo & INSN_READ_HI)
|
||||
|| (history[1].insn_mo->pinfo & INSN_READ_LO))))
|
||||
{
|
||||
/* Itbl support may require additional care here. */
|
||||
if (! history[1].noreorder_p)
|
||||
++nops;
|
||||
}
|
||||
|
||||
if (mips_fix_vr4120 && history[0].insn_mo->name)
|
||||
{
|
||||
int min_nops = 0;
|
||||
const char *pn = history[0].insn_mo->name;
|
||||
if (strncmp (pn, "macc", 4) == 0
|
||||
|| strncmp (pn, "dmacc", 5) == 0
|
||||
|| strncmp (pn, "dmult", 5) == 0
|
||||
|| strstr (pn, "div"))
|
||||
min_nops = 1;
|
||||
if (nops < min_nops)
|
||||
nops = min_nops;
|
||||
}
|
||||
|
||||
int nops = nops_for_insn (history, NULL);
|
||||
if (nops > 0)
|
||||
{
|
||||
struct insn_label_list *l;
|
||||
|
||||
if (insns)
|
||||
if (insns && mips_optimize != 0)
|
||||
{
|
||||
/* Record the frag which holds the nop instructions, so
|
||||
that we can remove them if we don't need them. */
|
||||
|
||||
Loading…
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Reference in New Issue
Block a user