aarch64: Tweak errors for base & offset registers

parse_address_main currently uses get_reg_expected_msg to
report invalid base and offset registers, but the disadvantage
of doing that is that it isn't immediately clear which register
is wrong (the base or the offset).

A later patch moves away from using get_reg_expected_msg for failed
type checks, but doing that here didn't seem like the best approach.
The patch tries to use more tailored messages instead.
This commit is contained in:
Richard Sandiford 2023-03-30 11:09:06 +01:00
parent f42fba9879
commit 72c1dab0ea
9 changed files with 308 additions and 293 deletions

View File

@ -3819,10 +3819,18 @@ parse_address_main (char **str, aarch64_opnd_info *operand,
/* [ */
bool alpha_base_p = ISALPHA (*p);
reg = aarch64_addr_reg_parse (&p, base_type, base_qualifier);
if (!reg || !aarch64_check_reg_type (reg, base_type))
{
set_syntax_error (_(get_reg_expected_msg (base_type)));
if (reg
&& aarch64_check_reg_type (reg, REG_TYPE_R_SP)
&& *base_qualifier == AARCH64_OPND_QLF_W)
set_syntax_error (_("expected a 64-bit base register"));
else if (alpha_base_p)
set_syntax_error (_("invalid base register"));
else
set_syntax_error (_("expected a base register"));
return false;
}
operand->addr.base_regno = reg->number;
@ -3838,7 +3846,7 @@ parse_address_main (char **str, aarch64_opnd_info *operand,
{
if (!aarch64_check_reg_type (reg, offset_type))
{
set_syntax_error (_(get_reg_expected_msg (offset_type)));
set_syntax_error (_("invalid offset register"));
return false;
}
@ -3974,7 +3982,7 @@ parse_address_main (char **str, aarch64_opnd_info *operand,
/* [Xn],Xm */
if (!aarch64_check_reg_type (reg, REG_TYPE_R_64))
{
set_syntax_error (_(get_reg_expected_msg (REG_TYPE_R_64)));
set_syntax_error (_("invalid offset register"));
return false;
}

View File

@ -54,7 +54,7 @@
[^:]*:56: Error: operand 2 must be a floating-point register -- `fcmp d0,x0'
[^:]*:57: Error: immediate zero expected at operand 3 -- `cmgt v0.4s,v2.4s,#1'
[^:]*:58: Error: unexpected characters following instruction at operand 2 -- `fmov d3,1.00,lsl#3'
[^:]*:59: Error: integer 64-bit register expected at operand 2 -- `st2 {v0.4s,v1.4s},\[sp\],sp'
[^:]*:59: Error: invalid offset register at operand 2 -- `st2 {v0.4s,v1.4s},\[sp\],sp'
[^:]*:60: Error: writeback value must be an immediate constant at operand 2 -- `st2 {v0.4s,v1.4s},\[sp\],zr'
[^:]*:61: Error: invalid shift for the register offset addressing mode at operand 2 -- `ldr q0,\[x0,w0,lsr#4\]'
[^:]*:62: Error: only 'LSL' shift is permitted at operand 3 -- `adds x1,sp,2134,uxtw#12'
@ -116,10 +116,10 @@
[^:]*:126: Warning: unpredictable transfer with writeback -- `ldp x0,x1,\[x1\],#16'
[^:]*:127: Error: this relocation modifier is not allowed on this instruction at operand 2 -- `adr x2,:got:s1'
[^:]*:128: Error: this relocation modifier is not allowed on this instruction at operand 2 -- `ldr x0,\[x0,:got:s1\]'
[^:]*:131: Error: 64-bit integer or SP register expected at operand 2 -- `ldr x1,\[wsp,#8\]!'
[^:]*:132: Error: 64-bit integer or SP register expected at operand 3 -- `ldp x6,x29,\[w7,#8\]!'
[^:]*:133: Error: 64-bit integer or SP register expected at operand 2 -- `str x30,\[w11,#8\]!'
[^:]*:134: Error: 64-bit integer or SP register expected at operand 3 -- `stp x8,x27,\[wsp,#8\]!'
[^:]*:131: Error: expected a 64-bit base register at operand 2 -- `ldr x1,\[wsp,#8\]!'
[^:]*:132: Error: expected a 64-bit base register at operand 3 -- `ldp x6,x29,\[w7,#8\]!'
[^:]*:133: Error: expected a 64-bit base register at operand 2 -- `str x30,\[w11,#8\]!'
[^:]*:134: Error: expected a 64-bit base register at operand 3 -- `stp x8,x27,\[wsp,#8\]!'
[^:]*:214: Error: register element index out of range 0 to 1 at operand 2 -- `dup v0\.2d,v1\.2d\[-1\]'
[^:]*:217: Error: register element index out of range 0 to 1 at operand 2 -- `dup v0\.2d,v1\.2d\[2\]'
[^:]*:218: Error: register element index out of range 0 to 1 at operand 2 -- `dup v0\.2d,v1\.2d\[64\]'
@ -144,8 +144,8 @@
[^:]*:256: Error: register element index out of range 0 to 15 at operand 1 -- `ld2 {v0\.b,v1\.b}\[-1\],\[x0\]'
[^:]*:259: Error: register element index out of range 0 to 15 at operand 1 -- `ld2 {v0\.b,v1\.b}\[16\],\[x0\]'
[^:]*:260: Error: register element index out of range 0 to 15 at operand 1 -- `ld2 {v0\.b,v1\.b}\[67\],\[x0\]'
[^:]*:267: Error: integer 64-bit register expected at operand 2 -- `st2 {v0.4s,v1.4s},\[sp\],xzr'
[^:]*:268: Error: integer or zero register expected at operand 2 -- `str x1,\[x2,sp\]'
[^:]*:267: Error: invalid offset register at operand 2 -- `st2 {v0.4s,v1.4s},\[sp\],xzr'
[^:]*:268: Error: invalid offset register at operand 2 -- `str x1,\[x2,sp\]'
[^:]*:271: Error: relocation not allowed at operand 3 -- `ldnp x1,x2,\[x3,#:lo12:foo\]'
[^:]*:272: Error: invalid addressing mode at operand 2 -- `ld1 {v0\.4s},\[x3,#:lo12:foo\]'
[^:]*:273: Error: the optional immediate offset can only be 0 at operand 2 -- `stuminl x0,\[x3,#:lo12:foo\]'
@ -183,3 +183,6 @@
[^:]*:312: Warning: unpredictable load of register pair -- `ldxp x26,x26,\[x5\]'
[^:]*:314: Error: expected element type rather than vector type at operand 1 -- `st4 {v0\.16b-v3\.16b}\[4\],\[x0\]'
[^:]*:315: Warning: unpredictable: identical base and status registers --`stlxp w3,w26,w26,\[x3\]'
[^:]*:317: Error: expected a base register at operand 2 -- `ldr x0,\[1\]'
[^:]*:318: Error: expected a base register at operand 2 -- `ldr x0,\[\]'
[^:]*:319: Error: expected a base register at operand 2 -- `ldr x0,\[,xzr\]'

View File

@ -313,3 +313,7 @@
ldxp x26, x1, [x26]
st4 {v0.16b-v3.16b}[4], [x0]
stlxp w3, w26, w26, [x3]
ldr x0, [1]
ldr x0, []
ldr x0, [,xzr]

View File

@ -2,7 +2,7 @@
[^:]+:18: Error: operand mismatch -- `ldaprb x0,\[x1\]'
[^:]+:19: Error: operand mismatch -- `ldaprh x0,\[x1\]'
[^:]+:20: Error: the optional immediate offset can only be 0 at operand 2 -- `ldapr x0,\[x1,#8\]'
[^:]+:5: Error: 64-bit integer or SP register expected at operand 2 -- `ldaprb w1,\[xz\]'
[^:]+:5: Error: invalid base register at operand 2 -- `ldaprb w1,\[xz\]'
[^:]+:23: Info: macro .*
[^:]+:6: Error: the optional immediate offset can only be 0 at operand 2 -- `ldaprb w1,\[x7,#8\]'
[^:]+:23: Info: macro .*
@ -10,7 +10,7 @@
[^:]+:23: Info: macro .*
[^:]+:8: Error: invalid addressing mode at operand 2 -- `ldaprb w1,\[x7\],#8'
[^:]+:23: Info: macro .*
[^:]+:5: Error: 64-bit integer or SP register expected at operand 2 -- `ldaprh w1,\[xz\]'
[^:]+:5: Error: invalid base register at operand 2 -- `ldaprh w1,\[xz\]'
[^:]+:23: Info: macro .*
[^:]+:6: Error: the optional immediate offset can only be 0 at operand 2 -- `ldaprh w1,\[x7,#8\]'
[^:]+:23: Info: macro .*
@ -18,7 +18,7 @@
[^:]+:23: Info: macro .*
[^:]+:8: Error: invalid addressing mode at operand 2 -- `ldaprh w1,\[x7\],#8'
[^:]+:23: Info: macro .*
[^:]+:5: Error: 64-bit integer or SP register expected at operand 2 -- `ldapr w1,\[xz\]'
[^:]+:5: Error: invalid base register at operand 2 -- `ldapr w1,\[xz\]'
[^:]+:23: Info: macro .*
[^:]+:6: Error: the optional immediate offset can only be 0 at operand 2 -- `ldapr w1,\[x7,#8\]'
[^:]+:23: Info: macro .*

View File

@ -5,7 +5,7 @@
[^:]+:12: Error: immediate offset out of range -4096 to 4088 at operand 2 -- `ldraa x0,\[x1,#4096\]'
[^:]+:13: Error: immediate offset out of range -4096 to 4088 at operand 2 -- `ldraa x0,\[x1,#5555\]'
[^:]+:14: Error: immediate offset out of range -4096 to 4088 at operand 2 -- `ldraa x0,\[x1,#-4104\]'
[^:]+:15: Error: 64-bit integer or SP register expected at operand 2 -- `ldraa x0,\[xz\]'
[^:]+:15: Error: invalid base register at operand 2 -- `ldraa x0,\[xz\]'
[^:]+:16: Error: invalid expression in the address at operand 2 -- `ldraa x0,\[sp\],'
[^:]+:17: Error: immediate value must be a multiple of 8 at operand 2 -- `ldraa x0,\[x1,#1\]!'
[^:]+:18: Error: immediate value must be a multiple of 8 at operand 2 -- `ldraa x0,\[x1,#4\]!'
@ -13,7 +13,7 @@
[^:]+:20: Error: immediate offset out of range -4096 to 4088 at operand 2 -- `ldraa x0,\[x1,#4096\]!'
[^:]+:21: Error: immediate offset out of range -4096 to 4088 at operand 2 -- `ldraa x0,\[x1,#5555\]!'
[^:]+:22: Error: immediate offset out of range -4096 to 4088 at operand 2 -- `ldraa x0,\[x1,#-4104\]!'
[^:]+:23: Error: 64-bit integer or SP register expected at operand 2 -- `ldraa x0,\[xz\]'
[^:]+:23: Error: invalid base register at operand 2 -- `ldraa x0,\[xz\]'
[^:]+:24: Error: invalid addressing mode at operand 2 -- `ldraa x0,\[x1\],#8'
[^:]+:27: Error: immediate value must be a multiple of 8 at operand 2 -- `ldrab x0,\[x1,#1\]'
[^:]+:28: Error: immediate value must be a multiple of 8 at operand 2 -- `ldrab x0,\[x1,#4\]'
@ -21,7 +21,7 @@
[^:]+:30: Error: immediate offset out of range -4096 to 4088 at operand 2 -- `ldrab x0,\[x1,#4096\]'
[^:]+:31: Error: immediate offset out of range -4096 to 4088 at operand 2 -- `ldrab x0,\[x1,#5555\]'
[^:]+:32: Error: immediate offset out of range -4096 to 4088 at operand 2 -- `ldrab x0,\[x1,#-4104\]'
[^:]+:33: Error: 64-bit integer or SP register expected at operand 2 -- `ldrab x0,\[xz\]'
[^:]+:33: Error: invalid base register at operand 2 -- `ldrab x0,\[xz\]'
[^:]+:34: Error: invalid expression in the address at operand 2 -- `ldrab x0,\[sp\],'
[^:]+:35: Error: immediate value must be a multiple of 8 at operand 2 -- `ldrab x0,\[x1,#1\]!'
[^:]+:36: Error: immediate value must be a multiple of 8 at operand 2 -- `ldrab x0,\[x1,#4\]!'
@ -29,5 +29,5 @@
[^:]+:38: Error: immediate offset out of range -4096 to 4088 at operand 2 -- `ldrab x0,\[x1,#4096\]!'
[^:]+:39: Error: immediate offset out of range -4096 to 4088 at operand 2 -- `ldrab x0,\[x1,#5555\]!'
[^:]+:40: Error: immediate offset out of range -4096 to 4088 at operand 2 -- `ldrab x0,\[x1,#-4104\]!'
[^:]+:41: Error: 64-bit integer or SP register expected at operand 2 -- `ldrab x0,\[xz\]'
[^:]+:41: Error: invalid base register at operand 2 -- `ldrab x0,\[xz\]'
[^:]+:42: Error: invalid addressing mode at operand 2 -- `ldrab x0,\[x1\],#8'

File diff suppressed because it is too large Load Diff

View File

@ -34,22 +34,22 @@
[^:]*:[0-9]+: Error: operand 3 must be an integer or stack pointer register -- `subps x1,x2,xzr'
[^:]*:[0-9]+: Error: operand 1 must be an integer or stack pointer register -- `cmpp xzr,x2'
[^:]*:[0-9]+: Error: operand 2 must be an integer or stack pointer register -- `cmpp x2,xzr'
[^:]*:[0-9]+: Error: 64-bit integer or SP register expected at operand 2 -- `stg x2,\[xzr,#0\]'
[^:]*:[0-9]+: Error: 64-bit integer or SP register expected at operand 2 -- `st2g x2,\[xzr,#0\]!'
[^:]*:[0-9]+: Error: 64-bit integer or SP register expected at operand 2 -- `stzg x2,\[xzr\],#0'
[^:]*:[0-9]+: Error: 64-bit integer or SP register expected at operand 2 -- `stz2g x2,\[xzr,#0\]'
[^:]*:[0-9]+: Error: invalid base register at operand 2 -- `stg x2,\[xzr,#0\]'
[^:]*:[0-9]+: Error: invalid base register at operand 2 -- `st2g x2,\[xzr,#0\]!'
[^:]*:[0-9]+: Error: invalid base register at operand 2 -- `stzg x2,\[xzr\],#0'
[^:]*:[0-9]+: Error: invalid base register at operand 2 -- `stz2g x2,\[xzr,#0\]'
[^:]*:[0-9]+: Error: operand 1 must be an integer or stack pointer register -- `stg xzr,\[x2,#0\]'
[^:]*:[0-9]+: Error: operand 1 must be an integer or stack pointer register -- `st2g xzr,\[x2,#0\]!'
[^:]*:[0-9]+: Error: operand 1 must be an integer or stack pointer register -- `stzg xzr,\[x2\],#0'
[^:]*:[0-9]+: Error: operand 1 must be an integer or stack pointer register -- `stz2g xzr,\[x2,#0\]'
[^:]*:[0-9]+: Error: operand 1 must be an integer register -- `stgp sp,x2,\[x3\]'
[^:]*:[0-9]+: Error: operand 2 must be an integer register -- `stgp x1,sp,\[x3\]'
[^:]*:[0-9]+: Error: 64-bit integer or SP register expected at operand 3 -- `stgp x0,x0,\[xzr\]'
[^:]*:[0-9]+: Error: invalid base register at operand 3 -- `stgp x0,x0,\[xzr\]'
[^:]*:[0-9]+: Error: operand 1 must be an integer register -- `ldg sp,\[x0,#16\]'
[^:]*:[0-9]+: Error: 64-bit integer or SP register expected at operand 2 -- `ldg x0,\[xzr,#16\]'
[^:]*:[0-9]+: Error: 64-bit integer or SP register expected at operand 2 -- `stzgm x0,\[xzr\]'
[^:]*:[0-9]+: Error: invalid base register at operand 2 -- `ldg x0,\[xzr,#16\]'
[^:]*:[0-9]+: Error: invalid base register at operand 2 -- `stzgm x0,\[xzr\]'
[^:]*:[0-9]+: Error: operand 1 must be an integer register -- `stzgm sp,\[x3\]'
[^:]*:[0-9]+: Error: 64-bit integer or SP register expected at operand 2 -- `ldgm x0,\[xzr\]'
[^:]*:[0-9]+: Error: invalid base register at operand 2 -- `ldgm x0,\[xzr\]'
[^:]*:[0-9]+: Error: operand 1 must be an integer register -- `ldgm sp,\[x3\]'
[^:]*:[0-9]+: Error: 64-bit integer or SP register expected at operand 2 -- `stgm x0,\[xzr\]'
[^:]*:[0-9]+: Error: invalid base register at operand 2 -- `stgm x0,\[xzr\]'
[^:]*:[0-9]+: Error: operand 1 must be an integer register -- `stgm sp,\[x3\]'

View File

@ -493,8 +493,8 @@
[^ :]+:[0-9]+: Info: ldnt1b {z0\.s}, p0/z, \[z0\.s, xzr\]
[^ :]+:[0-9]+: Error: operand 1 must be a list of SVE vector registers -- `ldnt1b {z32\.d},p0/z,\[z0\.d\]'
[^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `ldnt1b {z0\.d},p8/z,\[z0\.d\]'
[^ :]+:[0-9]+: Error: base register expected at operand 3 -- `ldnt1b {z0\.d},p0/z,\[z32\.d\]'
[^ :]+:[0-9]+: Error: offset register expected at operand 3 -- `ldnt1b {z0\.d},p0/z,\[z0\.d,sp\]'
[^ :]+:[0-9]+: Error: invalid base register at operand 3 -- `ldnt1b {z0\.d},p0/z,\[z32\.d\]'
[^ :]+:[0-9]+: Error: invalid offset register at operand 3 -- `ldnt1b {z0\.d},p0/z,\[z0\.d,sp\]'
[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ldnt1b {z0\.d},p0/z,\[z0\.d,x32\]'
[^ :]+:[0-9]+: Error: invalid use of 32-bit register offset at operand 3 -- `ldnt1b {z0\.d},p0/z,\[z0\.d,w16\]'
[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ldnt1b {z0\.d},p0/z,\[z0\.d,z0\.d\]'
@ -510,8 +510,8 @@
[^ :]+:[0-9]+: Info: ldnt1b {z0\.s}, p0/z, \[z0\.s, xzr\]
[^ :]+:[0-9]+: Error: operand 1 must be a list of SVE vector registers -- `ldnt1b {z32\.s},p0/z,\[z0\.s\]'
[^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `ldnt1b {z0\.s},p8/z,\[z0\.s\]'
[^ :]+:[0-9]+: Error: base register expected at operand 3 -- `ldnt1b {z0\.s},p0/z,\[z32\.s\]'
[^ :]+:[0-9]+: Error: offset register expected at operand 3 -- `ldnt1b {z0\.s},p0/z,\[z0\.s,sp\]'
[^ :]+:[0-9]+: Error: invalid base register at operand 3 -- `ldnt1b {z0\.s},p0/z,\[z32\.s\]'
[^ :]+:[0-9]+: Error: invalid offset register at operand 3 -- `ldnt1b {z0\.s},p0/z,\[z0\.s,sp\]'
[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ldnt1b {z0\.s},p0/z,\[z0\.s,x32\]'
[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ldnt1b {z0\.s},p0/z,\[z0\.s,z0\.s\]'
[^ :]+:[0-9]+: Error: invalid register list at operand 1 -- `ldnt1d {z0\.d,z1\.d},p0/z,\[z0\.d,x0\]'
@ -520,8 +520,8 @@
[^ :]+:[0-9]+: Info: ldnt1d {z0\.d}, p0/z, \[z0\.d, xzr\]
[^ :]+:[0-9]+: Error: operand 1 must be a list of SVE vector registers -- `ldnt1d {z32\.d},p0/z,\[z0\.d\]'
[^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `ldnt1d {z0\.d},p8/z,\[z0\.d\]'
[^ :]+:[0-9]+: Error: base register expected at operand 3 -- `ldnt1d {z0\.d},p0/z,\[z32\.d\]'
[^ :]+:[0-9]+: Error: offset register expected at operand 3 -- `ldnt1d {z0\.d},p0/z,\[z0\.d,sp\]'
[^ :]+:[0-9]+: Error: invalid base register at operand 3 -- `ldnt1d {z0\.d},p0/z,\[z32\.d\]'
[^ :]+:[0-9]+: Error: invalid offset register at operand 3 -- `ldnt1d {z0\.d},p0/z,\[z0\.d,sp\]'
[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ldnt1d {z0\.d},p0/z,\[z0\.d,x32\]'
[^ :]+:[0-9]+: Error: invalid use of 32-bit register offset at operand 3 -- `ldnt1d {z0\.d},p0/z,\[z0\.d,w16\]'
[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ldnt1d {z0\.d},p0/z,\[z0\.d,z0\.d\]'
@ -540,8 +540,8 @@
[^ :]+:[0-9]+: Info: ldnt1h {z0\.s}, p0/z, \[z0\.s, xzr\]
[^ :]+:[0-9]+: Error: operand 1 must be a list of SVE vector registers -- `ldnt1h {z32\.d},p0/z,\[z0\.d\]'
[^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `ldnt1h {z0\.d},p8/z,\[z0\.d\]'
[^ :]+:[0-9]+: Error: base register expected at operand 3 -- `ldnt1h {z0\.d},p0/z,\[z32\.d\]'
[^ :]+:[0-9]+: Error: offset register expected at operand 3 -- `ldnt1h {z0\.d},p0/z,\[z0\.d,sp\]'
[^ :]+:[0-9]+: Error: invalid base register at operand 3 -- `ldnt1h {z0\.d},p0/z,\[z32\.d\]'
[^ :]+:[0-9]+: Error: invalid offset register at operand 3 -- `ldnt1h {z0\.d},p0/z,\[z0\.d,sp\]'
[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ldnt1h {z0\.d},p0/z,\[z0\.d,x32\]'
[^ :]+:[0-9]+: Error: invalid use of 32-bit register offset at operand 3 -- `ldnt1h {z0\.d},p0/z,\[z0\.d,w16\]'
[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ldnt1h {z0\.d},p0/z,\[z0\.d,z0\.d\]'
@ -551,8 +551,8 @@
[^ :]+:[0-9]+: Error: type mismatch in vector register list at operand 1 -- `ldnt1h {z0\.s,z1\.d},p0/z,\[z0\.s,x0\]'
[^ :]+:[0-9]+: Error: operand 1 must be a list of SVE vector registers -- `ldnt1h {z32\.s},p0/z,\[z0\.s\]'
[^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `ldnt1h {z0\.s},p8/z,\[z0\.s\]'
[^ :]+:[0-9]+: Error: base register expected at operand 3 -- `ldnt1h {z0\.s},p0/z,\[z32\.s\]'
[^ :]+:[0-9]+: Error: offset register expected at operand 3 -- `ldnt1h {z0\.s},p0/z,\[z0\.s,sp\]'
[^ :]+:[0-9]+: Error: invalid base register at operand 3 -- `ldnt1h {z0\.s},p0/z,\[z32\.s\]'
[^ :]+:[0-9]+: Error: invalid offset register at operand 3 -- `ldnt1h {z0\.s},p0/z,\[z0\.s,sp\]'
[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ldnt1h {z0\.s},p0/z,\[z0\.s,x32\]'
[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ldnt1h {z0\.s},p0/z,\[z0\.s,z0\.s\]'
[^ :]+:[0-9]+: Error: invalid register list at operand 1 -- `ldnt1sb {z0\.d,z1\.d},p0/z,\[z0\.d,x0\]'
@ -563,8 +563,8 @@
[^ :]+:[0-9]+: Info: ldnt1sb {z0\.s}, p0/z, \[z0\.s, xzr\]
[^ :]+:[0-9]+: Error: operand 1 must be a list of SVE vector registers -- `ldnt1sb {z32\.d},p0/z,\[z0\.d\]'
[^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `ldnt1sb {z0\.d},p8/z,\[z0\.d\]'
[^ :]+:[0-9]+: Error: base register expected at operand 3 -- `ldnt1sb {z0\.d},p0/z,\[z32\.d\]'
[^ :]+:[0-9]+: Error: offset register expected at operand 3 -- `ldnt1sb {z0\.d},p0/z,\[z0\.d,sp\]'
[^ :]+:[0-9]+: Error: invalid base register at operand 3 -- `ldnt1sb {z0\.d},p0/z,\[z32\.d\]'
[^ :]+:[0-9]+: Error: invalid offset register at operand 3 -- `ldnt1sb {z0\.d},p0/z,\[z0\.d,sp\]'
[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ldnt1sb {z0\.d},p0/z,\[z0\.d,x32\]'
[^ :]+:[0-9]+: Error: invalid use of 32-bit register offset at operand 3 -- `ldnt1sb {z0\.d},p0/z,\[z0\.d,w16\]'
[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ldnt1sb {z0\.d},p0/z,\[z0\.d,z0\.d\]'
@ -576,8 +576,8 @@
[^ :]+:[0-9]+: Info: ldnt1sh {z0\.s}, p0/z, \[z0\.s, xzr\]
[^ :]+:[0-9]+: Error: operand 1 must be a list of SVE vector registers -- `ldnt1sh {z32\.d},p0/z,\[z0\.d\]'
[^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `ldnt1sh {z0\.d},p8/z,\[z0\.d\]'
[^ :]+:[0-9]+: Error: base register expected at operand 3 -- `ldnt1sh {z0\.d},p0/z,\[z32\.d\]'
[^ :]+:[0-9]+: Error: offset register expected at operand 3 -- `ldnt1sh {z0\.d},p0/z,\[z0\.d,sp\]'
[^ :]+:[0-9]+: Error: invalid base register at operand 3 -- `ldnt1sh {z0\.d},p0/z,\[z32\.d\]'
[^ :]+:[0-9]+: Error: invalid offset register at operand 3 -- `ldnt1sh {z0\.d},p0/z,\[z0\.d,sp\]'
[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ldnt1sh {z0\.d},p0/z,\[z0\.d,x32\]'
[^ :]+:[0-9]+: Error: invalid use of 32-bit register offset at operand 3 -- `ldnt1sh {z0\.d},p0/z,\[z0\.d,w16\]'
[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ldnt1sh {z0\.d},p0/z,\[z0\.d,z0\.d\]'
@ -589,8 +589,8 @@
[^ :]+:[0-9]+: Info: ldnt1sh {z0\.s}, p0/z, \[z0\.s, xzr\]
[^ :]+:[0-9]+: Error: operand 1 must be a list of SVE vector registers -- `ldnt1sh {z32\.d},p0/z,\[z0\.d\]'
[^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `ldnt1sh {z0\.d},p8/z,\[z0\.d\]'
[^ :]+:[0-9]+: Error: base register expected at operand 3 -- `ldnt1sh {z0\.d},p0/z,\[z32\.d\]'
[^ :]+:[0-9]+: Error: offset register expected at operand 3 -- `ldnt1sh {z0\.d},p0/z,\[z0\.d,sp\]'
[^ :]+:[0-9]+: Error: invalid base register at operand 3 -- `ldnt1sh {z0\.d},p0/z,\[z32\.d\]'
[^ :]+:[0-9]+: Error: invalid offset register at operand 3 -- `ldnt1sh {z0\.d},p0/z,\[z0\.d,sp\]'
[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ldnt1sh {z0\.d},p0/z,\[z0\.d,x32\]'
[^ :]+:[0-9]+: Error: invalid use of 32-bit register offset at operand 3 -- `ldnt1sh {z0\.d},p0/z,\[z0\.d,w16\]'
[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ldnt1sh {z0\.d},p0/z,\[z0\.d,z0\.d\]'
@ -600,8 +600,8 @@
[^ :]+:[0-9]+: Info: ldnt1w {z0\.s}, p0/z, \[z0\.s, xzr\]
[^ :]+:[0-9]+: Error: operand 1 must be a list of SVE vector registers -- `ldnt1w {z32\.d},p0/z,\[z0\.d\]'
[^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `ldnt1w {z0\.d},p8/z,\[z0\.d\]'
[^ :]+:[0-9]+: Error: base register expected at operand 3 -- `ldnt1w {z0\.d},p0/z,\[z32\.d\]'
[^ :]+:[0-9]+: Error: offset register expected at operand 3 -- `ldnt1w {z0\.d},p0/z,\[z0\.d,sp\]'
[^ :]+:[0-9]+: Error: invalid base register at operand 3 -- `ldnt1w {z0\.d},p0/z,\[z32\.d\]'
[^ :]+:[0-9]+: Error: invalid offset register at operand 3 -- `ldnt1w {z0\.d},p0/z,\[z0\.d,sp\]'
[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ldnt1w {z0\.d},p0/z,\[z0\.d,x32\]'
[^ :]+:[0-9]+: Error: invalid use of 32-bit register offset at operand 3 -- `ldnt1w {z0\.d},p0/z,\[z0\.d,w16\]'
[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ldnt1w {z0\.d},p0/z,\[z0\.d,z0\.d\]'
@ -611,8 +611,8 @@
[^ :]+:[0-9]+: Error: type mismatch in vector register list at operand 1 -- `ldnt1w {z0\.s,z1\.d},p0/z,\[z0\.s,x0\]'
[^ :]+:[0-9]+: Error: operand 1 must be a list of SVE vector registers -- `ldnt1w {z32\.s},p0/z,\[z0\.s\]'
[^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `ldnt1w {z0\.s},p8/z,\[z0\.s\]'
[^ :]+:[0-9]+: Error: base register expected at operand 3 -- `ldnt1w {z0\.s},p0/z,\[z32\.s\]'
[^ :]+:[0-9]+: Error: offset register expected at operand 3 -- `ldnt1w {z0\.s},p0/z,\[z0\.s,sp\]'
[^ :]+:[0-9]+: Error: invalid base register at operand 3 -- `ldnt1w {z0\.s},p0/z,\[z32\.s\]'
[^ :]+:[0-9]+: Error: invalid offset register at operand 3 -- `ldnt1w {z0\.s},p0/z,\[z0\.s,sp\]'
[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ldnt1w {z0\.s},p0/z,\[z0\.s,x32\]'
[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ldnt1w {z0\.s},p0/z,\[z0\.s,z0\.s\]'
[^ :]+:[0-9]+: Error: operand mismatch -- `match p0\.h,p0/z,z0\.b,z0\.b'
@ -2217,8 +2217,8 @@
[^ :]+:[0-9]+: Info: stnt1b {z0\.s}, p0, \[z0\.s, xzr\]
[^ :]+:[0-9]+: Error: operand 1 must be a list of SVE vector registers -- `stnt1b {z32\.d},p0,\[z0\.d\]'
[^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `stnt1b {z0\.d},p8,\[z0\.d\]'
[^ :]+:[0-9]+: Error: base register expected at operand 3 -- `stnt1b {z0\.d},p0,\[z32\.d\]'
[^ :]+:[0-9]+: Error: offset register expected at operand 3 -- `stnt1b {z0\.d},p0,\[z0\.d,sp\]'
[^ :]+:[0-9]+: Error: invalid base register at operand 3 -- `stnt1b {z0\.d},p0,\[z32\.d\]'
[^ :]+:[0-9]+: Error: invalid offset register at operand 3 -- `stnt1b {z0\.d},p0,\[z0\.d,sp\]'
[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `stnt1b {z0\.d},p0,\[z0\.d,x32\]'
[^ :]+:[0-9]+: Error: invalid use of 32-bit register offset at operand 3 -- `stnt1b {z0\.d},p0,\[z0\.d,w16\]'
[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `stnt1b {z0\.d},p0,\[z0\.d,z0\.d\]'
@ -2228,8 +2228,8 @@
[^ :]+:[0-9]+: Error: type mismatch in vector register list at operand 1 -- `stnt1b {z0\.s,z1\.d},p0,\[z0\.s,x0\]'
[^ :]+:[0-9]+: Error: operand 1 must be a list of SVE vector registers -- `stnt1b {z32\.s},p0,\[z0\.s\]'
[^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `stnt1b {z0\.s},p8,\[z0\.s\]'
[^ :]+:[0-9]+: Error: base register expected at operand 3 -- `stnt1b {z0\.s},p0,\[z32\.s\]'
[^ :]+:[0-9]+: Error: offset register expected at operand 3 -- `stnt1b {z0\.s},p0,\[z0\.s,sp\]'
[^ :]+:[0-9]+: Error: invalid base register at operand 3 -- `stnt1b {z0\.s},p0,\[z32\.s\]'
[^ :]+:[0-9]+: Error: invalid offset register at operand 3 -- `stnt1b {z0\.s},p0,\[z0\.s,sp\]'
[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `stnt1b {z0\.s},p0,\[z0\.s,x32\]'
[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `stnt1b {z0\.s},p0,\[z0\.s,z0\.s\]'
[^ :]+:[0-9]+: Error: invalid register list at operand 1 -- `stnt1d {z0\.d,z1\.d},p0,\[z0\.d,x0\]'
@ -2238,8 +2238,8 @@
[^ :]+:[0-9]+: Info: stnt1d {z0\.d}, p0, \[z0\.d, xzr\]
[^ :]+:[0-9]+: Error: operand 1 must be a list of SVE vector registers -- `stnt1d {z32\.d},p0,\[z0\.d\]'
[^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `stnt1d {z0\.d},p8,\[z0\.d\]'
[^ :]+:[0-9]+: Error: base register expected at operand 3 -- `stnt1d {z0\.d},p0,\[z32\.d\]'
[^ :]+:[0-9]+: Error: offset register expected at operand 3 -- `stnt1d {z0\.d},p0,\[z0\.d,sp\]'
[^ :]+:[0-9]+: Error: invalid base register at operand 3 -- `stnt1d {z0\.d},p0,\[z32\.d\]'
[^ :]+:[0-9]+: Error: invalid offset register at operand 3 -- `stnt1d {z0\.d},p0,\[z0\.d,sp\]'
[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `stnt1d {z0\.d},p0,\[z0\.d,x32\]'
[^ :]+:[0-9]+: Error: invalid use of 32-bit register offset at operand 3 -- `stnt1d {z0\.d},p0,\[z0\.d,w16\]'
[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `stnt1d {z0\.d},p0,\[z0\.d,z0\.d\]'
@ -2252,8 +2252,8 @@
[^ :]+:[0-9]+: Info: stnt1h {z0\.s}, p0, \[z0\.s, xzr\]
[^ :]+:[0-9]+: Error: operand 1 must be a list of SVE vector registers -- `stnt1h {z32\.d},p0,\[z0\.d\]'
[^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `stnt1h {z0\.d},p8,\[z0\.d\]'
[^ :]+:[0-9]+: Error: base register expected at operand 3 -- `stnt1h {z0\.d},p0,\[z32\.d\]'
[^ :]+:[0-9]+: Error: offset register expected at operand 3 -- `stnt1h {z0\.d},p0,\[z0\.d,sp\]'
[^ :]+:[0-9]+: Error: invalid base register at operand 3 -- `stnt1h {z0\.d},p0,\[z32\.d\]'
[^ :]+:[0-9]+: Error: invalid offset register at operand 3 -- `stnt1h {z0\.d},p0,\[z0\.d,sp\]'
[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `stnt1h {z0\.d},p0,\[z0\.d,x32\]'
[^ :]+:[0-9]+: Error: invalid use of 32-bit register offset at operand 3 -- `stnt1h {z0\.d},p0,\[z0\.d,w16\]'
[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `stnt1h {z0\.d},p0,\[z0\.d,z0\.d\]'
@ -2263,8 +2263,8 @@
[^ :]+:[0-9]+: Error: type mismatch in vector register list at operand 1 -- `stnt1h {z0\.s,z1\.d},p0,\[z0\.s,x0\]'
[^ :]+:[0-9]+: Error: operand 1 must be a list of SVE vector registers -- `stnt1h {z32\.s},p0,\[z0\.s\]'
[^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `stnt1h {z0\.s},p8,\[z0\.s\]'
[^ :]+:[0-9]+: Error: base register expected at operand 3 -- `stnt1h {z0\.s},p0,\[z32\.s\]'
[^ :]+:[0-9]+: Error: offset register expected at operand 3 -- `stnt1h {z0\.s},p0,\[z0\.s,sp\]'
[^ :]+:[0-9]+: Error: invalid base register at operand 3 -- `stnt1h {z0\.s},p0,\[z32\.s\]'
[^ :]+:[0-9]+: Error: invalid offset register at operand 3 -- `stnt1h {z0\.s},p0,\[z0\.s,sp\]'
[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `stnt1h {z0\.s},p0,\[z0\.s,x32\]'
[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `stnt1h {z0\.s},p0,\[z0\.s,z0\.s\]'
[^ :]+:[0-9]+: Error: invalid register list at operand 1 -- `stnt1w {z0\.d,z1\.d},p0,\[z0\.d,x0\]'
@ -2273,8 +2273,8 @@
[^ :]+:[0-9]+: Info: stnt1w {z0\.s}, p0, \[z0\.s, xzr\]
[^ :]+:[0-9]+: Error: operand 1 must be a list of SVE vector registers -- `stnt1w {z32\.d},p0,\[z0\.d\]'
[^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `stnt1w {z0\.d},p8,\[z0\.d\]'
[^ :]+:[0-9]+: Error: base register expected at operand 3 -- `stnt1w {z0\.d},p0,\[z32\.d\]'
[^ :]+:[0-9]+: Error: offset register expected at operand 3 -- `stnt1w {z0\.d},p0,\[z0\.d,sp\]'
[^ :]+:[0-9]+: Error: invalid base register at operand 3 -- `stnt1w {z0\.d},p0,\[z32\.d\]'
[^ :]+:[0-9]+: Error: invalid offset register at operand 3 -- `stnt1w {z0\.d},p0,\[z0\.d,sp\]'
[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `stnt1w {z0\.d},p0,\[z0\.d,x32\]'
[^ :]+:[0-9]+: Error: invalid use of 32-bit register offset at operand 3 -- `stnt1w {z0\.d},p0,\[z0\.d,w16\]'
[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `stnt1w {z0\.d},p0,\[z0\.d,z0\.d\]'
@ -2284,8 +2284,8 @@
[^ :]+:[0-9]+: Error: type mismatch in vector register list at operand 1 -- `stnt1w {z0\.s,z1\.d},p0,\[z0\.s,x0\]'
[^ :]+:[0-9]+: Error: operand 1 must be a list of SVE vector registers -- `stnt1w {z32\.s},p0,\[z0\.s\]'
[^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `stnt1w {z0\.s},p8,\[z0\.s\]'
[^ :]+:[0-9]+: Error: base register expected at operand 3 -- `stnt1w {z0\.s},p0,\[z32\.s\]'
[^ :]+:[0-9]+: Error: offset register expected at operand 3 -- `stnt1w {z0\.s},p0,\[z0\.s,sp\]'
[^ :]+:[0-9]+: Error: invalid base register at operand 3 -- `stnt1w {z0\.s},p0,\[z32\.s\]'
[^ :]+:[0-9]+: Error: invalid offset register at operand 3 -- `stnt1w {z0\.s},p0,\[z0\.s,sp\]'
[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `stnt1w {z0\.s},p0,\[z0\.s,x32\]'
[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `stnt1w {z0\.s},p0,\[z0\.s,z0\.s\]'
[^ :]+:[0-9]+: Error: operand mismatch -- `subhnb z0\.h,z0\.h,z0\.h'

View File

@ -3,11 +3,11 @@
.*: Error: operand 3 must be a SIMD vector register -- `cmeq v0\.4s,v1\.4s,s0'
.*: Error: immediate zero expected at operand 3 -- `cmeq v0\.4s,v1\.4s,p0\.b'
.*: Error: immediate zero expected at operand 3 -- `cmeq v0\.4s,v1\.4s,#p0\.b'
.*: Error: 64-bit integer or SP register expected at operand 2 -- `ldr x1,\[s0\]'
.*: Error: 64-bit integer or SP register expected at operand 2 -- `ldr x1,\[z0\]'
.*: Error: 64-bit integer or SP register expected at operand 2 -- `ldr x1,\[z0\.s\]'
.*: Error: 64-bit integer or SP register expected at operand 2 -- `ldr x1,\[p0\]'
.*: Error: 64-bit integer or SP register expected at operand 2 -- `ldr x1,\[p0\.b\]'
.*: Error: invalid base register at operand 2 -- `ldr x1,\[s0\]'
.*: Error: invalid base register at operand 2 -- `ldr x1,\[z0\]'
.*: Error: invalid base register at operand 2 -- `ldr x1,\[z0\.s\]'
.*: Error: invalid base register at operand 2 -- `ldr x1,\[p0\]'
.*: Error: invalid base register at operand 2 -- `ldr x1,\[p0\.b\]'
.*: Error: invalid shift amount at operand 2 -- `ldr x0,\[x1,x2,lsl p0\.b\]'
.*: Error: invalid shift amount at operand 2 -- `ldr x0,\[x1,x2,lsl#p0\.b\]'
.*: Error: immediate out of range at operand 3 -- `and x0,x0,#x0'