sim: sh: rework register layout with anonymous unions & structs
Now that we require C11, we can leverage anonymous unions & structs to fix a long standing issue with the SH register layout. The use of sregs.i for sh-dsp has generated a lot of compiler warnings about the access being out of bounds -- it only has 7 elements declared, but code goes beyond that to reach into the fregs that follow. But now that we have anonymous unions, we can reduce the nested names and have sregs cover all of these registers.
This commit is contained in:
Mike Frysinger
parent
eea68ebb33
commit
74bbe64132
@ -354,7 +354,7 @@ static op tab[] =
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/* sh4a */
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{ "", "", "clrdmxy", "0000000010001000",
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"saved_state.asregs.cregs.named.sr &= ~(SR_MASK_DMX | SR_MASK_DMY);"
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"saved_state.asregs.sr &= ~(SR_MASK_DMX | SR_MASK_DMY);"
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},
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{ "", "0", "cmp/eq #<imm>,R0", "10001000i8*1....",
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@ -1342,14 +1342,14 @@ static op tab[] =
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/* sh4a */
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{ "", "", "setdmx", "0000000010011000",
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"saved_state.asregs.cregs.named.sr |= SR_MASK_DMX;"
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"saved_state.asregs.cregs.named.sr &= ~SR_MASK_DMY;"
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"saved_state.asregs.sr |= SR_MASK_DMX;"
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"saved_state.asregs.sr &= ~SR_MASK_DMY;"
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},
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/* sh4a */
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{ "", "", "setdmy", "0000000011001000",
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"saved_state.asregs.cregs.named.sr |= SR_MASK_DMY;"
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"saved_state.asregs.cregs.named.sr &= ~SR_MASK_DMX;"
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"saved_state.asregs.sr |= SR_MASK_DMY;"
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"saved_state.asregs.sr &= ~SR_MASK_DMX;"
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},
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/* sh-dsp */
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106
sim/sh/interp.c
106
sim/sh/interp.c
@ -120,23 +120,23 @@ static int maskl = 0;
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#define UR (unsigned int) R
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#define UR (unsigned int) R
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#define SR0 saved_state.asregs.regs[0]
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#define CREG(n) (saved_state.asregs.cregs.i[(n)])
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#define GBR saved_state.asregs.cregs.named.gbr
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#define VBR saved_state.asregs.cregs.named.vbr
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#define DBR saved_state.asregs.cregs.named.dbr
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#define TBR saved_state.asregs.cregs.named.tbr
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#define IBCR saved_state.asregs.cregs.named.ibcr
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#define IBNR saved_state.asregs.cregs.named.ibnr
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#define BANKN (saved_state.asregs.cregs.named.ibnr & 0x1ff)
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#define ME ((saved_state.asregs.cregs.named.ibnr >> 14) & 0x3)
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#define SSR saved_state.asregs.cregs.named.ssr
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#define SPC saved_state.asregs.cregs.named.spc
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#define SGR saved_state.asregs.cregs.named.sgr
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#define SREG(n) (saved_state.asregs.sregs.i[(n)])
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#define MACH saved_state.asregs.sregs.named.mach
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#define MACL saved_state.asregs.sregs.named.macl
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#define PR saved_state.asregs.sregs.named.pr
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#define FPUL saved_state.asregs.sregs.named.fpul
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#define CREG(n) (saved_state.asregs.cregs[(n)])
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#define GBR saved_state.asregs.gbr
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#define VBR saved_state.asregs.vbr
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#define DBR saved_state.asregs.dbr
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#define TBR saved_state.asregs.tbr
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#define IBCR saved_state.asregs.ibcr
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#define IBNR saved_state.asregs.ibnr
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#define BANKN (saved_state.asregs.ibnr & 0x1ff)
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#define ME ((saved_state.asregs.ibnr >> 14) & 0x3)
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#define SSR saved_state.asregs.ssr
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#define SPC saved_state.asregs.spc
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#define SGR saved_state.asregs.sgr
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#define SREG(n) (saved_state.asregs.sregs[(n)])
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#define MACH saved_state.asregs.mach
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#define MACL saved_state.asregs.macl
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#define PR saved_state.asregs.pr
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#define FPUL saved_state.asregs.fpul
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#define PC insn_ptr
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@ -145,8 +145,8 @@ static int maskl = 0;
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/* Alternate bank of registers r0-r7 */
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/* Note: code controling SR handles flips between BANK0 and BANK1 */
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#define Rn_BANK(n) (saved_state.asregs.cregs.named.bank[(n)])
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#define SET_Rn_BANK(n, EXP) do { saved_state.asregs.cregs.named.bank[(n)] = (EXP); } while (0)
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#define Rn_BANK(n) (saved_state.asregs.bank[(n)])
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#define SET_Rn_BANK(n, EXP) do { saved_state.asregs.bank[(n)] = (EXP); } while (0)
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/* Manipulate SR */
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@ -167,28 +167,28 @@ static int maskl = 0;
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#define SR_MASK_RC 0x0fff0000
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#define SR_RC_INCREMENT -0x00010000
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#define BO ((saved_state.asregs.cregs.named.sr & SR_MASK_BO) != 0)
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#define CS ((saved_state.asregs.cregs.named.sr & SR_MASK_CS) != 0)
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#define M ((saved_state.asregs.cregs.named.sr & SR_MASK_M) != 0)
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#define Q ((saved_state.asregs.cregs.named.sr & SR_MASK_Q) != 0)
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#define S ((saved_state.asregs.cregs.named.sr & SR_MASK_S) != 0)
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#define T ((saved_state.asregs.cregs.named.sr & SR_MASK_T) != 0)
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#define LDST ((saved_state.asregs.cregs.named.ldst) != 0)
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#define BO ((saved_state.asregs.sr & SR_MASK_BO) != 0)
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#define CS ((saved_state.asregs.sr & SR_MASK_CS) != 0)
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#define M ((saved_state.asregs.sr & SR_MASK_M) != 0)
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#define Q ((saved_state.asregs.sr & SR_MASK_Q) != 0)
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#define S ((saved_state.asregs.sr & SR_MASK_S) != 0)
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#define T ((saved_state.asregs.sr & SR_MASK_T) != 0)
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#define LDST ((saved_state.asregs.ldst) != 0)
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#define SR_BL ((saved_state.asregs.cregs.named.sr & SR_MASK_BL) != 0)
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#define SR_RB ((saved_state.asregs.cregs.named.sr & SR_MASK_RB) != 0)
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#define SR_MD ((saved_state.asregs.cregs.named.sr & SR_MASK_MD) != 0)
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#define SR_DMY ((saved_state.asregs.cregs.named.sr & SR_MASK_DMY) != 0)
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#define SR_DMX ((saved_state.asregs.cregs.named.sr & SR_MASK_DMX) != 0)
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#define SR_RC ((saved_state.asregs.cregs.named.sr & SR_MASK_RC))
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#define SR_BL ((saved_state.asregs.sr & SR_MASK_BL) != 0)
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#define SR_RB ((saved_state.asregs.sr & SR_MASK_RB) != 0)
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#define SR_MD ((saved_state.asregs.sr & SR_MASK_MD) != 0)
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#define SR_DMY ((saved_state.asregs.sr & SR_MASK_DMY) != 0)
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#define SR_DMX ((saved_state.asregs.sr & SR_MASK_DMX) != 0)
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#define SR_RC ((saved_state.asregs.sr & SR_MASK_RC))
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/* Note: don't use this for privileged bits */
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#define SET_SR_BIT(EXP, BIT) \
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do { \
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if ((EXP) & 1) \
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saved_state.asregs.cregs.named.sr |= (BIT); \
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saved_state.asregs.sr |= (BIT); \
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else \
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saved_state.asregs.cregs.named.sr &= ~(BIT); \
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saved_state.asregs.sr &= ~(BIT); \
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} while (0)
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#define SET_SR_BO(EXP) SET_SR_BIT ((EXP), SR_MASK_BO)
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@ -205,16 +205,16 @@ do { \
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#define SET_SR_Q(EXP) SET_SR_BIT ((EXP), SR_MASK_Q)
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#define SET_SR_S(EXP) SET_SR_BIT ((EXP), SR_MASK_S)
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#define SET_SR_T(EXP) SET_SR_BIT ((EXP), SR_MASK_T)
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#define SET_LDST(EXP) (saved_state.asregs.cregs.named.ldst = ((EXP) != 0))
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#define SET_LDST(EXP) (saved_state.asregs.ldst = ((EXP) != 0))
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/* stc currently relies on being able to read SR without modifications. */
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#define GET_SR() (saved_state.asregs.cregs.named.sr - 0)
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#define GET_SR() (saved_state.asregs.sr - 0)
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#define SET_SR(x) set_sr (x)
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#define SET_RC(x) \
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(saved_state.asregs.cregs.named.sr \
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= (saved_state.asregs.cregs.named.sr & 0xf000ffff) | ((x) & 0xfff) << 16)
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(saved_state.asregs.sr \
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= (saved_state.asregs.sr & 0xf000ffff) | ((x) & 0xfff) << 16)
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/* Manipulate FPSCR */
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@ -229,10 +229,10 @@ do { \
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static void
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set_fpscr1 (int x)
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{
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int old = saved_state.asregs.sregs.named.fpscr;
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saved_state.asregs.sregs.named.fpscr = (x);
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int old = saved_state.asregs.fpscr;
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saved_state.asregs.fpscr = (x);
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/* swap the floating point register banks */
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if ((saved_state.asregs.sregs.named.fpscr ^ old) & FPSCR_MASK_FR
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if ((saved_state.asregs.fpscr ^ old) & FPSCR_MASK_FR
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/* Ignore bit change if simulating sh-dsp. */
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&& ! target_dsp)
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{
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@ -243,13 +243,13 @@ set_fpscr1 (int x)
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}
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/* sts relies on being able to read fpscr directly. */
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#define GET_FPSCR() (saved_state.asregs.sregs.named.fpscr)
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#define GET_FPSCR() (saved_state.asregs.fpscr)
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#define SET_FPSCR(x) \
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do { \
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set_fpscr1 (x); \
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} while (0)
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#define DSR (saved_state.asregs.sregs.named.fpscr)
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#define DSR (saved_state.asregs.fpscr)
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#define RAISE_EXCEPTION(x) \
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(saved_state.asregs.exception = x, saved_state.asregs.insn_end = 0)
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@ -410,15 +410,15 @@ set_dr (int n, double exp)
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#define XF(n) (saved_state.asregs.fregs[(n) >> 5].i[(n) & 0x1f])
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#define SET_XF(n,EXP) (saved_state.asregs.fregs[(n) >> 5].i[(n) & 0x1f] = (EXP))
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#define RS saved_state.asregs.cregs.named.rs
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#define RE saved_state.asregs.cregs.named.re
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#define MOD (saved_state.asregs.cregs.named.mod)
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#define RS saved_state.asregs.rs
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#define RE saved_state.asregs.re
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#define MOD (saved_state.asregs.mod)
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#define SET_MOD(i) \
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(MOD = (i), \
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MOD_ME = (unsigned) MOD >> 16 | (SR_DMY ? ~0xffff : (SR_DMX ? 0 : 0x10000)), \
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MOD_DELTA = (MOD & 0xffff) - ((unsigned) MOD >> 16))
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#define DSP_R(n) saved_state.asregs.sregs.i[(n)]
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#define DSP_R(n) saved_state.asregs.sregs[(n)]
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#define DSP_GRD(n) DSP_R ((n) + 8)
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#define GET_DSP_GRD(n) ((n | 2) == 7 ? SEXT (DSP_GRD (n)) : SIGN32 (DSP_R (n)))
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#define A1 DSP_R (5)
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@ -485,12 +485,12 @@ set_sr (int new_sr)
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int i, tmp;
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for (i = 0; i < 8; i++)
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{
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tmp = saved_state.asregs.cregs.named.bank[i];
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saved_state.asregs.cregs.named.bank[i] = saved_state.asregs.regs[i];
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tmp = saved_state.asregs.bank[i];
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saved_state.asregs.bank[i] = saved_state.asregs.regs[i];
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saved_state.asregs.regs[i] = tmp;
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}
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}
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saved_state.asregs.cregs.named.sr = new_sr;
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saved_state.asregs.sr = new_sr;
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SET_MOD (MOD);
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}
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@ -1768,7 +1768,7 @@ sim_resume (SIM_DESC sd, int step, int siggnal)
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CHECK_INSN_PTR (insn_ptr);
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#ifndef PR
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PR = saved_state.asregs.sregs.named.pr;
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PR = saved_state.asregs.pr;
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#endif
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/*T = GET_SR () & SR_MASK_T;*/
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prevlock = saved_state.asregs.prevlock;
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@ -1849,7 +1849,7 @@ sim_resume (SIM_DESC sd, int step, int siggnal)
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}
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if (saved_state.asregs.insn_end == loop.end)
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{
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saved_state.asregs.cregs.named.sr += SR_RC_INCREMENT;
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saved_state.asregs.sr += SR_RC_INCREMENT;
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if (SR_RC)
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insn_ptr = loop.start;
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else
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@ -1876,7 +1876,7 @@ sim_resume (SIM_DESC sd, int step, int siggnal)
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saved_state.asregs.insts += insts;
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saved_state.asregs.pc = PH2T (insn_ptr);
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#ifndef PR
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saved_state.asregs.sregs.named.pr = PR;
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saved_state.asregs.pr = PR;
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#endif
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saved_state.asregs.prevlock = prevlock;
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@ -36,34 +36,26 @@ typedef union
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int pc;
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/* System registers. For sh-dsp this also includes A0 / X0 / X1 / Y0 / Y1
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which are located in fregs, i.e. strictly speaking, these are
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out-of-bounds accesses of sregs.i . This wart of the code could be
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fixed by making fregs part of sregs, and including pc too - to avoid
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alignment repercussions - but this would cause very onerous union /
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structure nesting, which would only be managable with anonymous
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unions and structs. */
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union
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{
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struct
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{
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int mach;
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int macl;
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int pr;
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int dummy3, dummy4;
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int fpul; /* A1 for sh-dsp - but only for movs etc. */
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int fpscr; /* dsr for sh-dsp */
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} named;
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int i[7];
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} sregs;
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which are located in fregs. Probably should include pc too - to avoid
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alignment repercussions. */
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union {
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struct {
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int mach;
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int macl;
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int pr;
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int dummy3, dummy4;
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int fpul; /* A1 for sh-dsp - but only for movs etc. */
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int fpscr; /* dsr for sh-dsp */
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/* sh3e / sh-dsp */
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union fregs_u
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{
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float f[16];
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double d[8];
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int i[16];
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}
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fregs[2];
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/* sh3e / sh-dsp */
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union fregs_u {
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float f[16];
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double d[8];
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int i[16];
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} fregs[2];
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};
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int sregs[39];
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};
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/* Control registers; on the SH4, ldc / stc is privileged, except when
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accessing gbr. */
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@ -88,9 +80,9 @@ typedef union
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int tbr;
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int ibcr; /* sh2a bank control register */
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int ibnr; /* sh2a bank number register */
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} named;
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int i[16];
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} cregs;
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};
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int cregs[16];
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};
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unsigned char *insn_end;
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