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RISC-V: make .insn actually work for 64-bit insns

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Presently in this case, due to an undefined behavior shift, at least
with x86 cross builds I'm observing:

Error: value conflicts with instruction length `8,0x0000003f'

Eliminate the UB and extend the respective testcase.
This commit is contained in:
Jan Beulich 2022-03-04 13:37:59 +01:00
parent 6a778a2100
commit 7919e5667c
3 changed files with 9 additions and 1 deletions
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2
gas/config/tc-riscv.c
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@ -3248,7 +3248,7 @@ riscv_ip_hardcode (char *str,
insn->match = values[num - 1];
create_insn (ip, insn);
unsigned int bytes = riscv_insn_length (insn->match);
if (values[num - 1] >> (8 * bytes) != 0
if ((bytes < sizeof(values[0]) && values[num - 1] >> (8 * bytes) != 0)
|| (num == 2 && values[0] != bytes))
return _("value conflicts with instruction length");

4
gas/testsuite/gas/riscv/insn.d
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@ -71,5 +71,9 @@ Disassembly of section .text:
[^:]+:[ ]+00c58533[ ]+add[ ]+a0,a1,a2
[^:]+:[ ]+0001[ ]+nop
[^:]+:[ ]+00000013[ ]+nop
[^:]+:[ ]+001f 0000 0000[ ].*
[^:]+:[ ]+0000003f 00000000[ ].*
[^:]+:[ ]+0001[ ]+nop
[^:]+:[ ]+00000013[ ]+nop
[^:]+:[ ]+001f 0000 0000[ ].*
[^:]+:[ ]+0000003f 00000000[ ].*

4
gas/testsuite/gas/riscv/insn.s
View File

@ -56,5 +56,9 @@ target:
.insn 0x0001
.insn 0x00000013
.insn 0x0000001f
.insn 0x0000003f
.insn 0x2, 0x0001
.insn 0x4, 0x00000013
.insn 6, 0x0000001f
.insn 8, 0x0000003f