From 7b08cc32165912395838e7bb995d880f623fe636 Mon Sep 17 00:00:00 2001
From: Victor Do Nascimento <victor.donascimento@arm.com>
Date: Wed, 15 Nov 2023 12:21:33 +0000
Subject: [PATCH] aarch64: Add +d128 architectural feature support
Indicating the presence of the Armv9.4-a features concerning 128-bit
Page Table Descriptors, 128-bit System Registers and Instructions,
the "+d128" architectural extension flag is added to the list of
possible -march options in Binutils, together with the necessary macro
for encoding d128 instructions.
---
gas/config/tc-aarch64.c | 2 ++
gas/doc/c-aarch64.texi | 2 ++
include/opcode/aarch64.h | 3 +++
opcodes/aarch64-tbl.h | 5 +++++
4 files changed, 12 insertions(+)
diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
index cf586267ee8..b28c05fbd82 100644
--- a/gas/config/tc-aarch64.c
+++ b/gas/config/tc-aarch64.c
@@ -10286,6 +10286,8 @@ static const struct aarch64_option_cpu_value_table aarch64_features[] = {
{"the", AARCH64_FEATURE (THE), AARCH64_NO_FEATURES},
{"rasv2", AARCH64_FEATURE (RASv2), AARCH64_FEATURE (RAS)},
{"ite", AARCH64_FEATURE (ITE), AARCH64_NO_FEATURES},
+ {"d128", AARCH64_FEATURE (D128),
+ AARCH64_FEATURE (LSE128)},
{NULL, AARCH64_NO_FEATURES, AARCH64_NO_FEATURES},
};
diff --git a/gas/doc/c-aarch64.texi b/gas/doc/c-aarch64.texi
index 97233b5c0e5..ccf18ee2661 100644
--- a/gas/doc/c-aarch64.texi
+++ b/gas/doc/c-aarch64.texi
@@ -274,6 +274,8 @@ automatically cause those extensions to be disabled.
@tab Enable Prediction instructions.
@item @code{ite} @tab N/A @tab no
@tab Enable TRCIT instruction.
+@item @code{d128} @tab Armv9.4-A @tab No
+ @tab Enable the 128-bit Page Descriptor Extension. This implies @code{lse128}.
@end multitable
@node AArch64 Syntax
diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
index cc172afc879..7b7b15ae1a2 100644
--- a/include/opcode/aarch64.h
+++ b/include/opcode/aarch64.h
@@ -201,6 +201,9 @@ enum aarch64_feature_bit {
AARCH64_FEATURE_PREDRES2,
/* Instrumentation Extension. */
AARCH64_FEATURE_ITE,
+ /* 128-bit page table descriptor, system registers
+ and isntructions. */
+ AARCH64_FEATURE_D128,
AARCH64_NUM_FEATURES
};
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
index 5058cc9c492..27550fd1c8b 100644
--- a/opcodes/aarch64-tbl.h
+++ b/opcodes/aarch64-tbl.h
@@ -2582,6 +2582,8 @@ static const aarch64_feature_set aarch64_feature_gcs =
AARCH64_FEATURE (GCS);
static const aarch64_feature_set aarch64_feature_ite =
AARCH64_FEATURE (ITE);
+static const aarch64_feature_set aarch64_feature_d128 =
+ AARCH64_FEATURE (D128);
#define CORE &aarch64_feature_v8
#define FP &aarch64_feature_fp
@@ -2645,6 +2647,7 @@ static const aarch64_feature_set aarch64_feature_ite =
#define CHK &aarch64_feature_chk
#define GCS &aarch64_feature_gcs
#define ITE &aarch64_feature_ite
+#define D128 &aarch64_feature_d128
#define CORE_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS) \
{ NAME, OPCODE, MASK, CLASS, OP, CORE, OPS, QUALS, FLAGS, 0, 0, NULL }
@@ -2798,6 +2801,8 @@ static const aarch64_feature_set aarch64_feature_ite =
{ NAME, OPCODE, MASK, ic_system, 0, CHK, OPS, QUALS, FLAGS, 0, 0, NULL }
#define GCS_INSN(NAME, OPCODE, MASK, OPS, QUALS, FLAGS) \
{ NAME, OPCODE, MASK, gcs, 0, GCS, OPS, QUALS, FLAGS, 0, 0, NULL }
+#define D128_INSN(NAME,OPCODE,MASK,OPS,QUALS,FLAGS) \
+ { NAME, OPCODE, MASK, ic_system, 0, D128, OPS, QUALS, FLAGS, 0, 0, NULL }
#define MOPS_CPY_OP1_OP2_PME_INSN(NAME, OPCODE, MASK, FLAGS, CONSTRAINTS) \
MOPS_INSN (NAME, OPCODE, MASK, 0, \