aarch64: Move w12-w15 range check to libopcodes
In SME, the vector select register had to be in the range w12-w15, so it made sense to enforce that during parsing. However, SME2 adds instructions for which the range is w8-w11 instead. This patch therefore moves the range check from the parsing stage to the constraint-checking stage. Also, the previous error used a capitalised range W12-W15, whereas other register range errors used lowercase ranges like p0-p7. A quick internal poll showed a preference for the lowercase form, so the patch uses that. The patch uses "selection register" rather than "vector select register" so that the terminology extends more naturally to PSEL.
This commit is contained in:
Richard Sandiford
parent
61dac77e93
commit
7da28504bf
@ -4372,11 +4372,10 @@ parse_sme_immediate (char **str, int64_t *imm)
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return true;
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}
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/* Parse index with vector select register and immediate:
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/* Parse index with selection register and immediate offset:
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[<Wv>, <imm>]
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[<Wv>, #<imm>]
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where <Wv> is in W12-W15 range and # is optional for immediate.
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Return true on success, populating OPND with the parsed index. */
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@ -4391,12 +4390,11 @@ parse_sme_za_index (char **str, struct aarch64_indexed_za *opnd)
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return false;
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}
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/* Vector select register W12-W15 encoded in the 2-bit Rv field. */
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/* The selection register, encoded in the 2-bit Rv field. */
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reg = parse_reg (str);
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if (reg == NULL || reg->type != REG_TYPE_R_32
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|| reg->number < 12 || reg->number > 15)
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if (reg == NULL || reg->type != REG_TYPE_R_32)
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{
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set_syntax_error (_("expected vector select register W12-W15"));
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set_syntax_error (_("expected a 32-bit selection register"));
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return false;
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}
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opnd->index.regno = reg->number;
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@ -4424,9 +4422,8 @@ parse_sme_za_index (char **str, struct aarch64_indexed_za *opnd)
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/* Parse a register of type REG_TYPE that might have an element type
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qualifier and that is indexed by two values: a 32-bit register,
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followed by an immediate. The 32-bit register must be W12-W15.
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The range of the immediate varies by opcode and is checked in
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libopcodes.
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followed by an immediate. The ranges of the register and the
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immediate vary by opcode and are checked in libopcodes.
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Return true on success, populating OPND with information about
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the operand and setting QUALIFIER to the register qualifier.
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@ -11,12 +11,12 @@
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[^:]*:[0-9]+: Error: immediate offset must be 0 at operand 3 -- `mova z31\.q,p7/m,za15v\.q\[w15,#1\]'
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[^:]*:[0-9]+: Error: expected ',' at operand 3 -- `mova z31\.q,p7/m,za15v\.q\[w15\]'
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[^:]*:[0-9]+: Error: expected '\[' at operand 3 -- `mova z0\.b,p0/m,za0v.b'
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[^:]*:[0-9]+: Error: expected vector select register W12-W15 at operand 3 -- `mova z31\.b,p7/m,za0v\.b\[15,w15\]'
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[^:]*:[0-9]+: Error: expected a 32-bit selection register at operand 3 -- `mova z31\.b,p7/m,za0v\.b\[15,w15\]'
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[^:]*:[0-9]+: Error: expected ',' at operand 3 -- `mova z0\.h,p0/m,za0v\.h\[w12\. 0\]'
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[^:]*:[0-9]+: Error: expected vector select register W12-W15 at operand 3 -- `mova z0\.s,p0/m,za0v\.s\[x12,0]'
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[^:]*:[0-9]+: Error: expected vector select register W12-W15 at operand 3 -- `mova z0\.d,p0/m,za0v\.d\[w21,0\]'
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[^:]*:[0-9]+: Error: expected vector select register W12-W15 at operand 3 -- `mova z0\.q,p0/m,za0v\.q\[s12\]'
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[^:]*:[0-9]+: Error: expected vector select register W12-W15 at operand 3 -- `mova z0\.q,p0/m,za0v\.q\[d12\]'
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[^:]*:[0-9]+: Error: expected a 32-bit selection register at operand 3 -- `mova z0\.s,p0/m,za0v\.s\[x12,0]'
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[^:]*:[0-9]+: Error: expected a selection register in the range w12-w15 at operand 3 -- `mova z0\.d,p0/m,za0v\.d\[w21,0\]'
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[^:]*:[0-9]+: Error: expected a 32-bit selection register at operand 3 -- `mova z0\.q,p0/m,za0v\.q\[s12\]'
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[^:]*:[0-9]+: Error: expected a 32-bit selection register at operand 3 -- `mova z0\.q,p0/m,za0v\.q\[d12\]'
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[^:]*:[0-9]+: Error: index offset immediate expected at operand 3 -- `mova z0.q,p0/m,za0v\.q\[w12,\]'
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[^:]*:[0-9]+: Error: expected ',' at operand 3 -- `mova z0\.q,p0/m,za0v\.q\[w12\.\]'
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[^:]*:[0-9]+: Error: index offset immediate expected at operand 3 -- `mova z0\.q,p0/m,za0v\.q\[w12,abc\]'
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@ -1,6 +1,6 @@
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[^:]*: Assembler messages:
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[^:]*:[0-9]+: Error: expected vector select register W12-W15 at operand 1 -- `ld1b {za0h.b\[w11,0\]},p0/z,\[x0\]'
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[^:]*:[0-9]+: Error: expected vector select register W12-W15 at operand 1 -- `ld1h {za0h.h\[w16,0\]},p0/z,\[x0\]'
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[^:]*:[0-9]+: Error: expected a selection register in the range w12-w15 at operand 1 -- `ld1b {za0h.b\[w11,0\]},p0/z,\[x0\]'
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[^:]*:[0-9]+: Error: expected a selection register in the range w12-w15 at operand 1 -- `ld1h {za0h.h\[w16,0\]},p0/z,\[x0\]'
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[^:]*:[0-9]+: Error: invalid addressing mode at operand 3 -- `ld1h {za0v.h\[w12,0\]},p0/z,\[x0,x0,lsl#3\]'
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[^:]*:[0-9]+: Error: '\]' expected at operand 3 -- `ld1w {za3v.s\[w15,3\]},p7/z,\[sp,lsl#2\]'
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[^:]*:[0-9]+: Error: invalid addressing mode at operand 3 -- `ld1d {za0h.d\[w12,0\]},p0/z,\[sp,x0,lsl#12\]'
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@ -1,6 +1,6 @@
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[^:]*: Assembler messages:
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[^:]*:[0-9]+: Error: expected vector select register W12-W15 at operand 1 -- `st1b {za0h.b\[w11,0\]},p0,\[x0\]'
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[^:]*:[0-9]+: Error: expected vector select register W12-W15 at operand 1 -- `st1h {za0h.h\[w16,0\]},p0,\[x0\]'
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[^:]*:[0-9]+: Error: expected a selection register in the range w12-w15 at operand 1 -- `st1b {za0h.b\[w11,0\]},p0,\[x0\]'
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[^:]*:[0-9]+: Error: expected a selection register in the range w12-w15 at operand 1 -- `st1h {za0h.h\[w16,0\]},p0,\[x0\]'
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[^:]*:[0-9]+: Error: invalid addressing mode at operand 3 -- `st1h {za0v.h\[w12,0\]},p0,\[x0,x0,lsl#3\]'
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[^:]*:[0-9]+: Error: '\]' expected at operand 3 -- `st1w {za3v.s\[w15,3\]},p7,\[sp,lsl#2\]'
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[^:]*:[0-9]+: Error: invalid addressing mode at operand 3 -- `st1d {za0h.d\[w12,0\]},p0,\[sp,x0,lsl#12\]'
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@ -1,22 +1,22 @@
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[^:]*: Assembler messages:
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[^:]*:[0-9]+: Error: expected vector select register W12-W15 at operand 1 -- `ldr za\[w11,0\],\[x0\]'
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[^:]*:[0-9]+: Error: expected a selection register in the range w12-w15 at operand 1 -- `ldr za\[w11,0\],\[x0\]'
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[^:]*:[0-9]+: Error: invalid addressing mode at operand 2 -- `ldr za\[w12,1\],\[sp,x0\]'
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[^:]*:[0-9]+: Error: operand 2 must have the same immediate value as operand 1 -- `ldr za\[w12,0\],\[sp,#1,mul vl\]'
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[^:]*:[0-9]+: Error: operand 2 must have the same immediate value as operand 1 -- `ldr za\[w13,9\],\[x17,#19,mul vl\]'
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[^:]*:[0-9]+: Error: immediate offset out of range 0 to 15 at operand 1 -- `ldr za\[w13,21\],\[x17,#21,mul vl\]'
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[^:]*:[0-9]+: Error: operand 2 must have the same immediate value as operand 1 -- `ldr za\[w15,32\],\[x17,#15,mul vl\]'
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[^:]*:[0-9]+: Error: expected vector select register W12-W15 at operand 1 -- `ldr za\[w16,15\],\[sp,#15,mul vl\]'
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[^:]*:[0-9]+: Error: expected a selection register in the range w12-w15 at operand 1 -- `ldr za\[w16,15\],\[sp,#15,mul vl\]'
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[^:]*:[0-9]+: Error: only 'MUL VL' is permitted at operand 2 -- `ldr za\[w12,0\],\[x0,#0,mul#1\]'
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[^:]*:[0-9]+: Error: only 'MUL VL' is permitted at operand 2 -- `ldr za\[w13,0\],\[sp,#0,mul#2\]'
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[^:]*:[0-9]+: Error: only 'MUL VL' is permitted at operand 2 -- `ldr za\[w14,9\],\[x17,#9,mul#3\]'
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[^:]*:[0-9]+: Error: only 'MUL VL' is permitted at operand 2 -- `ldr za\[w15,15\],\[sp,#15,mul#4\]'
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[^:]*:[0-9]+: Error: expected vector select register W12-W15 at operand 1 -- `str za\[w11,0\],\[x0\]'
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[^:]*:[0-9]+: Error: expected a selection register in the range w12-w15 at operand 1 -- `str za\[w11,0\],\[x0\]'
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[^:]*:[0-9]+: Error: invalid addressing mode at operand 2 -- `str za\[w12,1\],\[sp,x0\]'
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[^:]*:[0-9]+: Error: operand 2 must have the same immediate value as operand 1 -- `str za\[w12,0\],\[sp,#1,mul vl\]'
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[^:]*:[0-9]+: Error: operand 2 must have the same immediate value as operand 1 -- `str za\[w13,9\],\[x17,#19,mul vl\]'
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[^:]*:[0-9]+: Error: immediate offset out of range 0 to 15 at operand 1 -- `str za\[w13,21\],\[x17,#21,mul vl\]'
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[^:]*:[0-9]+: Error: operand 2 must have the same immediate value as operand 1 -- `str za\[w15,32\],\[x17,#15,mul vl\]'
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[^:]*:[0-9]+: Error: expected vector select register W12-W15 at operand 1 -- `str za\[w16,15\],\[sp,#15,mul vl\]'
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[^:]*:[0-9]+: Error: expected a selection register in the range w12-w15 at operand 1 -- `str za\[w16,15\],\[sp,#15,mul vl\]'
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[^:]*:[0-9]+: Error: only 'MUL VL' is permitted at operand 2 -- `str za\[w12,0\],\[x0,#0,mul#1\]'
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[^:]*:[0-9]+: Error: only 'MUL VL' is permitted at operand 2 -- `str za\[w13,0\],\[sp,#0,mul#2\]'
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[^:]*:[0-9]+: Error: only 'MUL VL' is permitted at operand 2 -- `str za\[w14,9\],\[x17,#9,mul#3\]'
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@ -15,10 +15,14 @@
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[^:]*:[0-9]+: Info: psel p1, p15, p3.h\[w15, 0\]
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[^:]*:[0-9]+: Info: psel p1, p15, p3.s\[w15, 0\]
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[^:]*:[0-9]+: Info: psel p1, p15, p3.d\[w15, 0\]
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[^:]*:[0-9]+: Error: expected vector select register W12-W15 at operand 3 -- `psel p1,p15,p3.b\[w11\]'
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[^:]*:[0-9]+: Error: expected vector select register W12-W15 at operand 3 -- `psel p8,p11,p15.h\[w16\]'
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[^:]*:[0-9]+: Error: expected vector select register W12-W15 at operand 3 -- `psel p2,p7,p15.s\[w3\]'
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[^:]*:[0-9]+: Error: expected vector select register W12-W15 at operand 3 -- `psel p13,p3,p1.d\[w17\]'
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[^:]*:[0-9]+: Error: expected ',' at operand 3 -- `psel p1,p15,p3.b\[w11\]'
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[^:]*:[0-9]+: Error: expected ',' at operand 3 -- `psel p8,p11,p15.h\[w16\]'
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[^:]*:[0-9]+: Error: expected ',' at operand 3 -- `psel p2,p7,p15.s\[w3\]'
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[^:]*:[0-9]+: Error: expected ',' at operand 3 -- `psel p13,p3,p1.d\[w17\]'
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[^:]*:[0-9]+: Error: expected a selection register in the range w12-w15 at operand 3 -- `psel p1,p15,p3.b\[w11,#0\]'
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[^:]*:[0-9]+: Error: expected a selection register in the range w12-w15 at operand 3 -- `psel p8,p11,p15.h\[w16,#0\]'
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[^:]*:[0-9]+: Error: expected a selection register in the range w12-w15 at operand 3 -- `psel p2,p7,p15.s\[w3,#0\]'
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[^:]*:[0-9]+: Error: expected a selection register in the range w12-w15 at operand 3 -- `psel p13,p3,p1.d\[w17,#0\]'
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[^:]*:[0-9]+: Error: immediate offset out of range 0 to 15 at operand 3 -- `psel p5,p12,p9.b\[w15,#16\]'
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[^:]*:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 3 -- `psel p1,p8,p6.h\[w14,#8\]'
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[^:]*:[0-9]+: Error: immediate offset out of range 0 to 3 at operand 3 -- `psel p8,p4,p15.s\[w13,#4\]'
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@ -8,6 +8,10 @@ psel p1, p15, p3.b[w11]
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psel p8, p11, p15.h[w16]
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psel p2, p7, p15.s[w3]
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psel p13, p3, p1.d[w17]
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psel p1, p15, p3.b[w11, #0]
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psel p8, p11, p15.h[w16, #0]
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psel p2, p7, p15.s[w3, #0]
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psel p13, p3, p1.d[w17, #0]
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psel p5, p12, p9.b[w15, #16]
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psel p1, p8, p6.h[w14, #8]
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psel p8, p4, p15.s[w13, #4]
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@ -1438,14 +1438,28 @@ set_other_error (aarch64_operand_error *mismatch_detail, int idx,
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set_error (mismatch_detail, AARCH64_OPDE_OTHER_ERROR, idx, error);
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}
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/* Check that indexed ZA operand OPND has a vector select offset
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in the range [0, MAX_VALUE]. */
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/* Check that indexed ZA operand OPND has:
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- a selection register in the range [MIN_WREG, MIN_WREG + 3]
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- an immediate offset in the range [0, MAX_VALUE]. */
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static bool
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check_za_access (const aarch64_opnd_info *opnd,
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aarch64_operand_error *mismatch_detail, int idx,
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int max_value)
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int min_wreg, int max_value)
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{
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if (!value_in_range_p (opnd->indexed_za.index.regno, min_wreg, min_wreg + 3))
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{
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if (min_wreg == 12)
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set_other_error (mismatch_detail, idx,
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_("expected a selection register in the"
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" range w12-w15"));
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else
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abort ();
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return false;
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}
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if (!value_in_range_p (opnd->indexed_za.index.imm, 0, max_value))
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{
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set_offset_out_of_range_error (mismatch_detail, idx, 0, max_value);
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@ -1593,7 +1607,7 @@ operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx,
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case AARCH64_OPND_SME_PnT_Wm_imm:
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size = aarch64_get_qualifier_esize (opnd->qualifier);
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max_value = 16 / size - 1;
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if (!check_za_access (opnd, mismatch_detail, idx, max_value))
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if (!check_za_access (opnd, mismatch_detail, idx, 12, max_value))
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return 0;
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break;
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@ -1610,12 +1624,12 @@ operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx,
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case AARCH64_OPND_SME_ZA_HV_idx_ldstr:
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size = aarch64_get_qualifier_esize (opnd->qualifier);
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max_value = 16 / size - 1;
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if (!check_za_access (opnd, mismatch_detail, idx, max_value))
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if (!check_za_access (opnd, mismatch_detail, idx, 12, max_value))
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return 0;
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break;
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case AARCH64_OPND_SME_ZA_array:
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if (!check_za_access (opnd, mismatch_detail, idx, 15))
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if (!check_za_access (opnd, mismatch_detail, idx, 12, 15))
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return 0;
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break;
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