aarch64: Add the SME2 FMLA and FMLS instructions
This commit is contained in:
Richard Sandiford
parent
27f6a0bd65
commit
80752eb098
@ -6727,6 +6727,8 @@ parse_operands (char *str, const aarch64_opcode *opcode)
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case AARCH64_OPND_SVE_Zm4_11_INDEX:
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case AARCH64_OPND_SVE_Zm4_INDEX:
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case AARCH64_OPND_SVE_Zn_INDEX:
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case AARCH64_OPND_SME_Zm_INDEX1:
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case AARCH64_OPND_SME_Zm_INDEX2:
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case AARCH64_OPND_SME_Zn_INDEX1_16:
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case AARCH64_OPND_SME_Zn_INDEX2_15:
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case AARCH64_OPND_SME_Zn_INDEX2_16:
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3
gas/testsuite/gas/aarch64/sme2-11-invalid.d
Normal file
3
gas/testsuite/gas/aarch64/sme2-11-invalid.d
Normal file
@ -0,0 +1,3 @@
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#as: -march=armv8-a
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#source: sme2-11-invalid.s
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#error_output: sme2-11-invalid.l
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101
gas/testsuite/gas/aarch64/sme2-11-invalid.l
Normal file
101
gas/testsuite/gas/aarch64/sme2-11-invalid.l
Normal file
@ -0,0 +1,101 @@
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[^ :]+: Assembler messages:
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[^ :]+:[0-9]+: Error: expected a register at operand 1 -- `fmla 0,{z0\.s-z1\.s},z0\.s\[0\]'
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[^ :]+:[0-9]+: Error: expected '{' at operand 2 -- `fmla za\.s\[w8,0\],0,z0\.s\[0\]'
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[^ :]+:[0-9]+: Error: expected a register or register list at operand 3 -- `fmla za\.s\[w8,0\],{z0\.s-z1\.s},0'
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[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmla za\.s\[w7,0\],{z0\.s-z1\.s},z0\.s\[0\]'
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[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmla za\.s\[w12,0\],{z0\.s-z1\.s},z0\.s\[0\]'
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[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `fmla za\.s\[w8,-1\],{z0\.s-z1\.s},z0\.s\[0\]'
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[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `fmla za\.s\[w8,8\],{z0\.s-z1\.s},z0\.s\[0\]'
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[^ :]+:[0-9]+: Error: expected a list of 4 registers at operand 2 -- `fmla za\.s\[w8,0,vgx4\],{z0\.s-z1\.s},z0\.s\[0\]'
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[^ :]+:[0-9]+: Error: expected a list of 2 or 4 registers at operand 2 -- `fmla za\.s\[w8,0\],{z0\.s-z2\.s},z0\.s\[0\]'
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[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `fmla za\.s\[w8,0\],{z1\.s-z2\.s},z0\.s\[0\]'
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[^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `fmla za\.s\[w8,0\],{z0\.s-z1\.s},z16\.s\[0\]'
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[^ :]+:[0-9]+: Error: register element index out of range 0 to 3 at operand 3 -- `fmla za\.s\[w8,0\],{z0\.s-z1\.s},z0\.s\[-1\]'
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[^ :]+:[0-9]+: Error: register element index out of range 0 to 3 at operand 3 -- `fmla za\.s\[w8,0\],{z0\.s-z1\.s},z0\.s\[4\]'
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[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmla za\.s\[w7,0\],{z0\.s-z3\.s},z0\.s\[0\]'
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[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmla za\.s\[w12,0\],{z0\.s-z3\.s},z0\.s\[0\]'
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[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `fmla za\.s\[w8,-1\],{z0\.s-z3\.s},z0\.s\[0\]'
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[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `fmla za\.s\[w8,8\],{z0\.s-z3\.s},z0\.s\[0\]'
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[^ :]+:[0-9]+: Error: expected a list of 2 registers at operand 2 -- `fmla za\.s\[w8,0,vgx2\],{z0\.s-z3\.s},z0\.s\[0\]'
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[^ :]+:[0-9]+: Error: too many registers in vector register list at operand 2 -- `fmla za\.s\[w8,0\],{z0\.s-z4\.s},z0\.s\[0\]'
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[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `fmla za\.s\[w8,0\],{z1\.s-z4\.s},z0\.s\[0\]'
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[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `fmla za\.s\[w8,0\],{z2\.s-z5\.s},z0\.s\[0\]'
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[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `fmla za\.s\[w8,0\],{z3\.s-z6\.s},z0\.s\[0\]'
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[^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `fmla za\.s\[w8,0\],{z0\.s-z3\.s},z16\.s\[0\]'
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[^ :]+:[0-9]+: Error: register element index out of range 0 to 3 at operand 3 -- `fmla za\.s\[w8,0\],{z0\.s-z3\.s},z0\.s\[-1\]'
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[^ :]+:[0-9]+: Error: register element index out of range 0 to 3 at operand 3 -- `fmla za\.s\[w8,0\],{z0\.s-z3\.s},z0\.s\[4\]'
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[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmla za\.s\[w0,0\],{z0\.s-z1\.s},z0\.s'
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[^ :]+:[0-9]+: Error: expected a 32-bit selection register at operand 1 -- `fmla za\.s\[w31,0\],{z0\.s-z1\.s},z0\.s'
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[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `fmla za\.s\[w8,1<<63\],{z0\.s-z1\.s},z0\.s'
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[^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `fmla za\.s\[w8,0\],{z0\.s-z1\.s},z31\.s'
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[^ :]+:[0-9]+: Error: the last offset is equal to the first offset at operand 1 -- `fmla za\.s\[w8,0:0\],{z0\.s-z1\.s},z0\.s'
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[^ :]+:[0-9]+: Error: the last offset is less than the first offset at operand 1 -- `fmla za\.s\[w8,0:-1\],{z0\.s-z1\.s},z0\.s'
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[^ :]+:[0-9]+: Error: expected a single offset rather than a range at operand 1 -- `fmla za\.s\[w8,0:1\],{z0\.s-z1\.s},z0\.s'
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[^ :]+:[0-9]+: Error: expected a single offset rather than a range at operand 1 -- `fmla za\.s\[w8,0:100\],{z0\.s-z1\.s},z0\.s'
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[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmla za\.s\[w7,0\],{z0\.s-z1\.s},z0\.s'
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[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmla za\.s\[w12,0\],{z0\.s-z1\.s},z0\.s'
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[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `fmla za\.s\[w8,-1\],{z0\.s-z1\.s},z0\.s'
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[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `fmla za\.s\[w8,8\],{z0\.s-z1\.s},z0\.s'
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[^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `fmla za\.s\[w8,0\],{z0\.s-z1\.s},z16\.s'
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[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmla za\.s\[w7,0\],{z0\.s-z3\.s},z0\.s'
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[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmla za\.s\[w12,0\],{z0\.s-z3\.s},z0\.s'
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[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `fmla za\.s\[w8,-1\],{z0\.s-z3\.s},z0\.s'
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[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `fmla za\.s\[w8,8\],{z0\.s-z3\.s},z0\.s'
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[^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `fmla za\.s\[w8,0\],{z0\.s-z3\.s},z16\.s'
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[^ :]+:[0-9]+: Error: expected a list of 2 or 4 registers at operand 2 -- `fmla za\.s\[w8,0\],{z0\.s-z2\.s},z0\.s'
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[^ :]+:[0-9]+: Error: too many registers in vector register list at operand 2 -- `fmla za\.s\[w8,0\],{z0\.s-z4\.s},z0\.s'
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[^ :]+:[0-9]+: Error: expected a list of 2 or 4 registers at operand 2 -- `fmla za\.s\[w8,0\],{z0\.s,z1\.s,z2\.s},z0\.s'
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[^ :]+:[0-9]+: Error: invalid register list at operand 2 -- `fmla za\.s\[w8,0\],{z0\.s,z1\.s,z5\.s},z0\.s'
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[^ :]+:[0-9]+: Error: expected a list of 4 registers at operand 2 -- `fmla za\.s\[w8,0,vgx4\],{z0\.s-z1\.s},z0\.s'
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[^ :]+:[0-9]+: Error: expected a list of 2 registers at operand 2 -- `fmla za\.s\[w8,0,vgx2\],{z0\.s-z3\.s},z0\.s'
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[^ :]+:[0-9]+: Error: operand mismatch -- `fmla za\[w8,0\],{z0\.s-z1\.s},z0\.s'
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[^ :]+:[0-9]+: Info: did you mean this\?
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[^ :]+:[0-9]+: Info: fmla za\.s\[w8, 0\], {z0\.s-z1\.s}, z0\.s
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[^ :]+:[0-9]+: Info: other valid variant\(s\):
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[^ :]+:[0-9]+: Info: fmla za\.d\[w8, 0\], {z0\.d-z1\.d}, z0\.d
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[^ :]+:[0-9]+: Error: missing type suffix at operand 2 -- `fmla za\.s\[w8,0\],{z0-z1},z0\.s'
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[^ :]+:[0-9]+: Error: operand mismatch -- `fmla za\.s\[w8,0\],{z0\.s-z1\.s},z0'
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[^ :]+:[0-9]+: Info: did you mean this\?
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[^ :]+:[0-9]+: Info: fmla za\.s\[w8, 0\], {z0\.s-z1\.s}, z0\.s
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[^ :]+:[0-9]+: Info: other valid variant\(s\):
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[^ :]+:[0-9]+: Info: fmla za\.d\[w8, 0\], {z0\.d-z1\.d}, z0\.d
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[^ :]+:[0-9]+: Error: operand mismatch -- `fmla za\[w8,0\],{z0\.s-z1\.s},z0'
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[^ :]+:[0-9]+: Info: did you mean this\?
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[^ :]+:[0-9]+: Info: fmla za\.s\[w8, 0\], {z0\.s-z1\.s}, z0\.s
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[^ :]+:[0-9]+: Info: other valid variant\(s\):
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[^ :]+:[0-9]+: Info: fmla za\.d\[w8, 0\], {z0\.d-z1\.d}, z0\.d
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[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmla za\.s\[w7,0\],{z0\.s-z1\.s},{z0\.s-z1\.s}'
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[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmla za\.s\[w12,0\],{z0\.s-z1\.s},{z0\.s-z1\.s}'
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[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `fmla za\.s\[w8,-1\],{z0\.s-z1\.s},{z0\.s-z1\.s}'
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[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `fmla za\.s\[w8,8\],{z0\.s-z1\.s},{z0\.s-z1\.s}'
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[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `fmla za\.s\[w8,0\],{z1\.s-z2\.s},{z0\.s-z1\.s}'
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[^ :]+:[0-9]+: Error: start register out of range at operand 3 -- `fmla za\.s\[w8,0\],{z0\.s-z1\.s},{z15\.s-z16\.s}'
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[^ :]+:[0-9]+: Error: start register out of range at operand 3 -- `fmla za\.s\[w8,0\],{z0\.s-z1\.s},{z31\.s,z0\.s}'
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[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmla za\.s\[w7,0\],{z0\.s-z3\.s},{z0\.s-z3\.s}'
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[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmla za\.s\[w12,0\],{z0\.s-z3\.s},{z0\.s-z3\.s}'
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[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `fmla za\.s\[w8,-1\],{z0\.s-z3\.s},{z0\.s-z3\.s}'
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[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `fmla za\.s\[w8,8\],{z0\.s-z3\.s},{z0\.s-z3\.s}'
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[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `fmla za\.s\[w8,0\],{z1\.s-z4\.s},{z0\.s-z3\.s}'
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[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `fmla za\.s\[w8,0\],{z2\.s-z5\.s},{z0\.s-z3\.s}'
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[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `fmla za\.s\[w8,0\],{z3\.s-z6\.s},{z0\.s-z3\.s}'
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[^ :]+:[0-9]+: Error: start register out of range at operand 3 -- `fmla za\.s\[w8,0\],{z0\.s-z3\.s},{z15\.s-z18\.s}'
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[^ :]+:[0-9]+: Error: start register out of range at operand 3 -- `fmla za\.s\[w8,0\],{z0\.s-z3\.s},{z29\.s,z30\.s,z31\.s,z0\.s}'
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[^ :]+:[0-9]+: Error: expected a list of 2 or 4 registers at operand 2 -- `fmla za\.s\[w8,0\],{z0\.s-z2\.s},{z0\.s-z1\.s}'
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[^ :]+:[0-9]+: Error: expected a list of 4 registers at operand 3 -- `fmla za\.s\[w8,0\],{z0\.s-z3\.s},{z0\.s-z1\.s}'
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[^ :]+:[0-9]+: Error: expected a list of 2 registers at operand 3 -- `fmla za\.s\[w8,0\],{z0\.s-z1\.s},{z0\.s-z2\.s}'
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[^ :]+:[0-9]+: Error: expected a list of 2 registers at operand 3 -- `fmla za\.s\[w8,0\],{z0\.s-z1\.s},{z0\.s-z3\.s}'
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[^ :]+:[0-9]+: Error: too many registers in vector register list at operand 3 -- `fmla za\.s\[w8,0\],{z0\.s-z1\.s},{z0\.s-z4\.s}'
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[^ :]+:[0-9]+: Error: expected a list of 4 registers at operand 2 -- `fmla za\.s\[w8,0,vgx4\],{z0\.s-z1\.s},{z0\.s-z3\.s}'
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[^ :]+:[0-9]+: Error: expected a list of 4 registers at operand 3 -- `fmla za\.s\[w8,0,vgx4\],{z0\.s-z3\.s},{z0\.s-z1\.s}'
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[^ :]+:[0-9]+: Error: expected a list of 2 registers at operand 3 -- `fmla za\.s\[w8,0,vgx2\],{z0\.s-z1\.s},{z0\.s-z3\.s}'
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[^ :]+:[0-9]+: Error: expected a list of 2 registers at operand 2 -- `fmla za\.s\[w8,0,vgx2\],{z0\.s-z3\.s},{z0\.s-z1\.s}'
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[^ :]+:[0-9]+: Error: operand mismatch -- `fmla za\[w8,0\],{z0\.s-z1\.s},{z0\.s-z1\.s}'
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[^ :]+:[0-9]+: Info: did you mean this\?
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[^ :]+:[0-9]+: Info: fmla za\.s\[w8, 0\], {z0\.s-z1\.s}, {z0\.s-z1\.s}
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[^ :]+:[0-9]+: Info: other valid variant\(s\):
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[^ :]+:[0-9]+: Info: fmla za\.d\[w8, 0\], {z0\.d-z1\.d}, {z0\.d-z1\.d}
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[^ :]+:[0-9]+: Error: operand mismatch -- `fmla za\[w8,0\],{z0\.s-z3\.s},{z0\.s-z3\.s}'
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[^ :]+:[0-9]+: Info: did you mean this\?
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[^ :]+:[0-9]+: Info: fmla za\.s\[w8, 0\], {z0\.s-z3\.s}, {z0\.s-z3\.s}
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[^ :]+:[0-9]+: Info: other valid variant\(s\):
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[^ :]+:[0-9]+: Info: fmla za\.d\[w8, 0\], {z0\.d-z3\.d}, {z0\.d-z3\.d}
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91
gas/testsuite/gas/aarch64/sme2-11-invalid.s
Normal file
91
gas/testsuite/gas/aarch64/sme2-11-invalid.s
Normal file
@ -0,0 +1,91 @@
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fmla 0, { z0.s - z1.s }, z0.s[0]
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fmla za.s[w8, 0], 0, z0.s[0]
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fmla za.s[w8, 0], { z0.s - z1.s }, 0
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fmla za.s[w7, 0], { z0.s - z1.s }, z0.s[0]
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fmla za.s[w12, 0], { z0.s - z1.s }, z0.s[0]
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fmla za.s[w8, -1], { z0.s - z1.s }, z0.s[0]
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fmla za.s[w8, 8], { z0.s - z1.s }, z0.s[0]
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fmla za.s[w8, 0, vgx4], { z0.s - z1.s }, z0.s[0]
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fmla za.s[w8, 0], { z0.s - z2.s }, z0.s[0]
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fmla za.s[w8, 0], { z1.s - z2.s }, z0.s[0]
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fmla za.s[w8, 0], { z0.s - z1.s }, z16.s[0]
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fmla za.s[w8, 0], { z0.s - z1.s }, z0.s[-1]
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fmla za.s[w8, 0], { z0.s - z1.s }, z0.s[4]
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fmla za.s[w7, 0], { z0.s - z3.s }, z0.s[0]
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fmla za.s[w12, 0], { z0.s - z3.s }, z0.s[0]
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fmla za.s[w8, -1], { z0.s - z3.s }, z0.s[0]
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fmla za.s[w8, 8], { z0.s - z3.s }, z0.s[0]
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fmla za.s[w8, 0, vgx2], { z0.s - z3.s }, z0.s[0]
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fmla za.s[w8, 0], { z0.s - z4.s }, z0.s[0]
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fmla za.s[w8, 0], { z1.s - z4.s }, z0.s[0]
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fmla za.s[w8, 0], { z2.s - z5.s }, z0.s[0]
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fmla za.s[w8, 0], { z3.s - z6.s }, z0.s[0]
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fmla za.s[w8, 0], { z0.s - z3.s }, z16.s[0]
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fmla za.s[w8, 0], { z0.s - z3.s }, z0.s[-1]
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fmla za.s[w8, 0], { z0.s - z3.s }, z0.s[4]
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fmla za.s[w0, 0], { z0.s - z1.s }, z0.s
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fmla za.s[w31, 0], { z0.s - z1.s }, z0.s
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fmla za.s[w8, 1<<63], { z0.s - z1.s }, z0.s
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fmla za.s[w8, 0], { z0.s - z1.s }, z31.s
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fmla za.s[w8, 0:0], { z0.s - z1.s }, z0.s
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fmla za.s[w8, 0:-1], { z0.s - z1.s }, z0.s
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fmla za.s[w8, 0:1], { z0.s - z1.s }, z0.s
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fmla za.s[w8, 0:100], { z0.s - z1.s }, z0.s
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fmla za.s[w7, 0], { z0.s - z1.s }, z0.s
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fmla za.s[w12, 0], { z0.s - z1.s }, z0.s
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fmla za.s[w8, -1], { z0.s - z1.s }, z0.s
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fmla za.s[w8, 8], { z0.s - z1.s }, z0.s
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fmla za.s[w8, 0], { z0.s - z1.s }, z16.s
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fmla za.s[w7, 0], { z0.s - z3.s }, z0.s
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fmla za.s[w12, 0], { z0.s - z3.s }, z0.s
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fmla za.s[w8, -1], { z0.s - z3.s }, z0.s
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fmla za.s[w8, 8], { z0.s - z3.s }, z0.s
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fmla za.s[w8, 0], { z0.s - z3.s }, z16.s
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|
||||
fmla za.s[w8, 0], { z0.s - z2.s }, z0.s
|
||||
fmla za.s[w8, 0], { z0.s - z4.s }, z0.s
|
||||
fmla za.s[w8, 0], { z0.s, z1.s, z2.s }, z0.s
|
||||
fmla za.s[w8, 0], { z0.s, z1.s, z5.s }, z0.s
|
||||
|
||||
fmla za.s[w8, 0, vgx4], { z0.s - z1.s }, z0.s
|
||||
fmla za.s[w8, 0, vgx2], { z0.s - z3.s }, z0.s
|
||||
fmla za[w8, 0], { z0.s - z1.s }, z0.s
|
||||
fmla za.s[w8, 0], { z0 - z1 }, z0.s
|
||||
fmla za.s[w8, 0], { z0.s - z1.s }, z0
|
||||
fmla za[w8, 0], { z0.s - z1.s }, z0
|
||||
|
||||
fmla za.s[w7, 0], { z0.s - z1.s }, { z0.s - z1.s }
|
||||
fmla za.s[w12, 0], { z0.s - z1.s }, { z0.s - z1.s }
|
||||
fmla za.s[w8, -1], { z0.s - z1.s }, { z0.s - z1.s }
|
||||
fmla za.s[w8, 8], { z0.s - z1.s }, { z0.s - z1.s }
|
||||
fmla za.s[w8, 0], { z1.s - z2.s }, { z0.s - z1.s }
|
||||
fmla za.s[w8, 0], { z0.s - z1.s }, { z15.s - z16.s }
|
||||
fmla za.s[w8, 0], { z0.s - z1.s }, { z31.s, z0.s }
|
||||
|
||||
fmla za.s[w7, 0], { z0.s - z3.s }, { z0.s - z3.s }
|
||||
fmla za.s[w12, 0], { z0.s - z3.s }, { z0.s - z3.s }
|
||||
fmla za.s[w8, -1], { z0.s - z3.s }, { z0.s - z3.s }
|
||||
fmla za.s[w8, 8], { z0.s - z3.s }, { z0.s - z3.s }
|
||||
fmla za.s[w8, 0], { z1.s - z4.s }, { z0.s - z3.s }
|
||||
fmla za.s[w8, 0], { z2.s - z5.s }, { z0.s - z3.s }
|
||||
fmla za.s[w8, 0], { z3.s - z6.s }, { z0.s - z3.s }
|
||||
fmla za.s[w8, 0], { z0.s - z3.s }, { z15.s - z18.s }
|
||||
fmla za.s[w8, 0], { z0.s - z3.s }, { z29.s, z30.s, z31.s, z0.s }
|
||||
|
||||
fmla za.s[w8, 0], { z0.s - z2.s }, { z0.s - z1.s }
|
||||
fmla za.s[w8, 0], { z0.s - z3.s }, { z0.s - z1.s }
|
||||
fmla za.s[w8, 0], { z0.s - z1.s }, { z0.s - z2.s }
|
||||
fmla za.s[w8, 0], { z0.s - z1.s }, { z0.s - z3.s }
|
||||
fmla za.s[w8, 0], { z0.s - z1.s }, { z0.s - z4.s }
|
||||
|
||||
fmla za.s[w8, 0, vgx4], { z0.s - z1.s }, { z0.s - z3.s }
|
||||
fmla za.s[w8, 0, vgx4], { z0.s - z3.s }, { z0.s - z1.s }
|
||||
fmla za.s[w8, 0, vgx2], { z0.s - z1.s }, { z0.s - z3.s }
|
||||
fmla za.s[w8, 0, vgx2], { z0.s - z3.s }, { z0.s - z1.s }
|
||||
fmla za[w8, 0], { z0.s - z1.s }, { z0.s - z1.s }
|
||||
fmla za[w8, 0], { z0.s - z3.s }, { z0.s - z3.s }
|
||||
3
gas/testsuite/gas/aarch64/sme2-11-noarch.d
Normal file
3
gas/testsuite/gas/aarch64/sme2-11-noarch.d
Normal file
@ -0,0 +1,3 @@
|
||||
#as: -march=armv8-a+sme
|
||||
#source: sme2-11.s
|
||||
#error_output: sme2-11-noarch.l
|
||||
117
gas/testsuite/gas/aarch64/sme2-11-noarch.l
Normal file
117
gas/testsuite/gas/aarch64/sme2-11-noarch.l
Normal file
@ -0,0 +1,117 @@
|
||||
[^ :]+: Assembler messages:
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.s\[w8,0\],{z0\.s-z1\.s},z0\.s\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.s\[w8,0,vgx2\],{z0\.s-z1\.s},z0\.s\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fmla ZA\.S\[W8,0,VGx2\],{Z0\.S-Z1\.S},Z0\.S\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.s\[w11,0\],{z0\.s-z1\.s},z0\.s\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.s\[w8,7\],{z0\.s-z1\.s},z0\.s\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.s\[w8,0\],{z30\.s-z31\.s},z0\.s\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.s\[w8,0\],{z0\.s-z1\.s},z15\.s\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.s\[w8,0\],{z0\.s-z1\.s},z0\.s\[3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.s\[w9,6\],{z12\.s-z13\.s},z1\.s\[2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.s\[w8,0\],{z0\.s-z3\.s},z0\.s\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.s\[w8,0,vgx4\],{z0\.s-z3\.s},z0\.s\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fmla ZA\.S\[W8,0,VGX4\],{Z0\.S-Z3\.S},Z0\.S\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.s\[w11,0\],{z0\.s-z3\.s},z0\.s\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.s\[w8,7\],{z0\.s-z3\.s},z0\.s\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.s\[w8,0\],{z28\.s-z31\.s},z0\.s\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.s\[w8,0\],{z0\.s-z3\.s},z15\.s\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.s\[w8,0\],{z0\.s-z3\.s},z0\.s\[3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.s\[w10,4\],{z4\.s-z7\.s},z9\.s\[1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.s\[w8,0\],{z0\.s-z1\.s},z0\.s'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.s\[w8,0,vgx2\],{z0\.s-z1\.s},z0\.s'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fmla ZA\.s\[W8,0,VGx2\],{Z0\.s-Z1\.s},Z0\.s'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fmla ZA\.S\[W8,0,VGX2\],{Z0\.S-Z1\.S},Z0\.S'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.s\[w11,0\],{z0\.s-z1\.s},z0\.s'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.s\[w8,7\],{z0\.s-z1\.s},z0\.s'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.s\[w8,0\],{z30\.s-z31\.s},z0\.s'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.s\[w8,0\],{z31\.s,z0\.s},z0\.s'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.s\[w8,0\],{z31\.s-z0\.s},z0\.s'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.s\[w8,0\],{z0\.s-z1\.s},z15\.s'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.s\[w9,5\],{z9\.s-z10\.s},z6\.s'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.s\[w8,0\],{z0\.s-z3\.s},z0\.s'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.s\[w8,0,vgx4\],{z0\.s-z3\.s},z0\.s'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fmla ZA\.s\[W8,0,VGx4\],{Z0\.s-Z3\.s},Z0\.s'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fmla ZA\.S\[W8,0,VGX4\],{Z0\.S-Z3\.S},Z0\.S'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.s\[w11,0\],{z0\.s-z3\.s},z0\.s'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.s\[w8,7\],{z0\.s-z3\.s},z0\.s'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.s\[w8,0\],{z28\.s-z31\.s},z0\.s'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.s\[w8,0\],{z31\.s,z0\.s,z1\.s,z2\.s},z0\.s'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.s\[w8,0\],{z31\.s-z2\.s},z0\.s'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.s\[w8,0\],{z0\.s-z3\.s},z15\.s'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.s\[w11,2\],{z23\.s-z26\.s},z13\.s'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.s\[w8,0\],{z0\.s-z1\.s},{z0\.s-z1\.s}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.s\[w8,0,vgx2\],{z0\.s-z1\.s},{z0\.s-z1\.s}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fmla ZA\.s\[W8,0,VGx2\],{Z0\.s-Z1\.s},{Z0\.s-Z1\.s}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fmla ZA\.S\[W8,0,VGX2\],{Z0\.S-Z1\.S},{Z0\.S-Z1\.S}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.s\[w11,0\],{z0\.s-z1\.s},{z0\.s-z1\.s}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.s\[w8,7\],{z0\.s-z1\.s},{z0\.s-z1\.s}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.s\[w8,0\],{z30\.s-z31\.s},{z0\.s-z1\.s}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.s\[w8,0\],{z0\.s-z1\.s},{z30\.s-z31\.s}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.s\[w10,1\],{z22\.s-z23\.s},{z18\.s-z19\.s}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.s\[w8,0\],{z0\.s-z3\.s},{z0\.s-z3\.s}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.s\[w8,0,vgx4\],{z0\.s-z3\.s},{z0\.s-z3\.s}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fmla ZA\.s\[W8,0,VGx4\],{Z0\.s-Z3\.s},{Z0\.s-Z3\.s}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fmla ZA\.S\[W8,0,VGX4\],{Z0\.S-Z3\.S},{Z0\.S-Z3\.S}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.s\[w11,0\],{z0\.s-z3\.s},{z0\.s-z3\.s}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.s\[w8,7\],{z0\.s-z3\.s},{z0\.s-z3\.s}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.s\[w8,0\],{z28\.s-z31\.s},{z0\.s-z3\.s}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.s\[w8,0\],{z0\.s-z3\.s},{z28\.s-z31\.s}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.s\[w11,3\],{z16\.s-z19\.s},{z24\.s-z27\.s}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.s\[w8,0\],{z0\.s-z1\.s},z0\.s\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.s\[w8,0,vgx2\],{z0\.s-z1\.s},z0\.s\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fmls ZA\.S\[W8,0,VGx2\],{Z0\.S-Z1\.S},Z0\.S\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.s\[w11,0\],{z0\.s-z1\.s},z0\.s\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.s\[w8,7\],{z0\.s-z1\.s},z0\.s\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.s\[w8,0\],{z30\.s-z31\.s},z0\.s\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.s\[w8,0\],{z0\.s-z1\.s},z15\.s\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.s\[w8,0\],{z0\.s-z1\.s},z0\.s\[3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.s\[w9,6\],{z12\.s-z13\.s},z1\.s\[2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.s\[w8,0\],{z0\.s-z3\.s},z0\.s\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.s\[w8,0,vgx4\],{z0\.s-z3\.s},z0\.s\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fmls ZA\.S\[W8,0,VGX4\],{Z0\.S-Z3\.S},Z0\.S\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.s\[w11,0\],{z0\.s-z3\.s},z0\.s\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.s\[w8,7\],{z0\.s-z3\.s},z0\.s\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.s\[w8,0\],{z28\.s-z31\.s},z0\.s\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.s\[w8,0\],{z0\.s-z3\.s},z15\.s\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.s\[w8,0\],{z0\.s-z3\.s},z0\.s\[3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.s\[w10,4\],{z4\.s-z7\.s},z9\.s\[1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.s\[w8,0\],{z0\.s-z1\.s},z0\.s'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.s\[w8,0,vgx2\],{z0\.s-z1\.s},z0\.s'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fmls ZA\.s\[W8,0,VGx2\],{Z0\.s-Z1\.s},Z0\.s'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fmls ZA\.S\[W8,0,VGX2\],{Z0\.S-Z1\.S},Z0\.S'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.s\[w11,0\],{z0\.s-z1\.s},z0\.s'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.s\[w8,7\],{z0\.s-z1\.s},z0\.s'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.s\[w8,0\],{z30\.s-z31\.s},z0\.s'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.s\[w8,0\],{z31\.s,z0\.s},z0\.s'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.s\[w8,0\],{z31\.s-z0\.s},z0\.s'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.s\[w8,0\],{z0\.s-z1\.s},z15\.s'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.s\[w9,5\],{z9\.s-z10\.s},z6\.s'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.s\[w8,0\],{z0\.s-z3\.s},z0\.s'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.s\[w8,0,vgx4\],{z0\.s-z3\.s},z0\.s'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fmls ZA\.s\[W8,0,VGx4\],{Z0\.s-Z3\.s},Z0\.s'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fmls ZA\.S\[W8,0,VGX4\],{Z0\.S-Z3\.S},Z0\.S'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.s\[w11,0\],{z0\.s-z3\.s},z0\.s'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.s\[w8,7\],{z0\.s-z3\.s},z0\.s'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.s\[w8,0\],{z28\.s-z31\.s},z0\.s'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.s\[w8,0\],{z31\.s,z0\.s,z1\.s,z2\.s},z0\.s'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.s\[w8,0\],{z31\.s-z2\.s},z0\.s'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.s\[w8,0\],{z0\.s-z3\.s},z15\.s'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.s\[w11,2\],{z23\.s-z26\.s},z13\.s'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.s\[w8,0\],{z0\.s-z1\.s},{z0\.s-z1\.s}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.s\[w8,0,vgx2\],{z0\.s-z1\.s},{z0\.s-z1\.s}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fmls ZA\.s\[W8,0,VGx2\],{Z0\.s-Z1\.s},{Z0\.s-Z1\.s}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fmls ZA\.S\[W8,0,VGX2\],{Z0\.S-Z1\.S},{Z0\.S-Z1\.S}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.s\[w11,0\],{z0\.s-z1\.s},{z0\.s-z1\.s}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.s\[w8,7\],{z0\.s-z1\.s},{z0\.s-z1\.s}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.s\[w8,0\],{z30\.s-z31\.s},{z0\.s-z1\.s}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.s\[w8,0\],{z0\.s-z1\.s},{z30\.s-z31\.s}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.s\[w10,1\],{z22\.s-z23\.s},{z18\.s-z19\.s}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.s\[w8,0\],{z0\.s-z3\.s},{z0\.s-z3\.s}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.s\[w8,0,vgx4\],{z0\.s-z3\.s},{z0\.s-z3\.s}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fmls ZA\.s\[W8,0,VGx4\],{Z0\.s-Z3\.s},{Z0\.s-Z3\.s}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fmls ZA\.S\[W8,0,VGX4\],{Z0\.S-Z3\.S},{Z0\.S-Z3\.S}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.s\[w11,0\],{z0\.s-z3\.s},{z0\.s-z3\.s}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.s\[w8,7\],{z0\.s-z3\.s},{z0\.s-z3\.s}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.s\[w8,0\],{z28\.s-z31\.s},{z0\.s-z3\.s}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.s\[w8,0\],{z0\.s-z3\.s},{z28\.s-z31\.s}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.s\[w11,3\],{z16\.s-z19\.s},{z24\.s-z27\.s}'
|
||||
125
gas/testsuite/gas/aarch64/sme2-11.d
Normal file
125
gas/testsuite/gas/aarch64/sme2-11.d
Normal file
@ -0,0 +1,125 @@
|
||||
#as: -march=armv8-a+sme2
|
||||
#objdump: -dr
|
||||
|
||||
[^:]+: file format .*
|
||||
|
||||
|
||||
[^:]+:
|
||||
|
||||
[^:]+:
|
||||
[^:]+: c1500000 fmla za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s}, z0\.s\[0\]
|
||||
[^:]+: c1500000 fmla za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s}, z0\.s\[0\]
|
||||
[^:]+: c1500000 fmla za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s}, z0\.s\[0\]
|
||||
[^:]+: c1506000 fmla za\.s\[w11, 0, vgx2\], {z0\.s-z1\.s}, z0\.s\[0\]
|
||||
[^:]+: c1500007 fmla za\.s\[w8, 7, vgx2\], {z0\.s-z1\.s}, z0\.s\[0\]
|
||||
[^:]+: c15003c0 fmla za\.s\[w8, 0, vgx2\], {z30\.s-z31\.s}, z0\.s\[0\]
|
||||
[^:]+: c15f0000 fmla za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s}, z15\.s\[0\]
|
||||
[^:]+: c1500c00 fmla za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s}, z0\.s\[3\]
|
||||
[^:]+: c1512986 fmla za\.s\[w9, 6, vgx2\], {z12\.s-z13\.s}, z1\.s\[2\]
|
||||
[^:]+: c1508000 fmla za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s}, z0\.s\[0\]
|
||||
[^:]+: c1508000 fmla za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s}, z0\.s\[0\]
|
||||
[^:]+: c1508000 fmla za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s}, z0\.s\[0\]
|
||||
[^:]+: c150e000 fmla za\.s\[w11, 0, vgx4\], {z0\.s-z3\.s}, z0\.s\[0\]
|
||||
[^:]+: c1508007 fmla za\.s\[w8, 7, vgx4\], {z0\.s-z3\.s}, z0\.s\[0\]
|
||||
[^:]+: c1508380 fmla za\.s\[w8, 0, vgx4\], {z28\.s-z31\.s}, z0\.s\[0\]
|
||||
[^:]+: c15f8000 fmla za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s}, z15\.s\[0\]
|
||||
[^:]+: c1508c00 fmla za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s}, z0\.s\[3\]
|
||||
[^:]+: c159c484 fmla za\.s\[w10, 4, vgx4\], {z4\.s-z7\.s}, z9\.s\[1\]
|
||||
[^:]+: c1201800 fmla za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s}, z0\.s
|
||||
[^:]+: c1201800 fmla za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s}, z0\.s
|
||||
[^:]+: c1201800 fmla za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s}, z0\.s
|
||||
[^:]+: c1201800 fmla za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s}, z0\.s
|
||||
[^:]+: c1207800 fmla za\.s\[w11, 0, vgx2\], {z0\.s-z1\.s}, z0\.s
|
||||
[^:]+: c1201807 fmla za\.s\[w8, 7, vgx2\], {z0\.s-z1\.s}, z0\.s
|
||||
[^:]+: c1201bc0 fmla za\.s\[w8, 0, vgx2\], {z30\.s-z31\.s}, z0\.s
|
||||
[^:]+: c1201be0 fmla za\.s\[w8, 0, vgx2\], {z31\.s-z0\.s}, z0\.s
|
||||
[^:]+: c1201be0 fmla za\.s\[w8, 0, vgx2\], {z31\.s-z0\.s}, z0\.s
|
||||
[^:]+: c12f1800 fmla za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s}, z15\.s
|
||||
[^:]+: c1263925 fmla za\.s\[w9, 5, vgx2\], {z9\.s-z10\.s}, z6\.s
|
||||
[^:]+: c1301800 fmla za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s}, z0\.s
|
||||
[^:]+: c1301800 fmla za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s}, z0\.s
|
||||
[^:]+: c1301800 fmla za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s}, z0\.s
|
||||
[^:]+: c1301800 fmla za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s}, z0\.s
|
||||
[^:]+: c1307800 fmla za\.s\[w11, 0, vgx4\], {z0\.s-z3\.s}, z0\.s
|
||||
[^:]+: c1301807 fmla za\.s\[w8, 7, vgx4\], {z0\.s-z3\.s}, z0\.s
|
||||
[^:]+: c1301b80 fmla za\.s\[w8, 0, vgx4\], {z28\.s-z31\.s}, z0\.s
|
||||
[^:]+: c1301be0 fmla za\.s\[w8, 0, vgx4\], {z31\.s-z2\.s}, z0\.s
|
||||
[^:]+: c1301be0 fmla za\.s\[w8, 0, vgx4\], {z31\.s-z2\.s}, z0\.s
|
||||
[^:]+: c13f1800 fmla za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s}, z15\.s
|
||||
[^:]+: c13d7ae2 fmla za\.s\[w11, 2, vgx4\], {z23\.s-z26\.s}, z13\.s
|
||||
[^:]+: c1a01800 fmla za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s}, {z0\.s-z1\.s}
|
||||
[^:]+: c1a01800 fmla za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s}, {z0\.s-z1\.s}
|
||||
[^:]+: c1a01800 fmla za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s}, {z0\.s-z1\.s}
|
||||
[^:]+: c1a01800 fmla za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s}, {z0\.s-z1\.s}
|
||||
[^:]+: c1a07800 fmla za\.s\[w11, 0, vgx2\], {z0\.s-z1\.s}, {z0\.s-z1\.s}
|
||||
[^:]+: c1a01807 fmla za\.s\[w8, 7, vgx2\], {z0\.s-z1\.s}, {z0\.s-z1\.s}
|
||||
[^:]+: c1a01bc0 fmla za\.s\[w8, 0, vgx2\], {z30\.s-z31\.s}, {z0\.s-z1\.s}
|
||||
[^:]+: c1be1800 fmla za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s}, {z30\.s-z31\.s}
|
||||
[^:]+: c1b25ac1 fmla za\.s\[w10, 1, vgx2\], {z22\.s-z23\.s}, {z18\.s-z19\.s}
|
||||
[^:]+: c1a11800 fmla za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s}, {z0\.s-z3\.s}
|
||||
[^:]+: c1a11800 fmla za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s}, {z0\.s-z3\.s}
|
||||
[^:]+: c1a11800 fmla za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s}, {z0\.s-z3\.s}
|
||||
[^:]+: c1a11800 fmla za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s}, {z0\.s-z3\.s}
|
||||
[^:]+: c1a17800 fmla za\.s\[w11, 0, vgx4\], {z0\.s-z3\.s}, {z0\.s-z3\.s}
|
||||
[^:]+: c1a11807 fmla za\.s\[w8, 7, vgx4\], {z0\.s-z3\.s}, {z0\.s-z3\.s}
|
||||
[^:]+: c1a11b80 fmla za\.s\[w8, 0, vgx4\], {z28\.s-z31\.s}, {z0\.s-z3\.s}
|
||||
[^:]+: c1bd1800 fmla za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s}, {z28\.s-z31\.s}
|
||||
[^:]+: c1b97a03 fmla za\.s\[w11, 3, vgx4\], {z16\.s-z19\.s}, {z24\.s-z27\.s}
|
||||
[^:]+: c1500010 fmls za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s}, z0\.s\[0\]
|
||||
[^:]+: c1500010 fmls za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s}, z0\.s\[0\]
|
||||
[^:]+: c1500010 fmls za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s}, z0\.s\[0\]
|
||||
[^:]+: c1506010 fmls za\.s\[w11, 0, vgx2\], {z0\.s-z1\.s}, z0\.s\[0\]
|
||||
[^:]+: c1500017 fmls za\.s\[w8, 7, vgx2\], {z0\.s-z1\.s}, z0\.s\[0\]
|
||||
[^:]+: c15003d0 fmls za\.s\[w8, 0, vgx2\], {z30\.s-z31\.s}, z0\.s\[0\]
|
||||
[^:]+: c15f0010 fmls za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s}, z15\.s\[0\]
|
||||
[^:]+: c1500c10 fmls za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s}, z0\.s\[3\]
|
||||
[^:]+: c1512996 fmls za\.s\[w9, 6, vgx2\], {z12\.s-z13\.s}, z1\.s\[2\]
|
||||
[^:]+: c1508010 fmls za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s}, z0\.s\[0\]
|
||||
[^:]+: c1508010 fmls za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s}, z0\.s\[0\]
|
||||
[^:]+: c1508010 fmls za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s}, z0\.s\[0\]
|
||||
[^:]+: c150e010 fmls za\.s\[w11, 0, vgx4\], {z0\.s-z3\.s}, z0\.s\[0\]
|
||||
[^:]+: c1508017 fmls za\.s\[w8, 7, vgx4\], {z0\.s-z3\.s}, z0\.s\[0\]
|
||||
[^:]+: c1508390 fmls za\.s\[w8, 0, vgx4\], {z28\.s-z31\.s}, z0\.s\[0\]
|
||||
[^:]+: c15f8010 fmls za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s}, z15\.s\[0\]
|
||||
[^:]+: c1508c10 fmls za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s}, z0\.s\[3\]
|
||||
[^:]+: c159c494 fmls za\.s\[w10, 4, vgx4\], {z4\.s-z7\.s}, z9\.s\[1\]
|
||||
[^:]+: c1201808 fmls za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s}, z0\.s
|
||||
[^:]+: c1201808 fmls za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s}, z0\.s
|
||||
[^:]+: c1201808 fmls za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s}, z0\.s
|
||||
[^:]+: c1201808 fmls za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s}, z0\.s
|
||||
[^:]+: c1207808 fmls za\.s\[w11, 0, vgx2\], {z0\.s-z1\.s}, z0\.s
|
||||
[^:]+: c120180f fmls za\.s\[w8, 7, vgx2\], {z0\.s-z1\.s}, z0\.s
|
||||
[^:]+: c1201bc8 fmls za\.s\[w8, 0, vgx2\], {z30\.s-z31\.s}, z0\.s
|
||||
[^:]+: c1201be8 fmls za\.s\[w8, 0, vgx2\], {z31\.s-z0\.s}, z0\.s
|
||||
[^:]+: c1201be8 fmls za\.s\[w8, 0, vgx2\], {z31\.s-z0\.s}, z0\.s
|
||||
[^:]+: c12f1808 fmls za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s}, z15\.s
|
||||
[^:]+: c126392d fmls za\.s\[w9, 5, vgx2\], {z9\.s-z10\.s}, z6\.s
|
||||
[^:]+: c1301808 fmls za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s}, z0\.s
|
||||
[^:]+: c1301808 fmls za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s}, z0\.s
|
||||
[^:]+: c1301808 fmls za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s}, z0\.s
|
||||
[^:]+: c1301808 fmls za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s}, z0\.s
|
||||
[^:]+: c1307808 fmls za\.s\[w11, 0, vgx4\], {z0\.s-z3\.s}, z0\.s
|
||||
[^:]+: c130180f fmls za\.s\[w8, 7, vgx4\], {z0\.s-z3\.s}, z0\.s
|
||||
[^:]+: c1301b88 fmls za\.s\[w8, 0, vgx4\], {z28\.s-z31\.s}, z0\.s
|
||||
[^:]+: c1301be8 fmls za\.s\[w8, 0, vgx4\], {z31\.s-z2\.s}, z0\.s
|
||||
[^:]+: c1301be8 fmls za\.s\[w8, 0, vgx4\], {z31\.s-z2\.s}, z0\.s
|
||||
[^:]+: c13f1808 fmls za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s}, z15\.s
|
||||
[^:]+: c13d7aea fmls za\.s\[w11, 2, vgx4\], {z23\.s-z26\.s}, z13\.s
|
||||
[^:]+: c1a01808 fmls za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s}, {z0\.s-z1\.s}
|
||||
[^:]+: c1a01808 fmls za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s}, {z0\.s-z1\.s}
|
||||
[^:]+: c1a01808 fmls za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s}, {z0\.s-z1\.s}
|
||||
[^:]+: c1a01808 fmls za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s}, {z0\.s-z1\.s}
|
||||
[^:]+: c1a07808 fmls za\.s\[w11, 0, vgx2\], {z0\.s-z1\.s}, {z0\.s-z1\.s}
|
||||
[^:]+: c1a0180f fmls za\.s\[w8, 7, vgx2\], {z0\.s-z1\.s}, {z0\.s-z1\.s}
|
||||
[^:]+: c1a01bc8 fmls za\.s\[w8, 0, vgx2\], {z30\.s-z31\.s}, {z0\.s-z1\.s}
|
||||
[^:]+: c1be1808 fmls za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s}, {z30\.s-z31\.s}
|
||||
[^:]+: c1b25ac9 fmls za\.s\[w10, 1, vgx2\], {z22\.s-z23\.s}, {z18\.s-z19\.s}
|
||||
[^:]+: c1a11808 fmls za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s}, {z0\.s-z3\.s}
|
||||
[^:]+: c1a11808 fmls za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s}, {z0\.s-z3\.s}
|
||||
[^:]+: c1a11808 fmls za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s}, {z0\.s-z3\.s}
|
||||
[^:]+: c1a11808 fmls za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s}, {z0\.s-z3\.s}
|
||||
[^:]+: c1a17808 fmls za\.s\[w11, 0, vgx4\], {z0\.s-z3\.s}, {z0\.s-z3\.s}
|
||||
[^:]+: c1a1180f fmls za\.s\[w8, 7, vgx4\], {z0\.s-z3\.s}, {z0\.s-z3\.s}
|
||||
[^:]+: c1a11b88 fmls za\.s\[w8, 0, vgx4\], {z28\.s-z31\.s}, {z0\.s-z3\.s}
|
||||
[^:]+: c1bd1808 fmls za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s}, {z28\.s-z31\.s}
|
||||
[^:]+: c1b97a0b fmls za\.s\[w11, 3, vgx4\], {z16\.s-z19\.s}, {z24\.s-z27\.s}
|
||||
127
gas/testsuite/gas/aarch64/sme2-11.s
Normal file
127
gas/testsuite/gas/aarch64/sme2-11.s
Normal file
@ -0,0 +1,127 @@
|
||||
fmla za.s[w8, 0], { z0.s - z1.s }, z0.s[0]
|
||||
fmla za.s[w8, 0, vgx2], { z0.s - z1.s }, z0.s[0]
|
||||
FMLA ZA.S[W8, 0, VGx2], { Z0.S - Z1.S }, Z0.S[0]
|
||||
fmla za.s[w11, 0], { z0.s - z1.s }, z0.s[0]
|
||||
fmla za.s[w8, 7], { z0.s - z1.s }, z0.s[0]
|
||||
fmla za.s[w8, 0], { z30.s - z31.s }, z0.s[0]
|
||||
fmla za.s[w8, 0], { z0.s - z1.s }, z15.s[0]
|
||||
fmla za.s[w8, 0], { z0.s - z1.s }, z0.s[3]
|
||||
fmla za.s[w9, 6], { z12.s - z13.s }, z1.s[2]
|
||||
|
||||
fmla za.s[w8, 0], { z0.s - z3.s }, z0.s[0]
|
||||
fmla za.s[w8, 0, vgx4], { z0.s - z3.s }, z0.s[0]
|
||||
FMLA ZA.S[W8, 0, VGX4], { Z0.S - Z3.S }, Z0.S[0]
|
||||
fmla za.s[w11, 0], { z0.s - z3.s }, z0.s[0]
|
||||
fmla za.s[w8, 7], { z0.s - z3.s }, z0.s[0]
|
||||
fmla za.s[w8, 0], { z28.s - z31.s }, z0.s[0]
|
||||
fmla za.s[w8, 0], { z0.s - z3.s }, z15.s[0]
|
||||
fmla za.s[w8, 0], { z0.s - z3.s }, z0.s[3]
|
||||
fmla za.s[w10, 4], { z4.s - z7.s }, z9.s[1]
|
||||
|
||||
fmla za.s[w8, 0], { z0.s - z1.s }, z0.s
|
||||
fmla za.s[w8, 0, vgx2], { z0.s - z1.s }, z0.s
|
||||
FMLA ZA.s[W8, 0, VGx2], { Z0.s - Z1.s }, Z0.s
|
||||
FMLA ZA.S[W8, 0, VGX2], { Z0.S - Z1.S }, Z0.S
|
||||
fmla za.s[w11, 0], { z0.s - z1.s }, z0.s
|
||||
fmla za.s[w8, 7], { z0.s - z1.s }, z0.s
|
||||
fmla za.s[w8, 0], { z30.s - z31.s }, z0.s
|
||||
fmla za.s[w8, 0], { z31.s, z0.s }, z0.s
|
||||
fmla za.s[w8, 0], { z31.s - z0.s }, z0.s
|
||||
fmla za.s[w8, 0], { z0.s - z1.s }, z15.s
|
||||
fmla za.s[w9, 5], { z9.s - z10.s }, z6.s
|
||||
|
||||
fmla za.s[w8, 0], { z0.s - z3.s }, z0.s
|
||||
fmla za.s[w8, 0, vgx4], { z0.s - z3.s }, z0.s
|
||||
FMLA ZA.s[W8, 0, VGx4], { Z0.s - Z3.s }, Z0.s
|
||||
FMLA ZA.S[W8, 0, VGX4], { Z0.S - Z3.S }, Z0.S
|
||||
fmla za.s[w11, 0], { z0.s - z3.s }, z0.s
|
||||
fmla za.s[w8, 7], { z0.s - z3.s }, z0.s
|
||||
fmla za.s[w8, 0], { z28.s - z31.s }, z0.s
|
||||
fmla za.s[w8, 0], { z31.s, z0.s, z1.s, z2.s }, z0.s
|
||||
fmla za.s[w8, 0], { z31.s - z2.s }, z0.s
|
||||
fmla za.s[w8, 0], { z0.s - z3.s }, z15.s
|
||||
fmla za.s[w11, 2], { z23.s - z26.s }, z13.s
|
||||
|
||||
fmla za.s[w8, 0], { z0.s - z1.s }, { z0.s - z1.s }
|
||||
fmla za.s[w8, 0, vgx2], { z0.s - z1.s }, { z0.s - z1.s }
|
||||
FMLA ZA.s[W8, 0, VGx2], { Z0.s - Z1.s }, { Z0.s - Z1.s }
|
||||
FMLA ZA.S[W8, 0, VGX2], { Z0.S - Z1.S }, { Z0.S - Z1.S }
|
||||
fmla za.s[w11, 0], { z0.s - z1.s }, { z0.s - z1.s }
|
||||
fmla za.s[w8, 7], { z0.s - z1.s }, { z0.s - z1.s }
|
||||
fmla za.s[w8, 0], { z30.s - z31.s }, { z0.s - z1.s }
|
||||
fmla za.s[w8, 0], { z0.s - z1.s }, { z30.s - z31.s }
|
||||
fmla za.s[w10, 1], { z22.s - z23.s }, { z18.s - z19.s }
|
||||
|
||||
fmla za.s[w8, 0], { z0.s - z3.s }, { z0.s - z3.s }
|
||||
fmla za.s[w8, 0, vgx4], { z0.s - z3.s }, { z0.s - z3.s }
|
||||
FMLA ZA.s[W8, 0, VGx4], { Z0.s - Z3.s }, { Z0.s - Z3.s }
|
||||
FMLA ZA.S[W8, 0, VGX4], { Z0.S - Z3.S }, { Z0.S - Z3.S }
|
||||
fmla za.s[w11, 0], { z0.s - z3.s }, { z0.s - z3.s }
|
||||
fmla za.s[w8, 7], { z0.s - z3.s }, { z0.s - z3.s }
|
||||
fmla za.s[w8, 0], { z28.s - z31.s }, { z0.s - z3.s }
|
||||
fmla za.s[w8, 0], { z0.s - z3.s }, { z28.s - z31.s }
|
||||
fmla za.s[w11, 3], { z16.s - z19.s }, { z24.s - z27.s }
|
||||
|
||||
fmls za.s[w8, 0], { z0.s - z1.s }, z0.s[0]
|
||||
fmls za.s[w8, 0, vgx2], { z0.s - z1.s }, z0.s[0]
|
||||
FMLS ZA.S[W8, 0, VGx2], { Z0.S - Z1.S }, Z0.S[0]
|
||||
fmls za.s[w11, 0], { z0.s - z1.s }, z0.s[0]
|
||||
fmls za.s[w8, 7], { z0.s - z1.s }, z0.s[0]
|
||||
fmls za.s[w8, 0], { z30.s - z31.s }, z0.s[0]
|
||||
fmls za.s[w8, 0], { z0.s - z1.s }, z15.s[0]
|
||||
fmls za.s[w8, 0], { z0.s - z1.s }, z0.s[3]
|
||||
fmls za.s[w9, 6], { z12.s - z13.s }, z1.s[2]
|
||||
|
||||
fmls za.s[w8, 0], { z0.s - z3.s }, z0.s[0]
|
||||
fmls za.s[w8, 0, vgx4], { z0.s - z3.s }, z0.s[0]
|
||||
FMLS ZA.S[W8, 0, VGX4], { Z0.S - Z3.S }, Z0.S[0]
|
||||
fmls za.s[w11, 0], { z0.s - z3.s }, z0.s[0]
|
||||
fmls za.s[w8, 7], { z0.s - z3.s }, z0.s[0]
|
||||
fmls za.s[w8, 0], { z28.s - z31.s }, z0.s[0]
|
||||
fmls za.s[w8, 0], { z0.s - z3.s }, z15.s[0]
|
||||
fmls za.s[w8, 0], { z0.s - z3.s }, z0.s[3]
|
||||
fmls za.s[w10, 4], { z4.s - z7.s }, z9.s[1]
|
||||
|
||||
fmls za.s[w8, 0], { z0.s - z1.s }, z0.s
|
||||
fmls za.s[w8, 0, vgx2], { z0.s - z1.s }, z0.s
|
||||
FMLS ZA.s[W8, 0, VGx2], { Z0.s - Z1.s }, Z0.s
|
||||
FMLS ZA.S[W8, 0, VGX2], { Z0.S - Z1.S }, Z0.S
|
||||
fmls za.s[w11, 0], { z0.s - z1.s }, z0.s
|
||||
fmls za.s[w8, 7], { z0.s - z1.s }, z0.s
|
||||
fmls za.s[w8, 0], { z30.s - z31.s }, z0.s
|
||||
fmls za.s[w8, 0], { z31.s, z0.s }, z0.s
|
||||
fmls za.s[w8, 0], { z31.s - z0.s }, z0.s
|
||||
fmls za.s[w8, 0], { z0.s - z1.s }, z15.s
|
||||
fmls za.s[w9, 5], { z9.s - z10.s }, z6.s
|
||||
|
||||
fmls za.s[w8, 0], { z0.s - z3.s }, z0.s
|
||||
fmls za.s[w8, 0, vgx4], { z0.s - z3.s }, z0.s
|
||||
FMLS ZA.s[W8, 0, VGx4], { Z0.s - Z3.s }, Z0.s
|
||||
FMLS ZA.S[W8, 0, VGX4], { Z0.S - Z3.S }, Z0.S
|
||||
fmls za.s[w11, 0], { z0.s - z3.s }, z0.s
|
||||
fmls za.s[w8, 7], { z0.s - z3.s }, z0.s
|
||||
fmls za.s[w8, 0], { z28.s - z31.s }, z0.s
|
||||
fmls za.s[w8, 0], { z31.s, z0.s, z1.s, z2.s }, z0.s
|
||||
fmls za.s[w8, 0], { z31.s - z2.s }, z0.s
|
||||
fmls za.s[w8, 0], { z0.s - z3.s }, z15.s
|
||||
fmls za.s[w11, 2], { z23.s - z26.s }, z13.s
|
||||
|
||||
fmls za.s[w8, 0], { z0.s - z1.s }, { z0.s - z1.s }
|
||||
fmls za.s[w8, 0, vgx2], { z0.s - z1.s }, { z0.s - z1.s }
|
||||
FMLS ZA.s[W8, 0, VGx2], { Z0.s - Z1.s }, { Z0.s - Z1.s }
|
||||
FMLS ZA.S[W8, 0, VGX2], { Z0.S - Z1.S }, { Z0.S - Z1.S }
|
||||
fmls za.s[w11, 0], { z0.s - z1.s }, { z0.s - z1.s }
|
||||
fmls za.s[w8, 7], { z0.s - z1.s }, { z0.s - z1.s }
|
||||
fmls za.s[w8, 0], { z30.s - z31.s }, { z0.s - z1.s }
|
||||
fmls za.s[w8, 0], { z0.s - z1.s }, { z30.s - z31.s }
|
||||
fmls za.s[w10, 1], { z22.s - z23.s }, { z18.s - z19.s }
|
||||
|
||||
fmls za.s[w8, 0], { z0.s - z3.s }, { z0.s - z3.s }
|
||||
fmls za.s[w8, 0, vgx4], { z0.s - z3.s }, { z0.s - z3.s }
|
||||
FMLS ZA.s[W8, 0, VGx4], { Z0.s - Z3.s }, { Z0.s - Z3.s }
|
||||
FMLS ZA.S[W8, 0, VGX4], { Z0.S - Z3.S }, { Z0.S - Z3.S }
|
||||
fmls za.s[w11, 0], { z0.s - z3.s }, { z0.s - z3.s }
|
||||
fmls za.s[w8, 7], { z0.s - z3.s }, { z0.s - z3.s }
|
||||
fmls za.s[w8, 0], { z28.s - z31.s }, { z0.s - z3.s }
|
||||
fmls za.s[w8, 0], { z0.s - z3.s }, { z28.s - z31.s }
|
||||
fmls za.s[w11, 3], { z16.s - z19.s }, { z24.s - z27.s }
|
||||
3
gas/testsuite/gas/aarch64/sme2-f64f64-2-invalid.d
Normal file
3
gas/testsuite/gas/aarch64/sme2-f64f64-2-invalid.d
Normal file
@ -0,0 +1,3 @@
|
||||
#as: -march=armv8-a
|
||||
#source: sme2-f64f64-2-invalid.s
|
||||
#error_output: sme2-f64f64-2-invalid.l
|
||||
98
gas/testsuite/gas/aarch64/sme2-f64f64-2-invalid.l
Normal file
98
gas/testsuite/gas/aarch64/sme2-f64f64-2-invalid.l
Normal file
@ -0,0 +1,98 @@
|
||||
[^ :]+: Assembler messages:
|
||||
[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmla za\.d\[w7,0\],{z0\.d-z1\.d},z0\.d\[0\]'
|
||||
[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmla za\.d\[w12,0\],{z0\.d-z1\.d},z0\.d\[0\]'
|
||||
[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `fmla za\.d\[w8,-1\],{z0\.d-z1\.d},z0\.d\[0\]'
|
||||
[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `fmla za\.d\[w8,8\],{z0\.d-z1\.d},z0\.d\[0\]'
|
||||
[^ :]+:[0-9]+: Error: expected a list of 4 registers at operand 2 -- `fmla za\.d\[w8,0,vgx4\],{z0\.d-z1\.d},z0\.d\[0\]'
|
||||
[^ :]+:[0-9]+: Error: expected a list of 2 or 4 registers at operand 2 -- `fmla za\.d\[w8,0\],{z0\.d-z2\.d},z0\.d\[0\]'
|
||||
[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `fmla za\.d\[w8,0\],{z1\.d-z2\.d},z0\.d\[0\]'
|
||||
[^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `fmla za\.d\[w8,0\],{z0\.d-z1\.d},z16\.d\[0\]'
|
||||
[^ :]+:[0-9]+: Error: register element index out of range 0 to 1 at operand 3 -- `fmla za\.d\[w8,0\],{z0\.d-z1\.d},z0\.d\[-1\]'
|
||||
[^ :]+:[0-9]+: Error: register element index out of range 0 to 1 at operand 3 -- `fmla za\.d\[w8,0\],{z0\.d-z1\.d},z0\.d\[2\]'
|
||||
[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmla za\.d\[w7,0\],{z0\.d-z3\.d},z0\.d\[0\]'
|
||||
[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmla za\.d\[w12,0\],{z0\.d-z3\.d},z0\.d\[0\]'
|
||||
[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `fmla za\.d\[w8,-1\],{z0\.d-z3\.d},z0\.d\[0\]'
|
||||
[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `fmla za\.d\[w8,8\],{z0\.d-z3\.d},z0\.d\[0\]'
|
||||
[^ :]+:[0-9]+: Error: expected a list of 2 registers at operand 2 -- `fmla za\.d\[w8,0,vgx2\],{z0\.d-z3\.d},z0\.d\[0\]'
|
||||
[^ :]+:[0-9]+: Error: too many registers in vector register list at operand 2 -- `fmla za\.d\[w8,0\],{z0\.d-z4\.d},z0\.d\[0\]'
|
||||
[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `fmla za\.d\[w8,0\],{z1\.d-z4\.d},z0\.d\[0\]'
|
||||
[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `fmla za\.d\[w8,0\],{z2\.d-z5\.d},z0\.d\[0\]'
|
||||
[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `fmla za\.d\[w8,0\],{z3\.d-z6\.d},z0\.d\[0\]'
|
||||
[^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `fmla za\.d\[w8,0\],{z0\.d-z3\.d},z16\.d\[0\]'
|
||||
[^ :]+:[0-9]+: Error: register element index out of range 0 to 1 at operand 3 -- `fmla za\.d\[w8,0\],{z0\.d-z3\.d},z0\.d\[-1\]'
|
||||
[^ :]+:[0-9]+: Error: register element index out of range 0 to 1 at operand 3 -- `fmla za\.d\[w8,0\],{z0\.d-z3\.d},z0\.d\[2\]'
|
||||
[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmla za\.d\[w0,0\],{z0\.d-z1\.d},z0\.d'
|
||||
[^ :]+:[0-9]+: Error: expected a 32-bit selection register at operand 1 -- `fmla za\.d\[w31,0\],{z0\.d-z1\.d},z0\.d'
|
||||
[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `fmla za\.d\[w8,1<<63\],{z0\.d-z1\.d},z0\.d'
|
||||
[^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `fmla za\.d\[w8,0\],{z0\.d-z1\.d},z31\.d'
|
||||
[^ :]+:[0-9]+: Error: the last offset is equal to the first offset at operand 1 -- `fmla za\.d\[w8,0:0\],{z0\.d-z1\.d},z0\.d'
|
||||
[^ :]+:[0-9]+: Error: the last offset is less than the first offset at operand 1 -- `fmla za\.d\[w8,0:-1\],{z0\.d-z1\.d},z0\.d'
|
||||
[^ :]+:[0-9]+: Error: expected a single offset rather than a range at operand 1 -- `fmla za\.d\[w8,0:1\],{z0\.d-z1\.d},z0\.d'
|
||||
[^ :]+:[0-9]+: Error: expected a single offset rather than a range at operand 1 -- `fmla za\.d\[w8,0:100\],{z0\.d-z1\.d},z0\.d'
|
||||
[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmla za\.d\[w7,0\],{z0\.d-z1\.d},z0\.d'
|
||||
[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmla za\.d\[w12,0\],{z0\.d-z1\.d},z0\.d'
|
||||
[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `fmla za\.d\[w8,-1\],{z0\.d-z1\.d},z0\.d'
|
||||
[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `fmla za\.d\[w8,8\],{z0\.d-z1\.d},z0\.d'
|
||||
[^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `fmla za\.d\[w8,0\],{z0\.d-z1\.d},z16\.d'
|
||||
[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmla za\.d\[w7,0\],{z0\.d-z3\.d},z0\.d'
|
||||
[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmla za\.d\[w12,0\],{z0\.d-z3\.d},z0\.d'
|
||||
[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `fmla za\.d\[w8,-1\],{z0\.d-z3\.d},z0\.d'
|
||||
[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `fmla za\.d\[w8,8\],{z0\.d-z3\.d},z0\.d'
|
||||
[^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `fmla za\.d\[w8,0\],{z0\.d-z3\.d},z16\.d'
|
||||
[^ :]+:[0-9]+: Error: expected a list of 2 or 4 registers at operand 2 -- `fmla za\.d\[w8,0\],{z0\.d-z2\.d},z0\.d'
|
||||
[^ :]+:[0-9]+: Error: too many registers in vector register list at operand 2 -- `fmla za\.d\[w8,0\],{z0\.d-z4\.d},z0\.d'
|
||||
[^ :]+:[0-9]+: Error: expected a list of 2 or 4 registers at operand 2 -- `fmla za\.d\[w8,0\],{z0\.d,z1\.d,z2\.d},z0\.d'
|
||||
[^ :]+:[0-9]+: Error: invalid register list at operand 2 -- `fmla za\.d\[w8,0\],{z0\.d,z1\.d,z5\.d},z0\.d'
|
||||
[^ :]+:[0-9]+: Error: expected a list of 4 registers at operand 2 -- `fmla za\.d\[w8,0,vgx4\],{z0\.d-z1\.d},z0\.d'
|
||||
[^ :]+:[0-9]+: Error: expected a list of 2 registers at operand 2 -- `fmla za\.d\[w8,0,vgx2\],{z0\.d-z3\.d},z0\.d'
|
||||
[^ :]+:[0-9]+: Error: operand mismatch -- `fmla za\[w8,0\],{z0\.d-z1\.d},z0\.d'
|
||||
[^ :]+:[0-9]+: Info: did you mean this\?
|
||||
[^ :]+:[0-9]+: Info: fmla za\.d\[w8, 0\], {z0\.d-z1\.d}, z0\.d
|
||||
[^ :]+:[0-9]+: Info: other valid variant\(s\):
|
||||
[^ :]+:[0-9]+: Info: fmla za\.s\[w8, 0\], {z0\.s-z1\.s}, z0\.s
|
||||
[^ :]+:[0-9]+: Error: missing type suffix at operand 2 -- `fmla za\.d\[w8,0\],{z0-z1},z0\.d'
|
||||
[^ :]+:[0-9]+: Error: operand mismatch -- `fmla za\.d\[w8,0\],{z0\.d-z1\.d},z0'
|
||||
[^ :]+:[0-9]+: Info: did you mean this\?
|
||||
[^ :]+:[0-9]+: Info: fmla za\.d\[w8, 0\], {z0\.d-z1\.d}, z0\.d
|
||||
[^ :]+:[0-9]+: Info: other valid variant\(s\):
|
||||
[^ :]+:[0-9]+: Info: fmla za\.s\[w8, 0\], {z0\.s-z1\.s}, z0\.s
|
||||
[^ :]+:[0-9]+: Error: operand mismatch -- `fmla za\[w8,0\],{z0\.d-z1\.d},z0'
|
||||
[^ :]+:[0-9]+: Info: did you mean this\?
|
||||
[^ :]+:[0-9]+: Info: fmla za\.d\[w8, 0\], {z0\.d-z1\.d}, z0\.d
|
||||
[^ :]+:[0-9]+: Info: other valid variant\(s\):
|
||||
[^ :]+:[0-9]+: Info: fmla za\.s\[w8, 0\], {z0\.s-z1\.s}, z0\.s
|
||||
[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmla za\.d\[w7,0\],{z0\.d-z1\.d},{z0\.d-z1\.d}'
|
||||
[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmla za\.d\[w12,0\],{z0\.d-z1\.d},{z0\.d-z1\.d}'
|
||||
[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `fmla za\.d\[w8,-1\],{z0\.d-z1\.d},{z0\.d-z1\.d}'
|
||||
[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `fmla za\.d\[w8,8\],{z0\.d-z1\.d},{z0\.d-z1\.d}'
|
||||
[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `fmla za\.d\[w8,0\],{z1\.d-z2\.d},{z0\.d-z1\.d}'
|
||||
[^ :]+:[0-9]+: Error: start register out of range at operand 3 -- `fmla za\.d\[w8,0\],{z0\.d-z1\.d},{z15\.d-z16\.d}'
|
||||
[^ :]+:[0-9]+: Error: start register out of range at operand 3 -- `fmla za\.d\[w8,0\],{z0\.d-z1\.d},{z31\.d,z0\.d}'
|
||||
[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmla za\.d\[w7,0\],{z0\.d-z3\.d},{z0\.d-z3\.d}'
|
||||
[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmla za\.d\[w12,0\],{z0\.d-z3\.d},{z0\.d-z3\.d}'
|
||||
[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `fmla za\.d\[w8,-1\],{z0\.d-z3\.d},{z0\.d-z3\.d}'
|
||||
[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `fmla za\.d\[w8,8\],{z0\.d-z3\.d},{z0\.d-z3\.d}'
|
||||
[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `fmla za\.d\[w8,0\],{z1\.d-z4\.d},{z0\.d-z3\.d}'
|
||||
[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `fmla za\.d\[w8,0\],{z2\.d-z5\.d},{z0\.d-z3\.d}'
|
||||
[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `fmla za\.d\[w8,0\],{z3\.d-z6\.d},{z0\.d-z3\.d}'
|
||||
[^ :]+:[0-9]+: Error: start register out of range at operand 3 -- `fmla za\.d\[w8,0\],{z0\.d-z3\.d},{z15\.d-z18\.d}'
|
||||
[^ :]+:[0-9]+: Error: start register out of range at operand 3 -- `fmla za\.d\[w8,0\],{z0\.d-z3\.d},{z29\.d,z30\.d,z31\.d,z0\.d}'
|
||||
[^ :]+:[0-9]+: Error: expected a list of 2 or 4 registers at operand 2 -- `fmla za\.d\[w8,0\],{z0\.d-z2\.d},{z0\.d-z1\.d}'
|
||||
[^ :]+:[0-9]+: Error: expected a list of 4 registers at operand 3 -- `fmla za\.d\[w8,0\],{z0\.d-z3\.d},{z0\.d-z1\.d}'
|
||||
[^ :]+:[0-9]+: Error: expected a list of 2 registers at operand 3 -- `fmla za\.d\[w8,0\],{z0\.d-z1\.d},{z0\.d-z2\.d}'
|
||||
[^ :]+:[0-9]+: Error: expected a list of 2 registers at operand 3 -- `fmla za\.d\[w8,0\],{z0\.d-z1\.d},{z0\.d-z3\.d}'
|
||||
[^ :]+:[0-9]+: Error: too many registers in vector register list at operand 3 -- `fmla za\.d\[w8,0\],{z0\.d-z1\.d},{z0\.d-z4\.d}'
|
||||
[^ :]+:[0-9]+: Error: expected a list of 4 registers at operand 2 -- `fmla za\.d\[w8,0,vgx4\],{z0\.d-z1\.d},{z0\.d-z3\.d}'
|
||||
[^ :]+:[0-9]+: Error: expected a list of 4 registers at operand 3 -- `fmla za\.d\[w8,0,vgx4\],{z0\.d-z3\.d},{z0\.d-z1\.d}'
|
||||
[^ :]+:[0-9]+: Error: expected a list of 2 registers at operand 3 -- `fmla za\.d\[w8,0,vgx2\],{z0\.d-z1\.d},{z0\.d-z3\.d}'
|
||||
[^ :]+:[0-9]+: Error: expected a list of 2 registers at operand 2 -- `fmla za\.d\[w8,0,vgx2\],{z0\.d-z3\.d},{z0\.d-z1\.d}'
|
||||
[^ :]+:[0-9]+: Error: operand mismatch -- `fmla za\[w8,0\],{z0\.d-z1\.d},{z0\.d-z1\.d}'
|
||||
[^ :]+:[0-9]+: Info: did you mean this\?
|
||||
[^ :]+:[0-9]+: Info: fmla za\.d\[w8, 0\], {z0\.d-z1\.d}, {z0\.d-z1\.d}
|
||||
[^ :]+:[0-9]+: Info: other valid variant\(s\):
|
||||
[^ :]+:[0-9]+: Info: fmla za\.s\[w8, 0\], {z0\.s-z1\.s}, {z0\.s-z1\.s}
|
||||
[^ :]+:[0-9]+: Error: operand mismatch -- `fmla za\[w8,0\],{z0\.d-z3\.d},{z0\.d-z3\.d}'
|
||||
[^ :]+:[0-9]+: Info: did you mean this\?
|
||||
[^ :]+:[0-9]+: Info: fmla za\.d\[w8, 0\], {z0\.d-z3\.d}, {z0\.d-z3\.d}
|
||||
[^ :]+:[0-9]+: Info: other valid variant\(s\):
|
||||
[^ :]+:[0-9]+: Info: fmla za\.s\[w8, 0\], {z0\.s-z3\.s}, {z0\.s-z3\.s}
|
||||
87
gas/testsuite/gas/aarch64/sme2-f64f64-2-invalid.s
Normal file
87
gas/testsuite/gas/aarch64/sme2-f64f64-2-invalid.s
Normal file
@ -0,0 +1,87 @@
|
||||
fmla za.d[w7, 0], { z0.d - z1.d }, z0.d[0]
|
||||
fmla za.d[w12, 0], { z0.d - z1.d }, z0.d[0]
|
||||
fmla za.d[w8, -1], { z0.d - z1.d }, z0.d[0]
|
||||
fmla za.d[w8, 8], { z0.d - z1.d }, z0.d[0]
|
||||
fmla za.d[w8, 0, vgx4], { z0.d - z1.d }, z0.d[0]
|
||||
fmla za.d[w8, 0], { z0.d - z2.d }, z0.d[0]
|
||||
fmla za.d[w8, 0], { z1.d - z2.d }, z0.d[0]
|
||||
fmla za.d[w8, 0], { z0.d - z1.d }, z16.d[0]
|
||||
fmla za.d[w8, 0], { z0.d - z1.d }, z0.d[-1]
|
||||
fmla za.d[w8, 0], { z0.d - z1.d }, z0.d[2]
|
||||
|
||||
fmla za.d[w7, 0], { z0.d - z3.d }, z0.d[0]
|
||||
fmla za.d[w12, 0], { z0.d - z3.d }, z0.d[0]
|
||||
fmla za.d[w8, -1], { z0.d - z3.d }, z0.d[0]
|
||||
fmla za.d[w8, 8], { z0.d - z3.d }, z0.d[0]
|
||||
fmla za.d[w8, 0, vgx2], { z0.d - z3.d }, z0.d[0]
|
||||
fmla za.d[w8, 0], { z0.d - z4.d }, z0.d[0]
|
||||
fmla za.d[w8, 0], { z1.d - z4.d }, z0.d[0]
|
||||
fmla za.d[w8, 0], { z2.d - z5.d }, z0.d[0]
|
||||
fmla za.d[w8, 0], { z3.d - z6.d }, z0.d[0]
|
||||
fmla za.d[w8, 0], { z0.d - z3.d }, z16.d[0]
|
||||
fmla za.d[w8, 0], { z0.d - z3.d }, z0.d[-1]
|
||||
fmla za.d[w8, 0], { z0.d - z3.d }, z0.d[2]
|
||||
|
||||
fmla za.d[w0, 0], { z0.d - z1.d }, z0.d
|
||||
fmla za.d[w31, 0], { z0.d - z1.d }, z0.d
|
||||
fmla za.d[w8, 1<<63], { z0.d - z1.d }, z0.d
|
||||
fmla za.d[w8, 0], { z0.d - z1.d }, z31.d
|
||||
fmla za.d[w8, 0:0], { z0.d - z1.d }, z0.d
|
||||
fmla za.d[w8, 0:-1], { z0.d - z1.d }, z0.d
|
||||
fmla za.d[w8, 0:1], { z0.d - z1.d }, z0.d
|
||||
fmla za.d[w8, 0:100], { z0.d - z1.d }, z0.d
|
||||
|
||||
fmla za.d[w7, 0], { z0.d - z1.d }, z0.d
|
||||
fmla za.d[w12, 0], { z0.d - z1.d }, z0.d
|
||||
fmla za.d[w8, -1], { z0.d - z1.d }, z0.d
|
||||
fmla za.d[w8, 8], { z0.d - z1.d }, z0.d
|
||||
fmla za.d[w8, 0], { z0.d - z1.d }, z16.d
|
||||
|
||||
fmla za.d[w7, 0], { z0.d - z3.d }, z0.d
|
||||
fmla za.d[w12, 0], { z0.d - z3.d }, z0.d
|
||||
fmla za.d[w8, -1], { z0.d - z3.d }, z0.d
|
||||
fmla za.d[w8, 8], { z0.d - z3.d }, z0.d
|
||||
fmla za.d[w8, 0], { z0.d - z3.d }, z16.d
|
||||
|
||||
fmla za.d[w8, 0], { z0.d - z2.d }, z0.d
|
||||
fmla za.d[w8, 0], { z0.d - z4.d }, z0.d
|
||||
fmla za.d[w8, 0], { z0.d, z1.d, z2.d }, z0.d
|
||||
fmla za.d[w8, 0], { z0.d, z1.d, z5.d }, z0.d
|
||||
|
||||
fmla za.d[w8, 0, vgx4], { z0.d - z1.d }, z0.d
|
||||
fmla za.d[w8, 0, vgx2], { z0.d - z3.d }, z0.d
|
||||
fmla za[w8, 0], { z0.d - z1.d }, z0.d
|
||||
fmla za.d[w8, 0], { z0 - z1 }, z0.d
|
||||
fmla za.d[w8, 0], { z0.d - z1.d }, z0
|
||||
fmla za[w8, 0], { z0.d - z1.d }, z0
|
||||
|
||||
fmla za.d[w7, 0], { z0.d - z1.d }, { z0.d - z1.d }
|
||||
fmla za.d[w12, 0], { z0.d - z1.d }, { z0.d - z1.d }
|
||||
fmla za.d[w8, -1], { z0.d - z1.d }, { z0.d - z1.d }
|
||||
fmla za.d[w8, 8], { z0.d - z1.d }, { z0.d - z1.d }
|
||||
fmla za.d[w8, 0], { z1.d - z2.d }, { z0.d - z1.d }
|
||||
fmla za.d[w8, 0], { z0.d - z1.d }, { z15.d - z16.d }
|
||||
fmla za.d[w8, 0], { z0.d - z1.d }, { z31.d, z0.d }
|
||||
|
||||
fmla za.d[w7, 0], { z0.d - z3.d }, { z0.d - z3.d }
|
||||
fmla za.d[w12, 0], { z0.d - z3.d }, { z0.d - z3.d }
|
||||
fmla za.d[w8, -1], { z0.d - z3.d }, { z0.d - z3.d }
|
||||
fmla za.d[w8, 8], { z0.d - z3.d }, { z0.d - z3.d }
|
||||
fmla za.d[w8, 0], { z1.d - z4.d }, { z0.d - z3.d }
|
||||
fmla za.d[w8, 0], { z2.d - z5.d }, { z0.d - z3.d }
|
||||
fmla za.d[w8, 0], { z3.d - z6.d }, { z0.d - z3.d }
|
||||
fmla za.d[w8, 0], { z0.d - z3.d }, { z15.d - z18.d }
|
||||
fmla za.d[w8, 0], { z0.d - z3.d }, { z29.d, z30.d, z31.d, z0.d }
|
||||
|
||||
fmla za.d[w8, 0], { z0.d - z2.d }, { z0.d - z1.d }
|
||||
fmla za.d[w8, 0], { z0.d - z3.d }, { z0.d - z1.d }
|
||||
fmla za.d[w8, 0], { z0.d - z1.d }, { z0.d - z2.d }
|
||||
fmla za.d[w8, 0], { z0.d - z1.d }, { z0.d - z3.d }
|
||||
fmla za.d[w8, 0], { z0.d - z1.d }, { z0.d - z4.d }
|
||||
|
||||
fmla za.d[w8, 0, vgx4], { z0.d - z1.d }, { z0.d - z3.d }
|
||||
fmla za.d[w8, 0, vgx4], { z0.d - z3.d }, { z0.d - z1.d }
|
||||
fmla za.d[w8, 0, vgx2], { z0.d - z1.d }, { z0.d - z3.d }
|
||||
fmla za.d[w8, 0, vgx2], { z0.d - z3.d }, { z0.d - z1.d }
|
||||
fmla za[w8, 0], { z0.d - z1.d }, { z0.d - z1.d }
|
||||
fmla za[w8, 0], { z0.d - z3.d }, { z0.d - z3.d }
|
||||
3
gas/testsuite/gas/aarch64/sme2-f64f64-2-noarch.d
Normal file
3
gas/testsuite/gas/aarch64/sme2-f64f64-2-noarch.d
Normal file
@ -0,0 +1,3 @@
|
||||
#as: -march=armv8-a+sme2
|
||||
#source: sme2-f64f64-2.s
|
||||
#error_output: sme2-f64f64-2-noarch.l
|
||||
117
gas/testsuite/gas/aarch64/sme2-f64f64-2-noarch.l
Normal file
117
gas/testsuite/gas/aarch64/sme2-f64f64-2-noarch.l
Normal file
@ -0,0 +1,117 @@
|
||||
[^ :]+: Assembler messages:
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.d\[w8,0\],{z0\.d-z1\.d},z0\.d\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.d\[w8,0,vgx2\],{z0\.d-z1\.d},z0\.d\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fmla ZA\.d\[W8,0,VGx2\],{Z0\.d-Z1\.d},Z0\.d\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.d\[w11,0\],{z0\.d-z1\.d},z0\.d\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.d\[w8,7\],{z0\.d-z1\.d},z0\.d\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.d\[w8,0\],{z30\.d-z31\.d},z0\.d\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.d\[w8,0\],{z0\.d-z1\.d},z15\.d\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.d\[w8,0\],{z0\.d-z1\.d},z0\.d\[1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.d\[w10,2\],{z6\.d-z7\.d},z5\.d\[1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.d\[w8,0\],{z0\.d-z3\.d},z0\.d\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.d\[w8,0,vgx4\],{z0\.d-z3\.d},z0\.d\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fmla ZA\.D\[W8,0,VGX4\],{Z0\.D-Z3\.D},Z0\.D\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.d\[w11,0\],{z0\.d-z3\.d},z0\.d\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.d\[w8,7\],{z0\.d-z3\.d},z0\.d\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.d\[w8,0\],{z28\.d-z31\.d},z0\.d\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.d\[w8,0\],{z0\.d-z3\.d},z15\.d\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.d\[w8,0\],{z0\.d-z3\.d},z0\.d\[1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.d\[w9,3\],{z8\.d-z11\.d},z14\.d\[1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.d\[w8,0\],{z0\.d-z1\.d},z0\.d'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.d\[w8,0,vgx2\],{z0\.d-z1\.d},z0\.d'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fmla ZA\.d\[W8,0,VGx2\],{Z0\.d-Z1\.d},Z0\.d'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fmla ZA\.D\[W8,0,VGX2\],{Z0\.D-Z1\.D},Z0\.D'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.d\[w11,0\],{z0\.d-z1\.d},z0\.d'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.d\[w8,7\],{z0\.d-z1\.d},z0\.d'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.d\[w8,0\],{z30\.d-z31\.d},z0\.d'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.d\[w8,0\],{z31\.d,z0\.d},z0\.d'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.d\[w8,0\],{z31\.d-z0\.d},z0\.d'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.d\[w8,0\],{z0\.d-z1\.d},z15\.d'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.d\[w9,5\],{z9\.d-z10\.d},z6\.d'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.d\[w8,0\],{z0\.d-z3\.d},z0\.d'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.d\[w8,0,vgx4\],{z0\.d-z3\.d},z0\.d'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fmla ZA\.d\[W8,0,VGx4\],{Z0\.d-Z3\.d},Z0\.d'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fmla ZA\.D\[W8,0,VGX4\],{Z0\.D-Z3\.D},Z0\.D'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.d\[w11,0\],{z0\.d-z3\.d},z0\.d'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.d\[w8,7\],{z0\.d-z3\.d},z0\.d'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.d\[w8,0\],{z28\.d-z31\.d},z0\.d'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.d\[w8,0\],{z31\.d,z0\.d,z1\.d,z2\.d},z0\.d'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.d\[w8,0\],{z31\.d-z2\.d},z0\.d'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.d\[w8,0\],{z0\.d-z3\.d},z15\.d'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.d\[w11,2\],{z23\.d-z26\.d},z13\.d'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.d\[w8,0\],{z0\.d-z1\.d},{z0\.d-z1\.d}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.d\[w8,0,vgx2\],{z0\.d-z1\.d},{z0\.d-z1\.d}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fmla ZA\.d\[W8,0,VGx2\],{Z0\.d-Z1\.d},{Z0\.d-Z1\.d}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fmla ZA\.D\[W8,0,VGX2\],{Z0\.D-Z1\.D},{Z0\.D-Z1\.D}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.d\[w11,0\],{z0\.d-z1\.d},{z0\.d-z1\.d}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.d\[w8,7\],{z0\.d-z1\.d},{z0\.d-z1\.d}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.d\[w8,0\],{z30\.d-z31\.d},{z0\.d-z1\.d}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.d\[w8,0\],{z0\.d-z1\.d},{z30\.d-z31\.d}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.d\[w10,1\],{z22\.d-z23\.d},{z18\.d-z19\.d}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.d\[w8,0\],{z0\.d-z3\.d},{z0\.d-z3\.d}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.d\[w8,0,vgx4\],{z0\.d-z3\.d},{z0\.d-z3\.d}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fmla ZA\.d\[W8,0,VGx4\],{Z0\.d-Z3\.d},{Z0\.d-Z3\.d}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fmla ZA\.D\[W8,0,VGX4\],{Z0\.D-Z3\.D},{Z0\.D-Z3\.D}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.d\[w11,0\],{z0\.d-z3\.d},{z0\.d-z3\.d}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.d\[w8,7\],{z0\.d-z3\.d},{z0\.d-z3\.d}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.d\[w8,0\],{z28\.d-z31\.d},{z0\.d-z3\.d}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.d\[w8,0\],{z0\.d-z3\.d},{z28\.d-z31\.d}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.d\[w11,3\],{z16\.d-z19\.d},{z24\.d-z27\.d}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.d\[w8,0\],{z0\.d-z1\.d},z0\.d\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.d\[w8,0,vgx2\],{z0\.d-z1\.d},z0\.d\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fmls ZA\.d\[W8,0,VGx2\],{Z0\.d-Z1\.d},Z0\.d\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.d\[w11,0\],{z0\.d-z1\.d},z0\.d\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.d\[w8,7\],{z0\.d-z1\.d},z0\.d\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.d\[w8,0\],{z30\.d-z31\.d},z0\.d\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.d\[w8,0\],{z0\.d-z1\.d},z15\.d\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.d\[w8,0\],{z0\.d-z1\.d},z0\.d\[1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.d\[w10,2\],{z6\.d-z7\.d},z5\.d\[1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.d\[w8,0\],{z0\.d-z3\.d},z0\.d\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.d\[w8,0,vgx4\],{z0\.d-z3\.d},z0\.d\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fmls ZA\.D\[W8,0,VGX4\],{Z0\.D-Z3\.D},Z0\.D\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.d\[w11,0\],{z0\.d-z3\.d},z0\.d\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.d\[w8,7\],{z0\.d-z3\.d},z0\.d\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.d\[w8,0\],{z28\.d-z31\.d},z0\.d\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.d\[w8,0\],{z0\.d-z3\.d},z15\.d\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.d\[w8,0\],{z0\.d-z3\.d},z0\.d\[1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.d\[w9,3\],{z8\.d-z11\.d},z14\.d\[1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.d\[w8,0\],{z0\.d-z1\.d},z0\.d'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.d\[w8,0,vgx2\],{z0\.d-z1\.d},z0\.d'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fmls ZA\.d\[W8,0,VGx2\],{Z0\.d-Z1\.d},Z0\.d'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fmls ZA\.D\[W8,0,VGX2\],{Z0\.D-Z1\.D},Z0\.D'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.d\[w11,0\],{z0\.d-z1\.d},z0\.d'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.d\[w8,7\],{z0\.d-z1\.d},z0\.d'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.d\[w8,0\],{z30\.d-z31\.d},z0\.d'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.d\[w8,0\],{z31\.d,z0\.d},z0\.d'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.d\[w8,0\],{z31\.d-z0\.d},z0\.d'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.d\[w8,0\],{z0\.d-z1\.d},z15\.d'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.d\[w9,5\],{z9\.d-z10\.d},z6\.d'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.d\[w8,0\],{z0\.d-z3\.d},z0\.d'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.d\[w8,0,vgx4\],{z0\.d-z3\.d},z0\.d'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fmls ZA\.d\[W8,0,VGx4\],{Z0\.d-Z3\.d},Z0\.d'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fmls ZA\.D\[W8,0,VGX4\],{Z0\.D-Z3\.D},Z0\.D'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.d\[w11,0\],{z0\.d-z3\.d},z0\.d'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.d\[w8,7\],{z0\.d-z3\.d},z0\.d'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.d\[w8,0\],{z28\.d-z31\.d},z0\.d'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.d\[w8,0\],{z31\.d,z0\.d,z1\.d,z2\.d},z0\.d'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.d\[w8,0\],{z31\.d-z2\.d},z0\.d'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.d\[w8,0\],{z0\.d-z3\.d},z15\.d'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.d\[w11,2\],{z23\.d-z26\.d},z13\.d'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.d\[w8,0\],{z0\.d-z1\.d},{z0\.d-z1\.d}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.d\[w8,0,vgx2\],{z0\.d-z1\.d},{z0\.d-z1\.d}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fmls ZA\.d\[W8,0,VGx2\],{Z0\.d-Z1\.d},{Z0\.d-Z1\.d}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fmls ZA\.D\[W8,0,VGX2\],{Z0\.D-Z1\.D},{Z0\.D-Z1\.D}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.d\[w11,0\],{z0\.d-z1\.d},{z0\.d-z1\.d}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.d\[w8,7\],{z0\.d-z1\.d},{z0\.d-z1\.d}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.d\[w8,0\],{z30\.d-z31\.d},{z0\.d-z1\.d}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.d\[w8,0\],{z0\.d-z1\.d},{z30\.d-z31\.d}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.d\[w10,1\],{z22\.d-z23\.d},{z18\.d-z19\.d}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.d\[w8,0\],{z0\.d-z3\.d},{z0\.d-z3\.d}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.d\[w8,0,vgx4\],{z0\.d-z3\.d},{z0\.d-z3\.d}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fmls ZA\.d\[W8,0,VGx4\],{Z0\.d-Z3\.d},{Z0\.d-Z3\.d}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fmls ZA\.D\[W8,0,VGX4\],{Z0\.D-Z3\.D},{Z0\.D-Z3\.D}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.d\[w11,0\],{z0\.d-z3\.d},{z0\.d-z3\.d}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.d\[w8,7\],{z0\.d-z3\.d},{z0\.d-z3\.d}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.d\[w8,0\],{z28\.d-z31\.d},{z0\.d-z3\.d}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.d\[w8,0\],{z0\.d-z3\.d},{z28\.d-z31\.d}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.d\[w11,3\],{z16\.d-z19\.d},{z24\.d-z27\.d}'
|
||||
125
gas/testsuite/gas/aarch64/sme2-f64f64-2.d
Normal file
125
gas/testsuite/gas/aarch64/sme2-f64f64-2.d
Normal file
@ -0,0 +1,125 @@
|
||||
#as: -march=armv8-a+sme2+sme-f64f64
|
||||
#objdump: -dr
|
||||
|
||||
[^:]+: file format .*
|
||||
|
||||
|
||||
[^:]+:
|
||||
|
||||
[^:]+:
|
||||
[^:]+: c1d00000 fmla za\.d\[w8, 0, vgx2\], {z0\.d-z1\.d}, z0\.d\[0\]
|
||||
[^:]+: c1d00000 fmla za\.d\[w8, 0, vgx2\], {z0\.d-z1\.d}, z0\.d\[0\]
|
||||
[^:]+: c1d00000 fmla za\.d\[w8, 0, vgx2\], {z0\.d-z1\.d}, z0\.d\[0\]
|
||||
[^:]+: c1d06000 fmla za\.d\[w11, 0, vgx2\], {z0\.d-z1\.d}, z0\.d\[0\]
|
||||
[^:]+: c1d00007 fmla za\.d\[w8, 7, vgx2\], {z0\.d-z1\.d}, z0\.d\[0\]
|
||||
[^:]+: c1d003c0 fmla za\.d\[w8, 0, vgx2\], {z30\.d-z31\.d}, z0\.d\[0\]
|
||||
[^:]+: c1df0000 fmla za\.d\[w8, 0, vgx2\], {z0\.d-z1\.d}, z15\.d\[0\]
|
||||
[^:]+: c1d00400 fmla za\.d\[w8, 0, vgx2\], {z0\.d-z1\.d}, z0\.d\[1\]
|
||||
[^:]+: c1d544c2 fmla za\.d\[w10, 2, vgx2\], {z6\.d-z7\.d}, z5\.d\[1\]
|
||||
[^:]+: c1d08000 fmla za\.d\[w8, 0, vgx4\], {z0\.d-z3\.d}, z0\.d\[0\]
|
||||
[^:]+: c1d08000 fmla za\.d\[w8, 0, vgx4\], {z0\.d-z3\.d}, z0\.d\[0\]
|
||||
[^:]+: c1d08000 fmla za\.d\[w8, 0, vgx4\], {z0\.d-z3\.d}, z0\.d\[0\]
|
||||
[^:]+: c1d0e000 fmla za\.d\[w11, 0, vgx4\], {z0\.d-z3\.d}, z0\.d\[0\]
|
||||
[^:]+: c1d08007 fmla za\.d\[w8, 7, vgx4\], {z0\.d-z3\.d}, z0\.d\[0\]
|
||||
[^:]+: c1d08380 fmla za\.d\[w8, 0, vgx4\], {z28\.d-z31\.d}, z0\.d\[0\]
|
||||
[^:]+: c1df8000 fmla za\.d\[w8, 0, vgx4\], {z0\.d-z3\.d}, z15\.d\[0\]
|
||||
[^:]+: c1d08400 fmla za\.d\[w8, 0, vgx4\], {z0\.d-z3\.d}, z0\.d\[1\]
|
||||
[^:]+: c1dea503 fmla za\.d\[w9, 3, vgx4\], {z8\.d-z11\.d}, z14\.d\[1\]
|
||||
[^:]+: c1601800 fmla za\.d\[w8, 0, vgx2\], {z0\.d-z1\.d}, z0\.d
|
||||
[^:]+: c1601800 fmla za\.d\[w8, 0, vgx2\], {z0\.d-z1\.d}, z0\.d
|
||||
[^:]+: c1601800 fmla za\.d\[w8, 0, vgx2\], {z0\.d-z1\.d}, z0\.d
|
||||
[^:]+: c1601800 fmla za\.d\[w8, 0, vgx2\], {z0\.d-z1\.d}, z0\.d
|
||||
[^:]+: c1607800 fmla za\.d\[w11, 0, vgx2\], {z0\.d-z1\.d}, z0\.d
|
||||
[^:]+: c1601807 fmla za\.d\[w8, 7, vgx2\], {z0\.d-z1\.d}, z0\.d
|
||||
[^:]+: c1601bc0 fmla za\.d\[w8, 0, vgx2\], {z30\.d-z31\.d}, z0\.d
|
||||
[^:]+: c1601be0 fmla za\.d\[w8, 0, vgx2\], {z31\.d-z0\.d}, z0\.d
|
||||
[^:]+: c1601be0 fmla za\.d\[w8, 0, vgx2\], {z31\.d-z0\.d}, z0\.d
|
||||
[^:]+: c16f1800 fmla za\.d\[w8, 0, vgx2\], {z0\.d-z1\.d}, z15\.d
|
||||
[^:]+: c1663925 fmla za\.d\[w9, 5, vgx2\], {z9\.d-z10\.d}, z6\.d
|
||||
[^:]+: c1701800 fmla za\.d\[w8, 0, vgx4\], {z0\.d-z3\.d}, z0\.d
|
||||
[^:]+: c1701800 fmla za\.d\[w8, 0, vgx4\], {z0\.d-z3\.d}, z0\.d
|
||||
[^:]+: c1701800 fmla za\.d\[w8, 0, vgx4\], {z0\.d-z3\.d}, z0\.d
|
||||
[^:]+: c1701800 fmla za\.d\[w8, 0, vgx4\], {z0\.d-z3\.d}, z0\.d
|
||||
[^:]+: c1707800 fmla za\.d\[w11, 0, vgx4\], {z0\.d-z3\.d}, z0\.d
|
||||
[^:]+: c1701807 fmla za\.d\[w8, 7, vgx4\], {z0\.d-z3\.d}, z0\.d
|
||||
[^:]+: c1701b80 fmla za\.d\[w8, 0, vgx4\], {z28\.d-z31\.d}, z0\.d
|
||||
[^:]+: c1701be0 fmla za\.d\[w8, 0, vgx4\], {z31\.d-z2\.d}, z0\.d
|
||||
[^:]+: c1701be0 fmla za\.d\[w8, 0, vgx4\], {z31\.d-z2\.d}, z0\.d
|
||||
[^:]+: c17f1800 fmla za\.d\[w8, 0, vgx4\], {z0\.d-z3\.d}, z15\.d
|
||||
[^:]+: c17d7ae2 fmla za\.d\[w11, 2, vgx4\], {z23\.d-z26\.d}, z13\.d
|
||||
[^:]+: c1e01800 fmla za\.d\[w8, 0, vgx2\], {z0\.d-z1\.d}, {z0\.d-z1\.d}
|
||||
[^:]+: c1e01800 fmla za\.d\[w8, 0, vgx2\], {z0\.d-z1\.d}, {z0\.d-z1\.d}
|
||||
[^:]+: c1e01800 fmla za\.d\[w8, 0, vgx2\], {z0\.d-z1\.d}, {z0\.d-z1\.d}
|
||||
[^:]+: c1e01800 fmla za\.d\[w8, 0, vgx2\], {z0\.d-z1\.d}, {z0\.d-z1\.d}
|
||||
[^:]+: c1e07800 fmla za\.d\[w11, 0, vgx2\], {z0\.d-z1\.d}, {z0\.d-z1\.d}
|
||||
[^:]+: c1e01807 fmla za\.d\[w8, 7, vgx2\], {z0\.d-z1\.d}, {z0\.d-z1\.d}
|
||||
[^:]+: c1e01bc0 fmla za\.d\[w8, 0, vgx2\], {z30\.d-z31\.d}, {z0\.d-z1\.d}
|
||||
[^:]+: c1fe1800 fmla za\.d\[w8, 0, vgx2\], {z0\.d-z1\.d}, {z30\.d-z31\.d}
|
||||
[^:]+: c1f25ac1 fmla za\.d\[w10, 1, vgx2\], {z22\.d-z23\.d}, {z18\.d-z19\.d}
|
||||
[^:]+: c1e11800 fmla za\.d\[w8, 0, vgx4\], {z0\.d-z3\.d}, {z0\.d-z3\.d}
|
||||
[^:]+: c1e11800 fmla za\.d\[w8, 0, vgx4\], {z0\.d-z3\.d}, {z0\.d-z3\.d}
|
||||
[^:]+: c1e11800 fmla za\.d\[w8, 0, vgx4\], {z0\.d-z3\.d}, {z0\.d-z3\.d}
|
||||
[^:]+: c1e11800 fmla za\.d\[w8, 0, vgx4\], {z0\.d-z3\.d}, {z0\.d-z3\.d}
|
||||
[^:]+: c1e17800 fmla za\.d\[w11, 0, vgx4\], {z0\.d-z3\.d}, {z0\.d-z3\.d}
|
||||
[^:]+: c1e11807 fmla za\.d\[w8, 7, vgx4\], {z0\.d-z3\.d}, {z0\.d-z3\.d}
|
||||
[^:]+: c1e11b80 fmla za\.d\[w8, 0, vgx4\], {z28\.d-z31\.d}, {z0\.d-z3\.d}
|
||||
[^:]+: c1fd1800 fmla za\.d\[w8, 0, vgx4\], {z0\.d-z3\.d}, {z28\.d-z31\.d}
|
||||
[^:]+: c1f97a03 fmla za\.d\[w11, 3, vgx4\], {z16\.d-z19\.d}, {z24\.d-z27\.d}
|
||||
[^:]+: c1d00010 fmls za\.d\[w8, 0, vgx2\], {z0\.d-z1\.d}, z0\.d\[0\]
|
||||
[^:]+: c1d00010 fmls za\.d\[w8, 0, vgx2\], {z0\.d-z1\.d}, z0\.d\[0\]
|
||||
[^:]+: c1d00010 fmls za\.d\[w8, 0, vgx2\], {z0\.d-z1\.d}, z0\.d\[0\]
|
||||
[^:]+: c1d06010 fmls za\.d\[w11, 0, vgx2\], {z0\.d-z1\.d}, z0\.d\[0\]
|
||||
[^:]+: c1d00017 fmls za\.d\[w8, 7, vgx2\], {z0\.d-z1\.d}, z0\.d\[0\]
|
||||
[^:]+: c1d003d0 fmls za\.d\[w8, 0, vgx2\], {z30\.d-z31\.d}, z0\.d\[0\]
|
||||
[^:]+: c1df0010 fmls za\.d\[w8, 0, vgx2\], {z0\.d-z1\.d}, z15\.d\[0\]
|
||||
[^:]+: c1d00410 fmls za\.d\[w8, 0, vgx2\], {z0\.d-z1\.d}, z0\.d\[1\]
|
||||
[^:]+: c1d544d2 fmls za\.d\[w10, 2, vgx2\], {z6\.d-z7\.d}, z5\.d\[1\]
|
||||
[^:]+: c1d08010 fmls za\.d\[w8, 0, vgx4\], {z0\.d-z3\.d}, z0\.d\[0\]
|
||||
[^:]+: c1d08010 fmls za\.d\[w8, 0, vgx4\], {z0\.d-z3\.d}, z0\.d\[0\]
|
||||
[^:]+: c1d08010 fmls za\.d\[w8, 0, vgx4\], {z0\.d-z3\.d}, z0\.d\[0\]
|
||||
[^:]+: c1d0e010 fmls za\.d\[w11, 0, vgx4\], {z0\.d-z3\.d}, z0\.d\[0\]
|
||||
[^:]+: c1d08017 fmls za\.d\[w8, 7, vgx4\], {z0\.d-z3\.d}, z0\.d\[0\]
|
||||
[^:]+: c1d08390 fmls za\.d\[w8, 0, vgx4\], {z28\.d-z31\.d}, z0\.d\[0\]
|
||||
[^:]+: c1df8010 fmls za\.d\[w8, 0, vgx4\], {z0\.d-z3\.d}, z15\.d\[0\]
|
||||
[^:]+: c1d08410 fmls za\.d\[w8, 0, vgx4\], {z0\.d-z3\.d}, z0\.d\[1\]
|
||||
[^:]+: c1dea513 fmls za\.d\[w9, 3, vgx4\], {z8\.d-z11\.d}, z14\.d\[1\]
|
||||
[^:]+: c1601808 fmls za\.d\[w8, 0, vgx2\], {z0\.d-z1\.d}, z0\.d
|
||||
[^:]+: c1601808 fmls za\.d\[w8, 0, vgx2\], {z0\.d-z1\.d}, z0\.d
|
||||
[^:]+: c1601808 fmls za\.d\[w8, 0, vgx2\], {z0\.d-z1\.d}, z0\.d
|
||||
[^:]+: c1601808 fmls za\.d\[w8, 0, vgx2\], {z0\.d-z1\.d}, z0\.d
|
||||
[^:]+: c1607808 fmls za\.d\[w11, 0, vgx2\], {z0\.d-z1\.d}, z0\.d
|
||||
[^:]+: c160180f fmls za\.d\[w8, 7, vgx2\], {z0\.d-z1\.d}, z0\.d
|
||||
[^:]+: c1601bc8 fmls za\.d\[w8, 0, vgx2\], {z30\.d-z31\.d}, z0\.d
|
||||
[^:]+: c1601be8 fmls za\.d\[w8, 0, vgx2\], {z31\.d-z0\.d}, z0\.d
|
||||
[^:]+: c1601be8 fmls za\.d\[w8, 0, vgx2\], {z31\.d-z0\.d}, z0\.d
|
||||
[^:]+: c16f1808 fmls za\.d\[w8, 0, vgx2\], {z0\.d-z1\.d}, z15\.d
|
||||
[^:]+: c166392d fmls za\.d\[w9, 5, vgx2\], {z9\.d-z10\.d}, z6\.d
|
||||
[^:]+: c1701808 fmls za\.d\[w8, 0, vgx4\], {z0\.d-z3\.d}, z0\.d
|
||||
[^:]+: c1701808 fmls za\.d\[w8, 0, vgx4\], {z0\.d-z3\.d}, z0\.d
|
||||
[^:]+: c1701808 fmls za\.d\[w8, 0, vgx4\], {z0\.d-z3\.d}, z0\.d
|
||||
[^:]+: c1701808 fmls za\.d\[w8, 0, vgx4\], {z0\.d-z3\.d}, z0\.d
|
||||
[^:]+: c1707808 fmls za\.d\[w11, 0, vgx4\], {z0\.d-z3\.d}, z0\.d
|
||||
[^:]+: c170180f fmls za\.d\[w8, 7, vgx4\], {z0\.d-z3\.d}, z0\.d
|
||||
[^:]+: c1701b88 fmls za\.d\[w8, 0, vgx4\], {z28\.d-z31\.d}, z0\.d
|
||||
[^:]+: c1701be8 fmls za\.d\[w8, 0, vgx4\], {z31\.d-z2\.d}, z0\.d
|
||||
[^:]+: c1701be8 fmls za\.d\[w8, 0, vgx4\], {z31\.d-z2\.d}, z0\.d
|
||||
[^:]+: c17f1808 fmls za\.d\[w8, 0, vgx4\], {z0\.d-z3\.d}, z15\.d
|
||||
[^:]+: c17d7aea fmls za\.d\[w11, 2, vgx4\], {z23\.d-z26\.d}, z13\.d
|
||||
[^:]+: c1e01808 fmls za\.d\[w8, 0, vgx2\], {z0\.d-z1\.d}, {z0\.d-z1\.d}
|
||||
[^:]+: c1e01808 fmls za\.d\[w8, 0, vgx2\], {z0\.d-z1\.d}, {z0\.d-z1\.d}
|
||||
[^:]+: c1e01808 fmls za\.d\[w8, 0, vgx2\], {z0\.d-z1\.d}, {z0\.d-z1\.d}
|
||||
[^:]+: c1e01808 fmls za\.d\[w8, 0, vgx2\], {z0\.d-z1\.d}, {z0\.d-z1\.d}
|
||||
[^:]+: c1e07808 fmls za\.d\[w11, 0, vgx2\], {z0\.d-z1\.d}, {z0\.d-z1\.d}
|
||||
[^:]+: c1e0180f fmls za\.d\[w8, 7, vgx2\], {z0\.d-z1\.d}, {z0\.d-z1\.d}
|
||||
[^:]+: c1e01bc8 fmls za\.d\[w8, 0, vgx2\], {z30\.d-z31\.d}, {z0\.d-z1\.d}
|
||||
[^:]+: c1fe1808 fmls za\.d\[w8, 0, vgx2\], {z0\.d-z1\.d}, {z30\.d-z31\.d}
|
||||
[^:]+: c1f25ac9 fmls za\.d\[w10, 1, vgx2\], {z22\.d-z23\.d}, {z18\.d-z19\.d}
|
||||
[^:]+: c1e11808 fmls za\.d\[w8, 0, vgx4\], {z0\.d-z3\.d}, {z0\.d-z3\.d}
|
||||
[^:]+: c1e11808 fmls za\.d\[w8, 0, vgx4\], {z0\.d-z3\.d}, {z0\.d-z3\.d}
|
||||
[^:]+: c1e11808 fmls za\.d\[w8, 0, vgx4\], {z0\.d-z3\.d}, {z0\.d-z3\.d}
|
||||
[^:]+: c1e11808 fmls za\.d\[w8, 0, vgx4\], {z0\.d-z3\.d}, {z0\.d-z3\.d}
|
||||
[^:]+: c1e17808 fmls za\.d\[w11, 0, vgx4\], {z0\.d-z3\.d}, {z0\.d-z3\.d}
|
||||
[^:]+: c1e1180f fmls za\.d\[w8, 7, vgx4\], {z0\.d-z3\.d}, {z0\.d-z3\.d}
|
||||
[^:]+: c1e11b88 fmls za\.d\[w8, 0, vgx4\], {z28\.d-z31\.d}, {z0\.d-z3\.d}
|
||||
[^:]+: c1fd1808 fmls za\.d\[w8, 0, vgx4\], {z0\.d-z3\.d}, {z28\.d-z31\.d}
|
||||
[^:]+: c1f97a0b fmls za\.d\[w11, 3, vgx4\], {z16\.d-z19\.d}, {z24\.d-z27\.d}
|
||||
127
gas/testsuite/gas/aarch64/sme2-f64f64-2.s
Normal file
127
gas/testsuite/gas/aarch64/sme2-f64f64-2.s
Normal file
@ -0,0 +1,127 @@
|
||||
fmla za.d[w8, 0], { z0.d - z1.d }, z0.d[0]
|
||||
fmla za.d[w8, 0, vgx2], { z0.d - z1.d }, z0.d[0]
|
||||
FMLA ZA.d[W8, 0, VGx2], { Z0.d - Z1.d }, Z0.d[0]
|
||||
fmla za.d[w11, 0], { z0.d - z1.d }, z0.d[0]
|
||||
fmla za.d[w8, 7], { z0.d - z1.d }, z0.d[0]
|
||||
fmla za.d[w8, 0], { z30.d - z31.d }, z0.d[0]
|
||||
fmla za.d[w8, 0], { z0.d - z1.d }, z15.d[0]
|
||||
fmla za.d[w8, 0], { z0.d - z1.d }, z0.d[1]
|
||||
fmla za.d[w10, 2], { z6.d - z7.d }, z5.d[1]
|
||||
|
||||
fmla za.d[w8, 0], { z0.d - z3.d }, z0.d[0]
|
||||
fmla za.d[w8, 0, vgx4], { z0.d - z3.d }, z0.d[0]
|
||||
FMLA ZA.D[W8, 0, VGX4], { Z0.D - Z3.D }, Z0.D[0]
|
||||
fmla za.d[w11, 0], { z0.d - z3.d }, z0.d[0]
|
||||
fmla za.d[w8, 7], { z0.d - z3.d }, z0.d[0]
|
||||
fmla za.d[w8, 0], { z28.d - z31.d }, z0.d[0]
|
||||
fmla za.d[w8, 0], { z0.d - z3.d }, z15.d[0]
|
||||
fmla za.d[w8, 0], { z0.d - z3.d }, z0.d[1]
|
||||
fmla za.d[w9, 3], { z8.d - z11.d }, z14.d[1]
|
||||
|
||||
fmla za.d[w8, 0], { z0.d - z1.d }, z0.d
|
||||
fmla za.d[w8, 0, vgx2], { z0.d - z1.d }, z0.d
|
||||
FMLA ZA.d[W8, 0, VGx2], { Z0.d - Z1.d }, Z0.d
|
||||
FMLA ZA.D[W8, 0, VGX2], { Z0.D - Z1.D }, Z0.D
|
||||
fmla za.d[w11, 0], { z0.d - z1.d }, z0.d
|
||||
fmla za.d[w8, 7], { z0.d - z1.d }, z0.d
|
||||
fmla za.d[w8, 0], { z30.d - z31.d }, z0.d
|
||||
fmla za.d[w8, 0], { z31.d, z0.d }, z0.d
|
||||
fmla za.d[w8, 0], { z31.d - z0.d }, z0.d
|
||||
fmla za.d[w8, 0], { z0.d - z1.d }, z15.d
|
||||
fmla za.d[w9, 5], { z9.d - z10.d }, z6.d
|
||||
|
||||
fmla za.d[w8, 0], { z0.d - z3.d }, z0.d
|
||||
fmla za.d[w8, 0, vgx4], { z0.d - z3.d }, z0.d
|
||||
FMLA ZA.d[W8, 0, VGx4], { Z0.d - Z3.d }, Z0.d
|
||||
FMLA ZA.D[W8, 0, VGX4], { Z0.D - Z3.D }, Z0.D
|
||||
fmla za.d[w11, 0], { z0.d - z3.d }, z0.d
|
||||
fmla za.d[w8, 7], { z0.d - z3.d }, z0.d
|
||||
fmla za.d[w8, 0], { z28.d - z31.d }, z0.d
|
||||
fmla za.d[w8, 0], { z31.d, z0.d, z1.d, z2.d }, z0.d
|
||||
fmla za.d[w8, 0], { z31.d - z2.d }, z0.d
|
||||
fmla za.d[w8, 0], { z0.d - z3.d }, z15.d
|
||||
fmla za.d[w11, 2], { z23.d - z26.d }, z13.d
|
||||
|
||||
fmla za.d[w8, 0], { z0.d - z1.d }, { z0.d - z1.d }
|
||||
fmla za.d[w8, 0, vgx2], { z0.d - z1.d }, { z0.d - z1.d }
|
||||
FMLA ZA.d[W8, 0, VGx2], { Z0.d - Z1.d }, { Z0.d - Z1.d }
|
||||
FMLA ZA.D[W8, 0, VGX2], { Z0.D - Z1.D }, { Z0.D - Z1.D }
|
||||
fmla za.d[w11, 0], { z0.d - z1.d }, { z0.d - z1.d }
|
||||
fmla za.d[w8, 7], { z0.d - z1.d }, { z0.d - z1.d }
|
||||
fmla za.d[w8, 0], { z30.d - z31.d }, { z0.d - z1.d }
|
||||
fmla za.d[w8, 0], { z0.d - z1.d }, { z30.d - z31.d }
|
||||
fmla za.d[w10, 1], { z22.d - z23.d }, { z18.d - z19.d }
|
||||
|
||||
fmla za.d[w8, 0], { z0.d - z3.d }, { z0.d - z3.d }
|
||||
fmla za.d[w8, 0, vgx4], { z0.d - z3.d }, { z0.d - z3.d }
|
||||
FMLA ZA.d[W8, 0, VGx4], { Z0.d - Z3.d }, { Z0.d - Z3.d }
|
||||
FMLA ZA.D[W8, 0, VGX4], { Z0.D - Z3.D }, { Z0.D - Z3.D }
|
||||
fmla za.d[w11, 0], { z0.d - z3.d }, { z0.d - z3.d }
|
||||
fmla za.d[w8, 7], { z0.d - z3.d }, { z0.d - z3.d }
|
||||
fmla za.d[w8, 0], { z28.d - z31.d }, { z0.d - z3.d }
|
||||
fmla za.d[w8, 0], { z0.d - z3.d }, { z28.d - z31.d }
|
||||
fmla za.d[w11, 3], { z16.d - z19.d }, { z24.d - z27.d }
|
||||
|
||||
fmls za.d[w8, 0], { z0.d - z1.d }, z0.d[0]
|
||||
fmls za.d[w8, 0, vgx2], { z0.d - z1.d }, z0.d[0]
|
||||
FMLS ZA.d[W8, 0, VGx2], { Z0.d - Z1.d }, Z0.d[0]
|
||||
fmls za.d[w11, 0], { z0.d - z1.d }, z0.d[0]
|
||||
fmls za.d[w8, 7], { z0.d - z1.d }, z0.d[0]
|
||||
fmls za.d[w8, 0], { z30.d - z31.d }, z0.d[0]
|
||||
fmls za.d[w8, 0], { z0.d - z1.d }, z15.d[0]
|
||||
fmls za.d[w8, 0], { z0.d - z1.d }, z0.d[1]
|
||||
fmls za.d[w10, 2], { z6.d - z7.d }, z5.d[1]
|
||||
|
||||
fmls za.d[w8, 0], { z0.d - z3.d }, z0.d[0]
|
||||
fmls za.d[w8, 0, vgx4], { z0.d - z3.d }, z0.d[0]
|
||||
FMLS ZA.D[W8, 0, VGX4], { Z0.D - Z3.D }, Z0.D[0]
|
||||
fmls za.d[w11, 0], { z0.d - z3.d }, z0.d[0]
|
||||
fmls za.d[w8, 7], { z0.d - z3.d }, z0.d[0]
|
||||
fmls za.d[w8, 0], { z28.d - z31.d }, z0.d[0]
|
||||
fmls za.d[w8, 0], { z0.d - z3.d }, z15.d[0]
|
||||
fmls za.d[w8, 0], { z0.d - z3.d }, z0.d[1]
|
||||
fmls za.d[w9, 3], { z8.d - z11.d }, z14.d[1]
|
||||
|
||||
fmls za.d[w8, 0], { z0.d - z1.d }, z0.d
|
||||
fmls za.d[w8, 0, vgx2], { z0.d - z1.d }, z0.d
|
||||
FMLS ZA.d[W8, 0, VGx2], { Z0.d - Z1.d }, Z0.d
|
||||
FMLS ZA.D[W8, 0, VGX2], { Z0.D - Z1.D }, Z0.D
|
||||
fmls za.d[w11, 0], { z0.d - z1.d }, z0.d
|
||||
fmls za.d[w8, 7], { z0.d - z1.d }, z0.d
|
||||
fmls za.d[w8, 0], { z30.d - z31.d }, z0.d
|
||||
fmls za.d[w8, 0], { z31.d, z0.d }, z0.d
|
||||
fmls za.d[w8, 0], { z31.d - z0.d }, z0.d
|
||||
fmls za.d[w8, 0], { z0.d - z1.d }, z15.d
|
||||
fmls za.d[w9, 5], { z9.d - z10.d }, z6.d
|
||||
|
||||
fmls za.d[w8, 0], { z0.d - z3.d }, z0.d
|
||||
fmls za.d[w8, 0, vgx4], { z0.d - z3.d }, z0.d
|
||||
FMLS ZA.d[W8, 0, VGx4], { Z0.d - Z3.d }, Z0.d
|
||||
FMLS ZA.D[W8, 0, VGX4], { Z0.D - Z3.D }, Z0.D
|
||||
fmls za.d[w11, 0], { z0.d - z3.d }, z0.d
|
||||
fmls za.d[w8, 7], { z0.d - z3.d }, z0.d
|
||||
fmls za.d[w8, 0], { z28.d - z31.d }, z0.d
|
||||
fmls za.d[w8, 0], { z31.d, z0.d, z1.d, z2.d }, z0.d
|
||||
fmls za.d[w8, 0], { z31.d - z2.d }, z0.d
|
||||
fmls za.d[w8, 0], { z0.d - z3.d }, z15.d
|
||||
fmls za.d[w11, 2], { z23.d - z26.d }, z13.d
|
||||
|
||||
fmls za.d[w8, 0], { z0.d - z1.d }, { z0.d - z1.d }
|
||||
fmls za.d[w8, 0, vgx2], { z0.d - z1.d }, { z0.d - z1.d }
|
||||
FMLS ZA.d[W8, 0, VGx2], { Z0.d - Z1.d }, { Z0.d - Z1.d }
|
||||
FMLS ZA.D[W8, 0, VGX2], { Z0.D - Z1.D }, { Z0.D - Z1.D }
|
||||
fmls za.d[w11, 0], { z0.d - z1.d }, { z0.d - z1.d }
|
||||
fmls za.d[w8, 7], { z0.d - z1.d }, { z0.d - z1.d }
|
||||
fmls za.d[w8, 0], { z30.d - z31.d }, { z0.d - z1.d }
|
||||
fmls za.d[w8, 0], { z0.d - z1.d }, { z30.d - z31.d }
|
||||
fmls za.d[w10, 1], { z22.d - z23.d }, { z18.d - z19.d }
|
||||
|
||||
fmls za.d[w8, 0], { z0.d - z3.d }, { z0.d - z3.d }
|
||||
fmls za.d[w8, 0, vgx4], { z0.d - z3.d }, { z0.d - z3.d }
|
||||
FMLS ZA.d[W8, 0, VGx4], { Z0.d - Z3.d }, { Z0.d - Z3.d }
|
||||
FMLS ZA.D[W8, 0, VGX4], { Z0.D - Z3.D }, { Z0.D - Z3.D }
|
||||
fmls za.d[w11, 0], { z0.d - z3.d }, { z0.d - z3.d }
|
||||
fmls za.d[w8, 7], { z0.d - z3.d }, { z0.d - z3.d }
|
||||
fmls za.d[w8, 0], { z28.d - z31.d }, { z0.d - z3.d }
|
||||
fmls za.d[w8, 0], { z0.d - z3.d }, { z28.d - z31.d }
|
||||
fmls za.d[w11, 3], { z16.d - z19.d }, { z24.d - z27.d }
|
||||
@ -516,6 +516,8 @@ enum aarch64_opnd
|
||||
AARCH64_OPND_SME_ADDR_RI_U4xVL, /* SME [<Xn|SP>{, #<imm>, MUL VL}]. */
|
||||
AARCH64_OPND_SME_SM_ZA, /* SME {SM | ZA}. */
|
||||
AARCH64_OPND_SME_PnT_Wm_imm, /* SME <Pn>.<T>[<Wm>, #<imm>]. */
|
||||
AARCH64_OPND_SME_Zm_INDEX1, /* Zn.T[index], bits [19:16,10]. */
|
||||
AARCH64_OPND_SME_Zm_INDEX2, /* Zn.T[index], bits [19:16,11:10]. */
|
||||
AARCH64_OPND_SME_Zn_INDEX1_16, /* Zn[index], bits [9:5] and [16:16]. */
|
||||
AARCH64_OPND_SME_Zn_INDEX2_15, /* Zn[index], bits [9:5] and [16:15]. */
|
||||
AARCH64_OPND_SME_Zn_INDEX2_16, /* Zn[index], bits [9:5] and [17:16]. */
|
||||
|
||||
@ -685,7 +685,7 @@ aarch64_insert_operand (const aarch64_operand *self,
|
||||
case 33:
|
||||
case 34:
|
||||
case 35:
|
||||
case 257:
|
||||
case 259:
|
||||
return aarch64_ins_reglane (self, info, code, inst, errors);
|
||||
case 36:
|
||||
return aarch64_ins_reglist (self, info, code, inst, errors);
|
||||
@ -731,12 +731,12 @@ aarch64_insert_operand (const aarch64_operand *self,
|
||||
case 193:
|
||||
case 194:
|
||||
case 237:
|
||||
case 251:
|
||||
case 252:
|
||||
case 253:
|
||||
case 254:
|
||||
case 256:
|
||||
case 261:
|
||||
case 262:
|
||||
case 258:
|
||||
case 263:
|
||||
case 264:
|
||||
return aarch64_ins_imm (self, info, code, inst, errors);
|
||||
case 44:
|
||||
case 45:
|
||||
@ -805,8 +805,8 @@ aarch64_insert_operand (const aarch64_operand *self,
|
||||
case 107:
|
||||
return aarch64_ins_prfop (self, info, code, inst, errors);
|
||||
case 108:
|
||||
case 253:
|
||||
case 255:
|
||||
case 257:
|
||||
return aarch64_ins_none (self, info, code, inst, errors);
|
||||
case 109:
|
||||
return aarch64_ins_hint (self, info, code, inst, errors);
|
||||
@ -925,6 +925,8 @@ aarch64_insert_operand (const aarch64_operand *self,
|
||||
case 248:
|
||||
case 249:
|
||||
case 250:
|
||||
case 251:
|
||||
case 252:
|
||||
return aarch64_ins_simple_index (self, info, code, inst, errors);
|
||||
case 239:
|
||||
case 240:
|
||||
@ -936,9 +938,9 @@ aarch64_insert_operand (const aarch64_operand *self,
|
||||
return aarch64_ins_sme_sm_za (self, info, code, inst, errors);
|
||||
case 244:
|
||||
return aarch64_ins_sme_pred_reg_with_index (self, info, code, inst, errors);
|
||||
case 258:
|
||||
case 259:
|
||||
case 260:
|
||||
case 261:
|
||||
case 262:
|
||||
return aarch64_ins_x0_to_x30 (self, info, code, inst, errors);
|
||||
default: assert (0); abort ();
|
||||
}
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -269,6 +269,8 @@ const struct aarch64_operand aarch64_operands[] =
|
||||
{AARCH64_OPND_CLASS_ADDRESS, "SME_ADDR_RI_U4xVL", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_imm4_0}, "memory offset"},
|
||||
{AARCH64_OPND_CLASS_ADDRESS, "SME_SM_ZA", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_CRm}, "streaming mode"},
|
||||
{AARCH64_OPND_CLASS_SVE_REG, "SME_PnT_Wm_imm", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Rm,FLD_SVE_Pn,FLD_SME_i1,FLD_SME_tszh,FLD_SME_tszl}, "Source scalable predicate register with index "},
|
||||
{AARCH64_OPND_CLASS_SVE_REG, "SME_Zm_INDEX1", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Zm, FLD_imm1_10}, "an indexed SVE vector register"},
|
||||
{AARCH64_OPND_CLASS_SVE_REG, "SME_Zm_INDEX2", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Zm, FLD_imm2_10}, "an indexed SVE vector register"},
|
||||
{AARCH64_OPND_CLASS_SVE_REG, "SME_Zn_INDEX1_16", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zn, FLD_imm1_16}, "an indexed SVE vector register"},
|
||||
{AARCH64_OPND_CLASS_SVE_REG, "SME_Zn_INDEX2_15", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zn, FLD_imm2_15}, "an indexed SVE vector register"},
|
||||
{AARCH64_OPND_CLASS_SVE_REG, "SME_Zn_INDEX2_16", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zn, FLD_imm2_16}, "an indexed SVE vector register"},
|
||||
|
||||
@ -320,8 +320,10 @@ const aarch64_field fields[] =
|
||||
{ 5, 5 }, /* defgh: d:e:f:g:h bits in AdvSIMD modified immediate. */
|
||||
{ 21, 2 }, /* hw: in move wide constant instructions. */
|
||||
{ 8, 1 }, /* imm1_8: general immediate in bits [8]. */
|
||||
{ 10, 1 }, /* imm1_10: general immediate in bits [10]. */
|
||||
{ 16, 1 }, /* imm1_16: general immediate in bits [16]. */
|
||||
{ 8, 2 }, /* imm2_8: general immediate in bits [9:8]. */
|
||||
{ 10, 2 }, /* imm2_10: 2-bit immediate, bits [11:10] */
|
||||
{ 15, 2 }, /* imm2_15: 2-bit immediate, bits [16:15] */
|
||||
{ 16, 2 }, /* imm2_16: 2-bit immediate, bits [17:16] */
|
||||
{ 0, 3 }, /* imm3_0: general immediate in bits [2:0]. */
|
||||
@ -1765,6 +1767,14 @@ operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx,
|
||||
return 0;
|
||||
break;
|
||||
|
||||
case AARCH64_OPND_SME_Zm_INDEX1:
|
||||
case AARCH64_OPND_SME_Zm_INDEX2:
|
||||
size = get_operand_fields_width (get_operand_from_code (type)) - 4;
|
||||
if (!check_reglane (opnd, mismatch_detail, idx, "z", 0, 15,
|
||||
0, (1 << size) - 1))
|
||||
return 0;
|
||||
break;
|
||||
|
||||
case AARCH64_OPND_SME_Zm:
|
||||
if (opnd->reg.regno > 15)
|
||||
{
|
||||
@ -3926,6 +3936,8 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc,
|
||||
case AARCH64_OPND_SVE_Zm4_11_INDEX:
|
||||
case AARCH64_OPND_SVE_Zm4_INDEX:
|
||||
case AARCH64_OPND_SVE_Zn_INDEX:
|
||||
case AARCH64_OPND_SME_Zm_INDEX1:
|
||||
case AARCH64_OPND_SME_Zm_INDEX2:
|
||||
case AARCH64_OPND_SME_Zn_INDEX1_16:
|
||||
case AARCH64_OPND_SME_Zn_INDEX2_15:
|
||||
case AARCH64_OPND_SME_Zn_INDEX2_16:
|
||||
|
||||
@ -141,8 +141,10 @@ enum aarch64_field_kind
|
||||
FLD_defgh,
|
||||
FLD_hw,
|
||||
FLD_imm1_8,
|
||||
FLD_imm1_10,
|
||||
FLD_imm1_16,
|
||||
FLD_imm2_8,
|
||||
FLD_imm2_10,
|
||||
FLD_imm2_15,
|
||||
FLD_imm2_16,
|
||||
FLD_imm3_0,
|
||||
|
||||
@ -2509,6 +2509,8 @@ static const aarch64_feature_set aarch64_feature_sme_i16i64 =
|
||||
static const aarch64_feature_set aarch64_feature_sme2 =
|
||||
AARCH64_FEATURE (AARCH64_FEATURE_SVE2 | AARCH64_FEATURE_SME
|
||||
| AARCH64_FEATURE_SME2, 0);
|
||||
static const aarch64_feature_set aarch64_feature_sme2_f64f64 =
|
||||
AARCH64_FEATURE (AARCH64_FEATURE_SME2 | AARCH64_FEATURE_SME_F64F64, 0);
|
||||
static const aarch64_feature_set aarch64_feature_v8_6 =
|
||||
AARCH64_FEATURE (AARCH64_FEATURE_V8_6, 0);
|
||||
static const aarch64_feature_set aarch64_feature_v8_7 =
|
||||
@ -2578,6 +2580,7 @@ static const aarch64_feature_set aarch64_feature_cssc =
|
||||
#define SME_F64F64 &aarch64_feature_sme_f64f64
|
||||
#define SME_I16I64 &aarch64_feature_sme_i16i64
|
||||
#define SME2 &aarch64_feature_sme2
|
||||
#define SME2_F64F64 &aarch64_feature_sme2_f64f64
|
||||
#define ARMV8_6 &aarch64_feature_v8_6
|
||||
#define ARMV8_6_SVE &aarch64_feature_v8_6
|
||||
#define BFLOAT16_SVE &aarch64_feature_bfloat16_sve
|
||||
@ -2692,6 +2695,9 @@ static const aarch64_feature_set aarch64_feature_cssc =
|
||||
#define SME2_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,TIED) \
|
||||
{ NAME, OPCODE, MASK, CLASS, OP, SME2, OPS, QUALS, \
|
||||
F_STRICT | FLAGS, 0, TIED, NULL }
|
||||
#define SME2_F64F64_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,TIED) \
|
||||
{ NAME, OPCODE, MASK, CLASS, OP, SME2_F64F64, OPS, QUALS, \
|
||||
F_STRICT | FLAGS, 0, TIED, NULL }
|
||||
#define SVE2BITPERM_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,TIED) \
|
||||
{ NAME, OPCODE, MASK, CLASS, OP, SVE2_BITPERM, OPS, QUALS, \
|
||||
FLAGS | F_STRICT, 0, TIED, NULL }
|
||||
@ -5352,6 +5358,18 @@ const struct aarch64_opcode aarch64_opcode_table[] =
|
||||
SME2_INSN ("fminnm", 0xc120a921, 0xff30ffe3, sme_size_22_hsd, 0, OP3 (SME_Zdnx4, SME_Zdnx4, SME_Zm), OP_SVE_VVV_HSD, 0, 1),
|
||||
SME2_INSN ("fminnm", 0xc120b121, 0xff21ffe1, sme_size_22_hsd, 0, OP3 (SME_Zdnx2, SME_Zdnx2, SME_Zmx2), OP_SVE_VVV_HSD, 0, 1),
|
||||
SME2_INSN ("fminnm", 0xc120b921, 0xff23ffe3, sme_size_22_hsd, 0, OP3 (SME_Zdnx4, SME_Zdnx4, SME_Zmx4), OP_SVE_VVV_HSD, 0, 1),
|
||||
SME2_INSN ("fmla", 0xc1500000, 0xfff09038, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SME_Znx2, SME_Zm_INDEX2), OP_SVE_SSS, F_OD (2), 0),
|
||||
SME2_INSN ("fmla", 0xc1508000, 0xfff09078, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SME_Znx4, SME_Zm_INDEX2), OP_SVE_SSS, F_OD (4), 0),
|
||||
SME2_INSN ("fmla", 0xc1201800, 0xffb09c18, sme_fp_sd, 0, OP3 (SME_ZA_array_off3_0, SVE_ZnxN, SME_Zm), OP_SVE_VVV_SD, F_OD (2), 0),
|
||||
SME2_INSN ("fmla", 0xc1301800, 0xffb09c18, sme_fp_sd, 0, OP3 (SME_ZA_array_off3_0, SVE_ZnxN, SME_Zm), OP_SVE_VVV_SD, F_OD (4), 0),
|
||||
SME2_INSN ("fmla", 0xc1a01800, 0xffa19c38, sme_fp_sd, 0, OP3 (SME_ZA_array_off3_0, SME_Znx2, SME_Zmx2), OP_SVE_VVV_SD, F_OD (2), 0),
|
||||
SME2_INSN ("fmla", 0xc1a11800, 0xffa39c78, sme_fp_sd, 0, OP3 (SME_ZA_array_off3_0, SME_Znx4, SME_Zmx4), OP_SVE_VVV_SD, F_OD (4), 0),
|
||||
SME2_INSN ("fmls", 0xc1500010, 0xfff09038, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SME_Znx2, SME_Zm_INDEX2), OP_SVE_SSS, F_OD (2), 0),
|
||||
SME2_INSN ("fmls", 0xc1508010, 0xfff09078, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SME_Znx4, SME_Zm_INDEX2), OP_SVE_SSS, F_OD (4), 0),
|
||||
SME2_INSN ("fmls", 0xc1201808, 0xffb09c18, sme_fp_sd, 0, OP3 (SME_ZA_array_off3_0, SVE_ZnxN, SME_Zm), OP_SVE_VVV_SD, F_OD (2), 0),
|
||||
SME2_INSN ("fmls", 0xc1301808, 0xffb09c18, sme_fp_sd, 0, OP3 (SME_ZA_array_off3_0, SVE_ZnxN, SME_Zm), OP_SVE_VVV_SD, F_OD (4), 0),
|
||||
SME2_INSN ("fmls", 0xc1a01808, 0xffa19c38, sme_fp_sd, 0, OP3 (SME_ZA_array_off3_0, SME_Znx2, SME_Zmx2), OP_SVE_VVV_SD, F_OD (2), 0),
|
||||
SME2_INSN ("fmls", 0xc1a11808, 0xffa39c78, sme_fp_sd, 0, OP3 (SME_ZA_array_off3_0, SME_Znx4, SME_Zmx4), OP_SVE_VVV_SD, F_OD (4), 0),
|
||||
SME2_INSN ("fsub", 0xc1a01c08, 0xffbf9c38, sme_fp_sd, 0, OP2 (SME_ZA_array_off3_0, SME_Znx2), OP_SVE_VVV_SD, F_OD (2), 0),
|
||||
SME2_INSN ("fsub", 0xc1a11c08, 0xffbf9c78, sme_fp_sd, 0, OP2 (SME_ZA_array_off3_0, SME_Znx4), OP_SVE_VVV_SD, F_OD (4), 0),
|
||||
SME2_INSN ("ld1b", 0xa0400000, 0xfff0e001, sve_misc, 0, OP3 (SME_Zdnx2, SME_PNg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_BZU, 0, 0),
|
||||
@ -5557,6 +5575,12 @@ const struct aarch64_opcode aarch64_opcode_table[] =
|
||||
SME2_INSN ("whilelt", 0x25204410, 0xff20dc18, sme_size_22, 0, OP4 (SME_PNd3, Rn, Rm, SME_VLxN_13), OP_SVE_VXXU_BHSD, 0, 0),
|
||||
SME2_INSN ("zero", 0xc0480001, 0xffffffff, sme_misc, 0, OP1 (SME_ZT0_LIST), {}, 0, 0),
|
||||
|
||||
/* SME2 F64F64 instructions. */
|
||||
SME2_F64F64_INSN ("fmla", 0xc1d00000, 0xfff09838, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SME_Znx2, SME_Zm_INDEX1), OP_SVE_DDD, F_OD (2), 0),
|
||||
SME2_F64F64_INSN ("fmla", 0xc1d08000, 0xfff09878, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SME_Znx4, SME_Zm_INDEX1), OP_SVE_DDD, F_OD (4), 0),
|
||||
SME2_F64F64_INSN ("fmls", 0xc1d00010, 0xfff09838, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SME_Znx2, SME_Zm_INDEX1), OP_SVE_DDD, F_OD (2), 0),
|
||||
SME2_F64F64_INSN ("fmls", 0xc1d08010, 0xfff09878, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SME_Znx4, SME_Zm_INDEX1), OP_SVE_DDD, F_OD (4), 0),
|
||||
|
||||
/* SIMD Dot Product (optional in v8.2-A). */
|
||||
DOT_INSN ("udot", 0x2e009400, 0xbf20fc00, dotproduct, OP3 (Vd, Vn, Vm), QL_V3DOT, F_SIZEQ),
|
||||
DOT_INSN ("sdot", 0xe009400, 0xbf20fc00, dotproduct, OP3 (Vd, Vn, Vm), QL_V3DOT, F_SIZEQ),
|
||||
@ -6268,6 +6292,10 @@ const struct aarch64_opcode aarch64_opcode_table[] =
|
||||
Y(SVE_REG, sme_pred_reg_with_index, "SME_PnT_Wm_imm", 0, \
|
||||
F(FLD_SME_Rm,FLD_SVE_Pn,FLD_SME_i1,FLD_SME_tszh,FLD_SME_tszl), \
|
||||
"Source scalable predicate register with index ") \
|
||||
Y(SVE_REG, simple_index, "SME_Zm_INDEX1", 0, \
|
||||
F(FLD_SME_Zm, FLD_imm1_10), "an indexed SVE vector register") \
|
||||
Y(SVE_REG, simple_index, "SME_Zm_INDEX2", 0, \
|
||||
F(FLD_SME_Zm, FLD_imm2_10), "an indexed SVE vector register") \
|
||||
Y(SVE_REG, simple_index, "SME_Zn_INDEX1_16", 0, \
|
||||
F(FLD_SVE_Zn, FLD_imm1_16), "an indexed SVE vector register") \
|
||||
Y(SVE_REG, simple_index, "SME_Zn_INDEX2_15", 0, \
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user