x86: Encode AVX256/AVX512 vpsub[bwdq] with VEX128/EVEX128
When 2 source registers are identical, AVX256 and AVX512 vpsub[bwdq] instructions can be encoded with VEX128 or EVEX128 encodings. gas/ * config/tc-i386.c (optimize_encoding): Optimize AVX256 and AVX512 vpsub[bwdq] instructions. * testsuite/gas/i386/optimize-1.s: Add tests for AVX256 and AVX512 vpsub[bwdq] instructions. * testsuite/gas/i386/x86-64-optimize-2.s: Likewise. * testsuite/gas/i386/optimize-1.d: Updated. * testsuite/gas/i386/x86-64-optimize-2.d: Likewise. opcodes/ * * i386-opc.tbl: Add "Optimize" to AVX256 and AVX512 vpsub[bwdq] instructions. * i386-tbl.h: Regenerated.
This commit is contained in:
H.J. Lu
parent
b1223e7890
commit
8305403a1f
@ -1,3 +1,13 @@
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2018-03-01 H.J. Lu <hongjiu.lu@intel.com>
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* config/tc-i386.c (optimize_encoding): Optimize AVX256 and
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AVX512 vpsub[bwdq] instructions.
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* testsuite/gas/i386/optimize-1.s: Add tests for AVX256 and
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AVX512 vpsub[bwdq] instructions.
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* testsuite/gas/i386/x86-64-optimize-2.s: Likewise.
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* testsuite/gas/i386/optimize-1.d: Updated.
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* testsuite/gas/i386/x86-64-optimize-2.d: Likewise.
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2018-03-01 Alan Modra <amodra@gmail.com>
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* configure.ac (ALL_LINGUAS): Add uk. Sort.
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@ -3856,11 +3856,16 @@ optimize_encoding (void)
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|| i.tm.base_opcode == 0x66df
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|| i.tm.base_opcode == 0x57
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|| i.tm.base_opcode == 0x6657
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|| i.tm.base_opcode == 0x66ef)
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|| i.tm.base_opcode == 0x66ef
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|| i.tm.base_opcode == 0x66f8
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|| i.tm.base_opcode == 0x66f9
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|| i.tm.base_opcode == 0x66fa
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|| i.tm.base_opcode == 0x66fb)
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&& i.tm.extension_opcode == None))
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{
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/* Optimize: -O2:
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VOP, one of vandnps, vandnpd, vxorps and vxorpd:
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VOP, one of vandnps, vandnpd, vxorps, vxorpd, vpsubb, vpsubd,
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vpsubq and vpsubw:
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EVEX VOP %zmmM, %zmmM, %zmmN
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-> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
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-> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
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@ -42,4 +42,20 @@ Disassembly of section .text:
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+[a-f0-9]+: 62 f1 f5 af ef e9 vpxorq %ymm1,%ymm1,%ymm5\{%k7\}\{z\}
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+[a-f0-9]+: c5 f1 ef e9 vpxor %xmm1,%xmm1,%xmm5
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+[a-f0-9]+: c5 f1 ef e9 vpxor %xmm1,%xmm1,%xmm5
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+[a-f0-9]+: 62 f1 75 4f f8 e9 vpsubb %zmm1,%zmm1,%zmm5\{%k7\}
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+[a-f0-9]+: 62 f1 75 af f8 e9 vpsubb %ymm1,%ymm1,%ymm5\{%k7\}\{z\}
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+[a-f0-9]+: c5 f1 f8 e9 vpsubb %xmm1,%xmm1,%xmm5
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+[a-f0-9]+: c5 f1 f8 e9 vpsubb %xmm1,%xmm1,%xmm5
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+[a-f0-9]+: 62 f1 75 4f f9 e9 vpsubw %zmm1,%zmm1,%zmm5\{%k7\}
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+[a-f0-9]+: 62 f1 75 af f9 e9 vpsubw %ymm1,%ymm1,%ymm5\{%k7\}\{z\}
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+[a-f0-9]+: c5 f1 f9 e9 vpsubw %xmm1,%xmm1,%xmm5
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+[a-f0-9]+: c5 f1 f9 e9 vpsubw %xmm1,%xmm1,%xmm5
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+[a-f0-9]+: 62 f1 75 4f fa e9 vpsubd %zmm1,%zmm1,%zmm5\{%k7\}
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+[a-f0-9]+: 62 f1 75 af fa e9 vpsubd %ymm1,%ymm1,%ymm5\{%k7\}\{z\}
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+[a-f0-9]+: c5 f1 fa e9 vpsubd %xmm1,%xmm1,%xmm5
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+[a-f0-9]+: c5 f1 fa e9 vpsubd %xmm1,%xmm1,%xmm5
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+[a-f0-9]+: 62 f1 f5 4f fb e9 vpsubq %zmm1,%zmm1,%zmm5\{%k7\}
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+[a-f0-9]+: 62 f1 f5 af fb e9 vpsubq %ymm1,%ymm1,%ymm5\{%k7\}\{z\}
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+[a-f0-9]+: c5 f1 fb e9 vpsubq %xmm1,%xmm1,%xmm5
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+[a-f0-9]+: c5 f1 fb e9 vpsubq %xmm1,%xmm1,%xmm5
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#pass
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@ -46,3 +46,23 @@ _start:
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vpxorq %ymm1, %ymm1, %ymm5{z}{%k7}
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vpxorq %zmm1, %zmm1, %zmm5
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vpxorq %ymm1, %ymm1, %ymm5
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vpsubb %zmm1, %zmm1, %zmm5{%k7}
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vpsubb %ymm1, %ymm1, %ymm5{z}{%k7}
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vpsubb %zmm1, %zmm1, %zmm5
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vpsubb %ymm1, %ymm1, %ymm5
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vpsubw %zmm1, %zmm1, %zmm5{%k7}
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vpsubw %ymm1, %ymm1, %ymm5{z}{%k7}
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vpsubw %zmm1, %zmm1, %zmm5
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vpsubw %ymm1, %ymm1, %ymm5
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vpsubd %zmm1, %zmm1, %zmm5{%k7}
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vpsubd %ymm1, %ymm1, %ymm5{z}{%k7}
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vpsubd %zmm1, %zmm1, %zmm5
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vpsubd %ymm1, %ymm1, %ymm5
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vpsubq %zmm1, %zmm1, %zmm5{%k7}
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vpsubq %ymm1, %ymm1, %ymm5{z}{%k7}
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vpsubq %zmm1, %zmm1, %zmm5
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vpsubq %ymm1, %ymm1, %ymm5
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@ -74,4 +74,36 @@ Disassembly of section .text:
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+[a-f0-9]+: 62 e1 f5 08 ef c1 vpxorq %xmm1,%xmm1,%xmm16
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+[a-f0-9]+: 62 b1 f5 00 ef c9 vpxorq %xmm17,%xmm17,%xmm1
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+[a-f0-9]+: 62 b1 f5 00 ef c9 vpxorq %xmm17,%xmm17,%xmm1
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+[a-f0-9]+: 62 71 75 4f f8 f9 vpsubb %zmm1,%zmm1,%zmm15\{%k7\}
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+[a-f0-9]+: 62 71 75 af f8 f9 vpsubb %ymm1,%ymm1,%ymm15\{%k7\}\{z\}
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+[a-f0-9]+: c5 71 f8 f9 vpsubb %xmm1,%xmm1,%xmm15
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+[a-f0-9]+: c5 71 f8 f9 vpsubb %xmm1,%xmm1,%xmm15
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+[a-f0-9]+: 62 e1 75 08 f8 c1 vpsubb %xmm1,%xmm1,%xmm16
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+[a-f0-9]+: 62 e1 75 08 f8 c1 vpsubb %xmm1,%xmm1,%xmm16
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+[a-f0-9]+: 62 b1 75 00 f8 c9 vpsubb %xmm17,%xmm17,%xmm1
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+[a-f0-9]+: 62 b1 75 00 f8 c9 vpsubb %xmm17,%xmm17,%xmm1
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+[a-f0-9]+: 62 71 75 4f f9 f9 vpsubw %zmm1,%zmm1,%zmm15\{%k7\}
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+[a-f0-9]+: 62 71 75 af f9 f9 vpsubw %ymm1,%ymm1,%ymm15\{%k7\}\{z\}
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+[a-f0-9]+: c5 71 f9 f9 vpsubw %xmm1,%xmm1,%xmm15
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+[a-f0-9]+: c5 71 f9 f9 vpsubw %xmm1,%xmm1,%xmm15
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+[a-f0-9]+: 62 e1 75 08 f9 c1 vpsubw %xmm1,%xmm1,%xmm16
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+[a-f0-9]+: 62 e1 75 08 f9 c1 vpsubw %xmm1,%xmm1,%xmm16
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+[a-f0-9]+: 62 b1 75 00 f9 c9 vpsubw %xmm17,%xmm17,%xmm1
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+[a-f0-9]+: 62 b1 75 00 f9 c9 vpsubw %xmm17,%xmm17,%xmm1
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+[a-f0-9]+: 62 71 75 4f fa f9 vpsubd %zmm1,%zmm1,%zmm15\{%k7\}
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+[a-f0-9]+: 62 71 75 af fa f9 vpsubd %ymm1,%ymm1,%ymm15\{%k7\}\{z\}
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+[a-f0-9]+: c5 71 fa f9 vpsubd %xmm1,%xmm1,%xmm15
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+[a-f0-9]+: c5 71 fa f9 vpsubd %xmm1,%xmm1,%xmm15
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+[a-f0-9]+: 62 e1 75 08 fa c1 vpsubd %xmm1,%xmm1,%xmm16
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+[a-f0-9]+: 62 e1 75 08 fa c1 vpsubd %xmm1,%xmm1,%xmm16
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+[a-f0-9]+: 62 b1 75 00 fa c9 vpsubd %xmm17,%xmm17,%xmm1
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+[a-f0-9]+: 62 b1 75 00 fa c9 vpsubd %xmm17,%xmm17,%xmm1
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+[a-f0-9]+: 62 71 f5 4f fb f9 vpsubq %zmm1,%zmm1,%zmm15\{%k7\}
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+[a-f0-9]+: 62 71 f5 af fb f9 vpsubq %ymm1,%ymm1,%ymm15\{%k7\}\{z\}
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+[a-f0-9]+: c5 71 fb f9 vpsubq %xmm1,%xmm1,%xmm15
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+[a-f0-9]+: c5 71 fb f9 vpsubq %xmm1,%xmm1,%xmm15
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+[a-f0-9]+: 62 e1 f5 08 fb c1 vpsubq %xmm1,%xmm1,%xmm16
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+[a-f0-9]+: 62 e1 f5 08 fb c1 vpsubq %xmm1,%xmm1,%xmm16
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+[a-f0-9]+: 62 b1 f5 00 fb c9 vpsubq %xmm17,%xmm17,%xmm1
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+[a-f0-9]+: 62 b1 f5 00 fb c9 vpsubq %xmm17,%xmm17,%xmm1
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#pass
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@ -78,3 +78,39 @@ _start:
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vpxorq %ymm1, %ymm1, %ymm16
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vpxorq %zmm17, %zmm17, %zmm1
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vpxorq %ymm17, %ymm17, %ymm1
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vpsubb %zmm1, %zmm1, %zmm15{%k7}
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vpsubb %ymm1, %ymm1, %ymm15{z}{%k7}
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vpsubb %zmm1, %zmm1, %zmm15
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vpsubb %ymm1, %ymm1, %ymm15
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vpsubb %zmm1, %zmm1, %zmm16
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vpsubb %ymm1, %ymm1, %ymm16
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vpsubb %zmm17, %zmm17, %zmm1
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vpsubb %ymm17, %ymm17, %ymm1
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vpsubw %zmm1, %zmm1, %zmm15{%k7}
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vpsubw %ymm1, %ymm1, %ymm15{z}{%k7}
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vpsubw %zmm1, %zmm1, %zmm15
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vpsubw %ymm1, %ymm1, %ymm15
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vpsubw %zmm1, %zmm1, %zmm16
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vpsubw %ymm1, %ymm1, %ymm16
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vpsubw %zmm17, %zmm17, %zmm1
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vpsubw %ymm17, %ymm17, %ymm1
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vpsubd %zmm1, %zmm1, %zmm15{%k7}
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vpsubd %ymm1, %ymm1, %ymm15{z}{%k7}
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vpsubd %zmm1, %zmm1, %zmm15
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vpsubd %ymm1, %ymm1, %ymm15
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vpsubd %zmm1, %zmm1, %zmm16
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vpsubd %ymm1, %ymm1, %ymm16
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vpsubd %zmm17, %zmm17, %zmm1
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vpsubd %ymm17, %ymm17, %ymm1
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vpsubq %zmm1, %zmm1, %zmm15{%k7}
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vpsubq %ymm1, %ymm1, %ymm15{z}{%k7}
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vpsubq %zmm1, %zmm1, %zmm15
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vpsubq %ymm1, %ymm1, %ymm15
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vpsubq %zmm1, %zmm1, %zmm16
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vpsubq %ymm1, %ymm1, %ymm16
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vpsubq %zmm17, %zmm17, %zmm1
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vpsubq %ymm17, %ymm17, %ymm1
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@ -1,3 +1,9 @@
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2018-03-01 H.J. Lu <hongjiu.lu@intel.com>
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* * i386-opc.tbl: Add "Optimize" to AVX256 and AVX512
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vpsub[bwdq] instructions.
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* i386-tbl.h: Regenerated.
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2018-03-01 Alan Modra <amodra@gmail.com>
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* configure.ac (ALL_LINGUAS): Sort.
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@ -2382,14 +2382,14 @@ vpsrlq, 3, 0x6673, 0x2, 1, CpuAVX2, Modrm|Vex=2|VexOpcode=0|VexVVVV=2|VexW=1|Ign
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vpsrlq, 3, 0x66d3, None, 1, CpuAVX2, Modrm|Vex=2|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|RegXMM, RegYMM, RegYMM }
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vpsrlw, 3, 0x6671, 0x2, 1, CpuAVX2, Modrm|Vex=2|VexOpcode=0|VexVVVV=2|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegYMM, RegYMM }
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vpsrlw, 3, 0x66d1, None, 1, CpuAVX2, Modrm|Vex=2|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|RegXMM, RegYMM, RegYMM }
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vpsubb, 3, 0x66f8, None, 1, CpuAVX2, Modrm|Vex=2|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM }
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vpsubd, 3, 0x66fa, None, 1, CpuAVX2, Modrm|Vex=2|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM }
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vpsubq, 3, 0x66fb, None, 1, CpuAVX2, Modrm|Vex=2|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM }
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vpsubb, 3, 0x66f8, None, 1, CpuAVX2, Modrm|Vex=2|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Optimize, { Ymmword|Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM }
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vpsubd, 3, 0x66fa, None, 1, CpuAVX2, Modrm|Vex=2|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Optimize, { Ymmword|Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM }
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vpsubq, 3, 0x66fb, None, 1, CpuAVX2, Modrm|Vex=2|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Optimize, { Ymmword|Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM }
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vpsubsb, 3, 0x66e8, None, 1, CpuAVX2, Modrm|Vex=2|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM }
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vpsubsw, 3, 0x66e9, None, 1, CpuAVX2, Modrm|Vex=2|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM }
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vpsubusb, 3, 0x66d8, None, 1, CpuAVX2, Modrm|Vex=2|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM }
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vpsubusw, 3, 0x66d9, None, 1, CpuAVX2, Modrm|Vex=2|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM }
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vpsubw, 3, 0x66f9, None, 1, CpuAVX2, Modrm|Vex=2|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM }
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vpsubw, 3, 0x66f9, None, 1, CpuAVX2, Modrm|Vex=2|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Optimize, { Ymmword|Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM }
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vpunpckhbw, 3, 0x6668, None, 1, CpuAVX2, Modrm|Vex=2|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM }
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vpunpckhdq, 3, 0x666a, None, 1, CpuAVX2, Modrm|Vex=2|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM }
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vpunpckhqdq, 3, 0x666d, None, 1, CpuAVX2, Modrm|Vex=2|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM }
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@ -3938,7 +3938,7 @@ vpaddd, 3, 0x66FE, None, 1, CpuAVX512F, Modrm|EVex=1|Masking=3|VexOpcode=0|VexVV
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vpandd, 3, 0x66DB, None, 1, CpuAVX512F, Modrm|EVex=1|Masking=3|VexOpcode=0|VexVVVV=1|VexW=1|Broadcast=1|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegZMM|Dword|ZMMword|Unspecified|BaseIndex, RegZMM, RegZMM }
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vpandnd, 3, 0x66DF, None, 1, CpuAVX512F, Modrm|EVex=1|Masking=3|VexOpcode=0|VexVVVV=1|VexW=1|Broadcast=1|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Optimize, { RegZMM|Dword|ZMMword|Unspecified|BaseIndex, RegZMM, RegZMM }
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vpord, 3, 0x66EB, None, 1, CpuAVX512F, Modrm|EVex=1|Masking=3|VexOpcode=0|VexVVVV=1|VexW=1|Broadcast=1|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegZMM|Dword|ZMMword|Unspecified|BaseIndex, RegZMM, RegZMM }
|
||||
vpsubd, 3, 0x66FA, None, 1, CpuAVX512F, Modrm|EVex=1|Masking=3|VexOpcode=0|VexVVVV=1|VexW=1|Broadcast=1|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegZMM|Dword|ZMMword|Unspecified|BaseIndex, RegZMM, RegZMM }
|
||||
vpsubd, 3, 0x66FA, None, 1, CpuAVX512F, Modrm|EVex=1|Masking=3|VexOpcode=0|VexVVVV=1|VexW=1|Broadcast=1|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Optimize, { RegZMM|Dword|ZMMword|Unspecified|BaseIndex, RegZMM, RegZMM }
|
||||
vpunpckhdq, 3, 0x666A, None, 1, CpuAVX512F, Modrm|EVex=1|Masking=3|VexOpcode=0|VexVVVV=1|VexW=1|Broadcast=1|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegZMM|Dword|ZMMword|Unspecified|BaseIndex, RegZMM, RegZMM }
|
||||
vpunpckldq, 3, 0x6662, None, 1, CpuAVX512F, Modrm|EVex=1|Masking=3|VexOpcode=0|VexVVVV=1|VexW=1|Broadcast=1|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegZMM|Dword|ZMMword|Unspecified|BaseIndex, RegZMM, RegZMM }
|
||||
vpxord, 3, 0x66EF, None, 1, CpuAVX512F, Modrm|EVex=1|Masking=3|VexOpcode=0|VexVVVV=1|VexW=1|Broadcast=1|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Optimize, { RegZMM|Dword|ZMMword|Unspecified|BaseIndex, RegZMM, RegZMM }
|
||||
@ -3948,7 +3948,7 @@ vpandnq, 3, 0x66DF, None, 1, CpuAVX512F, Modrm|EVex=1|Masking=3|VexOpcode=0|VexV
|
||||
vpandq, 3, 0x66DB, None, 1, CpuAVX512F, Modrm|EVex=1|Masking=3|VexOpcode=0|VexVVVV=1|VexW=2|VecESize=1|Broadcast=2|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegZMM, RegZMM }
|
||||
vpmuludq, 3, 0x66F4, None, 1, CpuAVX512F, Modrm|EVex=1|Masking=3|VexOpcode=0|VexVVVV=1|VexW=2|VecESize=1|Broadcast=2|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegZMM, RegZMM }
|
||||
vporq, 3, 0x66EB, None, 1, CpuAVX512F, Modrm|EVex=1|Masking=3|VexOpcode=0|VexVVVV=1|VexW=2|VecESize=1|Broadcast=2|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegZMM, RegZMM }
|
||||
vpsubq, 3, 0x66FB, None, 1, CpuAVX512F, Modrm|EVex=1|Masking=3|VexOpcode=0|VexVVVV=1|VexW=2|VecESize=1|Broadcast=2|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegZMM, RegZMM }
|
||||
vpsubq, 3, 0x66FB, None, 1, CpuAVX512F, Modrm|EVex=1|Masking=3|VexOpcode=0|VexVVVV=1|VexW=2|VecESize=1|Broadcast=2|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Optimize, { RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegZMM, RegZMM }
|
||||
vpunpckhqdq, 3, 0x666D, None, 1, CpuAVX512F, Modrm|EVex=1|Masking=3|VexOpcode=0|VexVVVV=1|VexW=2|VecESize=1|Broadcast=2|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegZMM, RegZMM }
|
||||
vpunpcklqdq, 3, 0x666C, None, 1, CpuAVX512F, Modrm|EVex=1|Masking=3|VexOpcode=0|VexVVVV=1|VexW=2|VecESize=1|Broadcast=2|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegZMM, RegZMM }
|
||||
vpxorq, 3, 0x66EF, None, 1, CpuAVX512F, Modrm|EVex=1|Masking=3|VexOpcode=0|VexVVVV=1|VexW=2|VecESize=1|Broadcast=2|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Optimize, { RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegZMM, RegZMM }
|
||||
@ -4924,7 +4924,7 @@ vpsrld, 3, 0x6672, 2, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcod
|
||||
vpsrld, 3, 0x6672, 2, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=0|VexVVVV=2|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegYMM, RegYMM }
|
||||
vpsrld, 3, 0x6672, 2, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=0|VexVVVV=3|VexW=1|Broadcast=2|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Dword|YMMword|Unspecified|BaseIndex, RegYMM }
|
||||
vpsubd, 3, 0x66FA, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=0|VexVVVV=1|VexW=1|Broadcast=3|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Dword|XMMword|Unspecified|BaseIndex, RegXMM, RegXMM }
|
||||
vpsubd, 3, 0x66FA, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=0|VexVVVV=1|VexW=1|Broadcast=2|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|Dword|YMMword|Unspecified|BaseIndex, RegYMM, RegYMM }
|
||||
vpsubd, 3, 0x66FA, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=0|VexVVVV=1|VexW=1|Broadcast=2|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Optimize, { RegYMM|Dword|YMMword|Unspecified|BaseIndex, RegYMM, RegYMM }
|
||||
vpunpckhdq, 3, 0x666A, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=0|VexVVVV=1|VexW=1|Broadcast=3|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Dword|XMMword|Unspecified|BaseIndex, RegXMM, RegXMM }
|
||||
vpunpckhdq, 3, 0x666A, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=0|VexVVVV=1|VexW=1|Broadcast=2|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|Dword|YMMword|Unspecified|BaseIndex, RegYMM, RegYMM }
|
||||
vpunpckldq, 3, 0x6662, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=0|VexVVVV=1|VexW=1|Broadcast=3|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Dword|XMMword|Unspecified|BaseIndex, RegXMM, RegXMM }
|
||||
@ -4963,7 +4963,7 @@ vpsrlq, 3, 0x6673, 2, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcod
|
||||
vpsrlq, 3, 0x6673, 2, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=0|VexVVVV=2|VexW=2|VecESize=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegYMM, RegYMM }
|
||||
vpsrlq, 3, 0x6673, 2, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=0|VexVVVV=3|VexW=2|VecESize=1|Broadcast=3|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Qword|YMMword|Unspecified|BaseIndex, RegYMM }
|
||||
vpsubq, 3, 0x66FB, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=0|VexVVVV=1|VexW=2|VecESize=1|Broadcast=4|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Qword|XMMword|Unspecified|BaseIndex, RegXMM, RegXMM }
|
||||
vpsubq, 3, 0x66FB, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=0|VexVVVV=1|VexW=2|VecESize=1|Broadcast=3|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|Qword|YMMword|Unspecified|BaseIndex, RegYMM, RegYMM }
|
||||
vpsubq, 3, 0x66FB, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=0|VexVVVV=1|VexW=2|VecESize=1|Broadcast=3|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Optimize, { RegYMM|Qword|YMMword|Unspecified|BaseIndex, RegYMM, RegYMM }
|
||||
vpunpckhqdq, 3, 0x666D, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=0|VexVVVV=1|VexW=2|VecESize=1|Broadcast=4|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Qword|XMMword|Unspecified|BaseIndex, RegXMM, RegXMM }
|
||||
vpunpckhqdq, 3, 0x666D, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=0|VexVVVV=1|VexW=2|VecESize=1|Broadcast=3|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|Qword|YMMword|Unspecified|BaseIndex, RegYMM, RegYMM }
|
||||
vpunpcklqdq, 3, 0x666C, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=0|VexVVVV=1|VexW=2|VecESize=1|Broadcast=4|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Qword|XMMword|Unspecified|BaseIndex, RegXMM, RegXMM }
|
||||
@ -5320,9 +5320,9 @@ vpmaxub, 3, 0x66DE, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=3|Masking=3|Vex
|
||||
vpminub, 3, 0x66DA, None, 1, CpuAVX512BW, Modrm|EVex=1|Masking=3|VexOpcode=0|VexVVVV=1|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegZMM|ZMMword|Unspecified|BaseIndex, RegZMM, RegZMM }
|
||||
vpminub, 3, 0x66DA, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=0|VexVVVV=1|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|XMMword|Unspecified|BaseIndex, RegXMM, RegXMM }
|
||||
vpminub, 3, 0x66DA, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=0|VexVVVV=1|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|YMMword|Unspecified|BaseIndex, RegYMM, RegYMM }
|
||||
vpsubb, 3, 0x66F8, None, 1, CpuAVX512BW, Modrm|EVex=1|Masking=3|VexOpcode=0|VexVVVV=1|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegZMM|ZMMword|Unspecified|BaseIndex, RegZMM, RegZMM }
|
||||
vpsubb, 3, 0x66F8, None, 1, CpuAVX512BW, Modrm|EVex=1|Masking=3|VexOpcode=0|VexVVVV=1|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Optimize, { RegZMM|ZMMword|Unspecified|BaseIndex, RegZMM, RegZMM }
|
||||
vpsubb, 3, 0x66F8, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=0|VexVVVV=1|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|XMMword|Unspecified|BaseIndex, RegXMM, RegXMM }
|
||||
vpsubb, 3, 0x66F8, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=0|VexVVVV=1|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|YMMword|Unspecified|BaseIndex, RegYMM, RegYMM }
|
||||
vpsubb, 3, 0x66F8, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=0|VexVVVV=1|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Optimize, { RegYMM|YMMword|Unspecified|BaseIndex, RegYMM, RegYMM }
|
||||
vpsubsb, 3, 0x66E8, None, 1, CpuAVX512BW, Modrm|EVex=1|Masking=3|VexOpcode=0|VexVVVV=1|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegZMM|ZMMword|Unspecified|BaseIndex, RegZMM, RegZMM }
|
||||
vpsubsb, 3, 0x66E8, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=0|VexVVVV=1|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|XMMword|Unspecified|BaseIndex, RegXMM, RegXMM }
|
||||
vpsubsb, 3, 0x66E8, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=0|VexVVVV=1|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|YMMword|Unspecified|BaseIndex, RegYMM, RegYMM }
|
||||
@ -5396,9 +5396,9 @@ vpsubsw, 3, 0x66E9, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=3|Masking=3|Vex
|
||||
vpsubusw, 3, 0x66D9, None, 1, CpuAVX512BW, Modrm|EVex=1|Masking=3|VexOpcode=0|VexVVVV=1|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegZMM|ZMMword|Unspecified|BaseIndex, RegZMM, RegZMM }
|
||||
vpsubusw, 3, 0x66D9, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=0|VexVVVV=1|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|XMMword|Unspecified|BaseIndex, RegXMM, RegXMM }
|
||||
vpsubusw, 3, 0x66D9, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=0|VexVVVV=1|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|YMMword|Unspecified|BaseIndex, RegYMM, RegYMM }
|
||||
vpsubw, 3, 0x66F9, None, 1, CpuAVX512BW, Modrm|EVex=1|Masking=3|VexOpcode=0|VexVVVV=1|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegZMM|ZMMword|Unspecified|BaseIndex, RegZMM, RegZMM }
|
||||
vpsubw, 3, 0x66F9, None, 1, CpuAVX512BW, Modrm|EVex=1|Masking=3|VexOpcode=0|VexVVVV=1|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Optimize, { RegZMM|ZMMword|Unspecified|BaseIndex, RegZMM, RegZMM }
|
||||
vpsubw, 3, 0x66F9, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=0|VexVVVV=1|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|XMMword|Unspecified|BaseIndex, RegXMM, RegXMM }
|
||||
vpsubw, 3, 0x66F9, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=0|VexVVVV=1|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|YMMword|Unspecified|BaseIndex, RegYMM, RegYMM }
|
||||
vpsubw, 3, 0x66F9, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=0|VexVVVV=1|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Optimize, { RegYMM|YMMword|Unspecified|BaseIndex, RegYMM, RegYMM }
|
||||
vpunpckhwd, 3, 0x6669, None, 1, CpuAVX512BW, Modrm|EVex=1|Masking=3|VexOpcode=0|VexVVVV=1|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegZMM|ZMMword|Unspecified|BaseIndex, RegZMM, RegZMM }
|
||||
vpunpckhwd, 3, 0x6669, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=0|VexVVVV=1|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|XMMword|Unspecified|BaseIndex, RegXMM, RegXMM }
|
||||
vpunpckhwd, 3, 0x6669, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=0|VexVVVV=1|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|YMMword|Unspecified|BaseIndex, RegYMM, RegYMM }
|
||||
|
||||
@ -54062,7 +54062,7 @@ const insn_template i386_optab[] =
|
||||
0, 0, 0, 0, 0, 0 } },
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1,
|
||||
1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 2, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 2, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1,
|
||||
0, 0, 0, 0, 0, 0 },
|
||||
{ { { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1,
|
||||
0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0,
|
||||
@ -54082,7 +54082,7 @@ const insn_template i386_optab[] =
|
||||
0, 0, 0, 0, 0, 0 } },
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1,
|
||||
1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 3, 0, 0, 0, 0, 6, 0, 0, 0,
|
||||
0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 3, 0, 0, 0, 0, 6, 0, 0, 1,
|
||||
0, 0, 0, 0, 0, 0 },
|
||||
{ { { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1,
|
||||
0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0,
|
||||
@ -54122,7 +54122,7 @@ const insn_template i386_optab[] =
|
||||
0, 0, 0, 0, 0, 0 } },
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1,
|
||||
1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 3, 3, 0, 0, 0, 0, 5, 0, 0, 0,
|
||||
0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 3, 3, 0, 0, 0, 0, 5, 0, 0, 1,
|
||||
0, 0, 0, 0, 0, 0 },
|
||||
{ { { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1,
|
||||
0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0,
|
||||
@ -54162,7 +54162,7 @@ const insn_template i386_optab[] =
|
||||
0, 0, 0, 0, 0, 0 } },
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1,
|
||||
1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 2, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 2, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1,
|
||||
0, 0, 0, 0, 0, 0 },
|
||||
{ { { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1,
|
||||
0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0,
|
||||
@ -54182,7 +54182,7 @@ const insn_template i386_optab[] =
|
||||
0, 0, 0, 0, 0, 0 } },
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1,
|
||||
1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 1, 3, 0, 1, 0, 0, 6, 0, 0, 0,
|
||||
0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 1, 3, 0, 1, 0, 0, 6, 0, 0, 1,
|
||||
0, 0, 0, 0, 0, 0 },
|
||||
{ { { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1,
|
||||
0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 1, 0,
|
||||
@ -54222,7 +54222,7 @@ const insn_template i386_optab[] =
|
||||
0, 0, 0, 0, 0, 0 } },
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1,
|
||||
1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 3, 3, 0, 2, 0, 0, 5, 0, 0, 0,
|
||||
0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 3, 3, 0, 2, 0, 0, 5, 0, 0, 1,
|
||||
0, 0, 0, 0, 0, 0 },
|
||||
{ { { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1,
|
||||
0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 1, 0,
|
||||
@ -54262,7 +54262,7 @@ const insn_template i386_optab[] =
|
||||
0, 0, 0, 0, 0, 0 } },
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1,
|
||||
1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 2, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 2, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1,
|
||||
0, 0, 0, 0, 0, 0 },
|
||||
{ { { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1,
|
||||
0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0,
|
||||
@ -54282,7 +54282,7 @@ const insn_template i386_optab[] =
|
||||
0, 0, 0, 0, 0, 0 } },
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1,
|
||||
1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 1, 2, 0, 0, 0, 0, 0, 0, 1, 3, 1, 2, 0, 0, 6, 0, 0, 0,
|
||||
0, 0, 1, 2, 0, 0, 0, 0, 0, 0, 1, 3, 1, 2, 0, 0, 6, 0, 0, 1,
|
||||
0, 0, 0, 0, 0, 0 },
|
||||
{ { { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1,
|
||||
0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0,
|
||||
@ -54322,7 +54322,7 @@ const insn_template i386_optab[] =
|
||||
0, 0, 0, 0, 0, 0 } },
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1,
|
||||
1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 1, 2, 0, 0, 0, 0, 0, 0, 3, 3, 1, 3, 0, 0, 5, 0, 0, 0,
|
||||
0, 0, 1, 2, 0, 0, 0, 0, 0, 0, 3, 3, 1, 3, 0, 0, 5, 0, 0, 1,
|
||||
0, 0, 0, 0, 0, 0 },
|
||||
{ { { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1,
|
||||
0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0,
|
||||
@ -54762,7 +54762,7 @@ const insn_template i386_optab[] =
|
||||
0, 0, 0, 0, 0, 0 } },
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1,
|
||||
1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 2, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 2, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1,
|
||||
0, 0, 0, 0, 0, 0 },
|
||||
{ { { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1,
|
||||
0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0,
|
||||
@ -54782,7 +54782,7 @@ const insn_template i386_optab[] =
|
||||
0, 0, 0, 0, 0, 0 } },
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1,
|
||||
1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 3, 0, 0, 0, 0, 6, 0, 0, 0,
|
||||
0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 3, 0, 0, 0, 0, 6, 0, 0, 1,
|
||||
0, 0, 0, 0, 0, 0 },
|
||||
{ { { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1,
|
||||
0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0,
|
||||
@ -54822,7 +54822,7 @@ const insn_template i386_optab[] =
|
||||
0, 0, 0, 0, 0, 0 } },
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1,
|
||||
1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 3, 3, 0, 0, 0, 0, 5, 0, 0, 0,
|
||||
0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 3, 3, 0, 0, 0, 0, 5, 0, 0, 1,
|
||||
0, 0, 0, 0, 0, 0 },
|
||||
{ { { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1,
|
||||
0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0,
|
||||
|
||||
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Reference in New Issue
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