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x86: re-work AVX-VNNI support

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By putting the templates after their AVX512 counterparts, the AVX512
flavors will be picked by default. That way the need to always use {vex}
ceases to exist once respective CPU features (AVX512-VNNI or AVX512VL as
a whole) have been disabled. This way the need for the PseudoVexPrefix
attribute also disappears.
This commit is contained in:
Jan Beulich 2022-10-20 10:01:12 +02:00
parent 15ede33bfa
commit 837e225ba1
11 changed files with 7061 additions and 7041 deletions
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6
gas/config/tc-i386.c
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@ -6456,12 +6456,6 @@ match_template (char mnem_suffix)
if (cpu_flags_match (t) != CPU_FLAGS_PERFECT_MATCH)
continue;
/* Check Pseudo Prefix. */
if (t->opcode_modifier.pseudovexprefix
&& !(i.vec_encoding == vex_encoding_vex
|| i.vec_encoding == vex_encoding_vex3))
continue;
/* Check AT&T mnemonic. */
specific_error = progress (unsupported_with_intel_mnemonic);
if (intel_mnemonic && t->opcode_modifier.attmnemonic)

3
gas/testsuite/gas/i386/avx-vnni-inval.l
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@ -1,2 +1,3 @@
.* Assembler messages:
.*:6: Error: unsupported instruction `vpdpbusd'
.*:6: Error: unsupported .* `vpdpbusd'
.*:7: Error: operand .* `vpdpbusd'

3
gas/testsuite/gas/i386/avx-vnni-inval.s
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@ -3,4 +3,5 @@
.text
.arch .noavx512_vnni
_start:
vpdpbusd %xmm2,%xmm4,%xmm2
vpdpbusd %xmm2, %xmm4, %xmm2{%k6}
vpdpbusd %zmm2, %zmm4, %zmm2

7
gas/testsuite/gas/i386/avx-vnni.d
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@ -31,5 +31,12 @@ Disassembly of section .text:
+[a-f0-9]+: c4 e2 59 53 d2 \{vex\} vpdpwssds %xmm2,%xmm4,%xmm2
+[a-f0-9]+: c4 e2 59 53 11 \{vex\} vpdpwssds \(%ecx\),%xmm4,%xmm2
+[a-f0-9]+: c4 e2 59 53 11 \{vex\} vpdpwssds \(%ecx\),%xmm4,%xmm2
+[a-f0-9]+: 62 f2 7d 48 50 c0 vpdpbusd %zmm0,%zmm0,%zmm0
+[a-f0-9]+: c4 e2 7d 50 c0 \{vex\} vpdpbusd %ymm0,%ymm0,%ymm0
+[a-f0-9]+: c4 e2 79 50 c0 \{vex\} vpdpbusd %xmm0,%xmm0,%xmm0
+[a-f0-9]+: c4 e2 7d 50 c0 \{vex\} vpdpbusd %ymm0,%ymm0,%ymm0
+[a-f0-9]+: c4 e2 79 50 c0 \{vex\} vpdpbusd %xmm0,%xmm0,%xmm0
+[a-f0-9]+: c4 e2 7d 50 c0 \{vex\} vpdpbusd %ymm0,%ymm0,%ymm0
+[a-f0-9]+: c4 e2 79 50 c0 \{vex\} vpdpbusd %xmm0,%xmm0,%xmm0
+[a-f0-9]+: 62 f2 5d 08 50 d2 vpdpbusd %xmm2,%xmm4,%xmm2
#pass

19
gas/testsuite/gas/i386/avx-vnni.s
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@ -16,5 +16,24 @@ _start:
test_insn vpdpbusds
test_insn vpdpwssds
.arch .noavx512vl
vpdpbusd %zmm0, %zmm0, %zmm0
vpdpbusd %ymm0, %ymm0, %ymm0
vpdpbusd %xmm0, %xmm0, %xmm0
.arch default
.arch .noavx512_vnni
vpdpbusd %ymm0, %ymm0, %ymm0
vpdpbusd %xmm0, %xmm0, %xmm0
.arch default
.arch .noavx512f
vpdpbusd %ymm0, %ymm0, %ymm0
vpdpbusd %xmm0, %xmm0, %xmm0
.arch default
.arch .avx_vnni
vpdpbusd %xmm2, %xmm4, %xmm2

5
gas/testsuite/gas/i386/x86-64-avx-vnni-inval.l
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@ -1,3 +1,4 @@
.* Assembler messages:
.*:6: Error: unsupported instruction `vpdpbusds'
.*:7: Error: unsupported instruction `vpdpbusds'
.*:6: Error: unsupported .* `vpdpbusds'
.*:7: Error: unsupported .* `vpdpbusds'
.*:8: Error: operand .* `vpdpbusds'

5
gas/testsuite/gas/i386/x86-64-avx-vnni-inval.s
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@ -3,5 +3,6 @@
.text
.arch .noavx512_vnni
_start:
vpdpbusds %xmm2, %xmm4, %xmm2
vpdpbusds %xmm22, %xmm4, %xmm2
vpdpbusds %xmm2, %xmm4, %xmm2{%k6}
vpdpbusds %xmm22, %xmm4, %xmm2{%k1}
vpdpbusds %zmm2, %zmm4, %zmm2

1
opcodes/i386-gen.c
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@ -711,7 +711,6 @@ static bitfield opcode_modifiers[] =
BITFIELD (ImmExt),
BITFIELD (NoRex64),
BITFIELD (Ugh),
BITFIELD (PseudoVexPrefix),
BITFIELD (Vex),
BITFIELD (VexVVVV),
BITFIELD (VexW),

3
opcodes/i386-opc.h
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@ -531,8 +531,6 @@ enum
NoRex64,
/* deprecated fp insn, gets a warning */
Ugh,
/* Intel AVX Instructions support via {vex} prefix */
PseudoVexPrefix,
/* insn has VEX prefix:
1: 128bit VEX prefix (or operand dependent).
2: 256bit VEX prefix.
@ -741,7 +739,6 @@ typedef struct i386_opcode_modifier
unsigned int immext:1;
unsigned int norex64:1;
unsigned int ugh:1;
unsigned int pseudovexprefix:1;
unsigned int vex:2;
unsigned int vexvvvv:2;
unsigned int vexw:2;

20
opcodes/i386-opc.tbl
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@ -2861,16 +2861,6 @@ vpshrdw, 0x6672, None, CpuAVX512_VBMI2, Modrm|Masking=3|Space0F3A|VexVVVV|VexW1|
// AVX512_VBMI2 instructions end
// AVX_VNNI instructions
vpdpbusd, 0x6650, None, CpuAVX_VNNI, Modrm|Vex|PseudoVexPrefix|Space0F38|VexVVVV|VexW0|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
vpdpwssd, 0x6652, None, CpuAVX_VNNI, Modrm|Vex|PseudoVexPrefix|Space0F38|VexVVVV|VexW0|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
vpdpbusds, 0x6651, None, CpuAVX_VNNI, Modrm|Vex|PseudoVexPrefix|Space0F38|VexVVVV|VexW0|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
vpdpwssds, 0x6653, None, CpuAVX_VNNI, Modrm|Vex|PseudoVexPrefix|Space0F38|VexVVVV|VexW0|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
// AVX_VNNI instructions end
// AVX512_VNNI instructions
vpdpbusd, 0x6650, None, CpuAVX512_VNNI, Modrm|Masking=3|Space0F38|VexVVVV=1|VexW=1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
@ -2881,6 +2871,16 @@ vpdpwssds, 0x6653, None, CpuAVX512_VNNI, Modrm|Masking=3|Space0F38|VexVVVV=1|Vex
// AVX512_VNNI instructions end
// AVX_VNNI instructions
vpdpbusd, 0x6650, None, CpuAVX_VNNI, Modrm|Vex|Space0F38|VexVVVV|VexW0|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
vpdpwssd, 0x6652, None, CpuAVX_VNNI, Modrm|Vex|Space0F38|VexVVVV|VexW0|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
vpdpbusds, 0x6651, None, CpuAVX_VNNI, Modrm|Vex|Space0F38|VexVVVV|VexW0|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
vpdpwssds, 0x6653, None, CpuAVX_VNNI, Modrm|Vex|Space0F38|VexVVVV|VexW0|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
// AVX_VNNI instructions end
// AVX512_BITALG instructions
vpopcnt<bw>, 0x6654, None, CpuAVX512_BITALG, Modrm|Masking=3|Space0F38|<bw:vexw>|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }

14030
opcodes/i386-tbl.h
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