opcodes/
* micromips-opc.c (micromips_opcodes): Correct the encoding of the "swxc1" instruction. gas/testsuite/ * gas/mips/micromips.d: Correct the disassembly of SWXC1. * gas/mips/micromips-trap.d: Likewise. * gas/mips/micromips@24k-triple-stores-1.d: Likewise. * gas/mips/micromips@mips4-fp.d: Likewise.
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@ -1,3 +1,10 @@
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2012-09-18 Chao-ying Fu <fu@mips.com>
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* gas/mips/micromips.d: Correct the disassembly of SWXC1.
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* gas/mips/micromips-trap.d: Likewise.
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* gas/mips/micromips@24k-triple-stores-1.d: Likewise.
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* gas/mips/micromips@mips4-fp.d: Likewise.
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2012-09-17 Yufeng Zhang <yufeng.zhang@arm.com>
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* gas/aarch64/crypto.d (#as): Update for v8->v8-A change.
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@ -6504,14 +6504,14 @@ Disassembly of section \.text:
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[ 0-9a-f]+: 41a1 1234 lui at,0x1234
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[ 0-9a-f]+: 0081 0950 addu at,at,a0
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[ 0-9a-f]+: 9861 5678 swc1 \$f3,22136\(at\)
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[ 0-9a-f]+: 5400 0048 lwxc1 \$f0,zero\(zero\)
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[ 0-9a-f]+: 5402 0048 lwxc1 \$f0,zero\(v0\)
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[ 0-9a-f]+: 541f 0048 lwxc1 \$f0,zero\(ra\)
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[ 0-9a-f]+: 545f 0048 lwxc1 \$f0,v0\(ra\)
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[ 0-9a-f]+: 57ff 0048 lwxc1 \$f0,ra\(ra\)
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[ 0-9a-f]+: 57ff 0848 lwxc1 \$f1,ra\(ra\)
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[ 0-9a-f]+: 57ff 1048 lwxc1 \$f2,ra\(ra\)
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[ 0-9a-f]+: 57ff f848 lwxc1 \$f31,ra\(ra\)
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[ 0-9a-f]+: 5400 0088 swxc1 \$f0,zero\(zero\)
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[ 0-9a-f]+: 5402 0088 swxc1 \$f0,zero\(v0\)
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[ 0-9a-f]+: 541f 0088 swxc1 \$f0,zero\(ra\)
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[ 0-9a-f]+: 545f 0088 swxc1 \$f0,v0\(ra\)
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[ 0-9a-f]+: 57ff 0088 swxc1 \$f0,ra\(ra\)
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[ 0-9a-f]+: 57ff 0888 swxc1 \$f1,ra\(ra\)
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[ 0-9a-f]+: 57ff 1088 swxc1 \$f2,ra\(ra\)
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[ 0-9a-f]+: 57ff f888 swxc1 \$f31,ra\(ra\)
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[ 0-9a-f]+: 5401 233b trunc\.l\.s \$f0,\$f1
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[ 0-9a-f]+: 57df 233b trunc\.l\.s \$f30,\$f31
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[ 0-9a-f]+: 5442 233b trunc\.l\.s \$f2,\$f2
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@ -6576,14 +6576,14 @@ Disassembly of section \.text:
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[ 0-9a-f]+: 41a1 1234 lui at,0x1234
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[ 0-9a-f]+: 0081 0950 addu at,at,a0
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[ 0-9a-f]+: 9861 5678 swc1 \$f3,22136\(at\)
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[ 0-9a-f]+: 5400 0048 lwxc1 \$f0,zero\(zero\)
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[ 0-9a-f]+: 5402 0048 lwxc1 \$f0,zero\(v0\)
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[ 0-9a-f]+: 541f 0048 lwxc1 \$f0,zero\(ra\)
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[ 0-9a-f]+: 545f 0048 lwxc1 \$f0,v0\(ra\)
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[ 0-9a-f]+: 57ff 0048 lwxc1 \$f0,ra\(ra\)
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[ 0-9a-f]+: 57ff 0848 lwxc1 \$f1,ra\(ra\)
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[ 0-9a-f]+: 57ff 1048 lwxc1 \$f2,ra\(ra\)
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[ 0-9a-f]+: 57ff f848 lwxc1 \$f31,ra\(ra\)
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[ 0-9a-f]+: 5400 0088 swxc1 \$f0,zero\(zero\)
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[ 0-9a-f]+: 5402 0088 swxc1 \$f0,zero\(v0\)
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[ 0-9a-f]+: 541f 0088 swxc1 \$f0,zero\(ra\)
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[ 0-9a-f]+: 545f 0088 swxc1 \$f0,v0\(ra\)
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[ 0-9a-f]+: 57ff 0088 swxc1 \$f0,ra\(ra\)
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[ 0-9a-f]+: 57ff 0888 swxc1 \$f1,ra\(ra\)
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[ 0-9a-f]+: 57ff 1088 swxc1 \$f2,ra\(ra\)
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[ 0-9a-f]+: 57ff f888 swxc1 \$f31,ra\(ra\)
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[ 0-9a-f]+: 5401 233b trunc\.l\.s \$f0,\$f1
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[ 0-9a-f]+: 57df 233b trunc\.l\.s \$f30,\$f31
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[ 0-9a-f]+: 5442 233b trunc\.l\.s \$f2,\$f2
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@ -58,11 +58,11 @@ Disassembly of section \.text:
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*[0-9a-f]+: 209d a010 sdc2 \$4,16\(sp\)
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*[0-9a-f]+: 20bd a018 sdc2 \$5,24\(sp\)
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*[0-9a-f]+: 20dd a020 sdc2 \$6,32\(sp\)
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*[0-9a-f]+: 5528 0048 lwxc1 \$f0,t1\(t0\)
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*[0-9a-f]+: 5548 0848 lwxc1 \$f1,t2\(t0\)
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*[0-9a-f]+: 5568 1048 lwxc1 \$f2,t3\(t0\)
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*[0-9a-f]+: 5588 1848 lwxc1 \$f3,t4\(t0\)
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*[0-9a-f]+: 55a8 2048 lwxc1 \$f4,t5\(t0\)
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*[0-9a-f]+: 5528 0088 swxc1 \$f0,t1\(t0\)
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*[0-9a-f]+: 5548 0888 swxc1 \$f1,t2\(t0\)
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*[0-9a-f]+: 5568 1088 swxc1 \$f2,t3\(t0\)
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*[0-9a-f]+: 5588 1888 swxc1 \$f3,t4\(t0\)
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*[0-9a-f]+: 55a8 2088 swxc1 \$f4,t5\(t0\)
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*[0-9a-f]+: 5528 0108 sdxc1 \$f0,t1\(t0\)
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*[0-9a-f]+: 5548 1108 sdxc1 \$f2,t2\(t0\)
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*[0-9a-f]+: 5568 2108 sdxc1 \$f4,t3\(t0\)
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@ -45,6 +45,6 @@ Disassembly of section \.text:
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[0-9a-f]+ <[^>]*> 5486 423b rsqrt\.d \$f4,\$f6
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[0-9a-f]+ <[^>]*> 5486 023b rsqrt\.s \$f4,\$f6
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[0-9a-f]+ <[^>]*> 5485 2108 sdxc1 \$f4,a0\(a1\)
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[0-9a-f]+ <[^>]*> 5485 2048 lwxc1 \$f4,a0\(a1\)
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[0-9a-f]+ <[^>]*> 5485 2088 swxc1 \$f4,a0\(a1\)
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[0-9a-f]+ <[^>]*> 0c00 nop
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\.\.\.
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@ -1,3 +1,8 @@
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2012-09-18 Chao-ying Fu <fu@mips.com>
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* micromips-opc.c (micromips_opcodes): Correct the encoding of
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the "swxc1" instruction.
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2012-09-17 Yufeng Zhang <yufeng.zhang@arm.com>
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* aarch64-asm.c (aarch64_ins_imm_half): Remove ATTRIBUTE_UNUSED from
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@ -911,7 +911,7 @@ const struct mips_opcode micromips_opcodes[] =
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{"invalidate", "t,~(b)",0x60009000, 0xfc00f000, SM|RD_b|RD_t, 0, I1 }, /* same */
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{"invalidate", "t,o(b)",0, (int) M_SWR_OB, INSN_MACRO, 0, I1 },
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{"invalidate", "t,A(b)",0, (int) M_SWR_AB, INSN_MACRO, 0, I1 },
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{"swxc1", "D,t(b)", 0x54000048, 0xfc0007ff, SM|RD_t|RD_b|FP_S, RD_D, I1 },
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{"swxc1", "D,t(b)", 0x54000088, 0xfc0007ff, SM|RD_t|RD_b|FP_S, RD_D, I1 },
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{"sync_acquire", "", 0x00116b7c, 0xffffffff, NODS, 0, I1 },
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{"sync_mb", "", 0x00106b7c, 0xffffffff, NODS, 0, I1 },
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{"sync_release", "", 0x00126b7c, 0xffffffff, NODS, 0, I1 },
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