aarch64: Add support for FEAT_SVE2p1.
Hi, This patch add support for FEAT_SVE2p1 (SVE2.1 Extension) feature along with +sve2p1 optional flag to enabe this feature. Also support for following SVE2p1 instructions is added addqv, andqv, smaxqv, sminqv, umaxqv, uminqv and uminqv. Regression testing for aarch64-none-elf target and found no regressions. Ok for binutils-master? Regards, Srinath.
This commit is contained in:
Srinath Parvathaneni
Nick Clifton
parent
89e06ec152
commit
88601c2d94
3
gas/NEWS
3
gas/NEWS
@ -3,6 +3,9 @@
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hand-written asm using the new command line option --scfi=experimental on
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x86-64. Only System V AMD64 ABI is supported.
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* Add support for the Arm Scalable Vector Extension version 2.1 (SVE2.1)
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instructions.
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* Add support for the AArch64 Scalable Matrix Extension version 2.1 (SME2.1)
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instructions.
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@ -10354,6 +10354,7 @@ static const struct aarch64_option_cpu_value_table aarch64_features[] = {
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AARCH64_FEATURE (LSE128)},
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{"b16b16", AARCH64_FEATURE (B16B16), AARCH64_FEATURE (SVE2)},
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{"sme2p1", AARCH64_FEATURE (SME2p1), AARCH64_FEATURE (SME2)},
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{"sve2p1", AARCH64_FEATURE (SVE2p1), AARCH64_FEATURE (SVE2)},
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{NULL, AARCH64_NO_FEATURES, AARCH64_NO_FEATURES},
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};
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@ -278,6 +278,8 @@ automatically cause those extensions to be disabled.
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@tab Enable the 128-bit Page Descriptor Extension. This implies @code{lse128}.
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@item @code{sme2p1} @tab N/A @tab No
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@tab Enable the SME2.1 Extension.
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@item @code{sve2p1} @tab N/A @tab No
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@tab Enable the SVE2.1 Extension.
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@end multitable
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@node AArch64 Syntax
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4
gas/testsuite/gas/aarch64/sve2p1-1-bad.d
Normal file
4
gas/testsuite/gas/aarch64/sve2p1-1-bad.d
Normal file
@ -0,0 +1,4 @@
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#name: Illegal test of SVE2.1 min max instructions.
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#as: -march=armv9.4-a
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#source: sve2p1-1.s
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#error_output: sve2p1-1-bad.l
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37
gas/testsuite/gas/aarch64/sve2p1-1-bad.l
Normal file
37
gas/testsuite/gas/aarch64/sve2p1-1-bad.l
Normal file
@ -0,0 +1,37 @@
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.*: Assembler messages:
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.*: Error: selected processor does not support `addqv v0.16b,p0,z16.b'
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.*: Error: selected processor does not support `addqv v1.8h,p1,z8.h'
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.*: Error: selected processor does not support `addqv v2.4s,p2,z4.s'
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.*: Error: selected processor does not support `addqv v4.2d,p3,z2.d'
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.*: Error: selected processor does not support `addqv v8.2d,p4,z1.d'
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.*: Error: selected processor does not support `addqv v16.4s,p7,z0.s'
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.*: Error: selected processor does not support `andqv v0.16b,p0,z16.b'
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.*: Error: selected processor does not support `andqv v1.8h,p1,z8.h'
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.*: Error: selected processor does not support `andqv v2.4s,p2,z4.s'
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.*: Error: selected processor does not support `andqv v4.2d,p3,z2.d'
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.*: Error: selected processor does not support `andqv v8.2d,p4,z1.d'
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.*: Error: selected processor does not support `andqv v16.4s,p7,z0.s'
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.*: Error: selected processor does not support `smaxqv v0.16b,p0,z16.b'
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.*: Error: selected processor does not support `smaxqv v1.8h,p1,z8.h'
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.*: Error: selected processor does not support `smaxqv v2.4s,p2,z4.s'
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.*: Error: selected processor does not support `smaxqv v4.2d,p3,z2.d'
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.*: Error: selected processor does not support `smaxqv v8.2d,p4,z1.d'
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.*: Error: selected processor does not support `smaxqv v16.4s,p7,z0.s'
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.*: Error: selected processor does not support `umaxqv v0.16b,p0,z16.b'
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.*: Error: selected processor does not support `umaxqv v1.8h,p1,z8.h'
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.*: Error: selected processor does not support `umaxqv v2.4s,p2,z4.s'
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.*: Error: selected processor does not support `umaxqv v4.2d,p3,z2.d'
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.*: Error: selected processor does not support `umaxqv v8.2d,p4,z1.d'
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.*: Error: selected processor does not support `umaxqv v16.4s,p7,z0.s'
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.*: Error: selected processor does not support `sminqv v0.16b,p0,z16.b'
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.*: Error: selected processor does not support `sminqv v1.8h,p1,z8.h'
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.*: Error: selected processor does not support `sminqv v2.4s,p2,z4.s'
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.*: Error: selected processor does not support `sminqv v4.2d,p3,z2.d'
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.*: Error: selected processor does not support `sminqv v8.2d,p4,z1.d'
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.*: Error: selected processor does not support `sminqv v16.4s,p7,z0.s'
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.*: Error: selected processor does not support `uminqv v0.16b,p0,z16.b'
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.*: Error: selected processor does not support `uminqv v1.8h,p1,z8.h'
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.*: Error: selected processor does not support `uminqv v2.4s,p2,z4.s'
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.*: Error: selected processor does not support `uminqv v4.2d,p3,z2.d'
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.*: Error: selected processor does not support `uminqv v8.2d,p4,z1.d'
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.*: Error: selected processor does not support `uminqv v16.4s,p7,z0.s'
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46
gas/testsuite/gas/aarch64/sve2p1-1.d
Normal file
46
gas/testsuite/gas/aarch64/sve2p1-1.d
Normal file
@ -0,0 +1,46 @@
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#name: Test of SVE2.1 min max instructions.
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#as: -march=armv9.4-a+sve2p1
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#objdump: -dr
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[^:]+: file format .*
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[^:]+:
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[^:]+:
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.*: 04052200 addqv v0.16b, p0, z16.b
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.*: 04452501 addqv v1.8h, p1, z8.h
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.*: 04852882 addqv v2.4s, p2, z4.s
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.*: 04c52c44 addqv v4.2d, p3, z2.d
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.*: 04c53028 addqv v8.2d, p4, z1.d
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.*: 04853c10 addqv v16.4s, p7, z0.s
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.*: 041e2200 andqv v0.16b, p0, z16.b
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.*: 045e2501 andqv v1.8h, p1, z8.h
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.*: 049e2882 andqv v2.4s, p2, z4.s
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.*: 04de2c44 andqv v4.2d, p3, z2.d
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.*: 04de3028 andqv v8.2d, p4, z1.d
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.*: 049e3c10 andqv v16.4s, p7, z0.s
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.*: 040c2200 smaxqv v0.16b, p0, z16.b
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.*: 044c2501 smaxqv v1.8h, p1, z8.h
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.*: 048c2882 smaxqv v2.4s, p2, z4.s
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.*: 04cc2c44 smaxqv v4.2d, p3, z2.d
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.*: 04cc3028 smaxqv v8.2d, p4, z1.d
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.*: 048c3c10 smaxqv v16.4s, p7, z0.s
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.*: 040d2200 umaxqv v0.16b, p0, z16.b
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.*: 044d2501 umaxqv v1.8h, p1, z8.h
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.*: 048d2882 umaxqv v2.4s, p2, z4.s
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.*: 04cd2c44 umaxqv v4.2d, p3, z2.d
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.*: 04cd3028 umaxqv v8.2d, p4, z1.d
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.*: 048d3c10 umaxqv v16.4s, p7, z0.s
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.*: 040e2200 sminqv v0.16b, p0, z16.b
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.*: 044e2501 sminqv v1.8h, p1, z8.h
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.*: 048e2882 sminqv v2.4s, p2, z4.s
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.*: 04ce2c44 sminqv v4.2d, p3, z2.d
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.*: 04ce3028 sminqv v8.2d, p4, z1.d
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.*: 048e3c10 sminqv v16.4s, p7, z0.s
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.*: 040f2200 uminqv v0.16b, p0, z16.b
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.*: 044f2501 uminqv v1.8h, p1, z8.h
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.*: 048f2882 uminqv v2.4s, p2, z4.s
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.*: 04cf2c44 uminqv v4.2d, p3, z2.d
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.*: 04cf3028 uminqv v8.2d, p4, z1.d
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.*: 048f3c10 uminqv v16.4s, p7, z0.s
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41
gas/testsuite/gas/aarch64/sve2p1-1.s
Normal file
41
gas/testsuite/gas/aarch64/sve2p1-1.s
Normal file
@ -0,0 +1,41 @@
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addqv v0.16b, p0, z16.b
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addqv v1.8h, p1, z8.h
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addqv v2.4s, p2, z4.s
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addqv v4.2d, p3, z2.d
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addqv v8.2d, p4, z1.d
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addqv v16.4s, p7, z0.s
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andqv v0.16b, p0, z16.b
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andqv v1.8h, p1, z8.h
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andqv v2.4s, p2, z4.s
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andqv v4.2d, p3, z2.d
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andqv v8.2d, p4, z1.d
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andqv v16.4s, p7, z0.s
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smaxqv v0.16b, p0, z16.b
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smaxqv v1.8h, p1, z8.h
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smaxqv v2.4s, p2, z4.s
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smaxqv v4.2d, p3, z2.d
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smaxqv v8.2d, p4, z1.d
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smaxqv v16.4s, p7, z0.s
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umaxqv v0.16b, p0, z16.b
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umaxqv v1.8h, p1, z8.h
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umaxqv v2.4s, p2, z4.s
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umaxqv v4.2d, p3, z2.d
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umaxqv v8.2d, p4, z1.d
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umaxqv v16.4s, p7, z0.s
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sminqv v0.16b, p0, z16.b
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sminqv v1.8h, p1, z8.h
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sminqv v2.4s, p2, z4.s
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sminqv v4.2d, p3, z2.d
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sminqv v8.2d, p4, z1.d
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sminqv v16.4s, p7, z0.s
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uminqv v0.16b, p0, z16.b
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uminqv v1.8h, p1, z8.h
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uminqv v2.4s, p2, z4.s
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uminqv v4.2d, p3, z2.d
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uminqv v8.2d, p4, z1.d
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uminqv v16.4s, p7, z0.s
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@ -226,6 +226,8 @@ enum aarch64_feature_bit {
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AARCH64_FEATURE_B16B16,
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/* SME2.1 instructions. */
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AARCH64_FEATURE_SME2p1,
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/* SVE2.1 instructions. */
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AARCH64_FEATURE_SVE2p1,
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AARCH64_NUM_FEATURES
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};
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@ -1000,6 +1002,7 @@ enum aarch64_insn_class
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cssc,
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gcs,
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the,
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sve2_urqvs
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};
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/* Opcode enumerators. */
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@ -1272,7 +1275,9 @@ extern const aarch64_opcode aarch64_opcode_table[];
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allow. This impacts the constraintts on assembly but yelds no
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impact on disassembly. */
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#define F_OPD_NARROW (1ULL << 33)
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/* Next bit is 34. */
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/* For the instruction with size[22:23] field. */
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#define F_OPD_SIZE (1ULL << 34)
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/* Next bit is 35. */
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/* Instruction constraints. */
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/* This instruction has a predication constraint on the instruction at PC+4. */
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@ -1339,7 +1344,8 @@ static inline bool
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opcode_has_special_coder (const aarch64_opcode *opcode)
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{
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return (opcode->flags & (F_SF | F_LSE_SZ | F_SIZEQ | F_FPTYPE | F_SSIZE | F_T
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| F_GPRSIZE_IN_Q | F_LDS_SIZE | F_MISC | F_N | F_COND)) != 0;
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| F_GPRSIZE_IN_Q | F_LDS_SIZE | F_MISC | F_N | F_COND
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| F_OPD_SIZE)) != 0;
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}
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struct aarch64_name_value_pair
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@ -1981,6 +1981,20 @@ do_special_encoding (struct aarch64_inst *inst)
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gen_sub_field (FLD_imm5, 0, num + 1, &field);
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insert_field_2 (&field, &inst->value, 1 << num, inst->opcode->mask);
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}
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if ((inst->opcode->flags & F_OPD_SIZE) && inst->opcode->iclass == sve2_urqvs)
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{
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enum aarch64_opnd_qualifier qualifier[1];
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aarch64_insn value1 = 0;
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idx = 0;
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qualifier[0] = inst->operands[idx].qualifier;
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qualifier[1] = inst->operands[idx+2].qualifier;
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value = aarch64_get_qualifier_standard_value (qualifier[0]);
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value1 = aarch64_get_qualifier_standard_value (qualifier[1]);
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assert ((value >> 1) == value1);
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insert_field (FLD_size, &inst->value, value1, inst->opcode->mask);
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}
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if (inst->opcode->flags & F_GPRSIZE_IN_Q)
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{
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/* Use Rt to encode in the case of e.g.
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@ -2609,6 +2609,16 @@ do_special_decoding (aarch64_inst *inst)
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get_vreg_qualifier_from_value ((num << 1) | Q);
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}
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if ((inst->opcode->flags & F_OPD_SIZE) && inst->opcode->iclass == sve2_urqvs)
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{
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unsigned size;
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size = (unsigned) extract_field (FLD_size, inst->value,
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inst->opcode->mask);
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inst->operands[0].qualifier
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= get_vreg_qualifier_from_value (1 + (size << 1));
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inst->operands[2].qualifier = get_sreg_qualifier_from_value (size);
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}
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if (inst->opcode->flags & F_GPRSIZE_IN_Q)
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{
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/* Use Rt to encode in the case of e.g.
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@ -1487,6 +1487,10 @@
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- P: the operand has a /[ZM] suffix and the choice of suffix is not
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the same for all variants.
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- v: the operand has a V_[16B|8H|4S|2D] qualifier and the choice of
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qualifier suffix is not the same for all variants. This is used for
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the same kinds of operands as [BHSD] above.
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The _<sizes>, if present, give the subset of [BHSD] that are accepted
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by the V entries in <operands>. */
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#define OP_SVE_B \
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@ -1911,6 +1915,13 @@
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QLF3(S_S,S_H,NIL), \
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QLF3(S_D,S_S,NIL), \
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}
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#define OP_SVE_vUS_BHSD_BHSD \
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{ \
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QLF3(V_16B,NIL,S_B), \
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QLF3(V_8H,NIL,S_H), \
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QLF3(V_4S,NIL,S_S), \
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QLF3(V_2D,NIL,S_D), \
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}
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#define OP_SVE_VMV_SD \
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{ \
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QLF3(S_S,P_M,S_S), \
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@ -2620,6 +2631,8 @@ static const aarch64_feature_set aarch64_feature_b16b16 =
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AARCH64_FEATURE (B16B16);
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static const aarch64_feature_set aarch64_feature_sme2p1 =
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AARCH64_FEATURE (SME2p1);
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static const aarch64_feature_set aarch64_feature_sve2p1 =
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AARCH64_FEATURE (SVE2p1);
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#define CORE &aarch64_feature_v8
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#define FP &aarch64_feature_fp
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@ -2684,6 +2697,7 @@ static const aarch64_feature_set aarch64_feature_sme2p1 =
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#define D128_THE &aarch64_feature_d128_the
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#define B16B16 &aarch64_feature_b16b16
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#define SME2p1 &aarch64_feature_sme2p1
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#define SVE2p1 &aarch64_feature_sve2p1
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#define CORE_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS) \
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{ NAME, OPCODE, MASK, CLASS, OP, CORE, OPS, QUALS, FLAGS, 0, 0, NULL }
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@ -2762,6 +2776,12 @@ static const aarch64_feature_set aarch64_feature_sme2p1 =
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#define B16B16_INSNC(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,CONSTRAINTS,TIED) \
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{ NAME, OPCODE, MASK, CLASS, OP, B16B16, OPS, QUALS, \
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FLAGS | F_STRICT, CONSTRAINTS, TIED, NULL }
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#define SVE2p1_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,TIED) \
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{ NAME, OPCODE, MASK, CLASS, OP, SVE2p1, OPS, QUALS, \
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FLAGS | F_STRICT, 0, TIED, NULL }
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#define SVE2p1_INSNC(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,CONSTRAINTS,TIED) \
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{ NAME, OPCODE, MASK, CLASS, OP, SVE2p1, OPS, QUALS, \
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FLAGS | F_STRICT, CONSTRAINTS, TIED, NULL }
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#define SVE2AES_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,TIED) \
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{ NAME, OPCODE, MASK, CLASS, OP, SVE2_AES, OPS, QUALS, \
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FLAGS | F_STRICT, 0, TIED, NULL }
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@ -6309,6 +6329,15 @@ const struct aarch64_opcode aarch64_opcode_table[] =
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SME2p1_INSN ("movaz", 0xc0460200, 0xffff1f01, sme2_movaz, 0, OP2 (SME_Zdnx2, SME_ZA_array_vrsh_1), OP_SVE_HH, 0, 0),
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SME2p1_INSN ("movaz", 0xc0860200, 0xffff1f01, sme2_movaz, 0, OP2 (SME_Zdnx2, SME_ZA_array_vrss_1), OP_SVE_SS, 0, 0),
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SME2p1_INSN ("movaz", 0xc0c60200, 0xffff1f01, sme2_movaz, 0, OP2 (SME_Zdnx2, SME_ZA_array_vrsd_1), OP_SVE_DD, 0, 0),
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/* SVE2p1 Instructions. */
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SVE2p1_INSNC("addqv",0x04052000, 0xff3fe000, sve2_urqvs, 0, OP3 (Vd, SVE_Pg3, SVE_Zn), OP_SVE_vUS_BHSD_BHSD, F_OPD_SIZE, C_SCAN_MOVPRFX, 0),
|
||||
SVE2p1_INSNC("andqv",0x041e2000, 0xff3fe000, sve2_urqvs, 0, OP3 (Vd, SVE_Pg3, SVE_Zn), OP_SVE_vUS_BHSD_BHSD, F_OPD_SIZE, C_SCAN_MOVPRFX, 0),
|
||||
SVE2p1_INSNC("smaxqv",0x040c2000, 0xff3fe000, sve2_urqvs, 0, OP3 (Vd, SVE_Pg3, SVE_Zn), OP_SVE_vUS_BHSD_BHSD, F_OPD_SIZE, C_SCAN_MOVPRFX, 0),
|
||||
SVE2p1_INSNC("sminqv",0x040e2000, 0xff3fe000, sve2_urqvs, 0, OP3 (Vd, SVE_Pg3, SVE_Zn), OP_SVE_vUS_BHSD_BHSD, F_OPD_SIZE, C_SCAN_MOVPRFX, 0),
|
||||
SVE2p1_INSNC("umaxqv",0x040d2000, 0xff3fe000, sve2_urqvs, 0, OP3 (Vd, SVE_Pg3, SVE_Zn), OP_SVE_vUS_BHSD_BHSD, F_OPD_SIZE, C_SCAN_MOVPRFX, 0),
|
||||
SVE2p1_INSNC("uminqv",0x040f2000, 0xff3fe000, sve2_urqvs, 0, OP3 (Vd, SVE_Pg3, SVE_Zn), OP_SVE_vUS_BHSD_BHSD, F_OPD_SIZE, C_SCAN_MOVPRFX, 0),
|
||||
|
||||
{0, 0, 0, 0, 0, 0, {}, {}, 0, 0, 0, NULL},
|
||||
};
|
||||
|
||||
|
||||
Loading…
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Reference in New Issue
Block a user