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[PATCH] Add micromips support to the MIPS simulator

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2015-09-25  Andrew Bennett  <andrew.bennett@imgtec.com>
 	      Ali Lown  <ali.lown@imgtec.com>

	sim/common/
	* sim-bits.h (EXTEND6): New macro.
	(EXTEND12): New macro.
	(EXTEND25): New macro.

	sim/mips/
	* Makefile.in (tmp-micromips): New rule.
	(tmp-mach-multi): Add support for micromips.
	* configure.ac (mips*-sde-elf* | mips*-mti-elf*): Made a multi sim
	that works for both mips64 and micromips64.
	(mipsisa32r2*-*-*): Made a multi sim that works for mips32 and
	micromips32.
	Add build support for micromips.
	* dsp.igen (do_ph_s_absq, do_w_s_absq, do_qb_s_absq, do_addsc,
	do_addwc, do_bitrev, do_extpv, do_extrv, do_extrv_s_h, do_insv,
	do_lxx do_modsub, do_mthlip, do_mulsaq_s_w_ph, do_ph_packrl, do_qb_pick
	do_ph_pick, do_qb_ph_precequ, do_qb_ph_preceu, do_w_preceq
	do_w_ph_precrq, do_ph_qb_precrq, do_w_ph_rs_precrq do_qb_w_raddu,
	do_rddsp, do_repl, do_shilov, do_ph_shl, do_qb_shl do_w_s_shllv,
	do_ph_shrlv, do_w_r_shrav, do_wrdsp, do_qb_shrav, do_append,
	do_balign, do_ph_w_mulsa, do_ph_qb_precr, do_prepend): New functions.
	Refactored instruction code to use these functions.
	* dsp2.igen: Refactored instruction code to use the new functions.
	* interp.c (decode_coproc): Refactored to work with any instruction
	encoding.
	(isa_mode): New variable
	(RSVD_INSTRUCTION): Changed to 0x00000039.
	* m16.igen (BREAK16): Refactored instruction to use do_break16.
	(JALX32): Add mips32, mips64, mips32r2 and mips64r2 models.
	* micromips.dc: New file.
	* micromips.igen: New file.
	* micromips16.dc: New file.
	* micromipsdsp.igen: New file.
	* micromipsrun.c: New file.
	* mips.igen (do_swc1): Changed to work with any instruction encoding.
	(do_add do_addi do_andi do_dadd do_daddi do_dsll32 do_dsra32
	do_dsrl32, do_dsub, do_break, do_break16, do_clo, do_clz, do_dclo
	do_dclz, do_lb, do_lh, do_lwr, do_lwl, do_lwc, do_lw, do_lwu, do_lhu
	do_ldc, do_lbu, do_ll, do_lld, do_lui, do_madd, do_dsp_madd, do_maddu
	do_dsp_maddu, do_dsp_mfhi, do_dsp_mflo, do_movn, do_movz, do_msub
	do_dsp_msub, do_msubu, do_dsp_msubu, do_mthi, do_dsp_mthi, do_mtlo
	do_dsp_mtlo, do_mul, do_dsp_mult, do_dsp_multu, do_pref, do_sc, do_scd
	do_sub, do_sw, do_teq, do_teqi, do_tge, do_tgei, do_tgeiu, do_tgeu, do_tlt
	do_tlti, do_tltiu, do_tltu, do_tne, do_tnei, do_abs_fmt, do_add_fmt
	do_alnv_ps, do_c_cond_fmt, do_ceil_fmt, do_cfc1, do_ctc1, do_cvt_d_fmt
	do_cvt_l_fmt, do_cvt_ps_s, do_cvt_s_fmt, do_cvt_s_pl, do_cvt_s_pu
	do_cvt_w_fmt, do_div_fmt, do_dmfc1b, do_dmtc1b, do_floor_fmt, do_luxc1_32
	do_luxc1_64, do_lwc1, do_lwxc1, do_madd_fmt, do_mfc1b, do_mov_fmt, do_movtf
	do_movtf_fmt, do_movn_fmt, do_movz_fmt, do_msub_fmt, do_mtc1b, do_mul_fmt
	do_neg_fmt, do_nmadd_fmt, do_nmsub_fmt, do_pll_ps, do_plu_ps, do_pul_ps
	do_puu_ps, do_recip_fmt, do_round_fmt, do_rsqrt_fmt, do_prefx, do_sdc1
	do_suxc1_32, do_suxc1_64, do_sqrt_fmt, do_sub_fmt, do_swc1, do_swxc1
	do_trunc_fmt): New functions, refactored from existing instructions.
	Refactored instruction code to use these functions.
	(RSVD): Changed to use new reserved instruction.
	(loadstore_ea, not_word_value, unpredictable, check_mt_hilo, check_mf_hilo,
	check_mult_hilo, check_div_hilo, check_u64, do_luxc1_32, do_sdc1, do_suxc1_32,
	check_fmt_p, check_fpu, do_load_double, do_store_double):  Added micromips32
	and micromips64 models.
	Added include for micromips.igen and micromipsdsp.igen
	Add micromips32 and micromips64 models.
	(DecodeCoproc): Updated to use new macro definition.
	* mips3264r2.igen (do_dsbh, do_dshd, do_dext, do_dextm, do_dextu, do_di,
	do_dins, do_dinsm, do_ei, do_ext, do_mfhc1, do_mthc1, do_ins, do_dinsu,
	do_seb, do_seh do_rdhwr, do_wsbh): New functions.
	Refactored instruction code to use these functions.
	* sim-main.h (CP0_operation): New enum.
	(DecodeCoproc): Updated macro.
	(IMEM32_MICROMIPS, IMEM16_MICROMIPS, MICROMIPS_MINOR_OPCODE,
	MICROMIPS_DELAYSLOT_SIZE_ANY, MICROMIPS_DELAYSLOT_SIZE_16, MICROMIPS_DELAYSLOT_SIZE_32,
	ISA_MODE_MIPS32 and ISA_MODE_MICROMIPS): New defines.
	(sim_state): Add isa_mode field.

	sim/testsuite/sim/mips/
       * basic.exp (run_micromips_test, run_sim_tests): New functions
	Add support for micromips tests.
	* hilo-hazard-4.s: New file.
	* testutils.inc (_dowrite): Changed reserved instruction encoding.
	(writemsg): Moved the la and li instructions before the data they are
	assigned to, which prevents a bug where MIPS32 relocations are used instead
	of micromips relocations when building for micromips.
This commit is contained in:
Andrew Bennett 2015-09-25 15:52:18 +01:00
parent 8a9e7a9121
commit 8e394ffc7a
22 changed files with 7290 additions and 1468 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

7
sim/common/ChangeLog
View File

@ -1,3 +1,10 @@
2015-09-25 Andrew Bennett <andrew.bennett@imgtec.com>
Ali Lown <ali.lown@imgtec.com>
* sim-bits.h (EXTEND6): New macro.
(EXTEND12): New macro.
(EXTEND25): New macro.
2015-06-24 Mike Frysinger <vapier@gentoo.org>
* sim-trace.c (trace_one_insn): Delete.

3
sim/common/sim-bits.h
View File

@ -501,11 +501,14 @@ INLINE_SIM_BITS(unsigned_word) MSINSERTED (unsigned_word val, int start, int sto
#define EXTEND4(X) (LSSEXT ((X), 3))
#define EXTEND5(X) (LSSEXT ((X), 4))
#define EXTEND6(X) (LSSEXT ((X), 5))
#define EXTEND8(X) ((signed_word)(signed8)(X))
#define EXTEND11(X) (LSSEXT ((X), 10))
#define EXTEND12(X) (LSSEXT ((X), 11))
#define EXTEND15(X) (LSSEXT ((X), 14))
#define EXTEND16(X) ((signed_word)(signed16)(X))
#define EXTEND24(X) (LSSEXT ((X), 23))
#define EXTEND25(X) (LSSEXT ((X), 24))
#define EXTEND32(X) ((signed_word)(signed32)(X))
#define EXTEND64(X) ((signed_word)(signed64)(X))

72
sim/mips/ChangeLog
View File

@ -1,3 +1,75 @@
2015-09-25 Andrew Bennett <andrew.bennett@imgtec.com>
Ali Lown <ali.lown@imgtec.com>
* Makefile.in (tmp-micromips): New rule.
(tmp-mach-multi): Add support for micromips.
* configure.ac (mips*-sde-elf* | mips*-mti-elf*): Made a multi sim
that works for both mips64 and micromips64.
(mipsisa32r2*-*-*): Made a multi sim that works for mips32 and
micromips32.
Add build support for micromips.
* dsp.igen (do_ph_s_absq, do_w_s_absq, do_qb_s_absq, do_addsc,
do_addwc, do_bitrev, do_extpv, do_extrv, do_extrv_s_h, do_insv,
do_lxx do_modsub, do_mthlip, do_mulsaq_s_w_ph, do_ph_packrl, do_qb_pick
do_ph_pick, do_qb_ph_precequ, do_qb_ph_preceu, do_w_preceq
do_w_ph_precrq, do_ph_qb_precrq, do_w_ph_rs_precrq do_qb_w_raddu,
do_rddsp, do_repl, do_shilov, do_ph_shl, do_qb_shl do_w_s_shllv,
do_ph_shrlv, do_w_r_shrav, do_wrdsp, do_qb_shrav, do_append,
do_balign, do_ph_w_mulsa, do_ph_qb_precr, do_prepend): New functions.
Refactored instruction code to use these functions.
* dsp2.igen: Refactored instruction code to use the new functions.
* interp.c (decode_coproc): Refactored to work with any instruction
encoding.
(isa_mode): New variable
(RSVD_INSTRUCTION): Changed to 0x00000039.
* m16.igen (BREAK16): Refactored instruction to use do_break16.
(JALX32): Add mips32, mips64, mips32r2 and mips64r2 models.
* micromips.dc: New file.
* micromips.igen: New file.
* micromips16.dc: New file.
* micromipsdsp.igen: New file.
* micromipsrun.c: New file.
* mips.igen (do_swc1): Changed to work with any instruction encoding.
(do_add do_addi do_andi do_dadd do_daddi do_dsll32 do_dsra32
do_dsrl32, do_dsub, do_break, do_break16, do_clo, do_clz, do_dclo,
do_dclz, do_lb, do_lh, do_lwr, do_lwl, do_lwc, do_lw, do_lwu, do_lhu,
do_ldc, do_lbu, do_ll, do_lld, do_lui, do_madd, do_dsp_madd, do_maddu,
do_dsp_maddu, do_dsp_mfhi, do_dsp_mflo, do_movn, do_movz, do_msub,
do_dsp_msub, do_msubu, do_dsp_msubu, do_mthi, do_dsp_mthi, do_mtlo,
do_dsp_mtlo, do_mul, do_dsp_mult, do_dsp_multu, do_pref, do_sc,
do_scd, do_sub, do_sw, do_teq, do_teqi, do_tge, do_tgei, do_tgeiu,
do_tgeu, do_tlt do_tlti, do_tltiu, do_tltu, do_tne, do_tnei, do_abs_fmt,
do_add_fmt, do_alnv_ps, do_c_cond_fmt, do_ceil_fmt, do_cfc1, do_ctc1,
do_cvt_d_fmt, do_cvt_l_fmt, do_cvt_ps_s, do_cvt_s_fmt, do_cvt_s_pl,
do_cvt_s_pu, do_cvt_w_fmt, do_div_fmt, do_dmfc1b, do_dmtc1b, do_floor_fmt,
do_luxc1_32, do_luxc1_64, do_lwc1, do_lwxc1, do_madd_fmt, do_mfc1b,
do_mov_fmt, do_movtf, do_movtf_fmt, do_movn_fmt, do_movz_fmt, do_msub_fmt,
do_mtc1b, do_mul_fmt, do_neg_fmt, do_nmadd_fmt, do_nmsub_fmt, do_pll_ps,
do_plu_ps, do_pul_ps, do_puu_ps, do_recip_fmt, do_round_fmt, do_rsqrt_fmt,
do_prefx, do_sdc1, do_suxc1_32, do_suxc1_64, do_sqrt_fmt, do_sub_fmt,
do_swc1, do_swxc1, do_trunc_fmt): New functions, refactored from existing
instructions.
Refactored instruction code to use these functions.
(RSVD): Changed to use new reserved instruction.
(loadstore_ea, not_word_value, unpredictable, check_mt_hilo,
check_mf_hilo, check_mult_hilo, check_div_hilo, check_u64, do_luxc1_32,
do_sdc1, do_suxc1_32, check_fmt_p, check_fpu, do_load_double,
do_store_double): Added micromips32 and micromips64 models.
Added include for micromips.igen and micromipsdsp.igen
Add micromips32 and micromips64 models.
(DecodeCoproc): Updated to use new macro definition.
* mips3264r2.igen (do_dsbh, do_dshd, do_dext, do_dextm, do_dextu, do_di,
do_dins, do_dinsm, do_ei, do_ext, do_mfhc1, do_mthc1, do_ins, do_dinsu,
do_seb, do_seh do_rdhwr, do_wsbh): New functions.
Refactored instruction code to use these functions.
* sim-main.h (CP0_operation): New enum.
(DecodeCoproc): Updated macro.
(IMEM32_MICROMIPS, IMEM16_MICROMIPS, MICROMIPS_MINOR_OPCODE,
MICROMIPS_DELAYSLOT_SIZE_ANY, MICROMIPS_DELAYSLOT_SIZE_16,
MICROMIPS_DELAYSLOT_SIZE_32, ISA_MODE_MIPS32 and
ISA_MODE_MICROMIPS): New defines.
(sim_state): Add isa_mode field.
2015-06-23 Mike Frysinger <vapier@gentoo.org>
* configure: Regenerate.

324
sim/mips/Makefile.in
View File

@ -35,7 +35,29 @@ SIM_M16_OBJ = \
itable.o \
m16run.o \
SIM_MULTI_OBJ = itable.o @sim_multi_obj@
SIM_MICROMIPS_OBJ = \
micromips16_support.o \
micromips16_semantics.o \
micromips16_idecode.o \
micromips16_icache.o \
\
micromips32_support.o \
micromips32_semantics.o \
micromips32_idecode.o \
micromips32_icache.o \
\
micromips_m32_support.o \
micromips_m32_semantics.o \
micromips_m32_idecode.o \
micromips_m32_icache.o \
\
itable.o \
micromipsrun.o \
SIM_MULTI_OBJ = @sim_multi_obj@ \
itable.o \
multi-run.o \
MIPS_EXTRA_LIBS = @mips_extra_libs@
@ -68,11 +90,11 @@ SIM_EXTRA_LIBS = $(MIPS_EXTRA_LIBS)
## COMMON_POST_CONFIG_FRAG
interp.o: $(srcdir)/interp.c config.h sim-main.h itable.h
cp1.o: $(srcdir)/cp1.c config.h sim-main.h
mdmx.o: $(srcdir)/mdmx.c $(srcdir)/sim-main.h
m16run.o: sim-main.h m16_idecode.h m32_idecode.h m16run.c $(SIM_EXTRA_DEPS)
dsp.o: $(srcdir)/dsp.c $(srcdir)/sim-main.h
micromipsrun.o: sim-main.h micromips16_idecode.h micromips32_idecode.h \
micromips_m32_idecode.h micromipsrun.c $(SIM_EXTRA_DEPS)
multi-run.o: multi-include.h tmp-mach-multi
@ -83,7 +105,11 @@ IGEN_TRACE= # -G omit-line-numbers # -G trace-rule-selection -G trace-rule-rejec
IGEN_INSN=$(srcdir)/mips.igen
IGEN_DC=$(srcdir)/mips.dc
M16_DC=$(srcdir)/m16.dc
MICROMIPS32_DC=$(srcdir)/micromips.dc
MICROMIPS16_DC=$(srcdir)/micromips16.dc
IGEN_INCLUDE=\
$(srcdir)/micromipsdsp.igen \
$(srcdir)/micromips.igen \
$(srcdir)/m16.igen \
$(srcdir)/m16e.igen \
$(srcdir)/mdmx.igen \
@ -104,6 +130,7 @@ BUILT_SRC_FROM_GEN = \
SIM_IGEN_ALL = tmp-igen
SIM_M16_ALL = tmp-m16
SIM_MICROMIPS_ALL = tmp-micromips
SIM_MULTI_ALL = tmp-multi
$(BUILT_SRC_FROM_GEN): $(SIM_@sim_gen@_ALL)
@ -174,25 +201,6 @@ tmp-igen: $(IGEN_INSN) $(IGEN_DC) ../igen/igen $(IGEN_INCLUDE)
$(SHELL) $(srcdir)/../../move-if-change tmp-irun.c irun.c
touch tmp-igen
semantics.o: sim-main.h semantics.c $(SIM_EXTRA_DEPS)
engine.o: sim-main.h engine.c $(SIM_EXTRA_DEPS)
support.o: sim-main.h support.c $(SIM_EXTRA_DEPS)
idecode.o: sim-main.h idecode.c $(SIM_EXTRA_DEPS)
itable.o: sim-main.h itable.c $(SIM_EXTRA_DEPS)
m16run.o: sim-main.h m16_idecode.h m32_idecode.h $(SIM_EXTRA_DEPS)
m16_semantics.o: sim-main.h m16_semantics.c $(SIM_EXTRA_DEPS)
m16_support.o: sim-main.h m16_support.c $(SIM_EXTRA_DEPS)
m16_idecode.o: sim-main.h m16_idecode.c $(SIM_EXTRA_DEPS)
m16_icache.o: sim-main.h m16_icache.c $(SIM_EXTRA_DEPS)
m32_semantics.o: sim-main.h m32_semantics.c $(SIM_EXTRA_DEPS)
m32_support.o: sim-main.h m32_support.c $(SIM_EXTRA_DEPS)
m32_idecode.o: sim-main.h m32_idecode.c $(SIM_EXTRA_DEPS)
m32_icache.o: sim-main.h m32_icache.c $(SIM_EXTRA_DEPS)
$(SIM_MULTI_OBJ): sim-main.h $(SIM_EXTRA_DEPS)
BUILT_SRC_FROM_M16 = \
m16_icache.h \
m16_icache.c \
@ -284,8 +292,10 @@ tmp-m16: $(IGEN_INSN) $(IGEN_DC) ../igen/igen $(IGEN_INCLUDE)
$(SHELL) $(srcdir)/../../move-if-change tmp-icache.c m32_icache.c
$(SHELL) $(srcdir)/../../move-if-change tmp-idecode.h m32_idecode.h
$(SHELL) $(srcdir)/../../move-if-change tmp-idecode.c m32_idecode.c
$(SHELL) $(srcdir)/../../move-if-change tmp-semantics.h m32_semantics.h
$(SHELL) $(srcdir)/../../move-if-change tmp-semantics.c m32_semantics.c
$(SHELL) $(srcdir)/../../move-if-change tmp-semantics.h \
m32_semantics.h
$(SHELL) $(srcdir)/../../move-if-change tmp-semantics.c \
m32_semantics.c
$(SHELL) $(srcdir)/../../move-if-change tmp-model.h m32_model.h
$(SHELL) $(srcdir)/../../move-if-change tmp-model.c m32_model.c
$(SHELL) $(srcdir)/../../move-if-change tmp-support.h m32_support.h
@ -307,6 +317,196 @@ tmp-m16: $(IGEN_INSN) $(IGEN_DC) ../igen/igen $(IGEN_INCLUDE)
$(SHELL) $(srcdir)/../../move-if-change tmp-itable.c itable.c
touch tmp-m16
BUILT_SRC_FROM_MICROMIPS = \
micromips16_icache.h \
micromips16_icache.c \
micromips16_idecode.h \
micromips16_idecode.c \
micromips16_semantics.h \
micromips16_semantics.c \
micromips16_model.h \
micromips16_model.c \
micromips16_support.h \
micromips16_support.c \
\
micromips32_icache.h \
micromips32_icache.c \
micromips32_idecode.h \
micromips32_idecode.c \
micromips32_semantics.h \
micromips32_semantics.c \
micromips32_model.h \
micromips32_model.c \
micromips32_support.h \
micromips32_support.c \
\
micromips_m32_icache.h \
micromips_m32_icache.c \
micromips_m32_idecode.h \
micromips_m32_idecode.c \
micromips_m32_semantics.h \
micromips_m32_semantics.c \
micromips_m32_model.h \
micromips_m32_model.c \
micromips_m32_support.h \
micromips_m32_support.c \
$(BUILT_SRC_FROM_MICROMIPS): tmp-micromips
tmp-micromips: $(IGEN_INSN) $(IGEN_DC) ../igen/igen $(IGEN_INCLUDE)
cd ../igen && $(MAKE)
../igen/igen \
$(IGEN_TRACE) \
-I $(srcdir) \
-Werror \
-Wnodiscard \
@sim_micromips16_flags@ \
-G gen-direct-access \
-G gen-zero-r0 \
-B 16 \
-H 15 \
-i $(IGEN_INSN) \
-o $(MICROMIPS16_DC) \
-P micromips16_ \
-x \
-n micromips16_icache.h -hc tmp-icache.h \
-n micromips16_icache.c -c tmp-icache.c \
-n micromips16_semantics.h -hs tmp-semantics.h \
-n micromips16_semantics.c -s tmp-semantics.c \
-n micromips16_idecode.h -hd tmp-idecode.h \
-n micromips16_idecode.c -d tmp-idecode.c \
-n micromips16_model.h -hm tmp-model.h \
-n micromips16_model.c -m tmp-model.c \
-n micromips16_support.h -hf tmp-support.h \
-n micromips16_support.c -f tmp-support.c \
#
$(SHELL) $(srcdir)/../../move-if-change tmp-icache.h \
micromips16_icache.h
$(SHELL) $(srcdir)/../../move-if-change tmp-icache.c \
micromips16_icache.c
$(SHELL) $(srcdir)/../../move-if-change tmp-idecode.h \
micromips16_idecode.h
$(SHELL) $(srcdir)/../../move-if-change tmp-idecode.c \
micromips16_idecode.c
$(SHELL) $(srcdir)/../../move-if-change tmp-semantics.h \
micromips16_semantics.h
$(SHELL) $(srcdir)/../../move-if-change tmp-semantics.c \
micromips16_semantics.c
$(SHELL) $(srcdir)/../../move-if-change tmp-model.h \
micromips16_model.h
$(SHELL) $(srcdir)/../../move-if-change tmp-model.c \
micromips16_model.c
$(SHELL) $(srcdir)/../../move-if-change tmp-support.h \
micromips16_support.h
$(SHELL) $(srcdir)/../../move-if-change tmp-support.c \
micromips16_support.c
cd ../igen && $(MAKE)
../igen/igen \
$(IGEN_TRACE) \
-I $(srcdir) \
-Werror \
-Wnodiscard \
@sim_micromips_flags@ \
-G gen-direct-access \
-G gen-zero-r0 \
-B 32 \
-H 31 \
-i $(IGEN_INSN) \
-o $(MICROMIPS32_DC) \
-P micromips32_ \
-x \
-n micromips32_icache.h -hc tmp-icache.h \
-n micromips32_icache.c -c tmp-icache.c \
-n micromips32_semantics.h -hs tmp-semantics.h \
-n micromips32_semantics.c -s tmp-semantics.c \
-n micromips32_idecode.h -hd tmp-idecode.h \
-n micromips32_idecode.c -d tmp-idecode.c \
-n micromips32_model.h -hm tmp-model.h \
-n micromips32_model.c -m tmp-model.c \
-n micromips32_support.h -hf tmp-support.h \
-n micromips32_support.c -f tmp-support.c \
#
$(SHELL) $(srcdir)/../../move-if-change tmp-icache.h \
micromips32_icache.h
$(SHELL) $(srcdir)/../../move-if-change tmp-icache.c \
micromips32_icache.c
$(SHELL) $(srcdir)/../../move-if-change tmp-idecode.h \
micromips32_idecode.h
$(SHELL) $(srcdir)/../../move-if-change tmp-idecode.c \
micromips32_idecode.c
$(SHELL) $(srcdir)/../../move-if-change tmp-semantics.h \
micromips32_semantics.h
$(SHELL) $(srcdir)/../../move-if-change tmp-semantics.c \
micromips32_semantics.c
$(SHELL) $(srcdir)/../../move-if-change tmp-model.h \
micromips32_model.h
$(SHELL) $(srcdir)/../../move-if-change tmp-model.c \
micromips32_model.c
$(SHELL) $(srcdir)/../../move-if-change tmp-support.h \
micromips32_support.h
$(SHELL) $(srcdir)/../../move-if-change tmp-support.c \
micromips32_support.c
../igen/igen \
$(IGEN_TRACE) \
-I $(srcdir) \
-Werror \
-Wnodiscard \
@sim_igen_flags@ \
-G gen-direct-access \
-G gen-zero-r0 \
-B 32 \
-H 31 \
-i $(IGEN_INSN) \
-o $(IGEN_DC) \
-P micromips_m32_ \
-x \
-n micromips_m32_icache.h -hc tmp-icache.h \
-n micromips_m32_icache.c -c tmp-icache.c \
-n micromips_m32_semantics.h -hs tmp-semantics.h \
-n micromips_m32_semantics.c -s tmp-semantics.c \
-n micromips_m32_idecode.h -hd tmp-idecode.h \
-n micromips_m32_idecode.c -d tmp-idecode.c \
-n micromips_m32_model.h -hm tmp-model.h \
-n micromips_m32_model.c -m tmp-model.c \
-n micromips_m32_support.h -hf tmp-support.h \
-n micromips_m32_support.c -f tmp-support.c \
#
$(SHELL) $(srcdir)/../../move-if-change tmp-icache.h \
micromips_m32_icache.h
$(SHELL) $(srcdir)/../../move-if-change tmp-icache.c \
micromips_m32_icache.c
$(SHELL) $(srcdir)/../../move-if-change tmp-idecode.h \
micromips_m32_idecode.h
$(SHELL) $(srcdir)/../../move-if-change tmp-idecode.c \
micromips_m32_idecode.c
$(SHELL) $(srcdir)/../../move-if-change tmp-semantics.h \
micromips_m32_semantics.h
$(SHELL) $(srcdir)/../../move-if-change tmp-semantics.c \
micromips_m32_semantics.c
$(SHELL) $(srcdir)/../../move-if-change tmp-model.h \
micromips_m32_model.h
$(SHELL) $(srcdir)/../../move-if-change tmp-model.c \
micromips_m32_model.c
$(SHELL) $(srcdir)/../../move-if-change tmp-support.h \
micromips_m32_support.h
$(SHELL) $(srcdir)/../../move-if-change tmp-support.c \
micromips_m32_support.c
../igen/igen \
$(IGEN_TRACE) \
-I $(srcdir) \
-Werror \
-Wnodiscard \
-Wnowidth \
@sim_igen_flags@ @sim_micromips_flags@ @sim_micromips16_flags@\
-G gen-direct-access \
-G gen-zero-r0 \
-i $(IGEN_INSN) \
-n itable.h -ht tmp-itable.h \
-n itable.c -t tmp-itable.c \
#
$(SHELL) $(srcdir)/../../move-if-change tmp-itable.h itable.h
$(SHELL) $(srcdir)/../../move-if-change tmp-itable.c itable.c
touch tmp-micromips
BUILT_SRC_FROM_MULTI = @sim_multi_src@
SIM_MULTI_IGEN_CONFIGS = @sim_multi_igen_configs@
@ -319,6 +519,15 @@ tmp-mach-multi: $(IGEN_INSN) $(IGEN_DC) ../igen/igen $(IGEN_INCLUDE)
m=`echo $${t} | sed -e 's/.*:\(.*\):.*/\1/'` ; \
f=`echo $${t} | sed -e 's/.*://'` ; \
case $${p} in \
micromips16*) e="-B 16 -H 15 -o $(MICROMIPS16_DC) -F 16" ;; \
micromips32* | micromips64*) \
e="-B 32 -H 31 -o $(MICROMIPS32_DC) -F $${f}" ;; \
micromips_m32*) \
e="-B 32 -H 31 -o $(IGEN_DC) -F $${f}"; \
m="mips32r2,mips3d,mdmx,dsp,dsp2,smartmips" ;; \
micromips_m64*) \
e="-B 32 -H 31 -o $(IGEN_DC) -F $${f}"; \
m="mips64r2,mips3d,mdmx,dsp,dsp2,smartmips" ;; \
m16*) e="-B 16 -H 15 -o $(M16_DC) -F 16" ;; \
*) e="-B 32 -H 31 -o $(IGEN_DC) -F $${f}" ;; \
esac; \
@ -348,18 +557,30 @@ tmp-mach-multi: $(IGEN_INSN) $(IGEN_DC) ../igen/igen $(IGEN_INCLUDE)
-n $${p}_engine.h -he tmp-engine.h \
-n $${p}_engine.c -e tmp-engine.c \
|| exit; \
$(SHELL) $(srcdir)/../../move-if-change tmp-icache.h $${p}_icache.h ; \
$(SHELL) $(srcdir)/../../move-if-change tmp-icache.c $${p}_icache.c ; \
$(SHELL) $(srcdir)/../../move-if-change tmp-idecode.h $${p}_idecode.h ; \
$(SHELL) $(srcdir)/../../move-if-change tmp-idecode.c $${p}_idecode.c ; \
$(SHELL) $(srcdir)/../../move-if-change tmp-semantics.h $${p}_semantics.h ; \
$(SHELL) $(srcdir)/../../move-if-change tmp-semantics.c $${p}_semantics.c ; \
$(SHELL) $(srcdir)/../../move-if-change tmp-model.h $${p}_model.h ; \
$(SHELL) $(srcdir)/../../move-if-change tmp-model.c $${p}_model.c ; \
$(SHELL) $(srcdir)/../../move-if-change tmp-support.h $${p}_support.h ; \
$(SHELL) $(srcdir)/../../move-if-change tmp-support.c $${p}_support.c ; \
$(SHELL) $(srcdir)/../../move-if-change tmp-engine.h $${p}_engine.h ; \
$(SHELL) $(srcdir)/../../move-if-change tmp-engine.c $${p}_engine.c ; \
$(SHELL) $(srcdir)/../../move-if-change tmp-icache.h \
$${p}_icache.h ; \
$(SHELL) $(srcdir)/../../move-if-change tmp-icache.c \
$${p}_icache.c ; \
$(SHELL) $(srcdir)/../../move-if-change tmp-idecode.h \
$${p}_idecode.h ; \
$(SHELL) $(srcdir)/../../move-if-change tmp-idecode.c \
$${p}_idecode.c ; \
$(SHELL) $(srcdir)/../../move-if-change tmp-semantics.h \
$${p}_semantics.h ; \
$(SHELL) $(srcdir)/../../move-if-change tmp-semantics.c \
$${p}_semantics.c ; \
$(SHELL) $(srcdir)/../../move-if-change tmp-model.h \
$${p}_model.h ; \
$(SHELL) $(srcdir)/../../move-if-change tmp-model.c \
$${p}_model.c ; \
$(SHELL) $(srcdir)/../../move-if-change tmp-support.h \
$${p}_support.h ; \
$(SHELL) $(srcdir)/../../move-if-change tmp-support.c \
$${p}_support.c ; \
$(SHELL) $(srcdir)/../../move-if-change tmp-engine.h \
$${p}_engine.h ; \
$(SHELL) $(srcdir)/../../move-if-change tmp-engine.c \
$${p}_engine.c ; \
done
touch tmp-mach-multi
tmp-itable-multi: $(IGEN_INSN) $(IGEN_DC) ../igen/igen $(IGEN_INCLUDE)
@ -380,7 +601,7 @@ tmp-itable-multi: $(IGEN_INSN) $(IGEN_DC) ../igen/igen $(IGEN_INCLUDE)
$(SHELL) $(srcdir)/../../move-if-change tmp-itable.h itable.h
$(SHELL) $(srcdir)/../../move-if-change tmp-itable.c itable.c
touch tmp-itable-multi
tmp-run-multi: $(srcdir)/m16run.c
tmp-run-multi: $(srcdir)/m16run.c $(srcdir)/micromipsrun.c
for t in $(SIM_MULTI_IGEN_CONFIGS); do \
case $${t} in \
m16*) \
@ -389,7 +610,29 @@ tmp-run-multi: $(srcdir)/m16run.c
-e "s/^sim_/m16$${m}_/" \
-e "s/m16_/m16$${m}_/" \
-e "s/m32_/m32$${m}_/" ; \
$(SHELL) $(srcdir)/../../move-if-change tmp-run m16$${m}_run.c ; \
$(SHELL) $(srcdir)/../../move-if-change tmp-run \
m16$${m}_run.c ; \
;;\
micromips32*) \
m=`echo $${t} | sed -e 's/^micromips32//' -e 's/:.*//'`; \
sed < $(srcdir)/micromipsrun.c > tmp-run \
-e "s/^sim_/micromips32$${m}_/" \
-e "s/micromips16_/micromips16$${m}_/" \
-e "s/micromips32_/micromips32$${m}_/" \
-e "s/m32_/m32$${m}_/" ; \
$(SHELL) $(srcdir)/../../move-if-change tmp-run \
micromips$${m}_run.c ; \
;;\
micromips64*) \
m=`echo $${t} | sed -e 's/^micromips64//' -e 's/:.*//'`; \
sed < $(srcdir)/micromipsrun.c > tmp-run \
-e "s/^sim_/micromips64$${m}_/" \
-e "s/micromips16_/micromips16$${m}_/" \
-e "s/micromips32_/micromips64$${m}_/" \
-e "s/m32_/m64$${m}_/" ; \
$(SHELL) $(srcdir)/../../move-if-change tmp-run \
micromips$${m}_run.c ; \
;;\
esac \
done
touch tmp-run-multi
@ -398,9 +641,10 @@ clean-extra:
rm -f $(BUILT_SRC_FROM_GEN)
rm -f $(BUILT_SRC_FROM_IGEN)
rm -f $(BUILT_SRC_FROM_M16)
rm -f $(BUILT_SRC_FROM_MICROMIPS)
rm -f $(BUILT_SRC_FROM_MULTI)
rm -f tmp-*
rm -f m16*.o m32*.o itable*.o
rm -f micromips16*.o micromips32*.o m16*.o m32*.o itable*.o
distclean-extra:
rm -f multi-include.h multi-run.c

61
sim/mips/configure vendored
View File

@ -609,6 +609,8 @@ sim_multi_src
sim_multi_igen_configs
sim_multi_flags
sim_gen
sim_micromips16_flags
sim_micromips_flags
sim_m16_flags
sim_igen_flags
SIM_SUBTARGET
@ -12347,7 +12349,7 @@ else
lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2
lt_status=$lt_dlunknown
cat > conftest.$ac_ext <<_LT_EOF
#line 12350 "configure"
#line 12352 "configure"
#include "confdefs.h"
#if HAVE_DLFCN_H
@ -12453,7 +12455,7 @@ else
lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2
lt_status=$lt_dlunknown
cat > conftest.$ac_ext <<_LT_EOF
#line 12456 "configure"
#line 12458 "configure"
#include "confdefs.h"
#if HAVE_DLFCN_H
@ -13674,11 +13676,11 @@ case "${target}" in
sim_multi_default=mips5000
;;
mips*-sde-elf* | mips*-mti-elf*)
sim_gen=M16
sim_igen_machine="-M mips64r2,mips3d,mips16,mips16e,mdmx,dsp,dsp2,smartmips"
sim_m16_machine="-M mips16,mips16e,mips64r2"
sim_igen_filter="32,64,f"
sim_mach_default="mipsisa64r2"
sim_gen=MULTI
sim_multi_configs="\
micromips:micromips64,micromipsdsp:32,64,f:mips_micromips\
mips64r2:mips64r2,mips3d,mips16,mips16e,mdmx,dsp,dsp2,smartmips:32,64,f:mipsisa64r2"
sim_multi_default=mipsisa64r2
;;
mips64*-*-*) sim_igen_filter="32,64,f"
sim_gen=IGEN
@ -13687,11 +13689,11 @@ case "${target}" in
sim_igen_filter="32,64,f"
sim_m16_filter="16"
;;
mipsisa32r2*-*-*) sim_gen=M16
sim_igen_machine="-M mips32r2,mips16,mips16e,mdmx,dsp,dsp2,smartmips"
sim_m16_machine="-M mips16,mips16e,mips32r2"
sim_igen_filter="32,f"
sim_mach_default="mipsisa32r2"
mipsisa32r2*-*-*) sim_gen=MULTI
sim_multi_configs="\
micromips:micromips32,micromipsdsp:32,f:mips_micromips\
mips32r2:mips32r2,mips3d,mips16,mips16e,mdmx,dsp,dsp2,smartmips:32,f:mipsisa32r2"
sim_multi_default=mipsisa32r2
;;
mipsisa32*-*-*) sim_gen=M16
sim_igen_machine="-M mips32,mips16,mips16e,smartmips"
@ -13763,7 +13765,7 @@ if test ${sim_gen} = MULTI; then
rm -f multi-include.h multi-run.c
sim_multi_flags=
sim_multi_src=
sim_multi_obj=multi-run.o
sim_multi_obj=
sim_multi_igen_configs=
sim_seen_default=no
@ -13790,6 +13792,8 @@ if test ${sim_gen} = MULTI; then
#include "sim-main.h"
#include "multi-include.h"
#include "elf-bfd.h"
#include "elf/mips.h"
#define SD sd
#define CPU cpu
@ -13804,6 +13808,9 @@ sim_engine_run (SIM_DESC sd,
if (STATE_ARCHITECTURE (sd) == NULL)
mach = bfd_mach_${sim_multi_default};
else if (elf_elfheader (sd->base.prog_bfd)->e_flags
& EF_MIPS_ARCH_ASE_MICROMIPS)
mach = bfd_mach_mips_micromips;
else
mach = STATE_ARCHITECTURE (SD)->mach;
@ -13833,7 +13840,7 @@ __EOF__
# the ${sim_multi_configs} entry.
sim_multi_flags="${sim_multi_flags} -F ${filter} -M ${machine}"
# Check whether mips16 handling is needed.
# Check whether special handling is needed.
case ${c} in
*:*mips16*:*)
# Run igen twice, once for normal mode and once for mips16.
@ -13846,6 +13853,30 @@ __EOF__
sim_multi_obj="${sim_multi_obj} m16${name}_run.o"
sim_multi_flags="${sim_multi_flags} -F 16"
;;
*:*micromips32*:*)
# Run igen thrice, once for micromips32, once for micromips16,
# and once for m32.
ws="micromips_m32 micromips16 micromips32"
# The top-level function for the micromips simulator is
# in a file micromips${name}_run.c, generated by the
# tmp-run-multi Makefile rule.
sim_multi_src="${sim_multi_src} micromips${name}_run.c"
sim_multi_obj="${sim_multi_obj} micromips${name}_run.o"
sim_multi_flags="${sim_multi_flags} -F 16,32"
;;
*:*micromips64*:*)
# Run igen thrice, once for micromips64, once for micromips16,
# and once for m64.
ws="micromips_m64 micromips16 micromips64"
# The top-level function for the micromips simulator is
# in a file micromips${name}_run.c, generated by the
# tmp-run-multi Makefile rule.
sim_multi_src="${sim_multi_src} micromips${name}_run.c"
sim_multi_obj="${sim_multi_obj} micromips${name}_run.o"
sim_multi_flags="${sim_multi_flags} -F 16,32,64"
;;
*)
ws=m32
;;
@ -13931,6 +13962,8 @@ else
fi
sim_igen_flags="-F ${sim_igen_filter} ${sim_igen_machine} ${sim_igen_smp}"
sim_m16_flags=" -F ${sim_m16_filter} ${sim_m16_machine} ${sim_igen_smp}"
sim_micromips16_flags=" -F ${sim_micromips16_filter} ${sim_micromips16_machine} ${sim_igen_smp}"
sim_micromips_flags=" -F ${sim_micromips_filter} ${sim_micromips_machine} ${sim_igen_smp}"

59
sim/mips/configure.ac
View File

@ -139,11 +139,11 @@ case "${target}" in
sim_multi_default=mips5000
;;
mips*-sde-elf* | mips*-mti-elf*)
sim_gen=M16
sim_igen_machine="-M mips64r2,mips3d,mips16,mips16e,mdmx,dsp,dsp2,smartmips"
sim_m16_machine="-M mips16,mips16e,mips64r2"
sim_igen_filter="32,64,f"
sim_mach_default="mipsisa64r2"
sim_gen=MULTI
sim_multi_configs="\
micromips:micromips64,micromipsdsp:32,64,f:mips_micromips\
mips64r2:mips64r2,mips3d,mips16,mips16e,mdmx,dsp,dsp2,smartmips:32,64,f:mipsisa64r2"
sim_multi_default=mipsisa64r2
;;
mips64*-*-*) sim_igen_filter="32,64,f"
sim_gen=IGEN
@ -152,11 +152,11 @@ case "${target}" in
sim_igen_filter="32,64,f"
sim_m16_filter="16"
;;
mipsisa32r2*-*-*) sim_gen=M16
sim_igen_machine="-M mips32r2,mips16,mips16e,mdmx,dsp,dsp2,smartmips"
sim_m16_machine="-M mips16,mips16e,mips32r2"
sim_igen_filter="32,f"
sim_mach_default="mipsisa32r2"
mipsisa32r2*-*-*) sim_gen=MULTI
sim_multi_configs="\
micromips:micromips32,micromipsdsp:32,f:mips_micromips\
mips32r2:mips32r2,mips3d,mips16,mips16e,mdmx,dsp,dsp2,smartmips:32,f:mipsisa32r2"
sim_multi_default=mipsisa32r2
;;
mipsisa32*-*-*) sim_gen=M16
sim_igen_machine="-M mips32,mips16,mips16e,smartmips"
@ -228,7 +228,7 @@ if test ${sim_gen} = MULTI; then
rm -f multi-include.h multi-run.c
sim_multi_flags=
sim_multi_src=
sim_multi_obj=multi-run.o
sim_multi_obj=
sim_multi_igen_configs=
sim_seen_default=no
@ -255,6 +255,8 @@ if test ${sim_gen} = MULTI; then
#include "sim-main.h"
#include "multi-include.h"
#include "elf-bfd.h"
#include "elf/mips.h"
#define SD sd
#define CPU cpu
@ -269,6 +271,9 @@ sim_engine_run (SIM_DESC sd,
if (STATE_ARCHITECTURE (sd) == NULL)
mach = bfd_mach_${sim_multi_default};
else if (elf_elfheader (sd->base.prog_bfd)->e_flags
& EF_MIPS_ARCH_ASE_MICROMIPS)
mach = bfd_mach_mips_micromips;
else
mach = STATE_ARCHITECTURE (SD)->mach;
@ -298,7 +303,7 @@ __EOF__
# the ${sim_multi_configs} entry.
sim_multi_flags="${sim_multi_flags} -F ${filter} -M ${machine}"
# Check whether mips16 handling is needed.
# Check whether special handling is needed.
case ${c} in
*:*mips16*:*)
# Run igen twice, once for normal mode and once for mips16.
@ -311,6 +316,30 @@ __EOF__
sim_multi_obj="${sim_multi_obj} m16${name}_run.o"
sim_multi_flags="${sim_multi_flags} -F 16"
;;
*:*micromips32*:*)
# Run igen thrice, once for micromips32, once for micromips16,
# and once for m32.
ws="micromips_m32 micromips16 micromips32"
# The top-level function for the micromips simulator is
# in a file micromips${name}_run.c, generated by the
# tmp-run-multi Makefile rule.
sim_multi_src="${sim_multi_src} micromips${name}_run.c"
sim_multi_obj="${sim_multi_obj} micromips${name}_run.o"
sim_multi_flags="${sim_multi_flags} -F 16,32"
;;
*:*micromips64*:*)
# Run igen thrice, once for micromips64, once for micromips16,
# and once for m64.
ws="micromips_m64 micromips16 micromips64"
# The top-level function for the micromips simulator is
# in a file micromips${name}_run.c, generated by the
# tmp-run-multi Makefile rule.
sim_multi_src="${sim_multi_src} micromips${name}_run.c"
sim_multi_obj="${sim_multi_obj} micromips${name}_run.o"
sim_multi_flags="${sim_multi_flags} -F 16,32,64"
;;
*)
ws=m32
;;
@ -396,15 +425,17 @@ else
fi
sim_igen_flags="-F ${sim_igen_filter} ${sim_igen_machine} ${sim_igen_smp}"
sim_m16_flags=" -F ${sim_m16_filter} ${sim_m16_machine} ${sim_igen_smp}"
sim_micromips16_flags=" -F ${sim_micromips16_filter} ${sim_micromips16_machine} ${sim_igen_smp}"
sim_micromips_flags=" -F ${sim_micromips_filter} ${sim_micromips_machine} ${sim_igen_smp}"
AC_SUBST(sim_igen_flags)
AC_SUBST(sim_m16_flags)
AC_SUBST(sim_micromips_flags)
AC_SUBST(sim_micromips16_flags)
AC_SUBST(sim_gen)
AC_SUBST(sim_multi_flags)
AC_SUBST(sim_multi_igen_configs)
AC_SUBST(sim_multi_src)
AC_SUBST(sim_multi_obj)
#
# Add simulated hardware devices
#

1041
sim/mips/dsp.igen
View File

File diff suppressed because it is too large Load Diff

84
sim/mips/dsp2.igen
View File

@ -5,7 +5,7 @@
// Contributed by MIPS Technologies, Inc.
// Written by Chao-ying Fu (fu@mips.com).
//
// This file is part of GDB, the GNU debugger.
// This file is part of the MIPS sim
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
@ -353,23 +353,7 @@
"absq_s.qb r<RD>, r<RT>"
*dsp2:
{
int i;
signed8 q0;
unsigned32 v1 = GPR[RT];
unsigned32 result = 0;
for (i = 0; i < 32; i += 8, v1 >>= 8)
{
q0 = (signed8)(v1 & 0xff);
if (q0 == (signed8)0x80)
{
DSPCR |= DSPCR_OUFLAG4;
q0 = 0x7f;
}
else if (q0 & 0x80)
q0 = -q0;
result |= ((unsigned32)((unsigned8)q0) << i);
}
GPR[RD] = EXTEND32 (result);
do_qb_s_absq (SD_, RD, RT);
}
011111,5.RS,5.RT,5.RD,01000,010000:SPECIAL3:32::ADDU.PH
@ -404,26 +388,14 @@
"append r<RT>, r<RS>, <SA>"
*dsp2:
{
unsigned32 v0 = GPR[RS];
unsigned32 v1 = GPR[RT];
unsigned32 result;
unsigned32 mask = (1 << SA) - 1;
result = (v1 << SA) | (v0 & mask);
GPR[RT] = EXTEND32 (result);
do_append (SD_, RT, RS, SA);
}
011111,5.RS,5.RT,000,2.BP,10000,110001:SPECIAL3:32::BALIGN
"balign r<RT>, r<RS>, <BP>"
*dsp2:
{
unsigned32 v0 = GPR[RS];
unsigned32 v1 = GPR[RT];
unsigned32 result;
if (BP == 0)
result = v1;
else
result = (v1 << 8 * BP) | (v0 >> 8 * (4 - BP));
GPR[RT] = EXTEND32 (result);
do_balign (SD_, RT, RS, BP);
}
011111,5.RS,5.RT,5.RD,11000,010001:SPECIAL3:32::CMPGDU.EQ.QB
@ -500,40 +472,14 @@
"mulsa.w.ph ac<AC>, r<RS>, r<RT>"
*dsp2:
{
int i;
unsigned32 v1 = GPR[RS];
unsigned32 v2 = GPR[RT];
signed16 h1, h2;
signed32 result;
unsigned32 lo = DSPLO(AC);
unsigned32 hi = DSPHI(AC);
signed64 prod = (signed64)((((unsigned64)hi) << 32) + (unsigned64)lo);
for (i = 0; i < 32; i += 16, v1 >>= 16, v2 >>= 16)
{
h1 = (signed16)(v1 & 0xffff);
h2 = (signed16)(v2 & 0xffff);
result = (signed32)h1 * (signed32)h2;
if (i == 0)
prod -= (signed64) result;
else
prod += (signed64) result;
}
DSPLO(AC) = EXTEND32 (prod);
DSPHI(AC) = EXTEND32 (prod >> 32);
do_ph_w_mulsa (SD_, AC, RS, RT);
}
011111,5.RS,5.RT,5.RD,01101,010001:SPECIAL3:32::PRECR.QB.PH
"precr.qb.ph r<RD>, r<RS>, r<RT>"
*dsp2:
{
unsigned32 v1 = GPR[RS];
unsigned32 v2 = GPR[RT];
unsigned32 tempu = (v1 & 0xff0000) >> 16;
unsigned32 tempv = (v1 & 0xff);
unsigned32 tempw = (v2 & 0xff0000) >> 16;
unsigned32 tempx = (v2 & 0xff);
GPR[RD] = EXTEND32 ((tempu << 24) | (tempv << 16) | (tempw << 8) | tempx);
do_ph_qb_precr (SD_, RD, RS, RT);
}
011111,5.RS,5.RT,5.SA,11110,010001:SPECIAL3:32::PRECR_SRA.PH.W
@ -554,14 +500,7 @@
"prepend r<RT>, r<RS>, <SA>"
*dsp2:
{
unsigned32 v0 = GPR[RS];
unsigned32 v1 = GPR[RT];
unsigned32 result;
if (SA == 0)
result = v1;
else
result = (v0 << (32 - SA)) | (v1 >> SA);
GPR[RT] = EXTEND32 (result);
do_prepend (SD_, RT, RS, SA);
}
011111,00,3.SHIFT3,5.RT,5.RD,00100,010011:SPECIAL3:32::SHRA.QB
@ -582,16 +521,14 @@
"shrav.qb r<RD>, r<RT>, r<RS>"
*dsp2:
{
unsigned32 shift = GPR[RS] & 0x7;
do_qb_shra (SD_, RD, RT, shift, 0);
do_qb_shrav (SD_, RD, RT, RS, 0);
}
011111,5.RS,5.RT,5.RD,00111,010011:SPECIAL3:32::SHRAV_R.QB
"shrav_r.qb r<RD>, r<RT>, r<RS>"
*dsp2:
{
unsigned32 shift = GPR[RS] & 0x7;
do_qb_shra (SD_, RD, RT, shift, 1);
do_qb_shrav (SD_, RD, RT, RS, 1);
}
011111,0,4.SHIFT4,5.RT,5.RD,11001,010011:SPECIAL3:32::SHRL.PH
@ -605,8 +542,7 @@
"shrlv.ph r<RD>, r<RT>, r<RS>"
*dsp2:
{
unsigned32 shift = GPR[RS] & 0xf;
do_ph_shrl (SD_, RD, RT, shift);
do_ph_shrlv (SD_, RD, RT, RS);
}
011111,5.RS,5.RT,5.RD,01001,010000:SPECIAL3:32::SUBU.PH

53
sim/mips/interp.c
View File

@ -71,7 +71,7 @@ char* pr_uword64 (uword64 addr);
trap is required. NOTE: Care must be taken, since this value may be
used in later revisions of the MIPS ISA. */
#define RSVD_INSTRUCTION (0x00000005)
#define RSVD_INSTRUCTION (0x00000039)
#define RSVD_INSTRUCTION_MASK (0xFC00003F)
#define RSVD_INSTRUCTION_ARG_SHIFT 6
@ -146,7 +146,6 @@ static SIM_ADDR lsipmon_monitor_base = 0xBFC00200;
static SIM_RC sim_firmware_command (SIM_DESC sd, char* arg);
#define MEM_SIZE (8 << 20) /* 8 MBytes */
@ -2186,18 +2185,17 @@ void
decode_coproc (SIM_DESC sd,
sim_cpu *cpu,
address_word cia,
unsigned int instruction)
unsigned int instruction,
int coprocnum,
CP0_operation op,
int rt,
int rd,
int sel)
{
int coprocnum = ((instruction >> 26) & 3);
switch (coprocnum)
{
case 0: /* standard CPU control and cache registers */
{
int code = ((instruction >> 21) & 0x1F);
int rt = ((instruction >> 16) & 0x1F);
int rd = ((instruction >> 11) & 0x1F);
int tail = instruction & 0x3ff;
/* R4000 Users Manual (second edition) lists the following CP0
instructions:
CODE><-RT><RD-><--TAIL--->
@ -2212,15 +2210,10 @@ decode_coproc (SIM_DESC sd,
CACHE Cache operation (VR4100 = 101111bbbbbpppppiiiiiiiiiiiiiiii)
ERET Exception return (VR4100 = 01000010000000000000000000011000)
*/
if (((code == 0x00) || (code == 0x04) /* MFC0 / MTC0 */
|| (code == 0x01) || (code == 0x05)) /* DMFC0 / DMTC0 */
&& tail == 0)
if (((op == cp0_mfc0) || (op == cp0_mtc0) /* MFC0 / MTC0 */
|| (op == cp0_dmfc0) || (op == cp0_dmtc0)) /* DMFC0 / DMTC0 */
&& sel == 0)
{
/* Clear double/single coprocessor move bit. */
code &= ~1;
/* M[TF]C0 (32 bits) | DM[TF]C0 (64 bits) */
switch (rd) /* NOTEs: Standard CP0 registers */
{
/* 0 = Index R4000 VR4100 VR4300 */
@ -2248,7 +2241,7 @@ decode_coproc (SIM_DESC sd,
case 8:
/* 8 = BadVAddr R4000 VR4100 VR4300 */
if (code == 0x00)
if (op == cp0_mfc0 || op == cp0_dmfc0)
GPR[rt] = (signed_word) (signed_address) COP0_BADVADDR;
else
COP0_BADVADDR = GPR[rt];
@ -2256,21 +2249,21 @@ decode_coproc (SIM_DESC sd,
#endif /* SUBTARGET_R3900 */
case 12:
if (code == 0x00)
if (op == cp0_mfc0 || op == cp0_dmfc0)
GPR[rt] = SR;
else
SR = GPR[rt];
break;
/* 13 = Cause R4000 VR4100 VR4300 */
case 13:
if (code == 0x00)
if (op == cp0_mfc0 || op == cp0_dmfc0)
GPR[rt] = CAUSE;
else
CAUSE = GPR[rt];
break;
/* 14 = EPC R4000 VR4100 VR4300 */
case 14:
if (code == 0x00)
if (op == cp0_mfc0 || op == cp0_dmfc0)
GPR[rt] = (signed_word) (signed_address) EPC;
else
EPC = GPR[rt];
@ -2279,7 +2272,7 @@ decode_coproc (SIM_DESC sd,
#ifdef SUBTARGET_R3900
/* 16 = Debug */
case 16:
if (code == 0x00)
if (op == cp0_mfc0 || op == cp0_dmfc0)
GPR[rt] = Debug;
else
Debug = GPR[rt];
@ -2287,7 +2280,7 @@ decode_coproc (SIM_DESC sd,
#else
/* 16 = Config R4000 VR4100 VR4300 */
case 16:
if (code == 0x00)
if (op == cp0_mfc0 || op == cp0_dmfc0)
GPR[rt] = C0_CONFIG;
else
/* only bottom three bits are writable */
@ -2297,7 +2290,7 @@ decode_coproc (SIM_DESC sd,
#ifdef SUBTARGET_R3900
/* 17 = Debug */
case 17:
if (code == 0x00)
if (op == cp0_mfc0 || op == cp0_dmfc0)
GPR[rt] = DEPC;
else
DEPC = GPR[rt];
@ -2320,7 +2313,7 @@ decode_coproc (SIM_DESC sd,
GPR[rt] = 0xDEADC0DE; /* CPR[0,rd] */
/* CPR[0,rd] = GPR[rt]; */
default:
if (code == 0x00)
if (op == cp0_mfc0 || op == cp0_dmfc0)
GPR[rt] = (signed_word) (signed32) COP0_GPR[rd];
else
COP0_GPR[rd] = GPR[rt];
@ -2332,12 +2325,12 @@ decode_coproc (SIM_DESC sd,
#endif
}
}
else if ((code == 0x00 || code == 0x01)
else if ((op == cp0_mfc0 || op == cp0_dmfc0)
&& rd == 16)
{
/* [D]MFC0 RT,C0_CONFIG,SEL */
signed32 cfg = 0;
switch (tail & 0x07)
switch (sel)
{
case 0:
cfg = C0_CONFIG;
@ -2366,7 +2359,7 @@ decode_coproc (SIM_DESC sd,
}
GPR[rt] = cfg;
}
else if (code == 0x10 && (tail & 0x3f) == 0x18)
else if (op == cp0_eret && sel == 0x18)
{
/* ERET */
if (SR & status_ERL)
@ -2382,7 +2375,7 @@ decode_coproc (SIM_DESC sd,
SR &= ~status_EXL;
}
}
else if (code == 0x10 && (tail & 0x3f) == 0x10)
else if (op == cp0_rfe && sel == 0x10)
{
/* RFE */
#ifdef SUBTARGET_R3900
@ -2394,7 +2387,7 @@ decode_coproc (SIM_DESC sd,
/* TODO: CACHE register */
#endif /* SUBTARGET_R3900 */
}
else if (code == 0x10 && (tail & 0x3f) == 0x1F)
else if (op == cp0_deret && sel == 0x1F)
{
/* DERET */
Debug &= ~Debug_DM;

10
sim/mips/m16.igen
View File

@ -1075,6 +1075,10 @@
011101,26.IMMED:JALX:32::JALX32
"jalx <IMMED>"
*mips32:
*mips64:
*mips32r2:
*mips64r2:
*mips16:
*vr4100:
{
@ -1228,9 +1232,5 @@
*mips16:
*vr4100:
{
if (STATE & simDELAYSLOT)
PC = cia - 2; /* reference the branch instruction */
else
PC = cia;
SignalException (BreakPoint, instruction_0);
do_break16 (SD_, instruction_0);
}

15
sim/mips/micromips.dc Normal file
View File

@ -0,0 +1,15 @@
# most instructions
# ------ options ------ : Fst : Lst : ff : fl : fe : word : fmt : model ...
# { : mask : value : word }
# Top level - create a very big switch statement.
padded-switch,combine : 31 : 26 : : : : : :
switch,combine : 5 : 0 : : : : : :
switch,combine : 10 : 0 : : : : : :
switch,combine : 25 : 16 : : : : : :
switch,combine : 25 : 21 : : : : : :
switch,combine : 15 : 11 : : : : : :

3091
sim/mips/micromips.igen Normal file
View File

File diff suppressed because it is too large Load Diff

11
sim/mips/micromips16.dc Normal file
View File

@ -0,0 +1,11 @@
# most instructions
# ------ options ------ : Fst : Lst : ff : fl : fe : word : fmt : model ...
# { : mask : value : word }
# Top level - create a very big switch statement.
padded-switch,combine : 15 : 10 : : : : : :
switch,combine : 9 : 6 : : : : : :
switch,combine : 9 : 5 : : : : : :
switch,combine : 0 : 0 : : : : : :

1137
sim/mips/micromipsdsp.igen Normal file
View File

File diff suppressed because it is too large Load Diff

135
sim/mips/micromipsrun.c Normal file
View File

@ -0,0 +1,135 @@
/* Run function for the micromips simulator
Copyright (C) 2005-2015 Free Software Foundation, Inc.
Contributed by Imagination Technologies, Ltd.
Written by Andrew Bennett <andrew.bennett@imgtec.com>.
This file is part of the MIPS sim.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>. */
#include "sim-main.h"
#include "micromips16_idecode.h"
#include "micromips32_idecode.h"
#include "micromips_m32_idecode.h"
#include "bfd.h"
#include "sim-engine.h"
/* These definitions come from the *_support.h files generated by igen and are
required because they are used in some of the macros in the code below.
Unfortunately we can not just blindly include the *_support.h files to get
these definitions because some of the defines in these files are specific
for a particular configuration of the simulator for example instruction word
size is 16 bits for micromips16 and 32 bits for micromips32. This means we
could break future code changes by doing this, so a safer approach is to just
extract the defines that we need to get this file to compile. */
#define SD sd
#define CPU cpu
address_word
micromips_instruction_decode (SIM_DESC sd, sim_cpu * cpu,
address_word cia,
int instruction_size)
{
if (instruction_size == MICROMIPS_DELAYSLOT_SIZE_ANY)
{
micromips16_instruction_word instruction_0 = IMEM16_MICROMIPS (cia);
if (MICROMIPS_MINOR_OPCODE (instruction_0) > 0
&& MICROMIPS_MINOR_OPCODE (instruction_0) < 4)
return micromips16_idecode_issue (sd, instruction_0, cia);
else
{
micromips32_instruction_word instruction_0 = IMEM32_MICROMIPS (cia);
return micromips32_idecode_issue (sd, instruction_0, cia);
}
}
else if (instruction_size == MICROMIPS_DELAYSLOT_SIZE_16)
{
micromips16_instruction_word instruction_0 = IMEM16_MICROMIPS (cia);
if (MICROMIPS_MINOR_OPCODE (instruction_0) > 0
&& MICROMIPS_MINOR_OPCODE (instruction_0) < 4)
return micromips16_idecode_issue (sd, instruction_0, cia);
else
sim_engine_abort (sd, cpu, cia,
"Invalid 16 bit micromips instruction");
}
else if (instruction_size == MICROMIPS_DELAYSLOT_SIZE_32)
{
micromips32_instruction_word instruction_0 = IMEM32_MICROMIPS (cia);
return micromips32_idecode_issue (sd, instruction_0, cia);
}
else
return NULL_CIA;
}
void
sim_engine_run (SIM_DESC sd, int next_cpu_nr, int nr_cpus,
int signal)
{
micromips_m32_instruction_word instruction_0;
sim_cpu *cpu = STATE_CPU (sd, next_cpu_nr);
micromips32_instruction_address cia = CPU_PC_GET (cpu);
sd->isa_mode = ISA_MODE_MIPS32;
while (1)
{
micromips32_instruction_address nia;
/* Allow us to switch back from MIPS32 to microMIPS
This covers two cases:
1. Setting the correct isa mode based on the start address
from the elf header.
2. Setting the correct isa mode after a MIPS32 jump or branch
instruction. */
if ((sd->isa_mode == ISA_MODE_MIPS32)
&& ((cia & 0x1) == ISA_MODE_MICROMIPS))
{
sd->isa_mode = ISA_MODE_MICROMIPS;
cia = cia & ~0x1;
}
#if defined (ENGINE_ISSUE_PREFIX_HOOK)
ENGINE_ISSUE_PREFIX_HOOK ();
#endif
switch (sd->isa_mode)
{
case ISA_MODE_MICROMIPS:
nia =
micromips_instruction_decode (sd, cpu, cia,
MICROMIPS_DELAYSLOT_SIZE_ANY);
break;
case ISA_MODE_MIPS32:
instruction_0 = IMEM32 (cia);
nia = micromips_m32_idecode_issue (sd, instruction_0, cia);
break;
default:
nia = NULL_CIA;
}
#if defined (ENGINE_ISSUE_POSTFIX_HOOK)
ENGINE_ISSUE_POSTFIX_HOOK ();
#endif
/* Update the instruction address */
cia = nia;
/* process any events */
if (sim_events_tick (sd))
{
CPU_PC_SET (cpu, cia);
sim_events_process (sd);
cia = CPU_PC_GET (cpu);
}
}
}

2235
sim/mips/mips.igen
View File

File diff suppressed because it is too large Load Diff

290
sim/mips/mips3264r2.igen
View File

@ -4,7 +4,7 @@
// Copyright (C) 2004-2015 Free Software Foundation, Inc.
// Contributed by David Ung, of MIPS Technologies.
//
// This file is part of GDB, the GNU debugger.
// This file is part of the MIPS sim.
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
@ -19,15 +19,183 @@
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
:function:::void:do_dsbh:int rd, int rt
{
union { unsigned64 d; unsigned16 h[4]; } u;
TRACE_ALU_INPUT1 (GPR[rt]);
u.d = GPR[rt];
u.h[0] = SWAP_2 (u.h[0]);
u.h[1] = SWAP_2 (u.h[1]);
u.h[2] = SWAP_2 (u.h[2]);
u.h[3] = SWAP_2 (u.h[3]);
GPR[rd] = u.d;
TRACE_ALU_RESULT1 (GPR[rd]);
}
:function:::void:do_dshd:int rd, int rt
{
unsigned64 d;
TRACE_ALU_INPUT1 (GPR[rt]);
d = GPR[rt];
GPR[rd] = ((d >> 48)
| (d << 48)
| ((d & 0x0000ffff00000000ULL) >> 16)
| ((d & 0x00000000ffff0000ULL) << 16));
TRACE_ALU_RESULT1 (GPR[rd]);
}
:function:::void:do_dext:int rt, int rs, int lsb, int size
{
TRACE_ALU_INPUT3 (GPR[rs], lsb, size);
GPR[rt] = EXTRACTED64 (GPR[rs], lsb + size, lsb);
TRACE_ALU_RESULT1 (GPR[rt]);
}
:function:::void:do_dextm:int rt, int rs, int lsb, int size
{
TRACE_ALU_INPUT3 (GPR[rs], lsb, size);
GPR[rt] = EXTRACTED64 (GPR[rs], lsb + size + 32, lsb);
TRACE_ALU_RESULT1 (GPR[rt]);
}
:function:::void:do_dextu:int rt, int rs, int lsb, int size
{
TRACE_ALU_INPUT3 (GPR[rs], lsb, size);
GPR[rt] = EXTRACTED64 (GPR[rs], lsb + 32 + size, lsb + 32);
TRACE_ALU_RESULT1 (GPR[rt]);
}
:function:::void:do_di:int rt
{
TRACE_ALU_INPUT0 ();
GPR[rt] = EXTEND32 (SR);
SR &= ~status_IE;
TRACE_ALU_RESULT1 (GPR[rt]);
}
:function:::void:do_dins:int rt, int rs, int lsb, int msb
{
TRACE_ALU_INPUT4 (GPR[rt], GPR[rs], lsb, msb);
if (lsb <= msb)
GPR[rt] ^= (GPR[rt] ^ (GPR[rs] << lsb)) & MASK64 (msb, lsb);
TRACE_ALU_RESULT1 (GPR[rt]);
}
:function:::void:do_dinsm:int rt, int rs, int lsb, int msb
{
TRACE_ALU_INPUT4 (GPR[rt], GPR[rs], lsb, msb);
if (lsb <= msb + 32)
GPR[rt] ^= (GPR[rt] ^ (GPR[rs] << lsb)) & MASK64 (msb + 32, lsb);
TRACE_ALU_RESULT1 (GPR[rt]);
}
:function:::void:do_ei:int rt
{
TRACE_ALU_INPUT0 ();
GPR[rt] = EXTEND32 (SR);
SR |= status_IE;
TRACE_ALU_RESULT1 (GPR[rt]);
}
:function:::void:do_ext:int rt, int rs, int lsb, int size
{
TRACE_ALU_INPUT3 (GPR[rs], lsb, size);
GPR[rt] = EXTEND32 (EXTRACTED32 (GPR[rs], lsb + size, lsb));
TRACE_ALU_RESULT1 (GPR[rt]);
}
:function:::void:do_mfhc1:int rt, int fs
{
check_fpu (SD_);
if (SizeFGR() == 64)
GPR[rt] = EXTEND32 (WORD64HI (FGR[fs]));
else if ((fs & 0x1) == 0)
GPR[rt] = EXTEND32 (FGR[fs + 1]);
else
{
if (STATE_VERBOSE_P(SD))
sim_io_eprintf (SD,
"Warning: PC 0x%lx: MFHC1 32-bit use of odd FPR number\n",
(long) CIA);
GPR[rt] = EXTEND32 (0xBADF00D);
}
TRACE_ALU_RESULT (GPR[rt]);
}
:function:::void:do_mthc1:int rt, int fs
{
check_fpu (SD_);
if (SizeFGR() == 64)
StoreFPR (fs, fmt_uninterpreted_64, SET64HI (GPR[rt]) | VL4_8 (FGR[fs]));
else if ((fs & 0x1) == 0)
StoreFPR (fs + 1, fmt_uninterpreted_32, VL4_8 (GPR[rt]));
else
{
if (STATE_VERBOSE_P(SD))
sim_io_eprintf (SD,
"Warning: PC 0x%lx: MTHC1 32-bit use of odd FPR number\n",
(long) CIA);
StoreFPR (fs, fmt_uninterpreted_32, 0xDEADC0DE);
}
TRACE_FP_RESULT (GPR[rt]);
}
:function:::void:do_ins:int rt, int rs, int lsb, int msb
{
TRACE_ALU_INPUT4 (GPR[rt], GPR[rs], lsb, msb);
if (lsb <= msb)
GPR[rt] = EXTEND32 (GPR[rt] ^
((GPR[rt] ^ (GPR[rs] << lsb)) & MASK32 (msb, lsb)));
TRACE_ALU_RESULT1 (GPR[rt]);
}
:function:::void:do_dinsu:int rt, int rs, int lsb, int msb
{
TRACE_ALU_INPUT4 (GPR[rt], GPR[rs], lsb, msb);
if (lsb <= msb)
GPR[rt] ^= (GPR[rt] ^ (GPR[rs] << (lsb + 32)))
& MASK64 (msb + 32, lsb + 32);
TRACE_ALU_RESULT1 (GPR[rt]);
}
:function:::void:do_seb:int rd, int rt
{
TRACE_ALU_INPUT1 (GPR[rt]);
GPR[rd] = EXTEND8 (GPR[rt]);
TRACE_ALU_RESULT1 (GPR[rd]);
}
:function:::void:do_seh:int rd, int rt
{
TRACE_ALU_INPUT1 (GPR[rt]);
GPR[rd] = EXTEND16 (GPR[rt]);
TRACE_ALU_RESULT1 (GPR[rd]);
}
:function:::void:do_rdhwr:int rt, int rd
{
// Return 0 for all hardware registers currently
GPR[rt] = EXTEND32 (0);
TRACE_ALU_RESULT1 (GPR[rt]);
}
:function:::void:do_wsbh:int rd, int rt
{
union { unsigned32 w; unsigned16 h[2]; } u;
TRACE_ALU_INPUT1 (GPR[rt]);
u.w = GPR[rt];
u.h[0] = SWAP_2 (u.h[0]);
u.h[1] = SWAP_2 (u.h[1]);
GPR[rd] = EXTEND32 (u.w);
TRACE_ALU_RESULT1 (GPR[rd]);
}
011111,5.RS,5.RT,5.SIZE,5.LSB,000011::64::DEXT
"dext r<RT>, r<RS>, <LSB>, <SIZE+1>"
*mips64r2:
{
check_u64 (SD_, instruction_0);
TRACE_ALU_INPUT3 (GPR[RS], LSB, SIZE);
GPR[RT] = EXTRACTED64 (GPR[RS], LSB + SIZE, LSB);
TRACE_ALU_RESULT1 (GPR[RT]);
do_dext (SD_, RT, RS, LSB, SIZE);
}
011111,5.RS,5.RT,5.SIZE,5.LSB,000001::64::DEXTM
@ -35,9 +203,7 @@
*mips64r2:
{
check_u64 (SD_, instruction_0);
TRACE_ALU_INPUT3 (GPR[RS], LSB, SIZE);
GPR[RT] = EXTRACTED64 (GPR[RS], LSB + SIZE + 32, LSB);
TRACE_ALU_RESULT1 (GPR[RT]);
do_dextm (SD_, RT, RS, LSB, SIZE);
}
011111,5.RS,5.RT,5.SIZE,5.LSB,000010::64::DEXTU
@ -45,9 +211,7 @@
*mips64r2:
{
check_u64 (SD_, instruction_0);
TRACE_ALU_INPUT3 (GPR[RS], LSB, SIZE);
GPR[RT] = EXTRACTED64 (GPR[RS], LSB + 32 + SIZE, LSB + 32);
TRACE_ALU_RESULT1 (GPR[RT]);
do_dextu (SD_, RT, RS, LSB, SIZE);
}
@ -57,10 +221,7 @@
*mips32r2:
*mips64r2:
{
TRACE_ALU_INPUT0 ();
GPR[RT] = EXTEND32 (SR);
SR &= ~status_IE;
TRACE_ALU_RESULT1 (GPR[RT]);
do_di (SD_, RT);
}
@ -69,10 +230,7 @@
*mips64r2:
{
check_u64 (SD_, instruction_0);
TRACE_ALU_INPUT4 (GPR[RT], GPR[RS], LSB, MSB);
if (LSB <= MSB)
GPR[RT] ^= (GPR[RT] ^ (GPR[RS] << LSB)) & MASK64 (MSB, LSB);
TRACE_ALU_RESULT1 (GPR[RT]);
do_dins (SD_, RT, RS, LSB, MSB);
}
011111,5.RS,5.RT,5.MSB,5.LSB,000101::64::DINSM
@ -80,10 +238,7 @@
*mips64r2:
{
check_u64 (SD_, instruction_0);
TRACE_ALU_INPUT4 (GPR[RT], GPR[RS], LSB, MSB);
if (LSB <= MSB + 32)
GPR[RT] ^= (GPR[RT] ^ (GPR[RS] << LSB)) & MASK64 (MSB + 32, LSB);
TRACE_ALU_RESULT1 (GPR[RT]);
do_dinsm (SD_, RT, RS, LSB, MSB);
}
011111,5.RS,5.RT,5.MSB,5.LSB,000110::64::DINSU
@ -91,11 +246,7 @@
*mips64r2:
{
check_u64 (SD_, instruction_0);
TRACE_ALU_INPUT4 (GPR[RT], GPR[RS], LSB, MSB);
if (LSB <= MSB)
GPR[RT] ^= (GPR[RT] ^ (GPR[RS] << (LSB + 32)))
& MASK64 (MSB + 32, LSB + 32);
TRACE_ALU_RESULT1 (GPR[RT]);
do_dinsu (SD_, RT, RS, LSB, MSB);
}
@ -103,44 +254,25 @@
"dsbh r<RD>, r<RT>"
*mips64r2:
{
union { unsigned64 d; unsigned16 h[4]; } u;
check_u64 (SD_, instruction_0);
TRACE_ALU_INPUT1 (GPR[RT]);
u.d = GPR[RT];
u.h[0] = SWAP_2 (u.h[0]);
u.h[1] = SWAP_2 (u.h[1]);
u.h[2] = SWAP_2 (u.h[2]);
u.h[3] = SWAP_2 (u.h[3]);
GPR[RD] = u.d;
TRACE_ALU_RESULT1 (GPR[RD]);
do_dsbh (SD_, RD, RT);
}
011111,00000,5.RT,5.RD,00101,100100::64::DSHD
"dshd r<RD>, r<RT>"
*mips64r2:
{
unsigned64 d;
check_u64 (SD_, instruction_0);
TRACE_ALU_INPUT1 (GPR[RT]);
d = GPR[RT];
GPR[RD] = ((d >> 48)
| (d << 48)
| ((d & 0x0000ffff00000000ULL) >> 16)
| ((d & 0x00000000ffff0000ULL) << 16));
TRACE_ALU_RESULT1 (GPR[RD]);
do_dshd (SD_, RD, RT);
}
010000,01011,5.RT,01100,00000,1,00,000::32::EI
"ei":RT == 0
"ei r<RT>"
*mips32r2:
*mips64r2:
{
TRACE_ALU_INPUT0 ();
GPR[RT] = EXTEND32 (SR);
SR |= status_IE;
TRACE_ALU_RESULT1 (GPR[RT]);
do_ei (SD_, RT);
}
@ -149,9 +281,7 @@
*mips32r2:
*mips64r2:
{
TRACE_ALU_INPUT3 (GPR[RS], LSB, SIZE);
GPR[RT] = EXTEND32 (EXTRACTED32 (GPR[RS], LSB + SIZE, LSB));
TRACE_ALU_RESULT1 (GPR[RT]);
do_ext (SD_, RT, RS, LSB, SIZE);
}
@ -160,20 +290,7 @@
*mips32r2:
*mips64r2:
{
check_fpu (SD_);
if (SizeFGR() == 64)
GPR[RT] = EXTEND32 (WORD64HI (FGR[FS]));
else if ((FS & 0x1) == 0)
GPR[RT] = EXTEND32 (FGR[FS + 1]);
else
{
if (STATE_VERBOSE_P(SD))
sim_io_eprintf (SD,
"Warning: PC 0x%lx: MFHC1 32-bit use of odd FPR number\n",
(long) CIA);
GPR[RT] = EXTEND32 (0xBADF00D);
}
TRACE_ALU_RESULT (GPR[RT]);
do_mfhc1 (SD_, RT, FS);
}
010001,00111,5.RT,5.FS,00000000000:COP1Sa:32,f::MTHC1
@ -181,20 +298,7 @@
*mips32r2:
*mips64r2:
{
check_fpu (SD_);
if (SizeFGR() == 64)
StoreFPR (FS, fmt_uninterpreted_64, SET64HI (GPR[RT]) | VL4_8 (FGR[FS]));
else if ((FS & 0x1) == 0)
StoreFPR (FS + 1, fmt_uninterpreted_32, VL4_8 (GPR[RT]));
else
{
if (STATE_VERBOSE_P(SD))
sim_io_eprintf (SD,
"Warning: PC 0x%lx: MTHC1 32-bit use of odd FPR number\n",
(long) CIA);
StoreFPR (FS, fmt_uninterpreted_32, 0xDEADC0DE);
}
TRACE_FP_RESULT (GPR[RT]);
do_mthc1 (SD_, RT, FS);
}
@ -203,11 +307,7 @@
*mips32r2:
*mips64r2:
{
TRACE_ALU_INPUT4 (GPR[RT], GPR[RS], LSB, MSB);
if (LSB <= MSB)
GPR[RT] = EXTEND32 (GPR[RT] ^
((GPR[RT] ^ (GPR[RS] << LSB)) & MASK32 (MSB, LSB)));
TRACE_ALU_RESULT1 (GPR[RT]);
do_ins (SD_, RT, RS, LSB, MSB);
}
@ -216,9 +316,7 @@
*mips32r2:
*mips64r2:
{
TRACE_ALU_INPUT1 (GPR[RT]);
GPR[RD] = EXTEND8 (GPR[RT]);
TRACE_ALU_RESULT1 (GPR[RD]);
do_seb (SD_, RD, RT);
}
011111,00000,5.RT,5.RD,11000,100000::32::SEH
@ -226,9 +324,7 @@
*mips32r2:
*mips64r2:
{
TRACE_ALU_INPUT1 (GPR[RT]);
GPR[RD] = EXTEND16 (GPR[RT]);
TRACE_ALU_RESULT1 (GPR[RD]);
do_seh (SD_, RD, RT);
}
@ -246,9 +342,7 @@
*mips32r2:
*mips64r2:
{
// Return 0 for all hardware registers currently
GPR[RT] = EXTEND32 (0);
TRACE_ALU_RESULT1 (GPR[RT]);
do_rdhwr (SD_, RT, RD);
}
@ -257,13 +351,7 @@
*mips32r2:
*mips64r2:
{
union { unsigned32 w; unsigned16 h[2]; } u;
TRACE_ALU_INPUT1 (GPR[RT]);
u.w = GPR[RT];
u.h[0] = SWAP_2 (u.h[0]);
u.h[1] = SWAP_2 (u.h[1]);
GPR[RD] = EXTEND32 (u.w);
TRACE_ALU_RESULT1 (GPR[RD]);
do_wsbh (SD_, RD, RT);
}

47
sim/mips/sim-main.h
View File

@ -2,7 +2,7 @@
Copyright (C) 1997-2015 Free Software Foundation, Inc.
Contributed by Cygnus Support.
This file is part of GDB, the GNU debugger.
This file is part of the MIPS sim.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
@ -49,6 +49,20 @@ typedef unsigned64 uword64;
#define NOTHALFWORDVALUE(v) ((((((uword64)(v)>>16) == 0) && !((v) & ((unsigned)1 << 15))) || (((((uword64)(v)>>32) == 0xFFFFFFFF) && ((((uword64)(v)>>16) & 0xFFFF) == 0xFFFF)) && ((v) & ((unsigned)1 << 15)))) ? (1 == 0) : (1 == 1))
typedef enum {
cp0_dmfc0,
cp0_dmtc0,
cp0_mfc0,
cp0_mtc0,
cp0_tlbr,
cp0_tlbwi,
cp0_tlbwr,
cp0_tlbp,
cp0_cache,
cp0_eret,
cp0_deret,
cp0_rfe
} CP0_operation;
/* Floating-point operations: */
@ -479,6 +493,9 @@ struct sim_state {
sim_cpu *cpu[MAX_NR_PROCESSORS];
/* microMIPS ISA mode. */
int isa_mode;
sim_state_base base;
};
@ -690,9 +707,12 @@ cop_sw (SD, CPU, cia, coproc_num, coproc_reg)
cop_sd (SD, CPU, cia, coproc_num, coproc_reg)
void decode_coproc (SIM_DESC sd, sim_cpu *cpu, address_word cia, unsigned int instruction);
#define DecodeCoproc(instruction) \
decode_coproc (SD, CPU, cia, (instruction))
void decode_coproc (SIM_DESC sd, sim_cpu *cpu, address_word cia,
unsigned int instruction, int coprocnum, CP0_operation op,
int rt, int rd, int sel);
#define DecodeCoproc(instruction,coprocnum,op,rt,rd,sel) \
decode_coproc (SD, CPU, cia, (instruction), (coprocnum), (op), \
(rt), (rd), (sel))
int sim_monitor (SIM_DESC sd, sim_cpu *cpu, address_word cia, unsigned int arg);
@ -956,6 +976,25 @@ INLINE_SIM_MAIN (unsigned32) ifetch32 (SIM_DESC sd, sim_cpu *cpu, address_word c
INLINE_SIM_MAIN (unsigned16) ifetch16 (SIM_DESC sd, sim_cpu *cpu, address_word cia, address_word vaddr);
#define IMEM16(CIA) ifetch16 (SD, CPU, (CIA), ((CIA) & ~1))
#define IMEM16_IMMED(CIA,NR) ifetch16 (SD, CPU, (CIA), ((CIA) & ~1) + 2 * (NR))
#define IMEM32_MICROMIPS(CIA) \
(ifetch16 (SD, CPU, (CIA), (CIA)) << 16 | ifetch16 (SD, CPU, (CIA + 2), \
(CIA + 2)))
#define IMEM16_MICROMIPS(CIA) ifetch16 (SD, CPU, (CIA), ((CIA)))
#define MICROMIPS_MINOR_OPCODE(INSN) ((INSN & 0x1C00) >> 10)
#define MICROMIPS_DELAYSLOT_SIZE_ANY 0
#define MICROMIPS_DELAYSLOT_SIZE_16 2
#define MICROMIPS_DELAYSLOT_SIZE_32 4
extern int isa_mode;
#define ISA_MODE_MIPS32 0
#define ISA_MODE_MICROMIPS 1
address_word micromips_instruction_decode (SIM_DESC sd, sim_cpu * cpu,
address_word cia,
int instruction_size);
#if WITH_TRACE_ANY_P
void dotrace (SIM_DESC sd, sim_cpu *cpu, FILE *tracefh, int type, SIM_ADDR address, int width, char *comment, ...);

11
sim/testsuite/sim/mips/ChangeLog
View File

@ -1,3 +1,14 @@
2015-09-25 Andrew Bennett <andrew.bennett@imgtec.com>
Ali Lown <ali.lown@imgtec.com>
* basic.exp (run_micromips_test, run_sim_tests): New functions
Add support for micromips tests.
* hilo-hazard-4.s: New file.
* testutils.inc (_dowrite): Changed reserved instruction encoding.
(writemsg): Moved the la and li instructions before the data they are
assigned to, which prevents a bug where MIPS32 relocations are used
instead of micromips relocations when building for micromips.
2015-04-13 Hans-Peter Nilsson <hp@axis.com>
* basic.exp: Don't unset target ldscript here.

29
sim/testsuite/sim/mips/basic.exp
View File

@ -25,12 +25,28 @@ proc run_hilo_test {testfile models nops} {
}
}
# Runs micromips tests by adding -mmicromips to as options
proc run_micromips_test { name requested_machs } {
global global_as_options;
set gas_old $global_as_options;
append global_as_options " -mmicromips "
run_sim_test $name $requested_machs
set global_as_options $gas_old
}
# Runs all specified tests
proc run_sim_tests { name requested_machs { requested_micromips_machs "" } } {
run_sim_test $name $requested_machs
run_micromips_test $name $requested_micromips_machs
}
# Only test mips*-*-elf (e.g., no mips*-*-linux)
if {[istarget mips*-*-elf]} {
set dspmodels ""
set mdmxmodels ""
set micromipsmodels ""
set micromipsdspmodels ""
if {[istarget mipsisa64sb1*-*-elf]} {
set models "sb1"
@ -46,11 +62,15 @@ if {[istarget mips*-*-elf]} {
set submodels ""
append dspmodels " mips32r2 mips64r2"
append mdmxmodels " mips64 mips32r2 mips64r2"
append micromipsmodels " mips32r2"
append micromipsdspmodels " mips32r2 mips64r2"
} elseif {[istarget mipsisa32*-*-elf]} {
set models "mips32 mips32r2"
set submodels "mips1 mips2"
append dspmodels " mips32r2"
append mdmxmodels " mips32r2"
append micromipsmodels " mips32r2"
append micromipsdspmodels " mips32r2"
} elseif {[istarget mips64vr*-*-elf]} {
set models "vr4100 vr4111 vr4120 vr5000 vr5400 vr5500"
set submodels "mips1 mips2 mips3 mips4"
@ -65,12 +85,14 @@ if {[istarget mips*-*-elf]} {
append submodels " " $models
set cpu_option -march
run_sim_test sanity.s $submodels
run_sim_tests sanity.s $submodels $micromipsmodels
foreach nops {0 1} {
run_hilo_test hilo-hazard-1.s $models $nops
run_hilo_test hilo-hazard-2.s $models $nops
}
run_hilo_test hilo-hazard-3.s $models 2
run_hilo_test hilo-hazard-4.s $micromipsmodels 2
run_sim_test fpu64-ps.s $submodels
run_sim_test fpu64-ps-sb1.s $submodels
@ -78,6 +100,7 @@ if {[istarget mips*-*-elf]} {
run_sim_test mdmx-ob.s $mdmxmodels
run_sim_test mdmx-ob-sb1.s $mdmxmodels
run_sim_test mips32-dsp.s $dspmodels
run_sim_test mips32-dsp2.s $dspmodels
run_sim_tests mips32-dsp.s $dspmodels $micromipsdspmodels
run_sim_tests mips32-dsp2.s $dspmodels $micromipsdspmodels
}

37
sim/testsuite/sim/mips/hilo-hazard-4.s Normal file
View File

@ -0,0 +1,37 @@
# Test for mf{hi,lo} -> mult/div/mt{hi,lo} with 2 nops inbetween.
#
# mach: all
# as: -mabi=eabi -mmicromips
# ld: -N -Ttext=0x80010000
# output: pass\\n
# Copyright (C) 2013-2015 Imagination Technologies, Ltd.
# All rights reserved.
# Contributed by Andrew Bennett (andrew.bennett@imgtec.com)
#
# This file is part of the MIPS sim.
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 3, or (at your option)
# any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License along
# with this program; if not, see <http://www.gnu.org/licenses/>.
.include "hilo-hazard.inc"
.include "testutils.inc"
setup
.set noreorder
.ent DIAG
DIAG:
hilo
pass
.end DIAG

6
sim/testsuite/sim/mips/testutils.inc
View File

@ -21,12 +21,12 @@
# $1, $4, $5, %6, are used as temps by the macros defined here.
.macro writemsg msg
la $5, 901f
li $6, 902f - 901f
.data
901: .ascii "\msg\n"
902:
.previous
la $5, 901b
li $6, 902b - 901b
.set push
.set noreorder
jal _dowrite
@ -81,7 +81,7 @@ _pass:
_dowrite:
# Write opcode (reserved instruction). See sim_monitor and its
# callers in sim/mips/interp.c.
.word 0x00000005 | ((8 << 1) << 6)
.word 0x00000039 | ((8 << 1) << 6)
.end _dowrite
.endm # setup