x86: widen applicability and use of CheckRegSize
First of all make operand_type_register_match() apply to all sized operands, i.e. in Intel Syntax also to respective memory ones. This addresses gas wrongly accepting certain SIMD insns where register and memory operand sizes should match but don't. This apparently has affected all templates with one memory-only operand and one or more register ones, both permitting at least two sizes, due to CheckRegSize not taking effect. Then also add CheckRegSize to a couple of non-SIMD templates matching that same pattern of memory-only vs register operands. This replaces bogus (for Intel Syntax) diagnostics referring to a wrong suffix (when none was used at all) by "type mismatch" ones, just like already emitted for insns where the template allows a register operand alongside a memory one at any particular position. This also is a prereq to limiting (ideally eliminating in the long run) suffix "derivation" in Intel Syntax mode. While making the code adjustment also flip order of checks to do the cheaper one first in both cases.
This commit is contained in:
Jan Beulich
parent
a122baf523
commit
8ee52bcf39
@ -2192,7 +2192,7 @@ operand_type_match (i386_operand_type overlap,
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/* If given types g0 and g1 are registers they must be of the same type
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unless the expected operand type register overlap is null.
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Some Intel syntax memory operand size checking also happens here. */
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Intel syntax sized memory operands are also checked here. */
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static INLINE int
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operand_type_register_match (i386_operand_type g0,
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@ -2202,18 +2202,14 @@ operand_type_register_match (i386_operand_type g0,
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{
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if (g0.bitfield.class != Reg
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&& g0.bitfield.class != RegSIMD
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&& (!operand_type_check (g0, anymem)
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|| g0.bitfield.unspecified
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|| (t0.bitfield.class != Reg
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&& t0.bitfield.class != RegSIMD)))
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&& (g0.bitfield.unspecified
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|| !operand_type_check (g0, anymem)))
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return 1;
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if (g1.bitfield.class != Reg
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&& g1.bitfield.class != RegSIMD
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&& (!operand_type_check (g1, anymem)
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|| g1.bitfield.unspecified
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|| (t1.bitfield.class != Reg
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&& t1.bitfield.class != RegSIMD)))
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&& (g1.bitfield.unspecified
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|| !operand_type_check (g1, anymem)))
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return 1;
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if (g0.bitfield.byte == g1.bitfield.byte
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@ -169,3 +169,27 @@
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.*:192: Error: .*
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.*:193: Error: .*
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.*:194: Error: .*
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.*:196: Error: .*
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.*:197: Error: .*
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.*:199: Error: .*
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.*:200: Error: .*
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.*:202: Error: .*
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.*:203: Error: .*
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.*:205: Error: .*
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.*:206: Error: .*
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.*:208: Error: .*
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.*:209: Error: .*
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.*:211: Error: .*
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.*:212: Error: .*
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.*:214: Error: .*
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.*:215: Error: .*
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.*:217: Error: .*
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.*:218: Error: .*
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.*:220: Error: .*
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.*:221: Error: .*
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.*:223: Error: .*
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.*:224: Error: .*
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.*:226: Error: .*
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.*:227: Error: .*
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.*:229: Error: .*
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.*:230: Error: .*
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@ -192,3 +192,39 @@ start:
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lsl ax, eax
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lsl eax, dword ptr [eax]
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lsl ax, dword ptr [eax]
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mov eax, word ptr [eax]
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mov eax, qword ptr [eax]
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mov eax, word ptr [0x12345678]
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mov eax, qword ptr [0x12345678]
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xchg eax, word ptr [eax]
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xchg eax, qword ptr [eax]
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add eax, word ptr [eax]
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add eax, qword ptr [eax]
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test eax, word ptr [eax]
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test eax, qword ptr [eax]
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test word ptr [eax], eax
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test qword ptr [eax], eax
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movnti word ptr [eax], eax
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movnti qword ptr [eax], eax
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movbe eax, word ptr [eax]
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movbe eax, qword ptr [eax]
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vmovntdq xmmword ptr [eax], ymm0
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vmovntdq zmmword ptr [eax], ymm0
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vmovntdqa ymm0, xmmword ptr [eax]
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vmovntdqa ymm0, zmmword ptr [eax]
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movdiri word ptr [eax], eax
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movdiri qword ptr [eax], eax
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aadd word ptr [eax], eax
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aadd qword ptr [eax], eax
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@ -142,9 +142,9 @@
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### MARKER ###
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// Move instructions.
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mov, 0xa0, None, CpuNo64, D|W|No_sSuf|No_qSuf|No_ldSuf, { Disp16|Disp32|Unspecified|Byte|Word|Dword, Acc|Byte|Word|Dword }
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mov, 0xa0, None, Cpu64, D|W|No_sSuf|No_ldSuf, { Disp64|Unspecified|Byte|Word|Dword|Qword, Acc|Byte|Word|Dword|Qword }
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movabs, 0xa0, None, Cpu64, D|W|No_sSuf|No_ldSuf, { Disp64|Unspecified|Byte|Word|Dword|Qword, Acc|Byte|Word|Dword|Qword }
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mov, 0xa0, None, CpuNo64, D|W|CheckRegSize|No_sSuf|No_qSuf|No_ldSuf, { Disp16|Disp32|Unspecified|Byte|Word|Dword, Acc|Byte|Word|Dword }
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mov, 0xa0, None, Cpu64, D|W|CheckRegSize|No_sSuf|No_ldSuf, { Disp64|Unspecified|Byte|Word|Dword|Qword, Acc|Byte|Word|Dword|Qword }
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movabs, 0xa0, None, Cpu64, D|W|CheckRegSize|No_sSuf|No_ldSuf, { Disp64|Unspecified|Byte|Word|Dword|Qword, Acc|Byte|Word|Dword|Qword }
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movq, 0xa1, None, Cpu64, D|Size64|NoSuf, { Disp64|Unspecified|Qword, Acc|Qword }
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mov, 0x88, None, 0, D|W|CheckRegSize|Modrm|No_sSuf|No_ldSuf|HLEPrefixRelease, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
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movq, 0x89, None, Cpu64, D|Modrm|Size64|NoSuf|HLEPrefixRelease, { Reg64, Reg64|Unspecified|Qword|BaseIndex }
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@ -176,7 +176,7 @@ movq, 0xf21, None, Cpu64, D|RegMem|Size64|NoSuf|NoRex64, { Debug, Reg64 }
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mov, 0xf24, None, Cpu386|CpuNo64, D|RegMem|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_ldSuf, { Test, Reg32 }
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// Move after swapping the bytes
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movbe, 0x0f38f0, None, CpuMovbe, D|Modrm|No_bSuf|No_sSuf|No_ldSuf, { Word|Dword|Qword|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
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movbe, 0x0f38f0, None, CpuMovbe, D|Modrm|CheckRegSize|No_bSuf|No_sSuf|No_ldSuf, { Word|Dword|Qword|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
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// Move with sign extend.
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// "movsbl" & "movsbw" must not be unified into "movsb" to avoid
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@ -302,7 +302,7 @@ cmp, 0x3c, None, 0, W|No_sSuf|No_ldSuf, { Imm8|Imm16|Imm32|Imm32S, Acc|Byte|Word
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cmp, 0x80, 7, 0, W|Modrm|No_sSuf|No_ldSuf, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
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test, 0x84, None, 0, W|CheckRegSize|Modrm|No_sSuf|No_ldSuf, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Unspecified|Byte|Word|Dword|Qword|BaseIndex }
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test, 0x84, None, 0, W|Modrm|No_sSuf|No_ldSuf, { Byte|Word|Dword|Qword|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 }
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test, 0x84, None, 0, W|CheckRegSize|Modrm|No_sSuf|No_ldSuf, { Byte|Word|Dword|Qword|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 }
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test, 0xa8, None, 0, W|No_sSuf|No_ldSuf|Optimize, { Imm8|Imm16|Imm32|Imm32S, Acc|Byte|Word|Dword|Qword }
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test, 0xf6, 0, 0, W|Modrm|No_sSuf|No_ldSuf|Optimize, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
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@ -970,7 +970,7 @@ fucompi, 0xdfe8, None, Cpu687, NoSuf, { FloatReg }
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// Pentium4 extensions.
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movnti, 0xfc3, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex }
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movnti, 0xfc3, None, CpuSSE2, Modrm|CheckRegSize|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex }
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clflush, 0xfae, 7, CpuClflush, Modrm|Anysize|IgnoreSize|NoSuf, { BaseIndex }
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lfence, 0xfaee8, None, CpuSSE2, NoSuf, {}
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mfence, 0xfaef0, None, CpuSSE2, NoSuf, {}
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@ -3053,7 +3053,7 @@ cldemote, 0x0f1c, 0, CpuCLDEMOTE, Modrm|Anysize|IgnoreSize|NoSuf, { BaseIndex }
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// MOVDIR[I,64B] instructions.
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movdiri, 0xf38f9, None, CpuMOVDIRI, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex }
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movdiri, 0xf38f9, None, CpuMOVDIRI, Modrm|CheckRegSize|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex }
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movdir64b, 0x660f38f8, None, CpuMOVDIR64B, Modrm|AddrPrefixOpReg|NoSuf, { Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
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// MOVEDIR instructions end.
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@ -23,7 +23,7 @@
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const insn_template i386_optab[] =
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{
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{ "mov", 0xa0, 2, None,
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{ 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 0,
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{ 1, 1, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0 },
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{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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@ -38,7 +38,7 @@ const insn_template i386_optab[] =
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{ { 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 0,
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0, 0, 0, 0, 0, 0 } } } },
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{ "mov", 0xa0, 2, None,
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{ 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0,
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{ 1, 1, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0 },
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{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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@ -233,7 +233,7 @@ const insn_template i386_optab[] =
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{ { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0,
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0, 0, 0, 0, 0, 0 } } } },
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{ "movabs", 0xa0, 2, None,
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{ 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0,
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{ 1, 1, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0 },
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{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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@ -488,7 +488,7 @@ const insn_template i386_optab[] =
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{ { 6, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0 } } } },
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{ "movbe", 0xf0, 2, None,
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{ 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0,
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{ 1, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0 },
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{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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@ -1743,7 +1743,7 @@ const insn_template i386_optab[] =
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{ { 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 1, 1, 1, 0, 1, 0,
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0, 0, 0, 0, 1, 0 } } } },
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{ "test", 0x84, 2, None,
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{ 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0,
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{ 0, 1, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0 },
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{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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@ -9942,7 +9942,7 @@ const insn_template i386_optab[] =
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{ { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1,
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0, 0, 0, 0, 0, 0 } } } },
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{ "movnti", 0xc3, 2, None,
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{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 1, 0, 0, 0,
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{ 0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 1, 1, 1, 0, 1, 0, 1, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0 },
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{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0,
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@ -55177,7 +55177,7 @@ const insn_template i386_optab[] =
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{ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0 } } } },
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{ "movdiri", 0xf9, 2, None,
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{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 1, 0, 0, 0,
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{ 0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 1, 1, 1, 0, 1, 0, 1, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0 },
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{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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