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* elf32-arm.c (elf32_arm_final_link_relocate): Add support for

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R_ARM_MOVW_BREL_NC, R_ARM_MOVW_BREL, R_ARM_MOVT_BREL,
	R_ARM_THM_MOVW_BREL_NC, R_ARM_THM_MOVW_BREL and
	R_ARM_THM_MOVT_BREL relocations.
This commit is contained in:
Mark Shinwell 2006-10-18 15:34:50 +00:00
parent 3443977099
commit 92f5d02b57
2 changed files with 40 additions and 6 deletions
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7
bfd/ChangeLog
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@ -1,3 +1,10 @@
2006-10-17 Mark Shinwell <shinwell@codesourcery.com>
* elf32-arm.c (elf32_arm_final_link_relocate): Add support for
R_ARM_MOVW_BREL_NC, R_ARM_MOVW_BREL, R_ARM_MOVT_BREL,
R_ARM_THM_MOVW_BREL_NC, R_ARM_THM_MOVW_BREL and
R_ARM_THM_MOVT_BREL relocations.
2006-10-17 Mark Shinwell <shinwell@codesourcery.com> 2006-10-17 Mark Shinwell <shinwell@codesourcery.com>
* elf32-arm.c (elf32_arm_howto_table_1): Change offset for * elf32-arm.c (elf32_arm_howto_table_1): Change offset for

39
bfd/elf32-arm.c
View File

@ -4832,6 +4832,13 @@ elf32_arm_final_link_relocate (reloc_howto_type * howto,
case R_ARM_MOVT_ABS: case R_ARM_MOVT_ABS:
case R_ARM_MOVW_PREL_NC: case R_ARM_MOVW_PREL_NC:
case R_ARM_MOVT_PREL: case R_ARM_MOVT_PREL:
/* Until we properly support segment-base-relative addressing then
we assume the segment base to be zero, as for the group relocations.
Thus R_ARM_MOVW_BREL_NC has the same semantics as R_ARM_MOVW_ABS_NC
and R_ARM_MOVT_BREL has the same semantics as R_ARM_MOVT_ABS. */
case R_ARM_MOVW_BREL_NC:
case R_ARM_MOVW_BREL:
case R_ARM_MOVT_BREL:
{ {
bfd_vma insn = bfd_get_32 (input_bfd, hit_data); bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
@ -4840,15 +4847,21 @@ elf32_arm_final_link_relocate (reloc_howto_type * howto,
addend = ((insn >> 4) & 0xf000) | (insn & 0xfff); addend = ((insn >> 4) & 0xf000) | (insn & 0xfff);
signed_addend = (addend ^ 0x10000) - 0x10000; signed_addend = (addend ^ 0x10000) - 0x10000;
} }
value += signed_addend; value += signed_addend;
if (sym_flags == STT_ARM_TFUNC)
value |= 1;
if (r_type == R_ARM_MOVW_PREL_NC || r_type == R_ARM_MOVT_PREL) if (r_type == R_ARM_MOVW_PREL_NC || r_type == R_ARM_MOVT_PREL)
value -= (input_section->output_section->vma value -= (input_section->output_section->vma
+ input_section->output_offset + rel->r_offset); + input_section->output_offset + rel->r_offset);
if (r_type == R_ARM_MOVT_ABS || r_type == R_ARM_MOVT_PREL) if (r_type == R_ARM_MOVW_BREL && value >= 0x10000)
return bfd_reloc_overflow;
if (sym_flags == STT_ARM_TFUNC)
value |= 1;
if (r_type == R_ARM_MOVT_ABS || r_type == R_ARM_MOVT_PREL
|| r_type == R_ARM_MOVT_BREL)
value >>= 16; value >>= 16;
insn &= 0xfff0f000; insn &= 0xfff0f000;
@ -4862,6 +4875,14 @@ elf32_arm_final_link_relocate (reloc_howto_type * howto,
case R_ARM_THM_MOVT_ABS: case R_ARM_THM_MOVT_ABS:
case R_ARM_THM_MOVW_PREL_NC: case R_ARM_THM_MOVW_PREL_NC:
case R_ARM_THM_MOVT_PREL: case R_ARM_THM_MOVT_PREL:
/* Until we properly support segment-base-relative addressing then
we assume the segment base to be zero, as for the above relocations.
Thus R_ARM_THM_MOVW_BREL_NC has the same semantics as
R_ARM_THM_MOVW_ABS_NC and R_ARM_THM_MOVT_BREL has the same semantics
as R_ARM_THM_MOVT_ABS. */
case R_ARM_THM_MOVW_BREL_NC:
case R_ARM_THM_MOVW_BREL:
case R_ARM_THM_MOVT_BREL:
{ {
bfd_vma insn; bfd_vma insn;
@ -4876,15 +4897,21 @@ elf32_arm_final_link_relocate (reloc_howto_type * howto,
| (insn & 0x00ff); | (insn & 0x00ff);
signed_addend = (addend ^ 0x10000) - 0x10000; signed_addend = (addend ^ 0x10000) - 0x10000;
} }
value += signed_addend; value += signed_addend;
if (sym_flags == STT_ARM_TFUNC)
value |= 1;
if (r_type == R_ARM_THM_MOVW_PREL_NC || r_type == R_ARM_THM_MOVT_PREL) if (r_type == R_ARM_THM_MOVW_PREL_NC || r_type == R_ARM_THM_MOVT_PREL)
value -= (input_section->output_section->vma value -= (input_section->output_section->vma
+ input_section->output_offset + rel->r_offset); + input_section->output_offset + rel->r_offset);
if (r_type == R_ARM_THM_MOVT_ABS || r_type == R_ARM_THM_MOVT_PREL) if (r_type == R_ARM_THM_MOVW_BREL && value >= 0x10000)
return bfd_reloc_overflow;
if (sym_flags == STT_ARM_TFUNC)
value |= 1;
if (r_type == R_ARM_THM_MOVT_ABS || r_type == R_ARM_THM_MOVT_PREL
|| r_type == R_ARM_THM_MOVT_BREL)
value >>= 16; value >>= 16;
insn &= 0xfbf08f00; insn &= 0xfbf08f00;