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AArch64: Relax thumb-plt testcases regexpr.

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The regexpr in these two files are a bit strict in that they don't account for
the slight changes in tags in certain arm targets which cause our address
offsets to change.   This changes the tests to allow slight movement in
locations while still strictly checking the rest.

ld/ChangeLog:

2020-08-03  Tamar Christina  <tamar.christina@arm.com>

	* testsuite/ld-arm/thumb-plt-got.d: Relax regexpr.
	* testsuite/ld-arm/thumb-plt.d: Likewise.
This commit is contained in:
Tamar Christina 2020-08-14 07:51:03 +01:00
parent dac736f6a1
commit 95c210664d
3 changed files with 9 additions and 4 deletions
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5
ld/ChangeLog
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@ -1,3 +1,8 @@
2020-08-14 Tamar Christina <tamar.christina@arm.com>
* testsuite/ld-arm/thumb-plt-got.d: Relax regexpr.
* testsuite/ld-arm/thumb-plt.d: Likewise.
2020-08-13 Alan Modra <amodra@gmail.com>
* emultempl/ppc64elf.em (params): Init new field.

4
ld/testsuite/ld-arm/thumb-plt-got.d
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@ -6,9 +6,9 @@
Relocation section '.rel.plt' at offset 0x108 contains 1 entry:
Offset Info Type Sym.Value Sym. Name
000101c4 00000116 R_ARM_JUMP_SLOT 00000000 foo
000101.+ 00000116 R_ARM_JUMP_SLOT 00000000 foo
Hex dump of section '.got':
NOTE: This section has relocations against it, but these have NOT been applied to this dump.
0x000101b8 40010100 00000000 00000000 11010000 @...............
0x000101.+ 40010100 00000000 00000000 11010000 @...............

4
ld/testsuite/ld-arm/thumb-plt.d
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@ -14,10 +14,10 @@ Disassembly of section \.plt:
112: f8df e008 ldr.w lr, \[pc, #8\] ; 11c <\.plt\+0xc>
116: 44fe add lr, pc
118: f85e ff08 ldr.w pc, \[lr, #8\]!
11c: 0001009c \.word 0x0001009c
11c: 000100(.+) \.word 0x000100\1
00000120 <foo@plt>:
120: f240 0c98 movw ip, #152 ; 0x98
120: f240 0c.+ movw ip, #[0-9]+ ; 0x.+
124: f2c0 0c01 movt ip, #1
128: 44fc add ip, pc
12a: f8dc f000 ldr.w pc, \[ip\]