aarch64: Add support for 128-bit system register mrrs and msrr insns
With the addition of 128-bit system registers to the Arm architecture starting with Armv9.4-a, a mechanism for manipulating their contents is introduced with the `msrr' and `mrrs' instruction pair. These move values from one such 128-bit system register into a pair of contiguous general-purpose registers and vice-versa, as for example: msrr ttlb0_el1, x0, x1 mrrs x0, x1, ttlb0_el1 This patch adds the necessary support for these instructions, adding checks for system-register width by defining a new operand type in the form of `AARCH64_OPND_SYSREG128' and the `aarch64_sys_reg_128bit_p' predicate, responsible for checking whether the requested system register table entry is marked as implemented in the 128-bit mode via the F_REG_128 flag.
This commit is contained in:
Victor Do Nascimento
parent
33ccb0e0db
commit
9af8f67118
@ -4788,7 +4788,7 @@ parse_sme_sm_za (char **str)
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static int
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parse_sys_reg (char **str, htab_t sys_regs,
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int imple_defined_p, int pstatefield_p,
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uint32_t* flags)
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uint32_t* flags, bool sysreg128_p)
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{
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char *p, *q;
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char buf[AARCH64_MAX_SYSREG_NAME_LEN];
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@ -4838,6 +4838,9 @@ parse_sys_reg (char **str, htab_t sys_regs,
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&o->features))
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as_bad (_("selected processor does not support system register "
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"name '%s'"), buf);
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if (sysreg128_p && !aarch64_sys_reg_128bit_p (o->flags))
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as_bad (_("128-bit-wide accsess not allowed on selected system"
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" register '%s'"), buf);
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if (aarch64_sys_reg_deprecated_p (o->flags))
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as_warn (_("system register name '%s' is deprecated and may be "
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"removed in a future release"), buf);
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@ -7616,12 +7619,14 @@ parse_operands (char *str, const aarch64_opcode *opcode)
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}
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info->qualifier = base_qualifier;
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goto regoff_addr;
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case AARCH64_OPND_SYSREG:
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case AARCH64_OPND_SYSREG128:
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{
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bool sysreg128_p = operands[i] == AARCH64_OPND_SYSREG128;
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uint32_t sysreg_flags;
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if ((val = parse_sys_reg (&str, aarch64_sys_regs_hsh, 1, 0,
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&sysreg_flags)) == PARSE_FAIL)
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&sysreg_flags,
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sysreg128_p)) == PARSE_FAIL)
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{
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set_syntax_error (_("unknown or missing system register name"));
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goto failure;
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@ -7635,7 +7640,7 @@ parse_operands (char *str, const aarch64_opcode *opcode)
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{
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uint32_t sysreg_flags;
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if ((val = parse_sys_reg (&str, aarch64_pstatefield_hsh, 0, 1,
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&sysreg_flags)) == PARSE_FAIL)
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&sysreg_flags, false)) == PARSE_FAIL)
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{
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set_syntax_error (_("unknown or missing PSTATE field name"));
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goto failure;
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2
gas/testsuite/gas/aarch64/illegal-sysreg128.d
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2
gas/testsuite/gas/aarch64/illegal-sysreg128.d
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@ -0,0 +1,2 @@
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#name: Instruction validation testing for mrrs and msrr.
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#error_output: illegal-sysreg128.l
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11
gas/testsuite/gas/aarch64/illegal-sysreg128.l
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11
gas/testsuite/gas/aarch64/illegal-sysreg128.l
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@ -0,0 +1,11 @@
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.*: Assembler messages:
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.*: Error: 128-bit-wide accsess not allowed on selected system register 'accdata_el1'
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.*: Error: 128-bit-wide accsess not allowed on selected system register 'accdata_el1'
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.*: Error: operand mismatch -- `mrrs w0,w1,ttbr0_el1'
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.*: Info: did you mean this\?
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.*: Info: mrrs x0, x1, ttbr0_el1
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.*: Error: operand mismatch -- `msrr ttbr0_el1,w0,w1'
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.*: Info: did you mean this\?
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.*: Info: msrr ttbr0_el1, x0, x1
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.*: Error: reg pair must be contiguous at operand 2 -- `mrrs x0,x2,ttbr0_el1'
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.*: Error: reg pair must be contiguous at operand 3 -- `msrr ttbr0_el1,x0,x2'
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8
gas/testsuite/gas/aarch64/illegal-sysreg128.s
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8
gas/testsuite/gas/aarch64/illegal-sysreg128.s
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@ -0,0 +1,8 @@
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.arch armv8.1-a+d128
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mrrs x0, x1, accdata_el1
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msrr accdata_el1, x0, x1
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mrrs w0, w1, ttbr0_el1
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msrr ttbr0_el1, w0, w1
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mrrs x0, x2, ttbr0_el1
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msrr ttbr0_el1, x0, x2
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28
gas/testsuite/gas/aarch64/sysreg128.d
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28
gas/testsuite/gas/aarch64/sysreg128.d
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@ -0,0 +1,28 @@
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#objdump: -dr
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.*
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Disassembly of section \.text:
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0+ <\.text>:
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[^:]*: d5787402 mrrs x2, x3, par_el1
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[^:]*: d5587404 msrr par_el1, x4, x5
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[^:]*: d578d0c2 mrrs x2, x3, rcwmask_el1
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[^:]*: d558d0c4 msrr rcwmask_el1, x4, x5
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[^:]*: d578d062 mrrs x2, x3, rcwsmask_el1
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[^:]*: d558d064 msrr rcwsmask_el1, x4, x5
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[^:]*: d5782002 mrrs x2, x3, ttbr0_el1
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[^:]*: d5582004 msrr ttbr0_el1, x4, x5
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[^:]*: d57d2002 mrrs x2, x3, ttbr0_el12
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[^:]*: d55d2004 msrr ttbr0_el12, x4, x5
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[^:]*: d57c2002 mrrs x2, x3, ttbr0_el2
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[^:]*: d55c2004 msrr ttbr0_el2, x4, x5
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[^:]*: d5782022 mrrs x2, x3, ttbr1_el1
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[^:]*: d5582024 msrr ttbr1_el1, x4, x5
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[^:]*: d57d2022 mrrs x2, x3, ttbr1_el12
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[^:]*: d55d2024 msrr ttbr1_el12, x4, x5
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[^:]*: d57c2022 mrrs x2, x3, ttbr1_el2
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[^:]*: d55c2024 msrr ttbr1_el2, x4, x5
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[^:]*: d57c2102 mrrs x2, x3, vttbr_el2
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[^:]*: d55c2104 msrr vttbr_el2, x4, x5
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17
gas/testsuite/gas/aarch64/sysreg128.s
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17
gas/testsuite/gas/aarch64/sysreg128.s
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@ -0,0 +1,17 @@
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.arch armv9.4-a+d128+the
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.macro rwreg128, name
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mrrs x2, x3, \name
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msrr \name, x4, x5
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.endm
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rwreg128 par_el1
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rwreg128 rcwmask_el1
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rwreg128 rcwsmask_el1
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rwreg128 ttbr0_el1
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rwreg128 ttbr0_el12
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rwreg128 ttbr0_el2
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rwreg128 ttbr1_el1
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rwreg128 ttbr1_el12
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rwreg128 ttbr1_el2
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rwreg128 vttbr_el2
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@ -561,6 +561,7 @@ enum aarch64_opnd
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AARCH64_OPND_SIMD_ADDR_POST, /* Address of ld/st multiple post-indexed. */
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AARCH64_OPND_SYSREG, /* System register operand. */
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AARCH64_OPND_SYSREG128, /* 128-bit system register operand. */
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AARCH64_OPND_PSTATEFIELD, /* PSTATE field name operand. */
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AARCH64_OPND_SYSREG_AT, /* System register <at_op> operand. */
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AARCH64_OPND_SYSREG_DC, /* System register <dc_op> operand. */
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@ -1328,6 +1329,7 @@ typedef struct
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extern const aarch64_sys_reg aarch64_sys_regs [];
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extern const aarch64_sys_reg aarch64_pstatefields [];
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extern bool aarch64_sys_reg_deprecated_p (const uint32_t);
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extern bool aarch64_sys_reg_128bit_p (const uint32_t);
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extern bool aarch64_sys_reg_alias_p (const uint32_t);
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extern bool aarch64_pstatefield_supported_p (const aarch64_feature_set,
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const aarch64_sys_reg *);
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@ -302,6 +302,7 @@ aarch64_ext_regno_pair (const aarch64_operand *self ATTRIBUTE_UNUSED, aarch64_op
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aarch64_operand_error *errors ATTRIBUTE_UNUSED)
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{
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assert (info->idx == 1
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|| info->idx == 2
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|| info->idx == 3
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|| info->idx == 5);
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@ -1710,7 +1710,7 @@ operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx,
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else if (type == AARCH64_OPND_PAIRREG
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|| type == AARCH64_OPND_PAIRREG_OR_XZR)
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{
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assert (idx == 1 || idx == 3 || idx == 5);
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assert (idx == 1 || idx == 2 || idx == 3 || idx == 5);
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if (opnds[idx - 1].reg.regno % 2 != 0)
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{
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set_syntax_error (mismatch_detail, idx - 1,
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@ -4514,6 +4514,7 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc,
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break;
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case AARCH64_OPND_SYSREG:
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case AARCH64_OPND_SYSREG128:
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for (i = 0; aarch64_sys_regs[i].name; ++i)
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{
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const aarch64_sys_reg *sr = aarch64_sys_regs + i;
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@ -4723,6 +4724,12 @@ aarch64_sys_reg_deprecated_p (const uint32_t reg_flags)
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return (reg_flags & F_DEPRECATED) != 0;
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}
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bool
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aarch64_sys_reg_128bit_p (const uint32_t reg_flags)
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{
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return (reg_flags & F_REG_128) != 0;
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}
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bool
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aarch64_sys_reg_alias_p (const uint32_t reg_flags)
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{
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@ -4236,6 +4236,8 @@ const struct aarch64_opcode aarch64_opcode_table[] =
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CORE_INSN ("msr", 0xd5000000, 0xffe00000, ic_system, 0, OP2 (SYSREG, Rt), QL_SRC_X, F_SYS_WRITE),
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CORE_INSN ("sysl",0xd5280000, 0xfff80000, ic_system, 0, OP5 (Rt, UIMM3_OP1, CRn, CRm, UIMM3_OP2), QL_SYSL, 0),
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CORE_INSN ("mrs", 0xd5200000, 0xffe00000, ic_system, 0, OP2 (Rt, SYSREG), QL_DST_X, F_SYS_READ),
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D128_INSN ("mrrs", 0xd5700000, 0xfff00000, OP3 (Rt, PAIRREG, SYSREG128), QL_DST_X2, F_SYS_READ),
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D128_INSN ("msrr", 0xd5500000, 0xfff00000, OP3 (SYSREG128, Rt, PAIRREG), QL_SRC_X2, F_SYS_WRITE),
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CORE_INSN ("paciaz", 0xd503231f, 0xffffffff, ic_system, 0, OP0 (), {}, F_ALIAS),
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CORE_INSN ("paciasp", 0xd503233f, 0xffffffff, ic_system, 0, OP0 (), {}, F_ALIAS),
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CORE_INSN ("pacibz", 0xd503235f, 0xffffffff, ic_system, 0, OP0 (), {}, F_ALIAS),
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@ -6342,6 +6344,7 @@ const struct aarch64_opcode aarch64_opcode_table[] =
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Y(ADDRESS, simd_addr_post, "SIMD_ADDR_POST", 0, F(), \
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"a post-indexed address with immediate or register increment") \
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Y(SYSTEM, sysreg, "SYSREG", 0, F(), "a system register") \
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Y(SYSTEM, sysreg, "SYSREG128", 0, F(), "a 128-bit system register") \
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Y(SYSTEM, pstatefield, "PSTATEFIELD", 0, F(), \
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"a PSTATE field name") \
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Y(SYSTEM, sysins_op, "SYSREG_AT", 0, F(), \
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