From 9afe6eb82f6abc63f7235771b803497ebb6455f2 Mon Sep 17 00:00:00 2001
From: "H.J. Lu" <hjl.tools@gmail.com>
Date: Fri, 17 Jul 2009 17:08:34 +0000
Subject: [PATCH] 2009-07-17 H.J. Lu <hongjiu.lu@intel.com>
* config/tc-i386.c (md_assemble): Check implicit registers
only for instructions with 3 operands or less.
---
gas/ChangeLog | 5 +++++
gas/config/tc-i386.c | 15 +++++++++------
2 files changed, 14 insertions(+), 6 deletions(-)
diff --git a/gas/ChangeLog b/gas/ChangeLog
index 576c8589502..dba01f6822b 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,8 @@
+2009-07-17 H.J. Lu <hongjiu.lu@intel.com>
+
+ * config/tc-i386.c (md_assemble): Check implicit registers
+ only for instructions with 3 operands or less.
+
2009-07-17 Nick Clifton <nickc@redhat.com>
* config/tc-avr.c (md_apply_fix): Cast fixup reloc type to avoid
diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c
index f4660b4ec7d..0862ab00a73 100644
--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -2821,12 +2821,15 @@ md_assemble (char *line)
if (i.types[0].bitfield.imm1)
i.imm_operands = 0; /* kludge for shift insns. */
- for (j = 0; j < i.operands; j++)
- if (i.types[j].bitfield.inoutportreg
- || i.types[j].bitfield.shiftcount
- || i.types[j].bitfield.acc
- || i.types[j].bitfield.floatacc)
- i.reg_operands--;
+ /* We only need to check those implicit registers for instructions
+ with 3 operands or less. */
+ if (i.operands <= 3)
+ for (j = 0; j < i.operands; j++)
+ if (i.types[j].bitfield.inoutportreg
+ || i.types[j].bitfield.shiftcount
+ || i.types[j].bitfield.acc
+ || i.types[j].bitfield.floatacc)
+ i.reg_operands--;
/* ImmExt should be processed after SSE2AVX. */
if (!i.tm.opcode_modifier.sse2avx