aarch64: Consolidate ZA slice parsing
Now that parse_typed_reg checks the range of tile register numbers and libopcodes checks the range of vector select offsets, there's very little difference between the parsing of ZA tile indices, ZA array indices, and PSEL indices. The main one is that ZA array indices don't currently allow "za" to be qualified, but we need to remove that restriction for SME2. This patch therefore consolidates all three parsers into a single routine, parameterised by the type of register that they expect.
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Richard Sandiford
parent
ff60bcbfbe
commit
9d86238266
@ -4422,25 +4422,27 @@ parse_sme_za_index (char **str, struct aarch64_indexed_za *opnd)
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return true;
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}
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/* Parse SME ZA horizontal or vertical vector access to tiles.
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/* Parse a register of type REG_TYPE that might have an element type
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qualifier and that is indexed by two values: a 32-bit register,
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followed by an immediate. The 32-bit register must be W12-W15.
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The range of the immediate varies by opcode and is checked in
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libopcodes.
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Return true on success, populating OPND with information about
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the indexed tile and QUALIFIER with the qualifier that was applied
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to the tile name.
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the operand and setting QUALIFIER to the register qualifier.
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Field format examples:
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ZA0<HV>.B[<Wv>, #<imm>]
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<ZAn><HV>.H[<Wv>, #<imm>]
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<ZAn><HV>.S[<Wv>, #<imm>]
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<ZAn><HV>.D[<Wv>, #<imm>]
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<ZAn><HV>.Q[<Wv>, #<imm>]
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<Pm>.<T>[<Wv>< #<imm>]
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ZA[<Wv>, #<imm>]
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<ZAn><HV>.<T>[<Wv>, #<imm>]
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*/
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static bool
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parse_sme_za_hv_tiles_operand (char **str,
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struct aarch64_indexed_za *opnd,
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aarch64_opnd_qualifier_t *qualifier)
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parse_dual_indexed_reg (char **str, aarch64_reg_type reg_type,
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struct aarch64_indexed_za *opnd,
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aarch64_opnd_qualifier_t *qualifier)
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{
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const reg_entry *reg = parse_reg_with_qual (str, REG_TYPE_ZATHV, qualifier);
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const reg_entry *reg = parse_reg_with_qual (str, reg_type, qualifier);
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if (!reg)
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return false;
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@ -4464,7 +4466,7 @@ parse_sme_za_hv_tiles_operand_with_braces (char **str,
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return false;
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}
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if (!parse_sme_za_hv_tiles_operand (str, opnd, qualifier))
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if (!parse_dual_indexed_reg (str, REG_TYPE_ZATHV, opnd, qualifier))
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return false;
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if (!skip_past_char (str, '}'))
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@ -4585,33 +4587,6 @@ parse_sme_list_of_64bit_tiles (char **str)
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return regno;
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}
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/* Parse ZA array operand used in e.g. STR and LDR instruction.
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Operand format:
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ZA[<Wv>, <imm>]
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ZA[<Wv>, #<imm>]
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Return true on success, populating OPND with information about
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the operand. */
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static bool
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parse_sme_za_array (char **str, struct aarch64_indexed_za *opnd)
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{
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char *q;
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q = *str;
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const reg_entry *reg = parse_reg (&q);
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if (!reg || reg->type != REG_TYPE_ZA)
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{
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set_syntax_error (_("expected ZA array"));
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return false;
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}
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opnd->regno = -1;
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*str = q;
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return parse_sme_za_index (str, opnd);
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}
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/* Parse streaming mode operand for SMSTART and SMSTOP.
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{SM | ZA}
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@ -4638,32 +4613,6 @@ parse_sme_sm_za (char **str)
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return TOLOWER (p[0]);
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}
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/* Parse the name of the source scalable predicate register, the index base
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register W12-W15 and the element index. Function performs element index
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limit checks as well as qualifier type checks.
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<Pn>.<T>[<Wv>, <imm>]
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<Pn>.<T>[<Wv>, #<imm>]
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Return true on success, populating OPND with information about the index
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and setting QUALIFIER to <T>. */
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static bool
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parse_sme_pred_reg_with_index (char **str, struct aarch64_indexed_za *opnd,
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aarch64_opnd_qualifier_t *qualifier)
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{
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const reg_entry *reg = parse_reg_with_qual (str, REG_TYPE_PN, qualifier);
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if (reg == NULL)
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return false;
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opnd->regno = reg->number;
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if (! parse_sme_za_index (str, opnd))
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return false;
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return true;
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}
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/* Parse a system register or a PSTATE field name for an MSR/MRS instruction.
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Returns the encoding for the option, or PARSE_FAIL.
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@ -7060,9 +7009,8 @@ parse_operands (char *str, const aarch64_opcode *opcode)
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break;
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case AARCH64_OPND_SME_PnT_Wm_imm:
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/* <Pn>.<T>[<Wm>, #<imm>] */
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if (!parse_sme_pred_reg_with_index (&str, &info->indexed_za,
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&qualifier))
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if (!parse_dual_indexed_reg (&str, REG_TYPE_PN,
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&info->indexed_za, &qualifier))
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goto failure;
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info->qualifier = qualifier;
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break;
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@ -7396,8 +7344,8 @@ parse_operands (char *str, const aarch64_opcode *opcode)
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? !parse_sme_za_hv_tiles_operand_with_braces (&str,
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&info->indexed_za,
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&qualifier)
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: !parse_sme_za_hv_tiles_operand (&str, &info->indexed_za,
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&qualifier))
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: !parse_dual_indexed_reg (&str, REG_TYPE_ZATHV,
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&info->indexed_za, &qualifier))
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goto failure;
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info->qualifier = qualifier;
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break;
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@ -7410,8 +7358,10 @@ parse_operands (char *str, const aarch64_opcode *opcode)
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break;
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case AARCH64_OPND_SME_ZA_array:
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if (!parse_sme_za_array (&str, &info->indexed_za))
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if (!parse_dual_indexed_reg (&str, REG_TYPE_ZA,
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&info->indexed_za, &qualifier))
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goto failure;
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info->qualifier = qualifier;
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break;
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case AARCH64_OPND_MOPS_ADDR_Rd:
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@ -31,3 +31,20 @@
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[^:]*:[0-9]+: Error: operand 2 must have the same immediate value as operand 1 -- `str za\[w13,-1\],\[x17,#1,mul vl\]'
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[^:]*:[0-9]+: Error: operand 2 must have the same immediate value as operand 1 -- `ldr za\[w13,1\],\[x17,#-1,mul vl\]'
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[^:]*:[0-9]+: Error: operand 2 must have the same immediate value as operand 1 -- `str za\[w13,1\],\[x17,#-1,mul vl\]'
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[^:]*:[0-9]+: Error: operand mismatch -- `ldr za.b\[w12,0\],\[x0\]'
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[^:]*:[0-9]+: Info: did you mean this\?
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[^:]*:[0-9]+: Info: ldr za\[w12, 0\], \[x0\]
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[^:]*:[0-9]+: Error: operand mismatch -- `ldr za.h\[w12,0\],\[x0\]'
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[^:]*:[0-9]+: Info: did you mean this\?
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[^:]*:[0-9]+: Info: ldr za\[w12, 0\], \[x0\]
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[^:]*:[0-9]+: Error: operand mismatch -- `ldr za.s\[w12,0\],\[x0\]'
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[^:]*:[0-9]+: Info: did you mean this\?
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[^:]*:[0-9]+: Info: ldr za\[w12, 0\], \[x0\]
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[^:]*:[0-9]+: Error: operand mismatch -- `ldr za.d\[w12,0\],\[x0\]'
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[^:]*:[0-9]+: Info: did you mean this\?
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[^:]*:[0-9]+: Info: ldr za\[w12, 0\], \[x0\]
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[^:]*:[0-9]+: Error: operand mismatch -- `ldr za.q\[w12,0\],\[x0\]'
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[^:]*:[0-9]+: Info: did you mean this\?
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[^:]*:[0-9]+: Info: ldr za\[w12, 0\], \[x0\]
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[^:]*:[0-9]+: Error: expected '\[' at operand 1 -- `ldr za/z\[w12,0\],\[x0\]'
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[^:]*:[0-9]+: Error: unexpected character `2' in element size at operand 1 -- `ldr za.2b\[w12,0\],\[x0\]'
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@ -37,3 +37,11 @@ ldr za[w13, -1], [x17, #1, mul vl]
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str za[w13, -1], [x17, #1, mul vl]
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ldr za[w13, 1], [x17, #-1, mul vl]
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str za[w13, 1], [x17, #-1, mul vl]
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ldr za.b[w12, 0], [x0]
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ldr za.h[w12, 0], [x0]
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ldr za.s[w12, 0], [x0]
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ldr za.d[w12, 0], [x0]
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ldr za.q[w12, 0], [x0]
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ldr za/z[w12, 0], [x0]
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ldr za.2b[w12, 0], [x0]
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@ -8,6 +8,13 @@
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[^:]*:[0-9]+: Info: psel p1, p15, p3.h\[w15, 0\]
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[^:]*:[0-9]+: Info: psel p1, p15, p3.s\[w15, 0\]
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[^:]*:[0-9]+: Info: psel p1, p15, p3.d\[w15, 0\]
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[^:]*:[0-9]+: Error: operand mismatch -- `psel p1,p15,p3\[w15,#0\]'
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[^:]*:[0-9]+: Info: did you mean this\?
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[^:]*:[0-9]+: Info: psel p1, p15, p3.b\[w15, 0\]
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[^:]*:[0-9]+: Info: other valid variant\(s\):
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[^:]*:[0-9]+: Info: psel p1, p15, p3.h\[w15, 0\]
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[^:]*:[0-9]+: Info: psel p1, p15, p3.s\[w15, 0\]
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[^:]*:[0-9]+: Info: psel p1, p15, p3.d\[w15, 0\]
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[^:]*:[0-9]+: Error: expected vector select register W12-W15 at operand 3 -- `psel p1,p15,p3.b\[w11\]'
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[^:]*:[0-9]+: Error: expected vector select register W12-W15 at operand 3 -- `psel p8,p11,p15.h\[w16\]'
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[^:]*:[0-9]+: Error: expected vector select register W12-W15 at operand 3 -- `psel p2,p7,p15.s\[w3\]'
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@ -3,6 +3,7 @@
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psel p1, p15, p3.b[w12]
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psel p1, p15, p3.q[w15]
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psel p1, p15, p3.q[w15, #0]
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psel p1, p15, p3[w15,#0]
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psel p1, p15, p3.b[w11]
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psel p8, p11, p15.h[w16]
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psel p2, p7, p15.s[w3]
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