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Add support for 64-bit ARM architecture: AArch64

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This commit is contained in:
Nick Clifton 2012-08-13 14:52:54 +00:00
parent f47f77df4e
commit a06ea96464
307 changed files with 68333 additions and 39 deletions
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44
bfd/ChangeLog
View File

@ -1,3 +1,47 @@
2012-08-13 Ian Bolton <ian.bolton@arm.com>
Laurent Desnogues <laurent.desnogues@arm.com>
Jim MacArthur <jim.macarthur@arm.com>
Marcus Shawcroft <marcus.shawcroft@arm.com>
Nigel Stephens <nigel.stephens@arm.com>
Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
Richard Earnshaw <rearnsha@arm.com>
Sofiane Naci <sofiane.naci@arm.com>
Tejas Belagod <tejas.belagod@arm.com>
Yufeng Zhang <yufeng.zhang@arm.com>
* Makefile.am: Add AArch64 files.
* Makefile.in: Regenerate.
* archures.c (bfd_aarch64_arch): New declaration.
(bfd_archures_list): Use bfd_archures_list.
* bfd-in.h (bfd_elf64_aarch64_init_maps): New declaration.
(bfd_aarch64_process_before_allocation): New declaration.
(bfd_elf64_aarch64_process_before_allocation): New declaration.
(bfd_elf64_aarch64_set_options): New declaration.
(bfd_elf64_aarch64_add_glue_sections_to_bfd): New declaration.
(BFD_AARCH64_SPECIAL_SYM_TYPE_MAP): New definition.
(BFD_AARCH64_SPECIAL_SYM_TYPE_TAG): New definition.
(BFD_AARCH64_SPECIAL_SYM_TYPE_OTHER): New definition.
(BFD_AARCH64_SPECIAL_SYM_TYPE_ANY): New definition.
(bfd_is_aarch64_special_symbol_name): New declaration.
(bfd_aarch64_merge_machines): New declaration.
(bfd_aarch64_update_notes): New declaration.
(int bfd_aarch64_get_mach_from_notes): New declaration.
(elf64_aarch64_setup_section_lists): New declaration.
(elf64_aarch64_next_input_section): New declaration.
(elf64_aarch64_size_stubs): New declaration.
(elf64_aarch64_build_stubs): New declaration.
* config.bfd: Add AArch64.
* configure.in: Add AArch64.
* configure: Regenerate.
* cpu-aarch64.c: New file.
* elf-bfd.h: Add AArch64.
* bfd-in2.h: Regenerate.
* libbfd.h: Regenerate.
* elf64-aarch64.c: New file.
* reloc.c: Add AArch64 relocations.
* targets.c: Add AArch64.
* po/SRC-POTFILES.in: Regenerate.
2012-08-13 Maciej W. Rozycki <macro@codesourcery.com>
* elfxx-mips.c (mips_elf_calculate_relocation): Fix the handling

4
bfd/Makefile.am
View File

@ -71,6 +71,7 @@ BFD64_LIBS_CFILES = archive64.c
# This list is alphabetized to make it easier to keep in sync
# with the decls and initializer in archures.c.
ALL_MACHINES = \
cpu-aarch64.lo \
cpu-alpha.lo \
cpu-arc.lo \
cpu-arm.lo \
@ -151,6 +152,7 @@ ALL_MACHINES = \
cpu-z8k.lo
ALL_MACHINES_CFILES = \
cpu-aarch64.c \
cpu-alpha.c \
cpu-arc.c \
cpu-arm.c \
@ -613,6 +615,7 @@ BFD32_BACKENDS_CFILES = \
# elf32-ia64.c requires a 64-bit bfd_vma, and hence can not be put in
# BFD32_BACKENDS.
BFD64_BACKENDS = \
elf64-aarch64.lo \
aix5ppc-core.lo \
aout64.lo \
coff-alpha.lo \
@ -651,6 +654,7 @@ BFD64_BACKENDS = \
vms-alpha.lo
BFD64_BACKENDS_CFILES = \
elf64-aarch64.c \
aix5ppc-core.c \
aout64.c \
coff-alpha.c \

6
bfd/Makefile.in
View File

@ -370,6 +370,7 @@ BFD64_LIBS_CFILES = archive64.c
# This list is alphabetized to make it easier to keep in sync
# with the decls and initializer in archures.c.
ALL_MACHINES = \
cpu-aarch64.lo \
cpu-alpha.lo \
cpu-arc.lo \
cpu-arm.lo \
@ -450,6 +451,7 @@ ALL_MACHINES = \
cpu-z8k.lo
ALL_MACHINES_CFILES = \
cpu-aarch64.c \
cpu-alpha.c \
cpu-arc.c \
cpu-arm.c \
@ -914,6 +916,7 @@ BFD32_BACKENDS_CFILES = \
# elf32-ia64.c requires a 64-bit bfd_vma, and hence can not be put in
# BFD32_BACKENDS.
BFD64_BACKENDS = \
elf64-aarch64.lo \
aix5ppc-core.lo \
aout64.lo \
coff-alpha.lo \
@ -952,6 +955,7 @@ BFD64_BACKENDS = \
vms-alpha.lo
BFD64_BACKENDS_CFILES = \
elf64-aarch64.c \
aix5ppc-core.c \
aout64.c \
coff-alpha.c \
@ -1270,6 +1274,7 @@ distclean-compile:
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cofflink.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/compress.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/corefile.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpu-aarch64.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpu-alpha.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpu-arc.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpu-arm.Plo@am__quote@
@ -1427,6 +1432,7 @@ distclean-compile:
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf32-xstormy16.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf32-xtensa.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf32.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf64-aarch64.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf64-alpha.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf64-gen.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf64-hppa.Plo@am__quote@

4
bfd/archures.c
View File

@ -461,6 +461,8 @@ DESCRIPTION
.#define bfd_mach_tilepro 1
.#define bfd_mach_tilegx 1
.#define bfd_mach_tilegx32 2
. bfd_arch_aarch64, {* AArch64 *}
.#define bfd_mach_aarch64 0
. bfd_arch_last
. };
*/
@ -505,6 +507,7 @@ DESCRIPTION
.
*/
extern const bfd_arch_info_type bfd_aarch64_arch;
extern const bfd_arch_info_type bfd_alpha_arch;
extern const bfd_arch_info_type bfd_arc_arch;
extern const bfd_arch_info_type bfd_arm_arch;
@ -590,6 +593,7 @@ static const bfd_arch_info_type * const bfd_archures_list[] =
#ifdef SELECT_ARCHITECTURES
SELECT_ARCHITECTURES,
#else
&bfd_aarch64_arch,
&bfd_alpha_arch,
&bfd_arc_arch,
&bfd_arm_arch,

26
bfd/bfd-in.h
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@ -928,6 +928,32 @@ extern unsigned int _bfd_elf_ppc_at_tls_transform
extern unsigned int _bfd_elf_ppc_at_tprel_transform
(unsigned int, unsigned int);
extern void bfd_elf64_aarch64_init_maps
(bfd *);
void bfd_elf64_aarch64_set_options
(bfd *, struct bfd_link_info *, int, int, int);
/* ELF AArch64 mapping symbol support. */
#define BFD_AARCH64_SPECIAL_SYM_TYPE_MAP (1 << 0)
#define BFD_AARCH64_SPECIAL_SYM_TYPE_TAG (1 << 1)
#define BFD_AARCH64_SPECIAL_SYM_TYPE_OTHER (1 << 2)
#define BFD_AARCH64_SPECIAL_SYM_TYPE_ANY (~0)
extern bfd_boolean bfd_is_aarch64_special_symbol_name
(const char * name, int type);
/* AArch64 stub generation support. Called from the linker. */
extern int elf64_aarch64_setup_section_lists
(bfd *, struct bfd_link_info *);
extern void elf64_aarch64_next_input_section
(struct bfd_link_info *, struct bfd_section *);
extern bfd_boolean elf64_aarch64_size_stubs
(bfd *, bfd *, struct bfd_link_info *, bfd_signed_vma,
struct bfd_section * (*) (const char *, struct bfd_section *),
void (*) (void));
extern bfd_boolean elf64_aarch64_build_stubs
(struct bfd_link_info *);
/* TI COFF load page support. */
extern void bfd_ticoff_set_section_load_page
(struct bfd_section *, int);

242
bfd/bfd-in2.h
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@ -935,6 +935,32 @@ extern unsigned int _bfd_elf_ppc_at_tls_transform
extern unsigned int _bfd_elf_ppc_at_tprel_transform
(unsigned int, unsigned int);
extern void bfd_elf64_aarch64_init_maps
(bfd *);
void bfd_elf64_aarch64_set_options
(bfd *, struct bfd_link_info *, int, int, int);
/* ELF AArch64 mapping symbol support. */
#define BFD_AARCH64_SPECIAL_SYM_TYPE_MAP (1 << 0)
#define BFD_AARCH64_SPECIAL_SYM_TYPE_TAG (1 << 1)
#define BFD_AARCH64_SPECIAL_SYM_TYPE_OTHER (1 << 2)
#define BFD_AARCH64_SPECIAL_SYM_TYPE_ANY (~0)
extern bfd_boolean bfd_is_aarch64_special_symbol_name
(const char * name, int type);
/* AArch64 stub generation support. Called from the linker. */
extern int elf64_aarch64_setup_section_lists
(bfd *, struct bfd_link_info *);
extern void elf64_aarch64_next_input_section
(struct bfd_link_info *, struct bfd_section *);
extern bfd_boolean elf64_aarch64_size_stubs
(bfd *, bfd *, struct bfd_link_info *, bfd_signed_vma,
struct bfd_section * (*) (const char *, struct bfd_section *),
void (*) (void));
extern bfd_boolean elf64_aarch64_build_stubs
(struct bfd_link_info *);
/* TI COFF load page support. */
extern void bfd_ticoff_set_section_load_page
(struct bfd_section *, int);
@ -2164,6 +2190,8 @@ enum bfd_architecture
#define bfd_mach_tilepro 1
#define bfd_mach_tilegx 1
#define bfd_mach_tilegx32 2
bfd_arch_aarch64, /* AArch64 */
#define bfd_mach_aarch64 0
bfd_arch_last
};
@ -5040,6 +5068,220 @@ value in a word. The relocation is relative offset from */
the dynamic object into the runtime process image. */
BFD_RELOC_MICROBLAZE_COPY,
/* AArch64 ADD immediate instruction, holding bits 0 to 11 of the address.
Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL. */
BFD_RELOC_AARCH64_ADD_LO12,
/* Get to the page base of the global offset table entry for a symbol as
part of an ADRP instruction using a 21 bit PC relative value.Used in
conjunction with BFD_RELOC_AARCH64_LD64_GOT_LO12_NC. */
BFD_RELOC_AARCH64_ADR_GOT_PAGE,
/* AArch64 ADRP instruction, with bits 12 to 32 of a pc-relative page
offset, giving a 4KB aligned page base address. */
BFD_RELOC_AARCH64_ADR_HI21_PCREL,
/* AArch64 ADRP instruction, with bits 12 to 32 of a pc-relative page
offset, giving a 4KB aligned page base address, but with no overflow
checking. */
BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL,
/* AArch64 ADR instruction, holding a simple 21 bit pc-relative byte offset. */
BFD_RELOC_AARCH64_ADR_LO21_PCREL,
/* AArch64 19 bit pc-relative conditional branch and compare & branch.
The lowest two bits must be zero and are not stored in the instruction,
giving a 21 bit signed byte offset. */
BFD_RELOC_AARCH64_BRANCH19,
/* AArch64 26 bit pc-relative unconditional branch and link.
The lowest two bits must be zero and are not stored in the instruction,
giving a 28 bit signed byte offset. */
BFD_RELOC_AARCH64_CALL26,
/* AArch64 pseudo relocation code to be used internally by the AArch64
assembler and not (currently) written to any object files. */
BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP,
/* AArch64 26 bit pc-relative unconditional branch.
The lowest two bits must be zero and are not stored in the instruction,
giving a 28 bit signed byte offset. */
BFD_RELOC_AARCH64_JUMP26,
/* AArch64 Load Literal instruction, holding a 19 bit pc-relative word
offset. The lowest two bits must be zero and are not stored in the
instruction, giving a 21 bit signed byte offset. */
BFD_RELOC_AARCH64_LD_LO19_PCREL,
/* Unsigned 12 bit byte offset for 64 bit load/store from the page of
the GOT entry for this symbol. Used in conjunction with
BFD_RELOC_AARCH64_ADR_GOTPAGE. */
BFD_RELOC_AARCH64_LD64_GOT_LO12_NC,
/* AArch64 unspecified load/store instruction, holding bits 0 to 11 of the
address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL. */
BFD_RELOC_AARCH64_LDST_LO12,
/* AArch64 8-bit load/store instruction, holding bits 0 to 11 of the
address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL. */
BFD_RELOC_AARCH64_LDST8_LO12,
/* AArch64 16-bit load/store instruction, holding bits 0 to 11 of the
address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL. */
BFD_RELOC_AARCH64_LDST16_LO12,
/* AArch64 32-bit load/store instruction, holding bits 0 to 11 of the
address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL. */
BFD_RELOC_AARCH64_LDST32_LO12,
/* AArch64 64-bit load/store instruction, holding bits 0 to 11 of the
address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL. */
BFD_RELOC_AARCH64_LDST64_LO12,
/* AArch64 128-bit load/store instruction, holding bits 0 to 11 of the
address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL. */
BFD_RELOC_AARCH64_LDST128_LO12,
/* AArch64 MOV[NZK] instruction with most significant bits 0 to 15
of an unsigned address/value. */
BFD_RELOC_AARCH64_MOVW_G0,
/* AArch64 MOV[NZ] instruction with most significant bits 0 to 15
of a signed value. Changes instruction to MOVZ or MOVN depending on the
value's sign. */
BFD_RELOC_AARCH64_MOVW_G0_S,
/* AArch64 MOV[NZK] instruction with less significant bits 0 to 15 of
an address/value. No overflow checking. */
BFD_RELOC_AARCH64_MOVW_G0_NC,
/* AArch64 MOV[NZK] instruction with most significant bits 16 to 31
of an unsigned address/value. */
BFD_RELOC_AARCH64_MOVW_G1,
/* AArch64 MOV[NZK] instruction with less significant bits 16 to 31
of an address/value. No overflow checking. */
BFD_RELOC_AARCH64_MOVW_G1_NC,
/* AArch64 MOV[NZ] instruction with most significant bits 16 to 31
of a signed value. Changes instruction to MOVZ or MOVN depending on the
value's sign. */
BFD_RELOC_AARCH64_MOVW_G1_S,
/* AArch64 MOV[NZK] instruction with most significant bits 32 to 47
of an unsigned address/value. */
BFD_RELOC_AARCH64_MOVW_G2,
/* AArch64 MOV[NZK] instruction with less significant bits 32 to 47
of an address/value. No overflow checking. */
BFD_RELOC_AARCH64_MOVW_G2_NC,
/* AArch64 MOV[NZ] instruction with most significant bits 32 to 47
of a signed value. Changes instruction to MOVZ or MOVN depending on the
value's sign. */
BFD_RELOC_AARCH64_MOVW_G2_S,
/* AArch64 MOV[NZK] instruction with most signficant bits 48 to 64
of a signed or unsigned address/value. */
BFD_RELOC_AARCH64_MOVW_G3,
/* AArch64 TLS relocation. */
BFD_RELOC_AARCH64_TLSDESC,
/* AArch64 TLS DESC relocation. */
BFD_RELOC_AARCH64_TLSDESC_ADD,
/* AArch64 TLS DESC relocation. */
BFD_RELOC_AARCH64_TLSDESC_ADD_LO12_NC,
/* AArch64 TLS DESC relocation. */
BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE,
/* AArch64 TLS DESC relocation. */
BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21,
/* AArch64 TLS DESC relocation. */
BFD_RELOC_AARCH64_TLSDESC_CALL,
/* AArch64 TLS DESC relocation. */
BFD_RELOC_AARCH64_TLSDESC_LD64_LO12_NC,
/* AArch64 TLS DESC relocation. */
BFD_RELOC_AARCH64_TLSDESC_LD64_PREL19,
/* AArch64 TLS DESC relocation. */
BFD_RELOC_AARCH64_TLSDESC_LDR,
/* AArch64 TLS DESC relocation. */
BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC,
/* AArch64 TLS DESC relocation. */
BFD_RELOC_AARCH64_TLSDESC_OFF_G1,
/* Unsigned 12 bit byte offset to global offset table entry for a symbols
tls_index structure. Used in conjunction with
BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21. */
BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC,
/* Get to the page base of the global offset table entry for a symbols
tls_index structure as part of an adrp instruction using a 21 bit PC
relative value. Used in conjunction with
BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC. */
BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21,
/* AArch64 TLS INITIAL EXEC relocation. */
BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21,
/* AArch64 TLS INITIAL EXEC relocation. */
BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19,
/* AArch64 TLS INITIAL EXEC relocation. */
BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC,
/* AArch64 TLS INITIAL EXEC relocation. */
BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC,
/* AArch64 TLS INITIAL EXEC relocation. */
BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1,
/* AArch64 TLS LOCAL EXEC relocation. */
BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12,
/* AArch64 TLS LOCAL EXEC relocation. */
BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12,
/* AArch64 TLS LOCAL EXEC relocation. */
BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC,
/* AArch64 TLS LOCAL EXEC relocation. */
BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0,
/* AArch64 TLS LOCAL EXEC relocation. */
BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC,
/* AArch64 TLS LOCAL EXEC relocation. */
BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1,
/* AArch64 TLS LOCAL EXEC relocation. */
BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC,
/* AArch64 TLS LOCAL EXEC relocation. */
BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2,
/* AArch64 TLS relocation. */
BFD_RELOC_AARCH64_TLS_DTPMOD64,
/* AArch64 TLS relocation. */
BFD_RELOC_AARCH64_TLS_DTPREL64,
/* AArch64 TLS relocation. */
BFD_RELOC_AARCH64_TLS_TPREL64,
/* AArch64 14 bit pc-relative test bit and branch.
The lowest two bits must be zero and are not stored in the instruction,
giving a 16 bit signed byte offset. */
BFD_RELOC_AARCH64_TSTBR14,
/* Tilera TILEPro Relocations. */
BFD_RELOC_TILEPRO_COPY,
BFD_RELOC_TILEPRO_GLOB_DAT,

21
bfd/config.bfd
View File

@ -69,6 +69,7 @@ esac
targ_cpu=`echo $targ | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/\1/'`
case "${targ_cpu}" in
aarch64*) targ_archs="bfd_aarch64_arch bfd_arm_arch";;
alpha*) targ_archs=bfd_alpha_arch ;;
am34*|am33_2.0*) targ_archs=bfd_mn10300_arch ;;
arm*) targ_archs=bfd_arm_arch ;;
@ -143,6 +144,26 @@ case "${targ}" in
# START OF targmatch.h
#ifdef BFD64
aarch64-*-elf)
targ_defvec=bfd_elf64_littleaarch64_vec
targ_selvecs="bfd_elf64_bigaarch64_vec bfd_elf32_littlearm_vec bfd_elf32_bigarm_vec"
want64=true
;;
aarch64_be-*-elf)
targ_defvec=bfd_elf64_bigaarch64_vec
targ_selvecs="bfd_elf64_littleaarch64_vec bfd_elf32_bigarm_vec bfd_elf32_littlearm_vec"
want64=true
;;
aarch64-*-linux*)
targ_defvec=bfd_elf64_littleaarch64_vec
targ_selvecs="bfd_elf64_bigaarch64_vec bfd_elf32_littlearm_vec bfd_elf32_bigarm_vec"
want64=true
;;
aarch64_be-*-linux*)
targ_defvec=bfd_elf64_bigaarch64_vec
targ_selvecs="bfd_elf64_littleaarch64_vec bfd_elf32_bigarm_vec bfd_elf32_littlearm_vec"
want64=true
;;
alpha*-*-freebsd* | alpha*-*-kfreebsd*-gnu)
targ_defvec=bfd_elf64_alpha_freebsd_vec
targ_selvecs="bfd_elf64_alpha_vec ecoffalpha_little_vec"

2
bfd/configure vendored
View File

@ -15342,6 +15342,7 @@ do
bfd_elf32_xtensa_be_vec) tb="$tb xtensa-isa.lo xtensa-modules.lo elf32-xtensa.lo elf32.lo $elf" ;;
bfd_elf64_alpha_freebsd_vec) tb="$tb elf64-alpha.lo elf64.lo $elf"; target_size=64 ;;
bfd_elf64_alpha_vec) tb="$tb elf64-alpha.lo elf64.lo $elf"; target_size=64 ;;
bfd_elf64_bigaarch64_vec) tb="$tb elf64-aarch64.lo elf64.lo $elf"; target_size=64 ;;
bfd_elf64_big_generic_vec) tb="$tb elf64-gen.lo elf64.lo $elf"; target_size=64 ;;
bfd_elf64_bigmips_vec) tb="$tb elf64-mips.lo elf64.lo elfxx-mips.lo elf-vxworks.lo elf32.lo $elf ecofflink.lo"; target_size=64 ;;
bfd_elf64_hppa_linux_vec) tb="$tb elf64-hppa.lo elf64.lo $elf"; target_size=64 ;;
@ -15350,6 +15351,7 @@ do
bfd_elf64_ia64_hpux_big_vec) tb="$tb elf64-ia64.lo elfxx-ia64.lo elf64.lo $elf"; target_size=64 ;;
bfd_elf64_ia64_little_vec) tb="$tb elf64-ia64.lo elfxx-ia64.lo elf64.lo $elf"; target_size=64 ;;
bfd_elf64_ia64_vms_vec) tb="$tb elf64-ia64-vms.lo elf64-ia64.lo elfxx-ia64.lo elf64.lo vms-lib.lo vms-misc.lo $elf"; target_size=64 ;;
bfd_elf64_littleaarch64_vec)tb="$tb elf64-aarch64.lo elf64.lo $elf"; target_size=64 ;;
bfd_elf64_little_generic_vec) tb="$tb elf64-gen.lo elf64.lo $elf"; target_size=64 ;;
bfd_elf64_littlemips_vec) tb="$tb elf64-mips.lo elf64.lo elfxx-mips.lo elf-vxworks.lo elf32.lo $elf ecofflink.lo"; target_size=64 ;;
bfd_elf64_mmix_vec) tb="$tb elf64-mmix.lo elf64.lo $elf" target_size=64 ;;

2
bfd/configure.in
View File

@ -832,6 +832,7 @@ do
bfd_elf32_xtensa_be_vec) tb="$tb xtensa-isa.lo xtensa-modules.lo elf32-xtensa.lo elf32.lo $elf" ;;
bfd_elf64_alpha_freebsd_vec) tb="$tb elf64-alpha.lo elf64.lo $elf"; target_size=64 ;;
bfd_elf64_alpha_vec) tb="$tb elf64-alpha.lo elf64.lo $elf"; target_size=64 ;;
bfd_elf64_bigaarch64_vec) tb="$tb elf64-aarch64.lo elf64.lo $elf"; target_size=64 ;;
bfd_elf64_big_generic_vec) tb="$tb elf64-gen.lo elf64.lo $elf"; target_size=64 ;;
bfd_elf64_bigmips_vec) tb="$tb elf64-mips.lo elf64.lo elfxx-mips.lo elf-vxworks.lo elf32.lo $elf ecofflink.lo"; target_size=64 ;;
bfd_elf64_hppa_linux_vec) tb="$tb elf64-hppa.lo elf64.lo $elf"; target_size=64 ;;
@ -840,6 +841,7 @@ do
bfd_elf64_ia64_hpux_big_vec) tb="$tb elf64-ia64.lo elfxx-ia64.lo elf64.lo $elf"; target_size=64 ;;
bfd_elf64_ia64_little_vec) tb="$tb elf64-ia64.lo elfxx-ia64.lo elf64.lo $elf"; target_size=64 ;;
bfd_elf64_ia64_vms_vec) tb="$tb elf64-ia64-vms.lo elf64-ia64.lo elfxx-ia64.lo elf64.lo vms-lib.lo vms-misc.lo $elf"; target_size=64 ;;
bfd_elf64_littleaarch64_vec)tb="$tb elf64-aarch64.lo elf64.lo $elf"; target_size=64 ;;
bfd_elf64_little_generic_vec) tb="$tb elf64-gen.lo elf64.lo $elf"; target_size=64 ;;
bfd_elf64_littlemips_vec) tb="$tb elf64-mips.lo elf64.lo elfxx-mips.lo elf-vxworks.lo elf32.lo $elf ecofflink.lo"; target_size=64 ;;
bfd_elf64_mmix_vec) tb="$tb elf64-mmix.lo elf64.lo $elf" target_size=64 ;;

121
bfd/cpu-aarch64.c Normal file
View File

@ -0,0 +1,121 @@
/* BFD support for AArch64.
Copyright 2009, 2010, 2011, 2012 Free Software Foundation, Inc.
Contributed by ARM Ltd.
This file is part of BFD, the Binary File Descriptor library.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; see the file COPYING3. If not,
see <http://www.gnu.org/licenses/>. */
#include "sysdep.h"
#include "bfd.h"
#include "libbfd.h"
#include "libiberty.h"
/* This routine is provided two arch_infos and works out which Aarch64
machine which would be compatible with both and returns a pointer
to its info structure. */
static const bfd_arch_info_type *
compatible (const bfd_arch_info_type * a, const bfd_arch_info_type * b)
{
/* If a & b are for different architecture we can do nothing. */
if (a->arch != b->arch)
return NULL;
/* If a & b are for the same machine then all is well. */
if (a->mach == b->mach)
return a;
/* Otherwise if either a or b is the 'default' machine
then it can be polymorphed into the other. */
if (a->the_default)
return b;
if (b->the_default)
return a;
/* So far all newer cores are
supersets of previous cores. */
if (a->mach < b->mach)
return b;
else if (a->mach > b->mach)
return a;
/* Never reached! */
return NULL;
}
static struct
{
unsigned int mach;
char *name;
}
processors[] =
{
/* These two are example CPUs supported in GCC, once we have real
CPUs they will be removed. */
{ bfd_mach_aarch64, "example-1" },
{ bfd_mach_aarch64, "example-2" }
};
static bfd_boolean
scan (const struct bfd_arch_info *info, const char *string)
{
int i;
/* First test for an exact match. */
if (strcasecmp (string, info->printable_name) == 0)
return TRUE;
/* Next check for a processor name instead of an Architecture name. */
for (i = sizeof (processors) / sizeof (processors[0]); i--;)
{
if (strcasecmp (string, processors[i].name) == 0)
break;
}
if (i != -1 && info->mach == processors[i].mach)
return TRUE;
/* Finally check for the default architecture. */
if (strcasecmp (string, "aarch64") == 0)
return info->the_default;
return FALSE;
}
#define N(NUMBER, PRINT, DEFAULT, NEXT) \
{ 64, 64, 8, bfd_arch_aarch64, NUMBER, \
"aarch64", PRINT, 4, DEFAULT, compatible, scan, \
bfd_arch_default_fill, NEXT }
const bfd_arch_info_type bfd_aarch64_arch =
N (0, "aarch64", TRUE, NULL);
bfd_boolean
bfd_is_aarch64_special_symbol_name (const char *name, int type)
{
if (!name || name[0] != '$')
return FALSE;
if (name[1] == 'x' || name[1] == 'd')
type &= BFD_AARCH64_SPECIAL_SYM_TYPE_MAP;
else if (name[1] == 'm' || name[1] == 'f' || name[1] == 'p')
type &= BFD_AARCH64_SPECIAL_SYM_TYPE_TAG;
else
return FALSE;
return (type != 0 && (name[2] == 0 || name[2] == '.'));
}

4
bfd/doc/Makefile.in
View File

@ -43,7 +43,8 @@ subdir = doc
DIST_COMMON = $(srcdir)/Makefile.in $(srcdir)/Makefile.am \
$(bfd_TEXINFOS)
ACLOCAL_M4 = $(top_srcdir)/aclocal.m4
am__aclocal_m4_deps = $(top_srcdir)/../config/acx.m4 \
am__aclocal_m4_deps = $(top_srcdir)/../bfd/bfd.m4 \
$(top_srcdir)/../bfd/warning.m4 $(top_srcdir)/../config/acx.m4 \
$(top_srcdir)/../config/depstand.m4 \
$(top_srcdir)/../config/gettext-sister.m4 \
$(top_srcdir)/../config/largefile.m4 \
@ -56,7 +57,6 @@ am__aclocal_m4_deps = $(top_srcdir)/../config/acx.m4 \
$(top_srcdir)/../config/stdint.m4 $(top_srcdir)/../libtool.m4 \
$(top_srcdir)/../ltoptions.m4 $(top_srcdir)/../ltsugar.m4 \
$(top_srcdir)/../ltversion.m4 $(top_srcdir)/../lt~obsolete.m4 \
$(top_srcdir)/bfd.m4 $(top_srcdir)/warning.m4 \
$(top_srcdir)/acinclude.m4 $(top_srcdir)/../config/zlib.m4 \
$(top_srcdir)/configure.in
am__configure_deps = $(am__aclocal_m4_deps) $(CONFIGURE_DEPENDENCIES) \

3
bfd/elf-bfd.h
View File

@ -402,7 +402,8 @@ struct eh_frame_hdr_info
one line. */
enum elf_target_id
{
ALPHA_ELF_DATA = 1,
AARCH64_ELF_DATA = 1,
ALPHA_ELF_DATA,
ARM_ELF_DATA,
AVR_ELF_DATA,
BFIN_ELF_DATA,

7016
bfd/elf64-aarch64.c Normal file
View File

File diff suppressed because it is too large Load Diff

57
bfd/libbfd.h
View File

@ -2420,6 +2420,63 @@ static const char *const bfd_reloc_code_real_names[] = { "@@uninitialized@@",
"BFD_RELOC_MICROBLAZE_64_GOTOFF",
"BFD_RELOC_MICROBLAZE_32_GOTOFF",
"BFD_RELOC_MICROBLAZE_COPY",
"BFD_RELOC_AARCH64_ADD_LO12",
"BFD_RELOC_AARCH64_ADR_GOT_PAGE",
"BFD_RELOC_AARCH64_ADR_HI21_PCREL",
"BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL",
"BFD_RELOC_AARCH64_ADR_LO21_PCREL",
"BFD_RELOC_AARCH64_BRANCH19",
"BFD_RELOC_AARCH64_CALL26",
"BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP",
"BFD_RELOC_AARCH64_JUMP26",
"BFD_RELOC_AARCH64_LD_LO19_PCREL",
"BFD_RELOC_AARCH64_LD64_GOT_LO12_NC",
"BFD_RELOC_AARCH64_LDST_LO12",
"BFD_RELOC_AARCH64_LDST8_LO12",
"BFD_RELOC_AARCH64_LDST16_LO12",
"BFD_RELOC_AARCH64_LDST32_LO12",
"BFD_RELOC_AARCH64_LDST64_LO12",
"BFD_RELOC_AARCH64_LDST128_LO12",
"BFD_RELOC_AARCH64_MOVW_G0",
"BFD_RELOC_AARCH64_MOVW_G0_S",
"BFD_RELOC_AARCH64_MOVW_G0_NC",
"BFD_RELOC_AARCH64_MOVW_G1",
"BFD_RELOC_AARCH64_MOVW_G1_NC",
"BFD_RELOC_AARCH64_MOVW_G1_S",
"BFD_RELOC_AARCH64_MOVW_G2",
"BFD_RELOC_AARCH64_MOVW_G2_NC",
"BFD_RELOC_AARCH64_MOVW_G2_S",
"BFD_RELOC_AARCH64_MOVW_G3",
"BFD_RELOC_AARCH64_TLSDESC",
"BFD_RELOC_AARCH64_TLSDESC_ADD",
"BFD_RELOC_AARCH64_TLSDESC_ADD_LO12_NC",
"BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE",
"BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21",
"BFD_RELOC_AARCH64_TLSDESC_CALL",
"BFD_RELOC_AARCH64_TLSDESC_LD64_LO12_NC",
"BFD_RELOC_AARCH64_TLSDESC_LD64_PREL19",
"BFD_RELOC_AARCH64_TLSDESC_LDR",
"BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC",
"BFD_RELOC_AARCH64_TLSDESC_OFF_G1",
"BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC",
"BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21",
"BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21",
"BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19",
"BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC",
"BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC",
"BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1",
"BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12",
"BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12",
"BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC",
"BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0",
"BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC",
"BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1",
"BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC",
"BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2",
"BFD_RELOC_AARCH64_TLS_DTPMOD64",
"BFD_RELOC_AARCH64_TLS_DTPREL64",
"BFD_RELOC_AARCH64_TLS_TPREL64",
"BFD_RELOC_AARCH64_TSTBR14",
"BFD_RELOC_TILEPRO_COPY",
"BFD_RELOC_TILEPRO_GLOB_DAT",
"BFD_RELOC_TILEPRO_JMP_SLOT",

274
bfd/reloc.c
View File

@ -5883,6 +5883,278 @@ ENUMDOC
This is used to tell the dynamic linker to copy the value out of
the dynamic object into the runtime process image.
ENUM
BFD_RELOC_AARCH64_ADD_LO12
ENUMDOC
AArch64 ADD immediate instruction, holding bits 0 to 11 of the address.
Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL.
ENUM
BFD_RELOC_AARCH64_ADR_GOT_PAGE
ENUMDOC
Get to the page base of the global offset table entry for a symbol as
part of an ADRP instruction using a 21 bit PC relative value.Used in
conjunction with BFD_RELOC_AARCH64_LD64_GOT_LO12_NC.
ENUM
BFD_RELOC_AARCH64_ADR_HI21_PCREL
ENUMDOC
AArch64 ADRP instruction, with bits 12 to 32 of a pc-relative page
offset, giving a 4KB aligned page base address.
ENUM
BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL
ENUMDOC
AArch64 ADRP instruction, with bits 12 to 32 of a pc-relative page
offset, giving a 4KB aligned page base address, but with no overflow
checking.
ENUM
BFD_RELOC_AARCH64_ADR_LO21_PCREL
ENUMDOC
AArch64 ADR instruction, holding a simple 21 bit pc-relative byte offset.
ENUM
BFD_RELOC_AARCH64_BRANCH19
ENUMDOC
AArch64 19 bit pc-relative conditional branch and compare & branch.
The lowest two bits must be zero and are not stored in the instruction,
giving a 21 bit signed byte offset.
ENUM
BFD_RELOC_AARCH64_CALL26
ENUMDOC
AArch64 26 bit pc-relative unconditional branch and link.
The lowest two bits must be zero and are not stored in the instruction,
giving a 28 bit signed byte offset.
ENUM
BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
ENUMDOC
AArch64 pseudo relocation code to be used internally by the AArch64
assembler and not (currently) written to any object files.
ENUM
BFD_RELOC_AARCH64_JUMP26
ENUMDOC
AArch64 26 bit pc-relative unconditional branch.
The lowest two bits must be zero and are not stored in the instruction,
giving a 28 bit signed byte offset.
ENUM
BFD_RELOC_AARCH64_LD_LO19_PCREL
ENUMDOC
AArch64 Load Literal instruction, holding a 19 bit pc-relative word
offset. The lowest two bits must be zero and are not stored in the
instruction, giving a 21 bit signed byte offset.
ENUM
BFD_RELOC_AARCH64_LD64_GOT_LO12_NC
ENUMDOC
Unsigned 12 bit byte offset for 64 bit load/store from the page of
the GOT entry for this symbol. Used in conjunction with
BFD_RELOC_AARCH64_ADR_GOTPAGE.
ENUM
BFD_RELOC_AARCH64_LDST_LO12
ENUMDOC
AArch64 unspecified load/store instruction, holding bits 0 to 11 of the
address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL.
ENUM
BFD_RELOC_AARCH64_LDST8_LO12
ENUMDOC
AArch64 8-bit load/store instruction, holding bits 0 to 11 of the
address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL.
ENUM
BFD_RELOC_AARCH64_LDST16_LO12
ENUMDOC
AArch64 16-bit load/store instruction, holding bits 0 to 11 of the
address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL.
ENUM
BFD_RELOC_AARCH64_LDST32_LO12
ENUMDOC
AArch64 32-bit load/store instruction, holding bits 0 to 11 of the
address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL.
ENUM
BFD_RELOC_AARCH64_LDST64_LO12
ENUMDOC
AArch64 64-bit load/store instruction, holding bits 0 to 11 of the
address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL.
ENUM
BFD_RELOC_AARCH64_LDST128_LO12
ENUMDOC
AArch64 128-bit load/store instruction, holding bits 0 to 11 of the
address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL.
ENUM
BFD_RELOC_AARCH64_MOVW_G0
ENUMDOC
AArch64 MOV[NZK] instruction with most significant bits 0 to 15
of an unsigned address/value.
ENUM
BFD_RELOC_AARCH64_MOVW_G0_S
ENUMDOC
AArch64 MOV[NZ] instruction with most significant bits 0 to 15
of a signed value. Changes instruction to MOVZ or MOVN depending on the
value's sign.
ENUM
BFD_RELOC_AARCH64_MOVW_G0_NC
ENUMDOC
AArch64 MOV[NZK] instruction with less significant bits 0 to 15 of
an address/value. No overflow checking.
ENUM
BFD_RELOC_AARCH64_MOVW_G1
ENUMDOC
AArch64 MOV[NZK] instruction with most significant bits 16 to 31
of an unsigned address/value.
ENUM
BFD_RELOC_AARCH64_MOVW_G1_NC
ENUMDOC
AArch64 MOV[NZK] instruction with less significant bits 16 to 31
of an address/value. No overflow checking.
ENUM
BFD_RELOC_AARCH64_MOVW_G1_S
ENUMDOC
AArch64 MOV[NZ] instruction with most significant bits 16 to 31
of a signed value. Changes instruction to MOVZ or MOVN depending on the
value's sign.
ENUM
BFD_RELOC_AARCH64_MOVW_G2
ENUMDOC
AArch64 MOV[NZK] instruction with most significant bits 32 to 47
of an unsigned address/value.
ENUM
BFD_RELOC_AARCH64_MOVW_G2_NC
ENUMDOC
AArch64 MOV[NZK] instruction with less significant bits 32 to 47
of an address/value. No overflow checking.
ENUM
BFD_RELOC_AARCH64_MOVW_G2_S
ENUMDOC
AArch64 MOV[NZ] instruction with most significant bits 32 to 47
of a signed value. Changes instruction to MOVZ or MOVN depending on the
value's sign.
ENUM
BFD_RELOC_AARCH64_MOVW_G3
ENUMDOC
AArch64 MOV[NZK] instruction with most signficant bits 48 to 64
of a signed or unsigned address/value.
ENUM
BFD_RELOC_AARCH64_TLSDESC
ENUMDOC
AArch64 TLS relocation.
ENUM
BFD_RELOC_AARCH64_TLSDESC_ADD
ENUMDOC
AArch64 TLS DESC relocation.
ENUM
BFD_RELOC_AARCH64_TLSDESC_ADD_LO12_NC
ENUMDOC
AArch64 TLS DESC relocation.
ENUM
BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE
ENUMDOC
AArch64 TLS DESC relocation.
ENUM
BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21
ENUMDOC
AArch64 TLS DESC relocation.
ENUM
BFD_RELOC_AARCH64_TLSDESC_CALL
ENUMDOC
AArch64 TLS DESC relocation.
ENUM
BFD_RELOC_AARCH64_TLSDESC_LD64_LO12_NC
ENUMDOC
AArch64 TLS DESC relocation.
ENUM
BFD_RELOC_AARCH64_TLSDESC_LD64_PREL19
ENUMDOC
AArch64 TLS DESC relocation.
ENUM
BFD_RELOC_AARCH64_TLSDESC_LDR
ENUMDOC
AArch64 TLS DESC relocation.
ENUM
BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC
ENUMDOC
AArch64 TLS DESC relocation.
ENUM
BFD_RELOC_AARCH64_TLSDESC_OFF_G1
ENUMDOC
AArch64 TLS DESC relocation.
ENUM
BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC
ENUMDOC
Unsigned 12 bit byte offset to global offset table entry for a symbols
tls_index structure. Used in conjunction with
BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21.
ENUM
BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21
ENUMDOC
Get to the page base of the global offset table entry for a symbols
tls_index structure as part of an adrp instruction using a 21 bit PC
relative value. Used in conjunction with
BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC.
ENUM
BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21
ENUMDOC
AArch64 TLS INITIAL EXEC relocation.
ENUM
BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19
ENUMDOC
AArch64 TLS INITIAL EXEC relocation.
ENUM
BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC
ENUMDOC
AArch64 TLS INITIAL EXEC relocation.
ENUM
BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC
ENUMDOC
AArch64 TLS INITIAL EXEC relocation.
ENUM
BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1
ENUMDOC
AArch64 TLS INITIAL EXEC relocation.
ENUM
BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
ENUMDOC
AArch64 TLS LOCAL EXEC relocation.
ENUM
BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
ENUMDOC
AArch64 TLS LOCAL EXEC relocation.
ENUM
BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC
ENUMDOC
AArch64 TLS LOCAL EXEC relocation.
ENUM
BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
ENUMDOC
AArch64 TLS LOCAL EXEC relocation.
ENUM
BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
ENUMDOC
AArch64 TLS LOCAL EXEC relocation.
ENUM
BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
ENUMDOC
AArch64 TLS LOCAL EXEC relocation.
ENUM
BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
ENUMDOC
AArch64 TLS LOCAL EXEC relocation.
ENUM
BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
ENUMDOC
AArch64 TLS LOCAL EXEC relocation.
ENUM
BFD_RELOC_AARCH64_TLS_DTPMOD64
ENUMDOC
AArch64 TLS relocation.
ENUM
BFD_RELOC_AARCH64_TLS_DTPREL64
ENUMDOC
AArch64 TLS relocation.
ENUM
BFD_RELOC_AARCH64_TLS_TPREL64
ENUMDOC
AArch64 TLS relocation.
ENUM
BFD_RELOC_AARCH64_TSTBR14
ENUMDOC
AArch64 14 bit pc-relative test bit and branch.
The lowest two bits must be zero and are not stored in the instruction,
giving a 16 bit signed byte offset.
ENUM
BFD_RELOC_TILEPRO_COPY
ENUMX
@ -6043,7 +6315,6 @@ ENUMX
BFD_RELOC_TILEPRO_IMM16_X1_TLS_LE_HA
ENUMDOC
Tilera TILEPro Relocations.
ENUM
BFD_RELOC_TILEGX_HW0
ENUMX
@ -6236,7 +6507,6 @@ ENUMX
BFD_RELOC_TILEGX_IMM8_Y1_TLS_ADD
ENUMDOC
Tilera TILE-Gx Relocations.
ENUM
BFD_RELOC_EPIPHANY_SIMM8
ENUMDOC

4
bfd/targets.c
View File

@ -730,6 +730,7 @@ extern const bfd_target bfd_elf64_alpha_freebsd_vec;
extern const bfd_target bfd_elf64_alpha_vec;
extern const bfd_target bfd_elf64_big_generic_vec;
extern const bfd_target bfd_elf64_bigmips_vec;
extern const bfd_target bfd_elf64_bigaarch64_vec;
extern const bfd_target bfd_elf64_hppa_linux_vec;
extern const bfd_target bfd_elf64_hppa_vec;
extern const bfd_target bfd_elf64_ia64_big_vec;
@ -738,6 +739,7 @@ extern const bfd_target bfd_elf64_ia64_little_vec;
extern const bfd_target bfd_elf64_ia64_vms_vec;
extern const bfd_target bfd_elf64_little_generic_vec;
extern const bfd_target bfd_elf64_littlemips_vec;
extern const bfd_target bfd_elf64_littleaarch64_vec;
extern const bfd_target bfd_elf64_mmix_vec;
extern const bfd_target bfd_elf64_powerpc_vec;
extern const bfd_target bfd_elf64_powerpcle_vec;
@ -1105,6 +1107,7 @@ static const bfd_target * const _bfd_target_vector[] =
&bfd_elf64_alpha_vec,
&bfd_elf64_big_generic_vec,
&bfd_elf64_bigmips_vec,
&bfd_elf64_bigaarch64_vec,
&bfd_elf64_hppa_linux_vec,
&bfd_elf64_hppa_vec,
&bfd_elf64_ia64_big_vec,
@ -1113,6 +1116,7 @@ static const bfd_target * const _bfd_target_vector[] =
&bfd_elf64_ia64_vms_vec,
&bfd_elf64_little_generic_vec,
&bfd_elf64_littlemips_vec,
&bfd_elf64_littleaarch64_vec,
&bfd_elf64_mmix_vec,
&bfd_elf64_powerpc_vec,
&bfd_elf64_powerpcle_vec,

23
binutils/ChangeLog
View File

@ -1,3 +1,26 @@
2012-08-13 Ian Bolton <ian.bolton@arm.com>
Laurent Desnogues <laurent.desnogues@arm.com>
Jim MacArthur <jim.macarthur@arm.com>
Marcus Shawcroft <marcus.shawcroft@arm.com>
Nigel Stephens <nigel.stephens@arm.com>
Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
Richard Earnshaw <rearnsha@arm.com>
Sofiane Naci <sofiane.naci@arm.com>
Tejas Belagod <tejas.belagod@arm.com>
Yufeng Zhang <yufeng.zhang@arm.com>
* readelf.c (guess_is_rela): Handle EM_AARCH64.
(get_machine_name): Likewise.
(get_aarch64_segment_type): New function.
(get_segment_type): Handle EM_AARCH64 by calling the new function.
(get_aarch64_section_type_name): New function.
(get_section_type_name): Handle EM_AARCH64 by calling the new function.
(is_32bit_abs_reloc): Handle EM_AARCH64.
(is_32bit_pcrel_reloc): Likewise.
(is_64bit_abs_reloc): Likewise.
(is_64bit_pcrel_reloc): Likewise.
(is_none_reloc): Likewise.
2012-08-09 Nick Clifton <nickc@redhat.com>
* po/vi.po: Updated Vietnamese translation.

1
binutils/MAINTAINERS
View File

@ -57,6 +57,7 @@ maintainer. The first maintainer is free to devolve that
responsibility among the other maintainers.
ALPHA Richard Henderson <rth@redhat.com>
AARCH64 Richard Earnshaw <rearnsha@arm.com>
ARM Nick Clifton <nickc@redhat.com>
ARM Richard Earnshaw <rearnsha@arm.com>
ARM Paul Brook <paul@codesourcery.com>

2
binutils/doc/Makefile.in
View File

@ -39,7 +39,7 @@ DIST_COMMON = $(srcdir)/Makefile.in $(srcdir)/Makefile.am
ACLOCAL_M4 = $(top_srcdir)/aclocal.m4
am__aclocal_m4_deps = $(top_srcdir)/../bfd/acinclude.m4 \
$(top_srcdir)/../config/zlib.m4 \
$(top_srcdir)/../bfd/warning.m4 \
$(top_srcdir)/../bfd/warning.m4 $(top_srcdir)/../config/acx.m4 \
$(top_srcdir)/../config/depstand.m4 \
$(top_srcdir)/../config/gettext-sister.m4 \
$(top_srcdir)/../config/iconv.m4 \

50
binutils/readelf.c
View File

@ -91,6 +91,7 @@
#define RELOC_MACROS_GEN_FUNC
#include "elf/aarch64.h"
#include "elf/alpha.h"
#include "elf/arc.h"
#include "elf/arm.h"
@ -551,6 +552,7 @@ guess_is_rela (unsigned int e_machine)
/* Targets that use RELA relocations. */
case EM_68K:
case EM_860:
case EM_AARCH64:
case EM_ADAPTEVA_EPIPHANY:
case EM_ALPHA:
case EM_ALTERA_NIOS2:
@ -983,6 +985,10 @@ dump_relocations (FILE * file,
rtype = NULL;
break;
case EM_AARCH64:
rtype = elf_aarch64_reloc_type (type);
break;
case EM_M32R:
case EM_CYGNUS_M32R:
rtype = elf_m32r_reloc_type (type);
@ -1830,6 +1836,7 @@ get_machine_name (unsigned e_machine)
switch (e_machine)
{
case EM_NONE: return _("None");
case EM_AARCH64: return "AArch64";
case EM_M32: return "WE32100";
case EM_SPARC: return "Sparc";
case EM_SPU: return "SPU";
@ -2694,6 +2701,20 @@ get_osabi_name (unsigned int osabi)
}
}
static const char *
get_aarch64_segment_type (unsigned long type)
{
switch (type)
{
case PT_AARCH64_ARCHEXT:
return "AARCH64_ARCHEXT";
default:
break;
}
return NULL;
}
static const char *
get_arm_segment_type (unsigned long type)
{
@ -2816,6 +2837,9 @@ get_segment_type (unsigned long p_type)
switch (elf_header.e_machine)
{
case EM_AARCH64:
result = get_aarch64_segment_type (p_type);
break;
case EM_ARM:
result = get_arm_segment_type (p_type);
break;
@ -2976,6 +3000,19 @@ get_x86_64_section_type_name (unsigned int sh_type)
return NULL;
}
static const char *
get_aarch64_section_type_name (unsigned int sh_type)
{
switch (sh_type)
{
case SHT_AARCH64_ATTRIBUTES:
return "AARCH64_ATTRIBUTES";
default:
break;
}
return NULL;
}
static const char *
get_arm_section_type_name (unsigned int sh_type)
{
@ -3075,6 +3112,9 @@ get_section_type_name (unsigned int sh_type)
case EM_K1OM:
result = get_x86_64_section_type_name (sh_type);
break;
case EM_AARCH64:
result = get_aarch64_section_type_name (sh_type);
break;
case EM_ARM:
result = get_arm_section_type_name (sh_type);
break;
@ -9770,6 +9810,8 @@ is_32bit_abs_reloc (unsigned int reloc_type)
return reloc_type == 1; /* R_860_32. */
case EM_960:
return reloc_type == 2; /* R_960_32. */
case EM_AARCH64:
return reloc_type == 258; /* R_AARCH64_ABS32 */
case EM_ALPHA:
return reloc_type == 1; /* R_ALPHA_REFLONG. */
case EM_ARC:
@ -9924,6 +9966,8 @@ is_32bit_pcrel_reloc (unsigned int reloc_type)
return reloc_type == 2; /* R_386_PC32. */
case EM_68K:
return reloc_type == 4; /* R_68K_PC32. */
case EM_AARCH64:
return reloc_type == 261; /* R_AARCH64_PREL32 */
case EM_ADAPTEVA_EPIPHANY:
return reloc_type == 6;
case EM_ALPHA:
@ -9978,6 +10022,8 @@ is_64bit_abs_reloc (unsigned int reloc_type)
{
switch (elf_header.e_machine)
{
case EM_AARCH64:
return reloc_type == 257; /* R_AARCH64_ABS64. */
case EM_ALPHA:
return reloc_type == 2; /* R_ALPHA_REFQUAD. */
case EM_IA_64:
@ -10014,6 +10060,8 @@ is_64bit_pcrel_reloc (unsigned int reloc_type)
{
switch (elf_header.e_machine)
{
case EM_AARCH64:
return reloc_type == 260; /* R_AARCH64_PREL64. */
case EM_ALPHA:
return reloc_type == 11; /* R_ALPHA_SREL64. */
case EM_IA_64:
@ -10143,6 +10191,8 @@ is_none_reloc (unsigned int reloc_type)
case EM_XC16X:
case EM_C166: /* R_XC16X_NONE. */
return reloc_type == 0;
case EM_AARCH64:
return reloc_type == 0 || reloc_type == 256;
case EM_XTENSA_OLD:
case EM_XTENSA:
return (reloc_type == 0 /* R_XTENSA_NONE. */

13
binutils/testsuite/ChangeLog
View File

@ -1,3 +1,16 @@
2012-08-13 Ian Bolton <ian.bolton@arm.com>
Laurent Desnogues <laurent.desnogues@arm.com>
Jim MacArthur <jim.macarthur@arm.com>
Marcus Shawcroft <marcus.shawcroft@arm.com>
Nigel Stephens <nigel.stephens@arm.com>
Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
Richard Earnshaw <rearnsha@arm.com>
Sofiane Naci <sofiane.naci@arm.com>
Tejas Belagod <tejas.belagod@arm.com>
Yufeng Zhang <yufeng.zhang@arm.com>
* objdump.exp: Add AArch64.
2012-08-02 H.J. Lu <hongjiu.lu@intel.com>
PR binutils/14420

2
binutils/testsuite/binutils-all/objdump.exp
View File

@ -36,7 +36,7 @@ send_user "Version [binutil_version $OBJDUMP]"
set got [binutils_run $OBJDUMP "$OBJDUMPFLAGS -i"]
set cpus_expected [list]
lappend cpus_expected alpha arc arm cris
lappend cpus_expected aarch64 alpha arc arm cris
lappend cpus_expected d10v d30v fr30 fr500 fr550 h8 hppa i386 i860 i960 ip2022
lappend cpus_expected m16c m32c m32r m68hc11 m68hc12 m68k m88k MCore MicroBlaze
lappend cpus_expected mips mn10200 mn10300 ms1 msp ns32k pj powerpc pyramid

24
gas/ChangeLog
View File

@ -1,3 +1,27 @@
2012-08-13 Ian Bolton <ian.bolton@arm.com>
Laurent Desnogues <laurent.desnogues@arm.com>
Jim MacArthur <jim.macarthur@arm.com>
Marcus Shawcroft <marcus.shawcroft@arm.com>
Nigel Stephens <nigel.stephens@arm.com>
Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
Richard Earnshaw <rearnsha@arm.com>
Sofiane Naci <sofiane.naci@arm.com>
Tejas Belagod <tejas.belagod@arm.com>
Yufeng Zhang <yufeng.zhang@arm.com>
* Makefile.am: Add AArch64.
* Makefile.in: Regenerate.
* config/tc-aarch64.c: New file.
* config/tc-aarch64.h: New file.
* configure.tgt: Add AArch64.
* doc/Makefile.am: Add AArch64.
* doc/Makefile.in: Regenerate.
* doc/all.texi: Add AArch64.
* doc/as.texinfo: Add AArch64.
* doc/c-aarch64.texi: New file.
* po/POTFILES.in: Regenerate.
* NEWS: Mention the new support.
2012-08-13 Maciej W. Rozycki <macro@codesourcery.com>
* config/tc-mips.c (NO_ISA_COP, COP_INSN): Remove macros.

2
gas/Makefile.am
View File

@ -107,6 +107,7 @@ HFILES = \
# CPU files in config.
TARGET_CPU_CFILES = \
config/tc-aarch64.c \
config/tc-alpha.c \
config/tc-arc.c \
config/tc-arm.c \
@ -176,6 +177,7 @@ TARGET_CPU_CFILES = \
config/xtensa-relax.c
TARGET_CPU_HFILES = \
config/tc-aarch64.h \
config/tc-alpha.h \
config/tc-arc.h \
config/tc-arm.h \

17
gas/Makefile.in
View File

@ -375,6 +375,7 @@ HFILES = \
# CPU files in config.
TARGET_CPU_CFILES = \
config/tc-aarch64.c \
config/tc-alpha.c \
config/tc-arc.c \
config/tc-arm.c \
@ -444,6 +445,7 @@ TARGET_CPU_CFILES = \
config/xtensa-relax.c
TARGET_CPU_HFILES = \
config/tc-aarch64.h \
config/tc-alpha.h \
config/tc-arc.h \
config/tc-arm.h \
@ -793,6 +795,7 @@ distclean-compile:
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/stabs.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/subsegs.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/symbols.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tc-aarch64.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tc-alpha.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tc-arc.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tc-arm.Po@am__quote@
@ -884,6 +887,20 @@ distclean-compile:
@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
@am__fastdepCC_FALSE@ $(LTCOMPILE) -c -o $@ $<
tc-aarch64.o: config/tc-aarch64.c
@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -MT tc-aarch64.o -MD -MP -MF $(DEPDIR)/tc-aarch64.Tpo -c -o tc-aarch64.o `test -f 'config/tc-aarch64.c' || echo '$(srcdir)/'`config/tc-aarch64.c
@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/tc-aarch64.Tpo $(DEPDIR)/tc-aarch64.Po
@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='config/tc-aarch64.c' object='tc-aarch64.o' libtool=no @AMDEPBACKSLASH@
@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -c -o tc-aarch64.o `test -f 'config/tc-aarch64.c' || echo '$(srcdir)/'`config/tc-aarch64.c
tc-aarch64.obj: config/tc-aarch64.c
@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -MT tc-aarch64.obj -MD -MP -MF $(DEPDIR)/tc-aarch64.Tpo -c -o tc-aarch64.obj `if test -f 'config/tc-aarch64.c'; then $(CYGPATH_W) 'config/tc-aarch64.c'; else $(CYGPATH_W) '$(srcdir)/config/tc-aarch64.c'; fi`
@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/tc-aarch64.Tpo $(DEPDIR)/tc-aarch64.Po
@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='config/tc-aarch64.c' object='tc-aarch64.obj' libtool=no @AMDEPBACKSLASH@
@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -c -o tc-aarch64.obj `if test -f 'config/tc-aarch64.c'; then $(CYGPATH_W) 'config/tc-aarch64.c'; else $(CYGPATH_W) '$(srcdir)/config/tc-aarch64.c'; fi`
tc-alpha.o: config/tc-alpha.c
@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -MT tc-alpha.o -MD -MP -MF $(DEPDIR)/tc-alpha.Tpo -c -o tc-alpha.o `test -f 'config/tc-alpha.c' || echo '$(srcdir)/'`config/tc-alpha.c
@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/tc-alpha.Tpo $(DEPDIR)/tc-alpha.Po

2
gas/NEWS
View File

@ -1,5 +1,7 @@
-*- text -*-
* Add support for the 64-bit ARM architecture: AArch64.
Changes in 2.23:
* Add support for S12X processor.

7349
gas/config/tc-aarch64.c Normal file
View File

File diff suppressed because it is too large Load Diff

231
gas/config/tc-aarch64.h Normal file
View File

@ -0,0 +1,231 @@
/* tc-aarch64.h -- Header file for tc-aarch64.c.
Copyright 2009, 2010, 2011, 2012 Free Software Foundation, Inc.
Contributed by ARM Ltd.
This file is part of GAS.
GAS is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the license, or
(at your option) any later version.
GAS is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; see the file COPYING3. If not,
see <http://www.gnu.org/licenses/>. */
#ifndef TC_AARCH64
#define TC_AARCH64 1
#include "opcode/aarch64.h"
#ifndef TARGET_BYTES_BIG_ENDIAN
#define TARGET_BYTES_BIG_ENDIAN 0
#endif
#define WORKING_DOT_WORD
#define TARGET_ARCH bfd_arch_aarch64
#define DIFF_EXPR_OK
/* Permit // comments. */
#define DOUBLESLASH_LINE_COMMENTS
#ifdef LITTLE_ENDIAN
#undef LITTLE_ENDIAN
#endif
#ifdef BIG_ENDIAN
#undef BIG_ENDIAN
#endif
#define LITTLE_ENDIAN 1234
#define BIG_ENDIAN 4321
#define SWAP_32(n) \
((((n) & 0xff) << 24) | (((n) & 0xff00) << 8) | (((n) >> 8) & 0xff00) \
| (((n) >> 24) & 0xff))
struct fix;
struct aarch64_fix
{
struct aarch64_inst *inst;
enum aarch64_opnd opnd;
};
#if defined OBJ_ELF
# define AARCH64_BI_ENDIAN
# define TARGET_FORMAT elf64_aarch64_target_format ()
#endif
#define TC_FORCE_RELOCATION(FIX) aarch64_force_relocation (FIX)
/* Currently there is no machine specific frags generated. */
#define md_convert_frag(b,s,f) as_fatal ("aarch64 convert_frag called\n")
#define md_cleanup() aarch64_cleanup ()
#define md_start_line_hook() aarch64_start_line_hook ()
#define tc_frob_label(S) aarch64_frob_label (S)
/* We also need to mark assembler created symbols: */
#define tc_frob_fake_label(S) aarch64_frob_label (S)
#define TC_FIX_TYPE struct aarch64_fix
#define TC_INIT_FIX_DATA(FIX) { (FIX)->tc_fix_data.inst = NULL; \
(FIX)->tc_fix_data.opnd = AARCH64_OPND_NIL; }
#define TC_SYMFIELD_TYPE unsigned int
#define AARCH64_GET_FLAG(s) (*symbol_get_tc (s))
void aarch64_copy_symbol_attributes (symbolS *, symbolS *);
#ifndef TC_COPY_SYMBOL_ATTRIBUTES
#define TC_COPY_SYMBOL_ATTRIBUTES(DEST, SRC) \
(aarch64_copy_symbol_attributes (DEST, SRC))
#endif
#define TC_START_LABEL(C,S,STR) ((C) == ':' \
|| ((C) == '/' && aarch64_data_in_code ()))
#define tc_canonicalize_symbol_name(str) aarch64_canonicalize_symbol_name (str);
#define obj_adjust_symtab() aarch64_adjust_symtab ()
#define LISTING_HEADER "AARCH64 GAS "
#define LOCAL_LABEL(name) (name[0] == '.' && name[1] == 'L')
#define LOCAL_LABELS_FB 1
/* This expression evaluates to true if the relocation is for a local
object for which we still want to do the relocation at runtime.
False if we are willing to perform this relocation while building
the .o file. GOTOFF does not need to be checked here because it is
not pcrel. I am not sure if some of the others are ever used with
pcrel, but it is easier to be safe than sorry. */
#define TC_FORCE_RELOCATION_LOCAL(FIX) \
(!(FIX)->fx_pcrel \
|| (FIX)->fx_r_type == BFD_RELOC_64 \
|| (FIX)->fx_r_type == BFD_RELOC_32 \
|| TC_FORCE_RELOCATION (FIX))
#define TC_CONS_FIX_NEW cons_fix_new_aarch64
/* Max code alignment is 32 bytes */
#define MAX_MEM_FOR_RS_ALIGN_CODE 31
/* For frags in code sections we need to record whether they contain
code or data. */
struct aarch64_frag_type
{
int recorded;
#ifdef OBJ_ELF
/* If there is a mapping symbol at offset 0 in this frag,
it will be saved in FIRST_MAP. If there are any mapping
symbols in this frag, the last one will be saved in
LAST_MAP. */
symbolS *first_map, *last_map;
#endif
};
#define TC_FRAG_TYPE struct aarch64_frag_type
/* NOTE: max_chars is a local variable from frag_var / frag_variant. */
#define TC_FRAG_INIT(fragp) aarch64_init_frag (fragp, max_chars)
#define HANDLE_ALIGN(fragp) aarch64_handle_align (fragp)
#define md_do_align(N, FILL, LEN, MAX, LABEL) \
if (FILL == NULL && (N) != 0 && ! need_pass_2 && subseg_text_p (now_seg)) \
{ \
aarch64_frag_align_code (N, MAX); \
goto LABEL; \
}
#define DWARF2_LINE_MIN_INSN_LENGTH 2
/* The lr register is r30. */
#define DWARF2_DEFAULT_RETURN_COLUMN 30
/* Registers are generally saved at negative offsets to the CFA. */
#define DWARF2_CIE_DATA_ALIGNMENT (-4)
#ifdef OBJ_ELF
# define obj_frob_symbol(sym, punt) aarch64elf_frob_symbol ((sym), & (punt))
# define GLOBAL_OFFSET_TABLE_NAME "_GLOBAL_OFFSET_TABLE_"
# define TC_SEGMENT_INFO_TYPE struct aarch64_segment_info_type
/* This is not really an alignment operation, but it's something we
need to do at the same time: whenever we are figuring out the
alignment for data, we should check whether a $d symbol is
necessary. */
# define md_cons_align(nbytes) mapping_state (MAP_DATA)
enum mstate
{
MAP_UNDEFINED = 0, /* Must be zero, for seginfo in new sections. */
MAP_DATA,
MAP_INSN,
};
void mapping_state (enum mstate);
struct aarch64_segment_info_type
{
enum mstate mapstate;
unsigned int marked_pr_dependency;
};
/* We want .cfi_* pseudo-ops for generating unwind info. */
#define TARGET_USE_CFIPOP 1
/* CFI hooks. */
#define tc_regname_to_dw2regnum tc_aarch64_regname_to_dw2regnum
#define tc_cfi_frame_initial_instructions tc_aarch64_frame_initial_instructions
#else /* Not OBJ_ELF. */
#define GLOBAL_OFFSET_TABLE_NAME "__GLOBAL_OFFSET_TABLE_"
#endif
#if defined OBJ_ELF || defined OBJ_COFF
# define EXTERN_FORCE_RELOC 1
# define tc_fix_adjustable(FIX) 1
/* Values passed to md_apply_fix don't include the symbol value. */
# define MD_APPLY_SYM_VALUE(FIX) 0
#endif
#define MD_PCREL_FROM_SECTION(F,S) md_pcrel_from_section(F,S)
extern long md_pcrel_from_section (struct fix *, segT);
extern void aarch64_frag_align_code (int, int);
extern const char * elf64_aarch64_target_format (void);
extern int aarch64_force_relocation (struct fix *);
extern void aarch64_cleanup (void);
extern void aarch64_start_line_hook (void);
extern void aarch64_frob_label (symbolS *);
extern int aarch64_data_in_code (void);
extern char * aarch64_canonicalize_symbol_name (char *);
extern void aarch64_adjust_symtab (void);
extern void aarch64elf_frob_symbol (symbolS *, int *);
extern void cons_fix_new_aarch64 (fragS *, int, int, expressionS *);
extern void aarch64_init_frag (struct frag *, int);
extern void aarch64_handle_align (struct frag *);
extern int tc_aarch64_regname_to_dw2regnum (char *regname);
extern void tc_aarch64_frame_initial_instructions (void);
#ifdef TE_PE
#define O_secrel O_md1
#define TC_DWARF2_EMIT_OFFSET tc_pe_dwarf2_emit_offset
void tc_pe_dwarf2_emit_offset (symbolS *, unsigned int);
#endif /* TE_PE */
#endif /* TC_AARCH64 */

7
gas/configure.tgt
View File

@ -29,6 +29,8 @@ eval `echo $targ | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/cpu=\1 vendor=\2 os=\3/'`
# endian and arch.
# Note: This table is alpha-sorted, please try to keep it that way.
case ${cpu} in
aarch64) cpu_type=aarch64 endian=little ;;
aarch64_be) cpu_type=aarch64 endian=big ;;
alpha*) cpu_type=alpha ;;
am33_2.0) cpu_type=mn10300 endian=little ;;
arm*be|arm*b) cpu_type=arm endian=big ;;
@ -96,6 +98,9 @@ esac
generic_target=${cpu_type}-$vendor-$os
# Note: This table is alpha-sorted, please try to keep it that way.
case ${generic_target} in
aarch64*-*-elf) fmt=elf;;
aarch64*-*-linux*) fmt=elf em=linux ;;
alpha-*-*vms*) fmt=evax ;;
alpha-*-osf*) fmt=ecoff ;;
alpha-*-linuxecoff*) fmt=ecoff ;;
@ -446,7 +451,7 @@ case ${generic_target} in
esac
case ${cpu_type} in
alpha | arm | i386 | ia64 | microblaze | mips | ns32k | pdp11 | ppc | sparc | z80 | z8k)
aarch64 | alpha | arm | i386 | ia64 | microblaze | mips | ns32k | pdp11 | ppc | sparc | z80 | z8k)
bfd_gas=yes
;;
esac

1
gas/doc/Makefile.am
View File

@ -29,6 +29,7 @@ asconfig.texi: $(CONFIG).texi
chmod u+w ./asconfig.texi
CPU_DOCS = \
c-aarch64.texi \
c-alpha.texi \
c-arc.texi \
c-arm.texi \

14
gas/doc/Makefile.in
View File

@ -38,7 +38,9 @@ subdir = doc
DIST_COMMON = $(srcdir)/Makefile.in $(srcdir)/Makefile.am \
$(as_TEXINFOS)
ACLOCAL_M4 = $(top_srcdir)/aclocal.m4
am__aclocal_m4_deps = $(top_srcdir)/../config/acx.m4 \
am__aclocal_m4_deps = $(top_srcdir)/../bfd/acinclude.m4 \
$(top_srcdir)/../config/zlib.m4 \
$(top_srcdir)/../bfd/warning.m4 $(top_srcdir)/../config/acx.m4 \
$(top_srcdir)/../config/depstand.m4 \
$(top_srcdir)/../config/gettext-sister.m4 \
$(top_srcdir)/../config/largefile.m4 \
@ -49,9 +51,9 @@ am__aclocal_m4_deps = $(top_srcdir)/../config/acx.m4 \
$(top_srcdir)/../config/plugins.m4 \
$(top_srcdir)/../config/po.m4 \
$(top_srcdir)/../config/progtest.m4 \
$(top_srcdir)/../bfd/acinclude.m4 \
$(top_srcdir)/../config/zlib.m4 \
$(top_srcdir)/../bfd/warning.m4 $(top_srcdir)/acinclude.m4 \
$(top_srcdir)/../libtool.m4 $(top_srcdir)/../ltoptions.m4 \
$(top_srcdir)/../ltsugar.m4 $(top_srcdir)/../ltversion.m4 \
$(top_srcdir)/../lt~obsolete.m4 $(top_srcdir)/acinclude.m4 \
$(top_srcdir)/configure.in
am__configure_deps = $(am__aclocal_m4_deps) $(CONFIGURE_DEPENDENCIES) \
$(ACLOCAL_M4)
@ -118,7 +120,6 @@ CYGPATH_W = @CYGPATH_W@
DATADIRNAME = @DATADIRNAME@
DEFS = @DEFS@
DEPDIR = @DEPDIR@
DLLTOOL = @DLLTOOL@
DSYMUTIL = @DSYMUTIL@
DUMPBIN = @DUMPBIN@
ECHO_C = @ECHO_C@
@ -154,7 +155,6 @@ LN_S = @LN_S@
LTLIBOBJS = @LTLIBOBJS@
MAINT = @MAINT@
MAKEINFO = @MAKEINFO@
MANIFEST_TOOL = @MANIFEST_TOOL@
MKDIR_P = @MKDIR_P@
MKINSTALLDIRS = @MKINSTALLDIRS@
MSGFMT = @MSGFMT@
@ -191,7 +191,6 @@ abs_builddir = @abs_builddir@
abs_srcdir = @abs_srcdir@
abs_top_builddir = @abs_top_builddir@
abs_top_srcdir = @abs_top_srcdir@
ac_ct_AR = @ac_ct_AR@
ac_ct_CC = @ac_ct_CC@
ac_ct_DUMPBIN = @ac_ct_DUMPBIN@
am__include = @am__include@
@ -271,6 +270,7 @@ TEXI2DVI = texi2dvi -I "$(srcdir)" -I "$(top_srcdir)/../libiberty" \
-I "$(top_srcdir)/../bfd/doc" -I ../../bfd/doc
CPU_DOCS = \
c-aarch64.texi \
c-alpha.texi \
c-arc.texi \
c-arm.texi \

1
gas/doc/all.texi
View File

@ -26,6 +26,7 @@
@c CPUs of interest
@c ================
@set AARCH64
@set ALPHA
@set ARC
@set ARM

31
gas/doc/as.texinfo
View File

@ -249,6 +249,11 @@ gcc(1), ld(1), and the Info entries for @file{binutils} and @file{ld}.
@c
@c Target dependent options are listed below. Keep the list sorted.
@c Add an empty line for separation.
@ifset AARCH64
@emph{Target AArch64 options:}
[@b{-EB}|@b{-EL}]
@end ifset
@ifset ALPHA
@emph{Target Alpha options:}
@ -733,6 +738,25 @@ Standard input, or source files to assemble.
@end table
@c man end
@ifset AARCH64
@ifclear man
@xref{AArch64 Options}, for the options available when @value{AS} is configured
for the 64-bit mode of the ARM Architecture (AArch64).
@end ifclear
@ifset man
@c man begin OPTIONS
The following options are available when @value{AS} is configured for the
64-bit mode of the ARM Architecture (AArch64).
@c man end
@c man begin INCLUDE
@include c-aarch64.texi
@c ended inside the included file
@end ifset
@end ifset
@ifset ALPHA
@ifclear man
@ -6914,6 +6938,9 @@ include details on any machine's instruction set. For details on that
subject, see the hardware manufacturer's manual.
@menu
@ifset AARCH64
* AArch64-Dependent:: AArch64 Dependent Features
@end ifset
@ifset ALPHA
* Alpha-Dependent:: Alpha Dependent Features
@end ifset
@ -7072,6 +7099,10 @@ subject, see the hardware manufacturer's manual.
@c node and sectioning commands; hence the repetition of @chapter BLAH
@c in both conditional blocks.
@ifset AARCH64
@include c-aarch64.texi
@end ifset
@ifset ALPHA
@include c-alpha.texi
@end ifset

275
gas/doc/c-aarch64.texi Normal file
View File

@ -0,0 +1,275 @@
@c Copyright 2009, 2010, 2011, 2012 Free Software Foundation, Inc.
@c Contributed by ARM Ltd.
@c This is part of the GAS manual.
@c For copying conditions, see the file as.texinfo.
@c man end
@ifset GENERIC
@page
@node AArch64-Dependent
@chapter AArch64 Dependent Features
@end ifset
@ifclear GENERIC
@node Machine Dependencies
@chapter AArch64 Dependent Features
@end ifclear
@cindex AArch64 support
@cindex Thumb support
@menu
* AArch64 Options:: Options
* AArch64 Syntax:: Syntax
* AArch64 Floating Point:: Floating Point
* AArch64 Directives:: AArch64 Machine Directives
* AArch64 Opcodes:: Opcodes
* AArch64 Mapping Symbols:: Mapping Symbols
@end menu
@node AArch64 Options
@section Options
@cindex AArch64 options (none)
@cindex options for AArch64 (none)
@c man begin OPTIONS
@table @gcctabopt
@cindex @code{-EB} command line option, AArch64
@item -EB
This option specifies that the output generated by the assembler should
be marked as being encoded for a big-endian processor.
@cindex @code{-EL} command line option, AArch64
@item -EL
This option specifies that the output generated by the assembler should
be marked as being encoded for a little-endian processor.
@end table
@c man end
@node AArch64 Syntax
@section Syntax
@menu
* AArch64-Chars:: Special Characters
* AArch64-Regs:: Register Names
* AArch64-Relocations:: Relocations
@end menu
@node AArch64-Chars
@subsection Special Characters
@cindex line comment character, AArch64
@cindex AArch64 line comment character
The presence of a @samp{//} on a line indicates the start of a comment
that extends to the end of the current line. If a @samp{#} appears as
the first character of a line, the whole line is treated as a comment.
@cindex line separator, AArch64
@cindex statement separator, AArch64
@cindex AArch64 line separator
The @samp{;} character can be used instead of a newline to separate
statements.
@cindex immediate character, AArch64
@cindex AArch64 immediate character
The @samp{#} can be optionally used to indicate immediate operands.
@node AArch64-Regs
@subsection Register Names
@cindex AArch64 register names
@cindex register names, AArch64
Please refer to the section @samp{4.4 Register Names} of
@samp{ARMv8 Instruction Set Overview}, which is available at
@uref{http://infocenter.arm.com}.
@node AArch64-Relocations
@subsection Relocations
@cindex relocations, AArch64
@cindex AArch64 relocations
@cindex MOVN, MOVZ and MOVK group relocations, AArch64
Relocations for @samp{MOVZ} and @samp{MOVK} instructions can be generated
by prefixing the label with @samp{#:abs_g2:} etc.
For example to load the 48-bit absolute address of @var{foo} into x0:
@smallexample
movz x0, #:abs_g2:foo // bits 32-47, overflow check
movk x0, #:abs_g1_nc:foo // bits 16-31, no overflow check
movk x0, #:abs_g0_nc:foo // bits 0-15, no overflow check
@end smallexample
@cindex ADRP, ADD, LDR/STR group relocations, AArch64
Relocations for @samp{ADRP}, and @samp{ADD}, @samp{LDR} or @samp{STR}
instructions can be generated by prefixing the label with
@samp{#:pg_hi21:} and @samp{#:lo12:} respectively.
For example to use 33-bit (+/-4GB) pc-relative addressing to
load the address of @var{foo} into x0:
@smallexample
adrp x0, #:pg_hi21:foo
add x0, x0, #:lo12:foo
@end smallexample
Or to load the value of @var{foo} into x0:
@smallexample
adrp x0, #:pg_hi21:foo
ldr x0, [x0, #:lo12:foo]
@end smallexample
Note that @samp{#:pg_hi21:} is optional.
@smallexample
adrp x0, foo
@end smallexample
is equivalent to
@smallexample
adrp x0, #:pg_hi21:foo
@end smallexample
@node AArch64 Floating Point
@section Floating Point
@cindex floating point, AArch64 (@sc{ieee})
@cindex AArch64 floating point (@sc{ieee})
The AArch64 architecture uses @sc{ieee} floating-point numbers.
@node AArch64 Directives
@section AArch64 Machine Directives
@cindex machine directives, AArch64
@cindex AArch64 machine directives
@table @code
@c AAAAAAAAAAAAAAAAAAAAAAAAA
@c BBBBBBBBBBBBBBBBBBBBBBBBBB
@cindex @code{.bss} directive, AArch64
@item .bss
This directive switches to the @code{.bss} section.
@c CCCCCCCCCCCCCCCCCCCCCCCCCC
@c DDDDDDDDDDDDDDDDDDDDDDDDDD
@c EEEEEEEEEEEEEEEEEEEEEEEEEE
@c FFFFFFFFFFFFFFFFFFFFFFFFFF
@c GGGGGGGGGGGGGGGGGGGGGGGGGG
@c HHHHHHHHHHHHHHHHHHHHHHHHHH
@c IIIIIIIIIIIIIIIIIIIIIIIIII
@c JJJJJJJJJJJJJJJJJJJJJJJJJJ
@c KKKKKKKKKKKKKKKKKKKKKKKKKK
@c LLLLLLLLLLLLLLLLLLLLLLLLLL
@cindex @code{.ltorg} directive, AArch64
@item .ltorg
This directive causes the current contents of the literal pool to be
dumped into the current section (which is assumed to be the .text
section) at the current location (aligned to a word boundary).
@code{GAS} maintains a separate literal pool for each section and each
sub-section. The @code{.ltorg} directive will only affect the literal
pool of the current section and sub-section. At the end of assembly
all remaining, un-empty literal pools will automatically be dumped.
Note - older versions of @code{GAS} would dump the current literal
pool any time a section change occurred. This is no longer done, since
it prevents accurate control of the placement of literal pools.
@c MMMMMMMMMMMMMMMMMMMMMMMMMM
@c NNNNNNNNNNNNNNNNNNNNNNNNNN
@c OOOOOOOOOOOOOOOOOOOOOOOOOO
@c PPPPPPPPPPPPPPPPPPPPPPPPPP
@cindex @code{.pool} directive, AArch64
@item .pool
This is a synonym for .ltorg.
@c QQQQQQQQQQQQQQQQQQQQQQQQQQ
@c RRRRRRRRRRRRRRRRRRRRRRRRRR
@cindex @code{.req} directive, AArch64
@item @var{name} .req @var{register name}
This creates an alias for @var{register name} called @var{name}. For
example:
@smallexample
foo .req w0
@end smallexample
@c SSSSSSSSSSSSSSSSSSSSSSSSSS
@c TTTTTTTTTTTTTTTTTTTTTTTTTT
@c UUUUUUUUUUUUUUUUUUUUUUUUUU
@cindex @code{.unreq} directive, AArch64
@item .unreq @var{alias-name}
This undefines a register alias which was previously defined using the
@code{req} directive. For example:
@smallexample
foo .req w0
.unreq foo
@end smallexample
An error occurs if the name is undefined. Note - this pseudo op can
be used to delete builtin in register name aliases (eg 'w0'). This
should only be done if it is really necessary.
@c VVVVVVVVVVVVVVVVVVVVVVVVVV
@c WWWWWWWWWWWWWWWWWWWWWWWWWW
@c XXXXXXXXXXXXXXXXXXXXXXXXXX
@c YYYYYYYYYYYYYYYYYYYYYYYYYY
@c ZZZZZZZZZZZZZZZZZZZZZZZZZZ
@end table
@node AArch64 Opcodes
@section Opcodes
@cindex AArch64 opcodes
@cindex opcodes for AArch64
@code{@value{AS}} implements all the standard AArch64 opcodes. It also
implements several pseudo opcodes, including several synthetic load
instructions.
@table @code
@cindex @code{LDR reg,=<expr>} pseudo op, AArch64
@item LDR =
@smallexample
ldr <register> , =<expression>
@end smallexample
The constant expression will be placed into the nearest literal pool (if it not
already there) and a PC-relative LDR instruction will be generated.
@end table
For more information on the AArch64 instruction set and assembly language
notation, see @samp{ARMv8 Instruction Set Overview} available at
@uref{http://infocenter.arm.com}.
@node AArch64 Mapping Symbols
@section Mapping Symbols
The AArch64 ELF specification requires that special symbols be inserted
into object files to mark certain features:
@table @code
@cindex @code{$x}
@item $x
At the start of a region of code containing AArch64 instructions.
@cindex @code{$d}
@item $d
At the start of a region of data.
@end table

124
gas/testsuite/ChangeLog
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@ -1,3 +1,127 @@
2012-08-13 Ian Bolton <ian.bolton@arm.com>
Laurent Desnogues <laurent.desnogues@arm.com>
Jim MacArthur <jim.macarthur@arm.com>
Marcus Shawcroft <marcus.shawcroft@arm.com>
Nigel Stephens <nigel.stephens@arm.com>
Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
Richard Earnshaw <rearnsha@arm.com>
Sofiane Naci <sofiane.naci@arm.com>
Tejas Belagod <tejas.belagod@arm.com>
Yufeng Zhang <yufeng.zhang@arm.com>
* gas/aarch64: New directory.
* gas/aarch64/aarch64.exp: New file.
* gas/aarch64/addsub.d: New file.
* gas/aarch64/addsub.s: New file.
* gas/aarch64/advsimd-across.d: New file.
* gas/aarch64/advsimd-across.s: New file.
* gas/aarch64/advsimd-misc.d: New file.
* gas/aarch64/advsimd-misc.s: New file.
* gas/aarch64/advsisd-copy.d: New file.
* gas/aarch64/advsisd-copy.s: New file.
* gas/aarch64/advsisd-misc.d: New file.
* gas/aarch64/advsisd-misc.s: New file.
* gas/aarch64/alias.d: New file.
* gas/aarch64/alias.s: New file.
* gas/aarch64/bitfield-alias.d: New file.
* gas/aarch64/bitfield-alias.s: New file.
* gas/aarch64/bitfield-bfm.d: New file.
* gas/aarch64/bitfield-bfm.s: New file.
* gas/aarch64/bitfield-dump: New file.
* gas/aarch64/bitfield-no-aliases.d: New file.
* gas/aarch64/crypto.d: New file.
* gas/aarch64/crypto.s: New file.
* gas/aarch64/diagnostic.d: New file.
* gas/aarch64/diagnostic.l: New file.
* gas/aarch64/diagnostic.s: New file.
* gas/aarch64/floatdp2.d: New file.
* gas/aarch64/floatdp2.s: New file.
* gas/aarch64/fp_cvt_int.d: New file.
* gas/aarch64/fp_cvt_int.s: New file.
* gas/aarch64/illegal-2.d: New file.
* gas/aarch64/illegal-2.l: New file.
* gas/aarch64/illegal-2.s: New file.
* gas/aarch64/illegal.d: New file.
* gas/aarch64/illegal.l: New file.
* gas/aarch64/illegal.s: New file.
* gas/aarch64/inst-directive.d: New file.
* gas/aarch64/inst-directive.s: New file.
* gas/aarch64/int-insns.d: New file.
* gas/aarch64/int-insns.s: New file.
* gas/aarch64/ldst-exclusive.d: New file.
* gas/aarch64/ldst-exclusive.s: New file.
* gas/aarch64/ldst-reg-imm-post-ind.d: New file.
* gas/aarch64/ldst-reg-imm-post-ind.s: New file.
* gas/aarch64/ldst-reg-imm-pre-ind.d: New file.
* gas/aarch64/ldst-reg-imm-pre-ind.s: New file.
* gas/aarch64/ldst-reg-pair.d: New file.
* gas/aarch64/ldst-reg-pair.s: New file.
* gas/aarch64/ldst-reg-reg-offset.d: New file.
* gas/aarch64/ldst-reg-reg-offset.s: New file.
* gas/aarch64/ldst-reg-uns-imm.d: New file.
* gas/aarch64/ldst-reg-uns-imm.s: New file.
* gas/aarch64/ldst-reg-unscaled-imm.d: New file.
* gas/aarch64/ldst-reg-unscaled-imm.s: New file.
* gas/aarch64/legacy_reg_names.d: New file.
* gas/aarch64/legacy_reg_names.l: New file.
* gas/aarch64/legacy_reg_names.s: New file.
* gas/aarch64/mapmisc.d: New file.
* gas/aarch64/mapmisc.dat: New file.
* gas/aarch64/mapmisc.s: New file.
* gas/aarch64/mapping.d: New file.
* gas/aarch64/mapping.s: New file.
* gas/aarch64/mapping2.d: New file.
* gas/aarch64/mapping2.s: New file.
* gas/aarch64/mapping3.d: New file.
* gas/aarch64/mapping3.s: New file.
* gas/aarch64/mapping4.d: New file.
* gas/aarch64/mapping4.s: New file.
* gas/aarch64/mov-no-aliases.d: New file.
* gas/aarch64/mov.d: New file.
* gas/aarch64/mov.s: New file.
* gas/aarch64/movi.d: New file.
* gas/aarch64/movi.s: New file.
* gas/aarch64/msr.d: New file.
* gas/aarch64/msr.s: New file.
* gas/aarch64/neon-fp-cvt-int.d: New file.
* gas/aarch64/neon-fp-cvt-int.s: New file.
* gas/aarch64/neon-frint.d: New file.
* gas/aarch64/neon-frint.s: New file.
* gas/aarch64/neon-ins.d: New file.
* gas/aarch64/neon-ins.s: New file.
* gas/aarch64/neon-not.d: New file.
* gas/aarch64/neon-not.s: New file.
* gas/aarch64/neon-vfp-reglist-post.d: New file.
* gas/aarch64/neon-vfp-reglist-post.s: New file.
* gas/aarch64/neon-vfp-reglist.d: New file.
* gas/aarch64/neon-vfp-reglist.s: New file.
* gas/aarch64/no-aliases.d: New file.
* gas/aarch64/optional.d: New file.
* gas/aarch64/optional.s: New file.
* gas/aarch64/programmer-friendly.d: New file.
* gas/aarch64/programmer-friendly.s: New file.
* gas/aarch64/reloc-data.d: New file.
* gas/aarch64/reloc-data.s: New file.
* gas/aarch64/reloc-insn.d: New file.
* gas/aarch64/reloc-insn.s: New file.
* gas/aarch64/shifted.d: New file.
* gas/aarch64/shifted.s: New file.
* gas/aarch64/symbol.d: New file.
* gas/aarch64/symbol.s: New file.
* gas/aarch64/sysreg-1.d: New file.
* gas/aarch64/sysreg-1.s: New file.
* gas/aarch64/sysreg.d: New file.
* gas/aarch64/sysreg.s: New file.
* gas/aarch64/system.d: New file.
* gas/aarch64/system.s: New file.
* gas/aarch64/tlbi_op.d: New file.
* gas/aarch64/tlbi_op.s: New file.
* gas/aarch64/tls.d: New file.
* gas/aarch64/tls.s: New file.
* gas/aarch64/verbose-error.d: New file.
* gas/aarch64/verbose-error.l: New file.
* gas/aarch64/verbose-error.s: New file.
2012-08-11 Saravanan Ekanathan <saravanan.ekanathan@amd.com>
PR gas/14423

7
gas/testsuite/gas/aarch64/aarch64.exp Normal file
View File

@ -0,0 +1,7 @@
#
# Some AArch64 tests
#
if {[istarget aarch64*-*-*]} {
run_dump_tests [lsort [glob -nocomplain $srcdir/$subdir/*.d]]
}

2371
gas/testsuite/gas/aarch64/addsub.d Normal file
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File diff suppressed because it is too large Load Diff

224
gas/testsuite/gas/aarch64/addsub.s Normal file
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@ -0,0 +1,224 @@
/* addsub.s Test file for AArch64 add-subtract instructions.
Copyright 2012 Free Software Foundation, Inc.
Contributed by ARM Ltd.
This file is part of GAS.
GAS is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the license, or
(at your option) any later version.
GAS is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; see the file COPYING3. If not,
see <http://www.gnu.org/licenses/>. */
// TODO: also cover the addsub_imm instructions.
/*
* Adjust Rm
*/
.macro adjust_rm op, rd, rn, rm_r, rm_n, extend, amount
// for 64-bit instruction, Rm is Xm when <extend> is explicitely
// or implicitly UXTX, SXTX or LSL; otherwise it Wm.
.ifc \rm_r, X
.ifnc \extend, UXTX
.ifnc \extend, SXTX
.ifnc \extend, LSL
.ifb \amount
\op \rd, \rn, W\()\rm_n, \extend
.else
\op \rd, \rn, W\()\rm_n, \extend #\amount
.endif
.exitm
.endif
.endif
.endif
.endif
.ifb \amount
\op \rd, \rn, \rm_r\()\rm_n, \extend
.else
\op \rd, \rn, \rm_r\()\rm_n, \extend #\amount
.endif
.endm
/*
* Emitting addsub_ext instruction
*/
.macro do_addsub_ext type, op, Rn, reg, extend, amount
.ifc \type, 0
// normal add/adds/sub/subs
.ifb \extend
\op \reg\()16, \Rn, \reg\()1
.else
.ifb \amount
adjust_rm \op, \reg\()16, \Rn, \reg, 1, \extend
.else
adjust_rm \op, \reg\()16, \Rn, \reg, 1, \extend, \amount
.endif
.endif
.else
.ifc \type, 1
// adds/subs with ZR as Rd
.ifb \extend
\op \reg\()ZR, \Rn, \reg\()1
.else
.ifb \amount
adjust_rm \op, \reg\()ZR, \Rn, \reg, 1, \extend
.else
adjust_rm \op, \reg\()ZR, \Rn, \reg, 1, \extend, \amount
.endif
.endif
.else
// cmn/cmp
.ifb \extend
\op \Rn, \reg\()1
.else
.ifb \amount
\op \Rn, \reg\()1, \extend
.else
\op \Rn, \reg\()1, \extend #\amount
.endif
.endif
.endif
.endif
.endm
/*
* Optional extension and optional shift amount
*/
.macro do_extend type, op, Rn, reg
// <extend> absent
// note that when SP is not used, the GAS will encode it as addsub_shift
do_addsub_ext \type, \op, \Rn, \reg
// optional absent <amount>
.irp extend, UXTB, UXTH, UXTW, UXTX, SXTB, SXTH, SXTW, SXTX
.irp amount, , 0, 1, 2, 3, 4
do_addsub_ext \type, \op, \Rn, \reg, \extend, \amount
.endr
.endr
// when <extend> is LSL, <amount> cannot be absent
// note that when SP is not used, the GAS will encode it as addsub_shift
.irp amount, 0, 1, 2, 3, 4
do_addsub_ext \type, \op, \Rn, \reg, LSL, \amount
.endr
.endm
/*
* Leaf macro emitting addsub_shift instruction
*/
.macro do_addsub_shift type, op, R, reg, shift, amount
.ifc \type, 0
// normal add/adds/sub/subs
.ifb \shift
\op \reg\()16, \R, \reg\()1
.else
\op \reg\()16, \R, \reg\()1, \shift #\amount
.endif
.else
.ifc \type, 1
// adds/subs with ZR as Rd
.ifb \shift
\op \reg\()ZR, \R, \reg\()1
.else
\op \reg\()ZR, \R, \reg\()1, \shift #\amount
.endif
.else
.ifc \type, 2
// cmn/cmp/neg/negs
.ifb \shift
\op \R, \reg\()1
.else
\op \R, \reg\()1, \shift #\amount
.endif
.else
// sub/subs with ZR as Rn
.ifb \shift
\op \R, \reg\()ZR, \reg\()1
.else
\op \R, \reg\()ZR, \reg\()1, \shift #\amount
.endif
.endif
.endif
.endif
.endm
/*
* Optional shift and optional shift amount
*/
.macro do_shift type, op, R, reg
// <shift> absent
do_addsub_shift \type, \op, \R, \reg
// optional absent <amount>
.irp shift, LSL, LSR, ASR
.irp amount, 0, 1, 2, 3, 4, 5, 16, 31
// amount cannot be absent when shift is present.
do_addsub_shift \type, \op, \R, \reg, \shift, \amount
.endr
.ifc \reg, X
do_addsub_shift \type, \op, \R, \reg, \shift, 63
.endif
.endr
.endm
func:
/*
* Add-subtract (extended register)
*/
.irp op, ADD, ADDS, SUB, SUBS
do_extend 0, \op, W7, W
do_extend 0, \op, WSP, W
do_extend 0, \op, X7, X
do_extend 0, \op, SP, X
.endr
.irp op, ADDS, SUBS
do_extend 1, \op, W7, W
do_extend 1, \op, WSP, W
do_extend 1, \op, X7, X
do_extend 1, \op, SP, X
.endr
.irp op, CMN, CMP
do_extend 2, \op, W7, W
do_extend 2, \op, WSP, W
do_extend 2, \op, X7, X
do_extend 2, \op, SP, X
.endr
/*
* Add-subtract (shift register)
*/
.irp op, ADD, ADDS, SUB, SUBS
do_shift 0, \op, W7, W
do_shift 0, \op, X7, X
.endr
.irp op, ADDS, SUBS
do_shift 1, \op, W7, W
do_shift 1, \op, X7, X
.endr
.irp op, CMN, CMP
do_shift 2, \op, W7, W
do_shift 2, \op, X7, X
.endr
.irp op, SUB, SUBS
do_shift 3, \op, W7, W
do_shift 3, \op, X7, X
.endr
.irp op, NEG, NEGS
do_shift 2, \op, W7, W
do_shift 2, \op, X7, X
.endr

46
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#objdump: -dr
.*: file format .*
Disassembly of section \.text:
0000000000000000 <.*>:
0: 0e303be7 saddlv h7, v31.8b
4: 4e303be7 saddlv h7, v31.16b
8: 0e703be7 saddlv s7, v31.4h
c: 4e703be7 saddlv s7, v31.8h
10: 4eb03be7 saddlv d7, v31.4s
14: 2e303be7 uaddlv h7, v31.8b
18: 6e303be7 uaddlv h7, v31.16b
1c: 2e703be7 uaddlv s7, v31.4h
20: 6e703be7 uaddlv s7, v31.8h
24: 6eb03be7 uaddlv d7, v31.4s
28: 0e30abe7 smaxv b7, v31.8b
2c: 4e30abe7 smaxv b7, v31.16b
30: 0e70abe7 smaxv h7, v31.4h
34: 4e70abe7 smaxv h7, v31.8h
38: 4eb0abe7 smaxv s7, v31.4s
3c: 2e30abe7 umaxv b7, v31.8b
40: 6e30abe7 umaxv b7, v31.16b
44: 2e70abe7 umaxv h7, v31.4h
48: 6e70abe7 umaxv h7, v31.8h
4c: 6eb0abe7 umaxv s7, v31.4s
50: 0e31abe7 sminv b7, v31.8b
54: 4e31abe7 sminv b7, v31.16b
58: 0e71abe7 sminv h7, v31.4h
5c: 4e71abe7 sminv h7, v31.8h
60: 4eb1abe7 sminv s7, v31.4s
64: 2e31abe7 uminv b7, v31.8b
68: 6e31abe7 uminv b7, v31.16b
6c: 2e71abe7 uminv h7, v31.4h
70: 6e71abe7 uminv h7, v31.8h
74: 6eb1abe7 uminv s7, v31.4s
78: 0e31bbe7 addv b7, v31.8b
7c: 4e31bbe7 addv b7, v31.16b
80: 0e71bbe7 addv h7, v31.4h
84: 4e71bbe7 addv h7, v31.8h
88: 4eb1bbe7 addv s7, v31.4s
8c: 6e30cbe7 fmaxnmv s7, v31.4s
90: 6eb0cbe7 fminnmv s7, v31.4s
94: 6e30fbe7 fmaxv s7, v31.4s
98: 6eb0fbe7 fminv s7, v31.4s

46
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/* advsimd-across.s Test file for AArch64 Advanced-SIMD across
instructions.
Copyright 2011, 2012 Free Software Foundation, Inc.
Contributed by ARM Ltd.
This file is part of GAS.
GAS is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the license, or
(at your option) any later version.
GAS is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; see the file COPYING3. If not,
see <http://www.gnu.org/licenses/>. */
.macro asimdall op, V, T
\op \V\()7, v31.\()\T
.endm
.text
.irp op, saddlv, uaddlv
asimdall \op, h, 8b
asimdall \op, h, 16b
asimdall \op, s, 4h
asimdall \op, s, 8h
asimdall \op, d, 4s
.endr
.irp op, smaxv, umaxv, sminv, uminv, addv
asimdall \op, b, 8b
asimdall \op, b, 16b
asimdall \op, h, 4h
asimdall \op, h, 8h
asimdall \op, s, 4s
.endr
.irp op, fmaxnmv, fminnmv, fmaxv, fminv
asimdall \op, s, 4s
.endr

35
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#objdump: -dr
.*: file format .*
Disassembly of section \.text:
0000000000000000 <.*>:
0: 0e20bbe0 abs v0.8b, v31.8b
4: 4e20bbe0 abs v0.16b, v31.16b
8: 0e60bbe0 abs v0.4h, v31.4h
c: 4e60bbe0 abs v0.8h, v31.8h
10: 0ea0bbe0 abs v0.2s, v31.2s
14: 4ea0bbe0 abs v0.4s, v31.4s
18: 4ee0bbe0 abs v0.2d, v31.2d
1c: 2e20bbe0 neg v0.8b, v31.8b
20: 6e20bbe0 neg v0.16b, v31.16b
24: 2e60bbe0 neg v0.4h, v31.4h
28: 6e60bbe0 neg v0.8h, v31.8h
2c: 2ea0bbe0 neg v0.2s, v31.2s
30: 6ea0bbe0 neg v0.4s, v31.4s
34: 6ee0bbe0 neg v0.2d, v31.2d
38: 0e207be0 sqabs v0.8b, v31.8b
3c: 4e207be0 sqabs v0.16b, v31.16b
40: 0e607be0 sqabs v0.4h, v31.4h
44: 4e607be0 sqabs v0.8h, v31.8h
48: 0ea07be0 sqabs v0.2s, v31.2s
4c: 4ea07be0 sqabs v0.4s, v31.4s
50: 4ee07be0 sqabs v0.2d, v31.2d
54: 2e207be0 sqneg v0.8b, v31.8b
58: 6e207be0 sqneg v0.16b, v31.16b
5c: 2e607be0 sqneg v0.4h, v31.4h
60: 6e607be0 sqneg v0.8h, v31.8h
64: 2ea07be0 sqneg v0.2s, v31.2s
68: 6ea07be0 sqneg v0.4s, v31.4s
6c: 6ee07be0 sqneg v0.2d, v31.2d

32
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/* advsimd-abs.s Test file for AArch64 Advanced-SIMD Integer absolute
instruction.
Copyright 2011, 2012 Free Software Foundation, Inc.
Contributed by ARM Ltd.
This file is part of GAS.
GAS is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the license, or
(at your option) any later version.
GAS is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; see the file COPYING3. If not,
see <http://www.gnu.org/licenses/>. */
.macro asimdabs op, T
\op v0.\()\T, v31.\()\T
.endm
.text
.irp op, abs, neg, sqabs, sqneg
.irp type, 8b, 16b, 4h, 8h, 2s, 4s, 2d
asimdabs \op \type
.endr
.endr

67
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#objdump: -dr
.*: file format .*
Disassembly of section \.text:
0000000000000000 <.*>:
0: 5e0104ff mov b31, v7.b\[0\]
4: 5e0304ff mov b31, v7.b\[1\]
8: 5e0504ff mov b31, v7.b\[2\]
c: 5e0704ff mov b31, v7.b\[3\]
10: 5e0904ff mov b31, v7.b\[4\]
14: 5e0b04ff mov b31, v7.b\[5\]
18: 5e0d04ff mov b31, v7.b\[6\]
1c: 5e0f04ff mov b31, v7.b\[7\]
20: 5e1104ff mov b31, v7.b\[8\]
24: 5e1304ff mov b31, v7.b\[9\]
28: 5e1504ff mov b31, v7.b\[10\]
2c: 5e1704ff mov b31, v7.b\[11\]
30: 5e1904ff mov b31, v7.b\[12\]
34: 5e1b04ff mov b31, v7.b\[13\]
38: 5e1d04ff mov b31, v7.b\[14\]
3c: 5e1f04ff mov b31, v7.b\[15\]
40: 5e0204ff mov h31, v7.h\[0\]
44: 5e0604ff mov h31, v7.h\[1\]
48: 5e0a04ff mov h31, v7.h\[2\]
4c: 5e0e04ff mov h31, v7.h\[3\]
50: 5e1204ff mov h31, v7.h\[4\]
54: 5e1604ff mov h31, v7.h\[5\]
58: 5e1a04ff mov h31, v7.h\[6\]
5c: 5e1e04ff mov h31, v7.h\[7\]
60: 5e0404ff mov s31, v7.s\[0\]
64: 5e0c04ff mov s31, v7.s\[1\]
68: 5e1404ff mov s31, v7.s\[2\]
6c: 5e1c04ff mov s31, v7.s\[3\]
70: 5e0804ff mov d31, v7.d\[0\]
74: 5e1804ff mov d31, v7.d\[1\]
78: 5e0104ff mov b31, v7.b\[0\]
7c: 5e0304ff mov b31, v7.b\[1\]
80: 5e0504ff mov b31, v7.b\[2\]
84: 5e0704ff mov b31, v7.b\[3\]
88: 5e0904ff mov b31, v7.b\[4\]
8c: 5e0b04ff mov b31, v7.b\[5\]
90: 5e0d04ff mov b31, v7.b\[6\]
94: 5e0f04ff mov b31, v7.b\[7\]
98: 5e1104ff mov b31, v7.b\[8\]
9c: 5e1304ff mov b31, v7.b\[9\]
a0: 5e1504ff mov b31, v7.b\[10\]
a4: 5e1704ff mov b31, v7.b\[11\]
a8: 5e1904ff mov b31, v7.b\[12\]
ac: 5e1b04ff mov b31, v7.b\[13\]
b0: 5e1d04ff mov b31, v7.b\[14\]
b4: 5e1f04ff mov b31, v7.b\[15\]
b8: 5e0204ff mov h31, v7.h\[0\]
bc: 5e0604ff mov h31, v7.h\[1\]
c0: 5e0a04ff mov h31, v7.h\[2\]
c4: 5e0e04ff mov h31, v7.h\[3\]
c8: 5e1204ff mov h31, v7.h\[4\]
cc: 5e1604ff mov h31, v7.h\[5\]
d0: 5e1a04ff mov h31, v7.h\[6\]
d4: 5e1e04ff mov h31, v7.h\[7\]
d8: 5e0404ff mov s31, v7.s\[0\]
dc: 5e0c04ff mov s31, v7.s\[1\]
e0: 5e1404ff mov s31, v7.s\[2\]
e4: 5e1c04ff mov s31, v7.s\[3\]
e8: 5e0804ff mov d31, v7.d\[0\]
ec: 5e1804ff mov d31, v7.d\[1\]

39
gas/testsuite/gas/aarch64/advsisd-copy.s Normal file
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/* advsisd-copy.s Test file for AArch64 Advanced-SISD copy instructions.
Copyright 2011, 2012 Free Software Foundation, Inc.
Contributed by ARM Ltd.
This file is part of GAS.
GAS is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the license, or
(at your option) any later version.
GAS is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; see the file COPYING3. If not,
see <http://www.gnu.org/licenses/>. */
.macro element2scalar op, type, index
\op \type\()31, V7.\type[\index]
.endm
.macro iterate op, type, from, to
element2scalar \op, \type, \from
.if \to-\from
iterate \op, \type, "(\from+1)", \to
.endif
.endm
.text
.irp op, dup, mov
iterate \op, b, 0, 15
iterate \op, h, 0, 7
iterate \op, s, 0, 3
iterate \op, d, 0, 1
.endr

17
gas/testsuite/gas/aarch64/advsisd-misc.d Normal file
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#objdump: -dr
.*: file format .*
Disassembly of section \.text:
0000000000000000 <.*>:
0: 5ee0bbe0 abs d0, d31
4: 7ee0bbe0 neg d0, d31
8: 5e207be0 sqabs b0, b31
c: 7e207be0 sqneg b0, b31
10: 5e607be0 sqabs h0, h31
14: 7e607be0 sqneg h0, h31
18: 5ea07be0 sqabs s0, s31
1c: 7ea07be0 sqneg s0, s31
20: 5ee07be0 sqabs d0, d31
24: 7ee07be0 sqneg d0, d31

36
gas/testsuite/gas/aarch64/advsisd-misc.s Normal file
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/* advsimd-abs.s Test file for AArch64 AdvSISD Scalar Misc
instructions.
Copyright 2011, 2012 Free Software Foundation, Inc.
Contributed by ARM Ltd.
This file is part of GAS.
GAS is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the license, or
(at your option) any later version.
GAS is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; see the file COPYING3. If not,
see <http://www.gnu.org/licenses/>. */
.macro asisd op T
\op \T\()0, \T\()31
.endm
.text
.irp op, abs, neg
asisd \op d
.endr
.irp type, b, h, s, d
.irp op, sqabs, sqneg
asisd \op \type
.endr
.endr

74
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#objdump: -dr
.*: file format .*
Disassembly of section \.text:
0000000000000000 <.*>:
0: 13823c20 extr w0, w1, w2, #15
4: 93c23c20 extr x0, x1, x2, #15
8: 13831c60 ror w0, w3, #7
c: 93c51ca0 ror x0, x5, #7
10: 138748e6 ror w6, w7, #18
14: 93c7a0e6 ror x6, x7, #40
18: 1b020c20 madd w0, w1, w2, w3
1c: 1b027c20 mul w0, w1, w2
20: 1b027c20 mul w0, w1, w2
24: 9b028c20 msub x0, x1, x2, x3
28: 9b02fc20 mneg x0, x1, x2
2c: 9b02fc20 mneg x0, x1, x2
30: 9b220c20 smaddl x0, w1, w2, x3
34: 9b227c20 smull x0, w1, w2
38: 9b227c20 smull x0, w1, w2
3c: 9b228c20 smsubl x0, w1, w2, x3
40: 9b22fc20 smnegl x0, w1, w2
44: 9b22fc20 smnegl x0, w1, w2
48: 9ba20c20 umaddl x0, w1, w2, x3
4c: 9ba27c20 umull x0, w1, w2
50: 9ba27c20 umull x0, w1, w2
54: 9ba28c20 umsubl x0, w1, w2, x3
58: 9ba2fc20 umnegl x0, w1, w2
5c: 9ba2fc20 umnegl x0, w1, w2
60: 1a9f0420 csinc w0, w1, wzr, eq
64: 1a810420 cinc w0, w1, ne
68: 1a810420 cinc w0, w1, ne
6c: 1a9f37e0 cset w0, cs
70: 1a9f37e0 cset w0, cs
74: da9f2020 csinv x0, x1, xzr, cs
78: da812020 cinv x0, x1, cc
7c: da812020 cinv x0, x1, cc
80: da9f43e0 csetm x0, pl
84: da9f43e0 csetm x0, pl
88: da9eb7e0 csneg x0, xzr, x30, lt
8c: da9eb7c0 cneg x0, x30, ge
90: da9eb7c0 cneg x0, x30, ge
94: ea020020 ands x0, x1, x2
98: ea02003f tst x1, x2
9c: ea02003f tst x1, x2
a0: 6ac27c3f tst w1, w2, ror #31
a4: 6ac27c3f tst w1, w2, ror #31
a8: aa220020 orn x0, x1, x2
ac: aa22003f orn xzr, x1, x2
b0: aa2203e0 mvn x0, x2
b4: aa2203e0 mvn x0, x2
b8: 2aa23c3f orn wzr, w1, w2, asr #15
bc: 2aa23fe0 mvn w0, w2, asr #15
c0: 2aa23fe0 mvn w0, w2, asr #15
c4: 0ea11c20 mov v0.8b, v1.8b
c8: 0ea21c20 orr v0.8b, v1.8b, v2.8b
cc: 0ea11c20 mov v0.8b, v1.8b
d0: aa1103e3 mov x3, x17
d4: aa110003 orr x3, x0, x17
d8: aa1103e3 mov x3, x17
dc: 92628421 and x1, x1, #0xffffffffc0000000
e0: 927ef800 and x0, x0, #0xfffffffffffffffd
e4: 121e7800 and w0, w0, #0xfffffffd
e8: 721d1f1f tst w24, #0x7f8
ec: 721d1f00 ands w0, w24, #0x7f8
f0: 721d1f1f tst w24, #0x7f8
f4: 7100807f cmp w3, #0x20
f8: 710083e3 subs w3, wsp, #0x20
fc: 7100807f cmp w3, #0x20
100: b13ffdff cmn x15, #0xfff
104: f13fffef subs x15, sp, #0xfff
108: b13ffdff cmn x15, #0xfff

101
gas/testsuite/gas/aarch64/alias.s Normal file
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/* alias.s Test file for AArch64 instructions aliases or disassembly
preference. It is also used to test the -Mno-aliases option in
the disassemler.
Copyright 2012 Free Software Foundation, Inc.
Contributed by ARM Ltd.
This file is part of GAS.
GAS is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the license, or
(at your option) any later version.
GAS is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; see the file COPYING3. If not,
see <http://www.gnu.org/licenses/>. */
.text
extr w0, w1, w2, #15
extr x0, x1, x2, #15
extr w0, w3, w3, #7
extr x0, x5, x5, #7
ror w6, w7, #18
ror x6, x7, #40
madd w0, w1, w2, w3
madd w0, w1, w2, wzr
mul w0, w1, w2
msub x0, x1, x2, x3
msub x0, x1, x2, xzr
mneg x0, x1, x2
smaddl x0, w1, w2, x3
smaddl x0, w1, w2, xzr
smull x0, w1, w2
smsubl x0, w1, w2, x3
smsubl x0, w1, w2, xzr
smnegl x0, w1, w2
umaddl x0, w1, w2, x3
umaddl x0, w1, w2, xzr
umull x0, w1, w2
umsubl x0, w1, w2, x3
umsubl x0, w1, w2, xzr
umnegl x0, w1, w2
csinc w0, w1, wzr, eq
csinc w0, w1, w1, eq
cinc w0, w1, ne
csinc w0, wzr, wzr, lo
cset w0, cs
csinv x0, x1, xzr, hs
csinv x0, x1, x1, hs
cinv x0, x1, cc
csinv x0, xzr, xzr, mi
csetm x0, pl
csneg x0, xzr, x30, lt
csneg x0, x30, x30, lt
cneg x0, x30, ge
ands x0, x1, x2
ands xzr, x1, x2
tst x1, x2
ands wzr, w1, w2, ror #31
tst w1, w2, ror #31
orn x0, x1, x2
orn xzr, x1, x2
orn x0, xzr, x2
mvn x0, x2
orn wzr, w1, w2, asr #15
orn w0, wzr, w2, asr #15
mvn w0, w2, asr #15
mov v0.8b, v1.8b
orr v0.8b, v1.8b, v2.8b
orr v0.8b, v1.8b, v1.8b
mov x3, x17
orr x3, x0, x17
orr x3, xzr, x17
bic x1, x1, #(1<<30)-1
bic x0, x0, #2
bic w0, w0, #2
ands wzr, w24, #0x7f8
ands w0, w24, #0x7f8
tst w24, #0x7f8
subs wzr, w3, #0x20
subs w3, wsp, #0x20
cmp w3, #0x20
adds xzr, x15, #0xfff
subs x15, sp, #0xfff
cmn x15, #0xfff

2
gas/testsuite/gas/aarch64/bitfield-alias.d Normal file
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@ -0,0 +1,2 @@
#objdump: -dr
#dump: bitfield-dump

112
gas/testsuite/gas/aarch64/bitfield-alias.s Normal file
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/* bitfield-alias.s Test file for AArch64 bitfield instructions
alias mnemonics.
Copyright 2011, 2012 Free Software Foundation, Inc.
Contributed by ARM Ltd.
This file is part of GAS.
GAS is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the license, or
(at your option) any later version.
GAS is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; see the file COPYING3. If not,
see <http://www.gnu.org/licenses/>. */
/* This file tests the GAS's ability in assembling the alias mnemonics
of sbfm, bfm and ubfm. Disassembler should prefer to use alias
mnemonics to display {[u|s]}bfm instructions.
bitfield-bfm.s and bitfield-alias.s will be assembled into idential
binary, which is why the two tests share the same dump match
file 'bitfield-dump'.
This assembly file is also used for the bitfield-no-aliases test. */
// <op> <Wd>, <Wn>
.macro bf_32r op
\op wzr, w7
.endm
// <op> <Xd>, <Wn>
.macro bf_64x op
\op xzr, w7
.endm
// <op> <Wd>, <Wn>, #<shift>
.macro bf_32s op, shift
\op wzr, w7, \shift
.endm
// <op> <Xd>, <Xn>, #<shift>
.macro bf_64s op, shift
\op xzr, x7, \shift
.endm
// <op> <Wd>, <Wn>, #<lsb>, #<width>
.macro bf_32 op, lsb, width
\op wzr, w7, #\lsb, #\width
.endm
// <op> <Xd>, <Xn>, #<lsb>, #<width>
.macro bf_64 op, lsb, width
\op xzr, x7, #\lsb, #\width
.endm
.text
/*
* extend
*/
bf_32r sxtb
bf_64x sxtb
bf_32r sxth
bf_64x sxth
bf_64x sxtw
bf_32r uxtb
bf_64x uxtb
bf_32r uxth
bf_64x uxth
bf_32r uxtw
bf_64x uxtw
/*
* shift
*/
.irp op, asr, lsr, lsl
.irp shift, 0, 16, 31
bf_32s \op, \shift
.endr
.irp shift, 0, 31, 63
bf_64s \op, \shift
.endr
.endr
/*
* Insert & Extract
*/
.irp op, sbfiz, sbfx, bfi, bfxil, ubfiz, ubfx
bf_32 \op, 0, 1
bf_32 \op, 0, 16
bf_32 \op, 0, 32
bf_32 \op, 16, 1
bf_32 \op, 16, 8
bf_32 \op, 16, 16
bf_32 \op, 31, 1
bf_64 \op, 0, 1
bf_64 \op, 0, 32
bf_64 \op, 0, 64
bf_64 \op, 32, 1
bf_64 \op, 32, 16
bf_64 \op, 32, 32
bf_64 \op, 63, 1
.endr

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#objdump: -dr
#dump: bitfield-dump

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/* bitfield-bfm.s Test file for AArch64 bitfield instructions
sbfm, bfm and ubfm mnemonics.
Copyright 2011, 2012 Free Software Foundation, Inc.
Contributed by ARM Ltd.
This file is part of GAS.
GAS is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the license, or
(at your option) any later version.
GAS is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; see the file COPYING3. If not,
see <http://www.gnu.org/licenses/>. */
/* This file tests the GAS's ability in assembling sbfm, bfm and ubfm
instructions. Disassembler should use alias mnemonics to display
{[u|s]}bfm instructions. bitfield-bfm.s and bitfield-alias.s will be
assembled into idential binary, which is why the two tests share the
same dump match file 'bitfield-dump'. */
// <op> <Wd>, <Wn>
.macro bf_32r op
\op wzr, w7
.endm
// <op> <Xd>, <Wn>
.macro bf_64x op
\op xzr, w7
.endm
// <op> <Wd>, <Wn>, #<shift>
.macro bf_32s op, shift
\op wzr, w7, \shift
.endm
// <op> <Xd>, <Xn>, #<shift>
.macro bf_64s op, shift
\op xzr, x7, \shift
.endm
.macro op_bfm signed, reg, immr, imms
\signed\()bfm \reg\()zr, \reg\()7, #\immr, #\imms // e.g. sbfm xzr, x7, #0, #15
.endm
.macro ext2bfm signed, reg, imms
op_bfm signed=\signed, reg=\reg, immr=0, imms=\imms
.endm
// shift right -> bfm
.macro sr2bfm signed, reg, shift, imms
op_bfm signed=\signed, reg=\reg, immr=\shift, imms=\imms
.endm
// shift left -> bfm
.macro sl2bfm signed, reg, shift
.ifc \reg, w
op_bfm signed=\signed, reg=\reg, immr="((32-\shift)&31)", imms="(31-\shift)"
.else
op_bfm signed=\signed, reg=\reg, immr="((64-\shift)&63)", imms="(63-\shift)"
.endif
.endm
// bitfield insert -> bfm
.macro ins2bfm signed, reg, lsb, width
.ifc \reg, w
op_bfm signed=\signed, reg=\reg, immr="((32-\lsb)&31)", imms="(\width-1)"
.else
op_bfm signed=\signed, reg=\reg, immr="((64-\lsb)&63)", imms="(\width-1)"
.endif
.endm
// bitfield extract -> bfm
.macro x2bfm signed, reg, lsb, width
op_bfm signed=\signed, reg=\reg, immr=\lsb, imms="(\lsb+\width-1)"
.endm
.text
/*
* aliasing extend
*/
ext2bfm s, w, 7 // sxtb wzr, w7
ext2bfm s, x, 7 // sxtb xzr, x7
ext2bfm s, w, 15 // sxth wzr, w7
ext2bfm s, x, 15 // sxth xzr, x7
ext2bfm s, x, 31 // sxtw xzr, x7
ext2bfm u, w, 7 // uxtb wzr, w7
ext2bfm u, w, 7 // uxtb xzr, w7
ext2bfm u, w, 15 // uxth wzr, w7
ext2bfm u, w, 15 // uxth xzr, w7
orr wzr, wzr, w7 // uxtw wzr, w7
orr wzr, wzr, w7 // uxtw wzr, w7
/*
* aliasing shift
*/
.irp shift 0, 16, 31 // asr wzr, w7, #\shift
sr2bfm s, w, \shift, 31
.endr
.irp shift 0, 31, 63 // asr xzr, x7, #\shift
sr2bfm s, x, \shift, 63
.endr
.irp shift 0, 16, 31 // lsr wzr, w7, #\shift
sr2bfm u, w, \shift, 31
.endr
.irp shift 0, 31, 63 // lsr xzr, x7, #\shift
sr2bfm u, x, \shift, 63
.endr
.irp shift 0, 16, 31 // lsl wzr, w7, #\shift
sl2bfm u, w, \shift
.endr
.irp shift 0, 31, 63 // lsl xzr, x7, #\shift
sl2bfm u, x, \shift
.endr
/*
* aliasing insert and extract
*/
.irp signed, s, , u
.irp whichm, ins2bfm, x2bfm
\whichm \signed, w, 0, 1
\whichm \signed, w, 0, 16
\whichm \signed, w, 0, 32
\whichm \signed, w, 16, 1
\whichm \signed, w, 16, 8
\whichm \signed, w, 16, 16
\whichm \signed, w, 31, 1
\whichm \signed, x, 0, 1
\whichm \signed, x, 0, 32
\whichm \signed, x, 0, 64
\whichm \signed, x, 32, 1
\whichm \signed, x, 32, 16
\whichm \signed, x, 32, 32
\whichm \signed, x, 63, 1
.endr
.endr

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.*: file format .*
Disassembly of section \.text:
0000000000000000 <.*>:
0: 13001cff sxtb wzr, w7
4: 93401cff sxtb xzr, w7
8: 13003cff sxth wzr, w7
c: 93403cff sxth xzr, w7
10: 93407cff sxtw xzr, w7
14: 53001cff uxtb wzr, w7
18: 53001cff uxtb wzr, w7
1c: 53003cff uxth wzr, w7
20: 53003cff uxth wzr, w7
24: 2a0703ff mov wzr, w7
28: 2a0703ff mov wzr, w7
2c: 13007cff asr wzr, w7, #0
30: 13107cff asr wzr, w7, #16
34: 131f7cff asr wzr, w7, #31
38: 9340fcff asr xzr, x7, #0
3c: 935ffcff asr xzr, x7, #31
40: 937ffcff asr xzr, x7, #63
44: 53007cff lsr wzr, w7, #0
48: 53107cff lsr wzr, w7, #16
4c: 531f7cff lsr wzr, w7, #31
50: d340fcff lsr xzr, x7, #0
54: d35ffcff lsr xzr, x7, #31
58: d37ffcff lsr xzr, x7, #63
5c: 53007cff lsr wzr, w7, #0
60: 53103cff lsl wzr, w7, #16
64: 530100ff lsl wzr, w7, #31
68: d340fcff lsr xzr, x7, #0
6c: d36180ff lsl xzr, x7, #31
70: d34100ff lsl xzr, x7, #63
74: 130000ff sbfx wzr, w7, #0, #1
78: 13003cff sxth wzr, w7
7c: 13007cff asr wzr, w7, #0
80: 131000ff sbfiz wzr, w7, #16, #1
84: 13101cff sbfiz wzr, w7, #16, #8
88: 13103cff sbfiz wzr, w7, #16, #16
8c: 130100ff sbfiz wzr, w7, #31, #1
90: 934000ff sbfx xzr, x7, #0, #1
94: 93407cff sxtw xzr, w7
98: 9340fcff asr xzr, x7, #0
9c: 936000ff sbfiz xzr, x7, #32, #1
a0: 93603cff sbfiz xzr, x7, #32, #16
a4: 93607cff sbfiz xzr, x7, #32, #32
a8: 934100ff sbfiz xzr, x7, #63, #1
ac: 130000ff sbfx wzr, w7, #0, #1
b0: 13003cff sxth wzr, w7
b4: 13007cff asr wzr, w7, #0
b8: 131040ff sbfx wzr, w7, #16, #1
bc: 13105cff sbfx wzr, w7, #16, #8
c0: 13107cff asr wzr, w7, #16
c4: 131f7cff asr wzr, w7, #31
c8: 934000ff sbfx xzr, x7, #0, #1
cc: 93407cff sxtw xzr, w7
d0: 9340fcff asr xzr, x7, #0
d4: 936080ff sbfx xzr, x7, #32, #1
d8: 9360bcff sbfx xzr, x7, #32, #16
dc: 9360fcff asr xzr, x7, #32
e0: 937ffcff asr xzr, x7, #63
e4: 330000ff bfxil wzr, w7, #0, #1
e8: 33003cff bfxil wzr, w7, #0, #16
ec: 33007cff bfxil wzr, w7, #0, #32
f0: 331000ff bfi wzr, w7, #16, #1
f4: 33101cff bfi wzr, w7, #16, #8
f8: 33103cff bfi wzr, w7, #16, #16
fc: 330100ff bfi wzr, w7, #31, #1
100: b34000ff bfxil xzr, x7, #0, #1
104: b3407cff bfxil xzr, x7, #0, #32
108: b340fcff bfxil xzr, x7, #0, #64
10c: b36000ff bfi xzr, x7, #32, #1
110: b3603cff bfi xzr, x7, #32, #16
114: b3607cff bfi xzr, x7, #32, #32
118: b34100ff bfi xzr, x7, #63, #1
11c: 330000ff bfxil wzr, w7, #0, #1
120: 33003cff bfxil wzr, w7, #0, #16
124: 33007cff bfxil wzr, w7, #0, #32
128: 331040ff bfxil wzr, w7, #16, #1
12c: 33105cff bfxil wzr, w7, #16, #8
130: 33107cff bfxil wzr, w7, #16, #16
134: 331f7cff bfxil wzr, w7, #31, #1
138: b34000ff bfxil xzr, x7, #0, #1
13c: b3407cff bfxil xzr, x7, #0, #32
140: b340fcff bfxil xzr, x7, #0, #64
144: b36080ff bfxil xzr, x7, #32, #1
148: b360bcff bfxil xzr, x7, #32, #16
14c: b360fcff bfxil xzr, x7, #32, #32
150: b37ffcff bfxil xzr, x7, #63, #1
154: 530000ff ubfx wzr, w7, #0, #1
158: 53003cff uxth wzr, w7
15c: 53007cff lsr wzr, w7, #0
160: 531000ff ubfiz wzr, w7, #16, #1
164: 53101cff ubfiz wzr, w7, #16, #8
168: 53103cff lsl wzr, w7, #16
16c: 530100ff lsl wzr, w7, #31
170: d34000ff ubfx xzr, x7, #0, #1
174: d3407cff ubfx xzr, x7, #0, #32
178: d340fcff lsr xzr, x7, #0
17c: d36000ff ubfiz xzr, x7, #32, #1
180: d3603cff ubfiz xzr, x7, #32, #16
184: d3607cff lsl xzr, x7, #32
188: d34100ff lsl xzr, x7, #63
18c: 530000ff ubfx wzr, w7, #0, #1
190: 53003cff uxth wzr, w7
194: 53007cff lsr wzr, w7, #0
198: 531040ff ubfx wzr, w7, #16, #1
19c: 53105cff ubfx wzr, w7, #16, #8
1a0: 53107cff lsr wzr, w7, #16
1a4: 531f7cff lsr wzr, w7, #31
1a8: d34000ff ubfx xzr, x7, #0, #1
1ac: d3407cff ubfx xzr, x7, #0, #32
1b0: d340fcff lsr xzr, x7, #0
1b4: d36080ff ubfx xzr, x7, #32, #1
1b8: d360bcff ubfx xzr, x7, #32, #16
1bc: d360fcff lsr xzr, x7, #32
1c0: d37ffcff lsr xzr, x7, #63

121
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#source: bitfield-alias.s
#objdump: -dr -Mno-aliases
.*: file format .*
Disassembly of section \.text:
0000000000000000 <.*>:
0: 13001cff sbfm wzr, w7, #0, #7
4: 93401cff sbfm xzr, x7, #0, #7
8: 13003cff sbfm wzr, w7, #0, #15
c: 93403cff sbfm xzr, x7, #0, #15
10: 93407cff sbfm xzr, x7, #0, #31
14: 53001cff ubfm wzr, w7, #0, #7
18: 53001cff ubfm wzr, w7, #0, #7
1c: 53003cff ubfm wzr, w7, #0, #15
20: 53003cff ubfm wzr, w7, #0, #15
24: 2a0703ff orr wzr, wzr, w7
28: 2a0703ff orr wzr, wzr, w7
2c: 13007cff sbfm wzr, w7, #0, #31
30: 13107cff sbfm wzr, w7, #16, #31
34: 131f7cff sbfm wzr, w7, #31, #31
38: 9340fcff sbfm xzr, x7, #0, #63
3c: 935ffcff sbfm xzr, x7, #31, #63
40: 937ffcff sbfm xzr, x7, #63, #63
44: 53007cff ubfm wzr, w7, #0, #31
48: 53107cff ubfm wzr, w7, #16, #31
4c: 531f7cff ubfm wzr, w7, #31, #31
50: d340fcff ubfm xzr, x7, #0, #63
54: d35ffcff ubfm xzr, x7, #31, #63
58: d37ffcff ubfm xzr, x7, #63, #63
5c: 53007cff ubfm wzr, w7, #0, #31
60: 53103cff ubfm wzr, w7, #16, #15
64: 530100ff ubfm wzr, w7, #1, #0
68: d340fcff ubfm xzr, x7, #0, #63
6c: d36180ff ubfm xzr, x7, #33, #32
70: d34100ff ubfm xzr, x7, #1, #0
74: 130000ff sbfm wzr, w7, #0, #0
78: 13003cff sbfm wzr, w7, #0, #15
7c: 13007cff sbfm wzr, w7, #0, #31
80: 131000ff sbfm wzr, w7, #16, #0
84: 13101cff sbfm wzr, w7, #16, #7
88: 13103cff sbfm wzr, w7, #16, #15
8c: 130100ff sbfm wzr, w7, #1, #0
90: 934000ff sbfm xzr, x7, #0, #0
94: 93407cff sbfm xzr, x7, #0, #31
98: 9340fcff sbfm xzr, x7, #0, #63
9c: 936000ff sbfm xzr, x7, #32, #0
a0: 93603cff sbfm xzr, x7, #32, #15
a4: 93607cff sbfm xzr, x7, #32, #31
a8: 934100ff sbfm xzr, x7, #1, #0
ac: 130000ff sbfm wzr, w7, #0, #0
b0: 13003cff sbfm wzr, w7, #0, #15
b4: 13007cff sbfm wzr, w7, #0, #31
b8: 131040ff sbfm wzr, w7, #16, #16
bc: 13105cff sbfm wzr, w7, #16, #23
c0: 13107cff sbfm wzr, w7, #16, #31
c4: 131f7cff sbfm wzr, w7, #31, #31
c8: 934000ff sbfm xzr, x7, #0, #0
cc: 93407cff sbfm xzr, x7, #0, #31
d0: 9340fcff sbfm xzr, x7, #0, #63
d4: 936080ff sbfm xzr, x7, #32, #32
d8: 9360bcff sbfm xzr, x7, #32, #47
dc: 9360fcff sbfm xzr, x7, #32, #63
e0: 937ffcff sbfm xzr, x7, #63, #63
e4: 330000ff bfm wzr, w7, #0, #0
e8: 33003cff bfm wzr, w7, #0, #15
ec: 33007cff bfm wzr, w7, #0, #31
f0: 331000ff bfm wzr, w7, #16, #0
f4: 33101cff bfm wzr, w7, #16, #7
f8: 33103cff bfm wzr, w7, #16, #15
fc: 330100ff bfm wzr, w7, #1, #0
100: b34000ff bfm xzr, x7, #0, #0
104: b3407cff bfm xzr, x7, #0, #31
108: b340fcff bfm xzr, x7, #0, #63
10c: b36000ff bfm xzr, x7, #32, #0
110: b3603cff bfm xzr, x7, #32, #15
114: b3607cff bfm xzr, x7, #32, #31
118: b34100ff bfm xzr, x7, #1, #0
11c: 330000ff bfm wzr, w7, #0, #0
120: 33003cff bfm wzr, w7, #0, #15
124: 33007cff bfm wzr, w7, #0, #31
128: 331040ff bfm wzr, w7, #16, #16
12c: 33105cff bfm wzr, w7, #16, #23
130: 33107cff bfm wzr, w7, #16, #31
134: 331f7cff bfm wzr, w7, #31, #31
138: b34000ff bfm xzr, x7, #0, #0
13c: b3407cff bfm xzr, x7, #0, #31
140: b340fcff bfm xzr, x7, #0, #63
144: b36080ff bfm xzr, x7, #32, #32
148: b360bcff bfm xzr, x7, #32, #47
14c: b360fcff bfm xzr, x7, #32, #63
150: b37ffcff bfm xzr, x7, #63, #63
154: 530000ff ubfm wzr, w7, #0, #0
158: 53003cff ubfm wzr, w7, #0, #15
15c: 53007cff ubfm wzr, w7, #0, #31
160: 531000ff ubfm wzr, w7, #16, #0
164: 53101cff ubfm wzr, w7, #16, #7
168: 53103cff ubfm wzr, w7, #16, #15
16c: 530100ff ubfm wzr, w7, #1, #0
170: d34000ff ubfm xzr, x7, #0, #0
174: d3407cff ubfm xzr, x7, #0, #31
178: d340fcff ubfm xzr, x7, #0, #63
17c: d36000ff ubfm xzr, x7, #32, #0
180: d3603cff ubfm xzr, x7, #32, #15
184: d3607cff ubfm xzr, x7, #32, #31
188: d34100ff ubfm xzr, x7, #1, #0
18c: 530000ff ubfm wzr, w7, #0, #0
190: 53003cff ubfm wzr, w7, #0, #15
194: 53007cff ubfm wzr, w7, #0, #31
198: 531040ff ubfm wzr, w7, #16, #16
19c: 53105cff ubfm wzr, w7, #16, #23
1a0: 53107cff ubfm wzr, w7, #16, #31
1a4: 531f7cff ubfm wzr, w7, #31, #31
1a8: d34000ff ubfm xzr, x7, #0, #0
1ac: d3407cff ubfm xzr, x7, #0, #31
1b0: d340fcff ubfm xzr, x7, #0, #63
1b4: d36080ff ubfm xzr, x7, #32, #32
1b8: d360bcff ubfm xzr, x7, #32, #47
1bc: d360fcff ubfm xzr, x7, #32, #63
1c0: d37ffcff ubfm xzr, x7, #63, #63

26
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#objdump: -dr
#as: -march=armv8+crypto
.*: file format .*
Disassembly of section \.text:
0000000000000000 <.*>:
0: 4e284be7 aese v7.16b, v31.16b
4: 4e285be7 aesd v7.16b, v31.16b
8: 4e286be7 aesmc v7.16b, v31.16b
c: 4e287be7 aesimc v7.16b, v31.16b
10: 5e280be7 sha1h s7, s31
14: 5e281be7 sha1su1 v7.4s, v31.4s
18: 5e282be7 sha256su0 v7.4s, v31.4s
1c: 5e1f01e7 sha1c q7, s15, v31.4s
20: 5e1f11e7 sha1p q7, s15, v31.4s
24: 5e1f21e7 sha1m q7, s15, v31.4s
28: 5e1f31e7 sha1su0 v7.4s, v15.4s, v31.4s
2c: 5e1f41e7 sha256h q7, q15, v31.4s
30: 5e1f51e7 sha256h2 q7, q15, v31.4s
34: 5e1f61e7 sha256su1 v7.4s, v15.4s, v31.4s
38: 0e3fe1e7 pmull v7.8h, v15.8b, v31.8b
3c: 0effe1e7 pmull v7.1q, v15.1d, v31.1d
40: 4e3fe1e7 pmull2 v7.8h, v15.16b, v31.16b
44: 4effe1e7 pmull2 v7.1q, v15.2d, v31.2d

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/* crypto.s Test file for AArch64 Advanced-SIMD Crypto instructions.
Copyright 2012 Free Software Foundation, Inc. Contributed by ARM Ltd.
This file is part of GAS.
GAS is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the license, or
(at your option) any later version.
GAS is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; see the file COPYING3. If not,
see <http://www.gnu.org/licenses/>. */
.text
aese v7.16b, v31.16b
aesd v7.16b, v31.16b
aesmc v7.16b, v31.16b
aesimc v7.16b, v31.16b
sha1h s7, s31
sha1su1 v7.4s, v31.4s
sha256su0 v7.4s, v31.4s
sha1c q7, s15, v31.4s
sha1p q7, s15, v31.4s
sha1m q7, s15, v31.4s
sha1su0 v7.4s, v15.4s, v31.4s
sha256h q7, q15, v31.4s
sha256h2 q7, q15, v31.4s
sha256su1 v7.4s, v15.4s, v31.4s
pmull v7.8h, v15.8b, v31.8b
pmull v7.1q, v15.1d, v31.1d
pmull2 v7.8h, v15.16b, v31.16b
pmull2 v7.1q, v15.2d, v31.2d

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gas/testsuite/gas/aarch64/diagnostic.d Normal file
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#name: Diagnostics Quality
#source: diagnostic.s
#error-output: diagnostic.l

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[^:]*: Assembler messages:
[^:]*:4: Error: unexpected comma after the mnemonic name `fmul' -- `fmul, s0,s1,s2'
[^:]*:5: Error: unexpected comma after the mnemonic name `fmul' -- `fmul ,s0,s1,s2'
[^:]*:6: Error: unexpected comma after the mnemonic name `fmul' -- `fmul ,s0,s1,s2'
[^:]*:7: Error: unknown mnemonic `b\.random' -- `b\.random label1'
[^:]*:8: Error: unknown mnemonic `fmull' -- `fmull s0'
[^:]*:9: Error: unknown mnemonic `aaaaaaaaaaaaaaaaaaaaaaaaaaaa\.\.\.' -- `aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa'
[^:]*:10: Error: unexpected comma before the omitted optional operand at operand 5 -- `sys 1,c1,c3,3,'
[^:]*:11: Error: immediate value out of range 0 to 7 at operand 4 -- `ext v0.8b,v1.8b,v2.8b,8'
[^:]*:12: Error: immediate value out of range 0 to 15 at operand 4 -- `ext v0.16b,v1.16b,v2.16b,20'
[^:]*:13: Error: immediate value out of range 0 to 65535 at operand 1 -- `svc -1'
[^:]*:14: Error: immediate value out of range 0 to 65535 at operand 1 -- `svc 65536'
[^:]*:15: Error: immediate value out of range 0 to 31 at operand 2 -- `ccmp w0,32,10,le'
[^:]*:16: Error: immediate value out of range 0 to 31 at operand 2 -- `ccmp x0,-1,10,le'
[^:]*:17: Error: extraneous register at operand 2 -- `tlbi alle3is,x0'
[^:]*:18: Error: missing register at operand 2 -- `tlbi vaale1is'
[^:]*:19: Error: unexpected characters following instruction at operand 1 -- `tlbi vaale1is x0'
[^:]*:20: Error: immediate value out of range 0 to 1 at operand 1 -- `msr spsel,3'
[^:]*:21: Error: immediate value out of range 1 to 64 at operand 3 -- `fcvtzu x15,d31,#66'
[^:]*:22: Error: immediate value out of range 1 to 32 at operand 3 -- `scvtf s0,w0,33'
[^:]*:23: Error: immediate value out of range 1 to 32 at operand 3 -- `scvtf s0,w0,0'
[^:]*:24: Error: register number out of range 0 to 15 at operand 3 -- `smlal v0.4s,v31.4h,v16.h\[1\]'
[^:]*:25: Error: register element index out of range 0 to 7 at operand 3 -- `smlal v0.4s,v31.4h,v15.h\[8\]'
[^:]*:26: Error: extend operator expected at operand 3 -- `add sp,x0,x7,lsr#2'
[^:]*:27: Error: shift amount out of range 0 to 4 at operand 3 -- `add x0,x0,x7,uxtx#5'
[^:]*:28: Error: 'ROR' operator not allowed at operand 3 -- `add x0,xzr,x7,ror#5'
[^:]*:29: Error: shift amount out of range 0 to 31 at operand 3 -- `add w0,wzr,w7,asr#32'
[^:]*:30: Error: invalid post-increment amount at operand 2 -- `st2 \{v0.4s,v1.4s\},\[sp\],#24'
[^:]*:31: Error: invalid shift amount at operand 2 -- `ldr q0,\[x0,w0,uxtw#5\]'
[^:]*:32: Error: invalid number of registers in the list; 2 registers are expected at operand 1 -- `st2 \{v0.4s,v1.4s,v2.4s,v3.4s\},\[sp\],#64'
[^:]*:33: Error: shift amount expected to be 0 or 12 at operand 3 -- `adds x1,sp,2134,lsl#4'
[^:]*:34: Error: shift amount should be a multiple of 16 at operand 2 -- `movz w0,2134,lsl#8'
[^:]*:35: Error: shift amount out of range 0 to 16 at operand 2 -- `movz w0,2134,lsl#32'
[^:]*:36: Error: shift amount should be a multiple of 16 at operand 2 -- `movz x0,2134,lsl#47'
[^:]*:37: Error: immediate value out of range 1 to 17 at operand 4 -- `sbfiz w0,w7,15,18'
[^:]*:38: Error: immediate value out of range 1 to 32 at operand 4 -- `sbfiz w0,w7,15,0'
[^:]*:39: Error: invalid shift amount at operand 3 -- `shll v1.4s,v2.4h,#15'
[^:]*:40: Error: invalid shift amount at operand 3 -- `shll v1.4s,v2.4h,#32'
[^:]*:41: Error: immediate value out of range 0 to 31 at operand 3 -- `shl v1.2s,v2.2s,32'
[^:]*:42: Error: immediate value out of range 1 to 8 at operand 3 -- `sqshrn2 v2.16b,v3.8h,#17'
[^:]*:43: Error: immediate value out of range 0 to 255 at operand 2 -- `movi v1.4h,256'
[^:]*:44: Error: immediate value out of range 0 to 255 at operand 2 -- `movi v1.4h,-1'
[^:]*:45: Error: invalid shift operator at operand 2 -- `movi v1.4h,255,msl#8'
[^:]*:46: Error: invalid value for immediate at operand 2 -- `movi d0,256'
[^:]*:47: Error: immediate value should be a multiple of 8 at operand 2 -- `movi v1.4h,255,lsl#7'
[^:]*:48: Error: immediate value out of range 0 to 8 at operand 2 -- `movi v1.4h,255,lsl#16'
[^:]*:49: Error: shift amount expected to be 0 or 16 at operand 2 -- `movi v2.2s,255,msl#0'
[^:]*:50: Error: shift amount expected to be 0 or 16 at operand 2 -- `movi v2.2s,255,msl#15'
[^:]*:51: Error: invalid floating-point constant at operand 2 -- `fmov v1.2s,1.01'
[^:]*:52: Error: invalid floating-point constant at operand 2 -- `fmov v1.2d,1.01'
[^:]*:53: Error: invalid floating-point constant at operand 2 -- `fmov s3,1.01'
[^:]*:54: Error: invalid floating-point constant at operand 2 -- `fmov d3,1.01'
[^:]*:55: Error: immediate zero expected at operand 2 -- `fcmp d0,#1.0'
[^:]*:56: Error: operand 2 should be a floating-point register -- `fcmp d0,x0'
[^:]*:57: Error: immediate zero expected at operand 3 -- `cmgt v0.4s,v2.4s,#1'
[^:]*:58: Error: unexpected characters following instruction at operand 2 -- `fmov d3,1.00,lsl#3'
[^:]*:59: Error: writeback value should be an immediate constant at operand 2 -- `st2 {v0.4s,v1.4s},\[sp\],sp'
[^:]*:60: Error: writeback value should be an immediate constant at operand 2 -- `st2 {v0.4s,v1.4s},\[sp\],zr'
[^:]*:61: Error: invalid shift for the register offset addressing mode at operand 2 -- `ldr q0,\[x0,w0,lsr#4\]'
[^:]*:62: Error: only 'LSL' shift is permitted at operand 3 -- `adds x1,sp,2134,uxtw#12'
[^:]*:63: Error: shift amount out of range 0 to 63 at operand 2 -- `movz x0,2134,lsl#64'
[^:]*:64: Error: operand 1 should be an integer register -- `adds sp,sp,2134,lsl#12'
[^:]*:65: Error: the optional immediate offset can only be 0 at operand 2 -- `ldxrb w2,\[x0,#1\]'
[^:]*:66: Error: invalid addressing mode at operand 2 -- `ldrb w0,x1,x2,sxtx'
[^:]*:67: Error: invalid shift amount at operand 2 -- `prfm PLDL3KEEP,\[x9,x15,sxtx#2\]'
[^:]*:68: Error: C0 - C15 expected at operand 3 -- `sysl x7,#1,C16,C30,#1'
[^:]*:69: Error: operand 4 should be a 4-bit opcode field named for historical reasons C0 - C15 -- `sysl x7,#1,C15,C77,#1'
[^:]*:70: Error: extending shift is not permitted at operand 3 -- `add x0,xzr,x7,uxtx#5'
[^:]*:71: Error: bad expression at operand 2 -- `mov x0,##5'
[^:]*:72: Error: unknown mnemonic `bad' -- `bad expression'
[^:]*:73: Error: unknown mnemonic `mockup' -- `mockup-op'
[^:]*:74: Error: comma expected between operands at operand 2 -- `orr x0. x0,#0xff,lsl#1'
[^:]*:75: Error: the specified relocation type is not allowed for MOVK at operand 2 -- `movk x1,#:abs_g1_s:s12'
[^:]*:76: Error: can't mix relocation modifier with explicit shift at operand 2 -- `movz x1,#:abs_g1_s:s12,lsl#16'
[^:]*:77: Error: register offset not allowed in pre-indexed addressing mode at operand 2 -- `prfm pldl3strm,\[sp,w0,sxtw#3\]!'
[^:]*:78: Error: immediate value out of range 0 to 31 at operand 1 -- `prfm 0x2f,LABEL1'
[^:]*:79: Error: immediate value out of range 0 to 15 at operand 1 -- `dmb #16'
[^:]*:80: Error: immediate value out of range 0 to 31 at operand 2 -- `tbz w0,#40,0x17c'
[^:]*:81: Error: invalid number of registers in the list; 2 registers are expected at operand 1 -- `st2 \{v4.2d,v5.2d,v6.2d\},\[x3\]'
[^:]*:82: Error: invalid register list at operand 1 -- `ld2 \{v1.4h,v0.4h\},\[x1\]'
[^:]*:83: Error: the specified option is not accepted in ISB at operand 1 -- `isb osh'
[^:]*:84: Error: invalid address at operand 2 -- `st2 \{v4.2d,v5.2d,v6.2d\},\\\[x3\\\]'
[^:]*:85: Error: immediate value should be a multiple of 4 at operand 3 -- `ldnp w7,w15,\[x3,#3\]'
[^:]*:86: Error: unexpected address writeback at operand 3 -- `stnp x7,x15,\[x3,#32\]!'
[^:]*:87: Error: immediate offset out of range -256 to 252 at operand 3 -- `ldnp w7,w15,\[x3,#256\]'
[^:]*:88: Error: shift is not permitted at operand 2 -- `movi v1.2d,4294967295,lsl#0'
[^:]*:89: Error: shift amount non-zero at operand 2 -- `movi v1.8b,97,lsl#8'

89
gas/testsuite/gas/aarch64/diagnostic.s Normal file
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// diagnostic.s Test file for diagnostic quality.
.text
fmul, s0, s1, s2
fmul , s0, s1, s2
fmul , s0, s1, s2
b.random label1
fmull s0
aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa
sys 1,c1,c3,3,
ext v0.8b, v1.8b, v2.8b, 8
ext v0.16b, v1.16b, v2.16b, 20
svc -1
svc 65536
ccmp w0, 32, 10, le
ccmp x0, -1, 10, le
tlbi alle3is, x0
tlbi vaale1is
tlbi vaale1is x0
msr spsel, 3
fcvtzu x15, d31, #66
scvtf s0, w0, 33
scvtf s0, w0, 0
smlal v0.4s, v31.4h, v16.h[1]
smlal v0.4s, v31.4h, v15.h[8]
add sp, x0, x7, lsr #2
add x0, x0, x7, uxtx #5
add x0, xzr, x7, ror #5
add w0, wzr, w7, asr #32
st2 {v0.4s, v1.4s}, [sp], #24
ldr q0, [x0, w0, uxtw #5]
st2 {v0.4s, v1.4s, v2.4s, v3.4s}, [sp], #64
adds x1, sp, 2134, lsl #4
movz w0, 2134, lsl #8
movz w0, 2134, lsl #32
movz x0, 2134, lsl #47
sbfiz w0, w7, 15, 18
sbfiz w0, w7, 15, 0
shll v1.4s, v2.4h, #15
shll v1.4s, v2.4h, #32
shl v1.2s, v2.2s, 32
sqshrn2 v2.16b, v3.8h, #17
movi v1.4h, 256
movi v1.4h, -1
movi v1.4h, 255, msl #8
movi d0, 256
movi v1.4h, 255, lsl #7
movi v1.4h, 255, lsl #16
movi v2.2s, 255, msl #0
movi v2.2s, 255, msl #15
fmov v1.2s, 1.01
fmov v1.2d, 1.01
fmov s3, 1.01
fmov d3, 1.01
fcmp d0, #1.0
fcmp d0, x0
cmgt v0.4s, v2.4s, #1
fmov d3, 1.00, lsl #3
st2 {v0.4s, v1.4s}, [sp], sp
st2 {v0.4s, v1.4s}, [sp], zr
ldr q0, [x0, w0, lsr #4]
adds x1, sp, 2134, uxtw #12
movz x0, 2134, lsl #64
adds sp, sp, 2134, lsl #12
ldxrb w2, [x0, #1]
ldrb w0, x1, x2, sxtx
prfm PLDL3KEEP, [x9, x15, sxtx #2]
sysl x7, #1, C16, C30, #1
sysl x7, #1, C15, C77, #1
add x0, xzr, x7, uxtx #5
mov x0, ##5
bad expression
mockup-op
orr x0. x0, #0xff, lsl #1
movk x1, #:abs_g1_s:s12
movz x1, #:abs_g1_s:s12, lsl #16
prfm pldl3strm, [sp, w0, sxtw #3]!
prfm 0x2f, LABEL1
dmb #16
tbz w0, #40, 0x17c
st2 {v4.2d, v5.2d, v6.2d}, [x3]
ld2 {v1.4h, v0.4h}, [x1]
isb osh
st2 {v4.2d, v5.2d, v6.2d}, \[x3\]
ldnp w7, w15, [x3, #3]
stnp x7, x15, [x3, #32]!
ldnp w7, w15, [x3, #256]
movi v1.2d, 4294967295, lsl #0
movi v1.8b, 97, lsl #8

25
gas/testsuite/gas/aarch64/floatdp2.d Normal file
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#objdump: -dr
.*: file format .*
Disassembly of section \.text:
0000000000000000 <.*>:
0: 1e2f08e0 fmul s0, s7, s15
4: 1e2f18e0 fdiv s0, s7, s15
8: 1e2f28e0 fadd s0, s7, s15
c: 1e2f38e0 fsub s0, s7, s15
10: 1e2f48e0 fmax s0, s7, s15
14: 1e2f58e0 fmin s0, s7, s15
18: 1e2f68e0 fmaxnm s0, s7, s15
1c: 1e2f78e0 fminnm s0, s7, s15
20: 1e2f88e0 fnmul s0, s7, s15
24: 1e6f08e0 fmul d0, d7, d15
28: 1e6f18e0 fdiv d0, d7, d15
2c: 1e6f28e0 fadd d0, d7, d15
30: 1e6f38e0 fsub d0, d7, d15
34: 1e6f48e0 fmax d0, d7, d15
38: 1e6f58e0 fmin d0, d7, d15
3c: 1e6f68e0 fmaxnm d0, d7, d15
40: 1e6f78e0 fminnm d0, d7, d15
44: 1e6f88e0 fnmul d0, d7, d15

32
gas/testsuite/gas/aarch64/floatdp2.s Normal file
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/* floatdp2.s Test file for AArch64 Floating-point data-processing
(2 source) instructions.
Copyright 2011, 2012 Free Software Foundation, Inc.
Contributed by ARM Ltd.
This file is part of GAS.
GAS is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the license, or
(at your option) any later version.
GAS is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; see the file COPYING3. If not,
see <http://www.gnu.org/licenses/>. */
.macro floatdp2 op, type
\op \type\()0, \type\()7, \type\()15
.endm
.text
.irp type, S, D
.irp op, FMUL, FDIV, FADD, FSUB, FMAX, FMIN, FMAXNM, FMINNM, FNMUL
floatdp2 \op, \type
.endr
.endr

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gas/testsuite/gas/aarch64/fp_cvt_int.d Normal file
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#objdump: -dr
.*: file format .*
Disassembly of section \.text:
0000000000000000 <.*>:
0: 1e2000e7 fcvtns w7, s7
4: 9e2000e7 fcvtns x7, s7
8: 1e2100e7 fcvtnu w7, s7
c: 9e2100e7 fcvtnu x7, s7
10: 1e2800e7 fcvtps w7, s7
14: 9e2800e7 fcvtps x7, s7
18: 1e2900e7 fcvtpu w7, s7
1c: 9e2900e7 fcvtpu x7, s7
20: 1e3000e7 fcvtms w7, s7
24: 9e3000e7 fcvtms x7, s7
28: 1e3100e7 fcvtmu w7, s7
2c: 9e3100e7 fcvtmu x7, s7
30: 1e3800e7 fcvtzs w7, s7
34: 9e3800e7 fcvtzs x7, s7
38: 1e3900e7 fcvtzu w7, s7
3c: 9e3900e7 fcvtzu x7, s7
40: 1e2200e7 scvtf s7, w7
44: 9e2200e7 scvtf s7, x7
48: 1e2300e7 ucvtf s7, w7
4c: 9e2300e7 ucvtf s7, x7
50: 1e2400e7 fcvtas w7, s7
54: 9e2400e7 fcvtas x7, s7
58: 1e2500e7 fcvtau w7, s7
5c: 9e2500e7 fcvtau x7, s7
60: 1e2600e7 fmov w7, s7
64: 1e2700e7 fmov s7, w7
68: 1e6000e7 fcvtns w7, d7
6c: 9e6000e7 fcvtns x7, d7
70: 1e6100e7 fcvtnu w7, d7
74: 9e6100e7 fcvtnu x7, d7
78: 1e6800e7 fcvtps w7, d7
7c: 9e6800e7 fcvtps x7, d7
80: 1e6900e7 fcvtpu w7, d7
84: 9e6900e7 fcvtpu x7, d7
88: 1e7000e7 fcvtms w7, d7
8c: 9e7000e7 fcvtms x7, d7
90: 1e7100e7 fcvtmu w7, d7
94: 9e7100e7 fcvtmu x7, d7
98: 1e7800e7 fcvtzs w7, d7
9c: 9e7800e7 fcvtzs x7, d7
a0: 1e7900e7 fcvtzu w7, d7
a4: 9e7900e7 fcvtzu x7, d7
a8: 1e6200e7 scvtf d7, w7
ac: 9e6200e7 scvtf d7, x7
b0: 1e6300e7 ucvtf d7, w7
b4: 9e6300e7 ucvtf d7, x7
b8: 1e6400e7 fcvtas w7, d7
bc: 9e6400e7 fcvtas x7, d7
c0: 1e6500e7 fcvtau w7, d7
c4: 9e6500e7 fcvtau x7, d7
c8: 1e2600e7 fmov w7, s7
cc: 1e2700e7 fmov s7, w7
d0: 1e18fce7 fcvtzs w7, s7, #1
d4: 9e18fce7 fcvtzs x7, s7, #1
d8: 1e19fce7 fcvtzu w7, s7, #1
dc: 9e19fce7 fcvtzu x7, s7, #1
e0: 1e02fce7 scvtf s7, w7, #1
e4: 9e02fce7 scvtf s7, x7, #1
e8: 1e03fce7 ucvtf s7, w7, #1
ec: 9e03fce7 ucvtf s7, x7, #1
f0: 1e58fce7 fcvtzs w7, d7, #1
f4: 9e58fce7 fcvtzs x7, d7, #1
f8: 1e59fce7 fcvtzu w7, d7, #1
fc: 9e59fce7 fcvtzu x7, d7, #1
100: 1e42fce7 scvtf d7, w7, #1
104: 9e42fce7 scvtf d7, x7, #1
108: 1e43fce7 ucvtf d7, w7, #1
10c: 9e43fce7 ucvtf d7, x7, #1
110: 1e18f8e7 fcvtzs w7, s7, #2
114: 9e18f8e7 fcvtzs x7, s7, #2
118: 1e19f8e7 fcvtzu w7, s7, #2
11c: 9e19f8e7 fcvtzu x7, s7, #2
120: 1e02f8e7 scvtf s7, w7, #2
124: 9e02f8e7 scvtf s7, x7, #2
128: 1e03f8e7 ucvtf s7, w7, #2
12c: 9e03f8e7 ucvtf s7, x7, #2
130: 1e58f8e7 fcvtzs w7, d7, #2
134: 9e58f8e7 fcvtzs x7, d7, #2
138: 1e59f8e7 fcvtzu w7, d7, #2
13c: 9e59f8e7 fcvtzu x7, d7, #2
140: 1e42f8e7 scvtf d7, w7, #2
144: 9e42f8e7 scvtf d7, x7, #2
148: 1e43f8e7 ucvtf d7, w7, #2
14c: 9e43f8e7 ucvtf d7, x7, #2
150: 1e18f4e7 fcvtzs w7, s7, #3
154: 9e18f4e7 fcvtzs x7, s7, #3
158: 1e19f4e7 fcvtzu w7, s7, #3
15c: 9e19f4e7 fcvtzu x7, s7, #3
160: 1e02f4e7 scvtf s7, w7, #3
164: 9e02f4e7 scvtf s7, x7, #3
168: 1e03f4e7 ucvtf s7, w7, #3
16c: 9e03f4e7 ucvtf s7, x7, #3
170: 1e58f4e7 fcvtzs w7, d7, #3
174: 9e58f4e7 fcvtzs x7, d7, #3
178: 1e59f4e7 fcvtzu w7, d7, #3
17c: 9e59f4e7 fcvtzu x7, d7, #3
180: 1e42f4e7 scvtf d7, w7, #3
184: 9e42f4e7 scvtf d7, x7, #3
188: 1e43f4e7 ucvtf d7, w7, #3
18c: 9e43f4e7 ucvtf d7, x7, #3
190: 1e18f0e7 fcvtzs w7, s7, #4
194: 9e18f0e7 fcvtzs x7, s7, #4
198: 1e19f0e7 fcvtzu w7, s7, #4
19c: 9e19f0e7 fcvtzu x7, s7, #4
1a0: 1e02f0e7 scvtf s7, w7, #4
1a4: 9e02f0e7 scvtf s7, x7, #4
1a8: 1e03f0e7 ucvtf s7, w7, #4
1ac: 9e03f0e7 ucvtf s7, x7, #4
1b0: 1e58f0e7 fcvtzs w7, d7, #4
1b4: 9e58f0e7 fcvtzs x7, d7, #4
1b8: 1e59f0e7 fcvtzu w7, d7, #4
1bc: 9e59f0e7 fcvtzu x7, d7, #4
1c0: 1e42f0e7 scvtf d7, w7, #4
1c4: 9e42f0e7 scvtf d7, x7, #4
1c8: 1e43f0e7 ucvtf d7, w7, #4
1cc: 9e43f0e7 ucvtf d7, x7, #4
1d0: 1e18ece7 fcvtzs w7, s7, #5
1d4: 9e18ece7 fcvtzs x7, s7, #5
1d8: 1e19ece7 fcvtzu w7, s7, #5
1dc: 9e19ece7 fcvtzu x7, s7, #5
1e0: 1e02ece7 scvtf s7, w7, #5
1e4: 9e02ece7 scvtf s7, x7, #5
1e8: 1e03ece7 ucvtf s7, w7, #5
1ec: 9e03ece7 ucvtf s7, x7, #5
1f0: 1e58ece7 fcvtzs w7, d7, #5
1f4: 9e58ece7 fcvtzs x7, d7, #5
1f8: 1e59ece7 fcvtzu w7, d7, #5
1fc: 9e59ece7 fcvtzu x7, d7, #5
200: 1e42ece7 scvtf d7, w7, #5
204: 9e42ece7 scvtf d7, x7, #5
208: 1e43ece7 ucvtf d7, w7, #5
20c: 9e43ece7 ucvtf d7, x7, #5
210: 1e18e8e7 fcvtzs w7, s7, #6
214: 9e18e8e7 fcvtzs x7, s7, #6
218: 1e19e8e7 fcvtzu w7, s7, #6
21c: 9e19e8e7 fcvtzu x7, s7, #6
220: 1e02e8e7 scvtf s7, w7, #6
224: 9e02e8e7 scvtf s7, x7, #6
228: 1e03e8e7 ucvtf s7, w7, #6
22c: 9e03e8e7 ucvtf s7, x7, #6
230: 1e58e8e7 fcvtzs w7, d7, #6
234: 9e58e8e7 fcvtzs x7, d7, #6
238: 1e59e8e7 fcvtzu w7, d7, #6
23c: 9e59e8e7 fcvtzu x7, d7, #6
240: 1e42e8e7 scvtf d7, w7, #6
244: 9e42e8e7 scvtf d7, x7, #6
248: 1e43e8e7 ucvtf d7, w7, #6
24c: 9e43e8e7 ucvtf d7, x7, #6
250: 1e18e4e7 fcvtzs w7, s7, #7
254: 9e18e4e7 fcvtzs x7, s7, #7
258: 1e19e4e7 fcvtzu w7, s7, #7
25c: 9e19e4e7 fcvtzu x7, s7, #7
260: 1e02e4e7 scvtf s7, w7, #7
264: 9e02e4e7 scvtf s7, x7, #7
268: 1e03e4e7 ucvtf s7, w7, #7
26c: 9e03e4e7 ucvtf s7, x7, #7
270: 1e58e4e7 fcvtzs w7, d7, #7
274: 9e58e4e7 fcvtzs x7, d7, #7
278: 1e59e4e7 fcvtzu w7, d7, #7
27c: 9e59e4e7 fcvtzu x7, d7, #7
280: 1e42e4e7 scvtf d7, w7, #7
284: 9e42e4e7 scvtf d7, x7, #7
288: 1e43e4e7 ucvtf d7, w7, #7
28c: 9e43e4e7 ucvtf d7, x7, #7
290: 1e18e0e7 fcvtzs w7, s7, #8
294: 9e18e0e7 fcvtzs x7, s7, #8
298: 1e19e0e7 fcvtzu w7, s7, #8
29c: 9e19e0e7 fcvtzu x7, s7, #8
2a0: 1e02e0e7 scvtf s7, w7, #8
2a4: 9e02e0e7 scvtf s7, x7, #8
2a8: 1e03e0e7 ucvtf s7, w7, #8
2ac: 9e03e0e7 ucvtf s7, x7, #8
2b0: 1e58e0e7 fcvtzs w7, d7, #8
2b4: 9e58e0e7 fcvtzs x7, d7, #8
2b8: 1e59e0e7 fcvtzu w7, d7, #8
2bc: 9e59e0e7 fcvtzu x7, d7, #8
2c0: 1e42e0e7 scvtf d7, w7, #8
2c4: 9e42e0e7 scvtf d7, x7, #8
2c8: 1e43e0e7 ucvtf d7, w7, #8
2cc: 9e43e0e7 ucvtf d7, x7, #8
2d0: 1e18dce7 fcvtzs w7, s7, #9
2d4: 9e18dce7 fcvtzs x7, s7, #9
2d8: 1e19dce7 fcvtzu w7, s7, #9
2dc: 9e19dce7 fcvtzu x7, s7, #9
2e0: 1e02dce7 scvtf s7, w7, #9
2e4: 9e02dce7 scvtf s7, x7, #9
2e8: 1e03dce7 ucvtf s7, w7, #9
2ec: 9e03dce7 ucvtf s7, x7, #9
2f0: 1e58dce7 fcvtzs w7, d7, #9
2f4: 9e58dce7 fcvtzs x7, d7, #9
2f8: 1e59dce7 fcvtzu w7, d7, #9
2fc: 9e59dce7 fcvtzu x7, d7, #9
300: 1e42dce7 scvtf d7, w7, #9
304: 9e42dce7 scvtf d7, x7, #9
308: 1e43dce7 ucvtf d7, w7, #9
30c: 9e43dce7 ucvtf d7, x7, #9
310: 1e18d8e7 fcvtzs w7, s7, #10
314: 9e18d8e7 fcvtzs x7, s7, #10
318: 1e19d8e7 fcvtzu w7, s7, #10
31c: 9e19d8e7 fcvtzu x7, s7, #10
320: 1e02d8e7 scvtf s7, w7, #10
324: 9e02d8e7 scvtf s7, x7, #10
328: 1e03d8e7 ucvtf s7, w7, #10
32c: 9e03d8e7 ucvtf s7, x7, #10
330: 1e58d8e7 fcvtzs w7, d7, #10
334: 9e58d8e7 fcvtzs x7, d7, #10
338: 1e59d8e7 fcvtzu w7, d7, #10
33c: 9e59d8e7 fcvtzu x7, d7, #10
340: 1e42d8e7 scvtf d7, w7, #10
344: 9e42d8e7 scvtf d7, x7, #10
348: 1e43d8e7 ucvtf d7, w7, #10
34c: 9e43d8e7 ucvtf d7, x7, #10
350: 1e18d4e7 fcvtzs w7, s7, #11
354: 9e18d4e7 fcvtzs x7, s7, #11
358: 1e19d4e7 fcvtzu w7, s7, #11
35c: 9e19d4e7 fcvtzu x7, s7, #11
360: 1e02d4e7 scvtf s7, w7, #11
364: 9e02d4e7 scvtf s7, x7, #11
368: 1e03d4e7 ucvtf s7, w7, #11
36c: 9e03d4e7 ucvtf s7, x7, #11
370: 1e58d4e7 fcvtzs w7, d7, #11
374: 9e58d4e7 fcvtzs x7, d7, #11
378: 1e59d4e7 fcvtzu w7, d7, #11
37c: 9e59d4e7 fcvtzu x7, d7, #11
380: 1e42d4e7 scvtf d7, w7, #11
384: 9e42d4e7 scvtf d7, x7, #11
388: 1e43d4e7 ucvtf d7, w7, #11
38c: 9e43d4e7 ucvtf d7, x7, #11
390: 1e18d0e7 fcvtzs w7, s7, #12
394: 9e18d0e7 fcvtzs x7, s7, #12
398: 1e19d0e7 fcvtzu w7, s7, #12
39c: 9e19d0e7 fcvtzu x7, s7, #12
3a0: 1e02d0e7 scvtf s7, w7, #12
3a4: 9e02d0e7 scvtf s7, x7, #12
3a8: 1e03d0e7 ucvtf s7, w7, #12
3ac: 9e03d0e7 ucvtf s7, x7, #12
3b0: 1e58d0e7 fcvtzs w7, d7, #12
3b4: 9e58d0e7 fcvtzs x7, d7, #12
3b8: 1e59d0e7 fcvtzu w7, d7, #12
3bc: 9e59d0e7 fcvtzu x7, d7, #12
3c0: 1e42d0e7 scvtf d7, w7, #12
3c4: 9e42d0e7 scvtf d7, x7, #12
3c8: 1e43d0e7 ucvtf d7, w7, #12
3cc: 9e43d0e7 ucvtf d7, x7, #12
3d0: 1e18cce7 fcvtzs w7, s7, #13
3d4: 9e18cce7 fcvtzs x7, s7, #13
3d8: 1e19cce7 fcvtzu w7, s7, #13
3dc: 9e19cce7 fcvtzu x7, s7, #13
3e0: 1e02cce7 scvtf s7, w7, #13
3e4: 9e02cce7 scvtf s7, x7, #13
3e8: 1e03cce7 ucvtf s7, w7, #13
3ec: 9e03cce7 ucvtf s7, x7, #13
3f0: 1e58cce7 fcvtzs w7, d7, #13
3f4: 9e58cce7 fcvtzs x7, d7, #13
3f8: 1e59cce7 fcvtzu w7, d7, #13
3fc: 9e59cce7 fcvtzu x7, d7, #13
400: 1e42cce7 scvtf d7, w7, #13
404: 9e42cce7 scvtf d7, x7, #13
408: 1e43cce7 ucvtf d7, w7, #13
40c: 9e43cce7 ucvtf d7, x7, #13
410: 1e18c8e7 fcvtzs w7, s7, #14
414: 9e18c8e7 fcvtzs x7, s7, #14
418: 1e19c8e7 fcvtzu w7, s7, #14
41c: 9e19c8e7 fcvtzu x7, s7, #14
420: 1e02c8e7 scvtf s7, w7, #14
424: 9e02c8e7 scvtf s7, x7, #14
428: 1e03c8e7 ucvtf s7, w7, #14
42c: 9e03c8e7 ucvtf s7, x7, #14
430: 1e58c8e7 fcvtzs w7, d7, #14
434: 9e58c8e7 fcvtzs x7, d7, #14
438: 1e59c8e7 fcvtzu w7, d7, #14
43c: 9e59c8e7 fcvtzu x7, d7, #14
440: 1e42c8e7 scvtf d7, w7, #14
444: 9e42c8e7 scvtf d7, x7, #14
448: 1e43c8e7 ucvtf d7, w7, #14
44c: 9e43c8e7 ucvtf d7, x7, #14
450: 1e18c4e7 fcvtzs w7, s7, #15
454: 9e18c4e7 fcvtzs x7, s7, #15
458: 1e19c4e7 fcvtzu w7, s7, #15
45c: 9e19c4e7 fcvtzu x7, s7, #15
460: 1e02c4e7 scvtf s7, w7, #15
464: 9e02c4e7 scvtf s7, x7, #15
468: 1e03c4e7 ucvtf s7, w7, #15
46c: 9e03c4e7 ucvtf s7, x7, #15
470: 1e58c4e7 fcvtzs w7, d7, #15
474: 9e58c4e7 fcvtzs x7, d7, #15
478: 1e59c4e7 fcvtzu w7, d7, #15
47c: 9e59c4e7 fcvtzu x7, d7, #15
480: 1e42c4e7 scvtf d7, w7, #15
484: 9e42c4e7 scvtf d7, x7, #15
488: 1e43c4e7 ucvtf d7, w7, #15
48c: 9e43c4e7 ucvtf d7, x7, #15
490: 1e18c0e7 fcvtzs w7, s7, #16
494: 9e18c0e7 fcvtzs x7, s7, #16
498: 1e19c0e7 fcvtzu w7, s7, #16
49c: 9e19c0e7 fcvtzu x7, s7, #16
4a0: 1e02c0e7 scvtf s7, w7, #16
4a4: 9e02c0e7 scvtf s7, x7, #16
4a8: 1e03c0e7 ucvtf s7, w7, #16
4ac: 9e03c0e7 ucvtf s7, x7, #16
4b0: 1e58c0e7 fcvtzs w7, d7, #16
4b4: 9e58c0e7 fcvtzs x7, d7, #16
4b8: 1e59c0e7 fcvtzu w7, d7, #16
4bc: 9e59c0e7 fcvtzu x7, d7, #16
4c0: 1e42c0e7 scvtf d7, w7, #16
4c4: 9e42c0e7 scvtf d7, x7, #16
4c8: 1e43c0e7 ucvtf d7, w7, #16
4cc: 9e43c0e7 ucvtf d7, x7, #16
4d0: 1e18bce7 fcvtzs w7, s7, #17
4d4: 9e18bce7 fcvtzs x7, s7, #17
4d8: 1e19bce7 fcvtzu w7, s7, #17
4dc: 9e19bce7 fcvtzu x7, s7, #17
4e0: 1e02bce7 scvtf s7, w7, #17
4e4: 9e02bce7 scvtf s7, x7, #17
4e8: 1e03bce7 ucvtf s7, w7, #17
4ec: 9e03bce7 ucvtf s7, x7, #17
4f0: 1e58bce7 fcvtzs w7, d7, #17
4f4: 9e58bce7 fcvtzs x7, d7, #17
4f8: 1e59bce7 fcvtzu w7, d7, #17
4fc: 9e59bce7 fcvtzu x7, d7, #17
500: 1e42bce7 scvtf d7, w7, #17
504: 9e42bce7 scvtf d7, x7, #17
508: 1e43bce7 ucvtf d7, w7, #17
50c: 9e43bce7 ucvtf d7, x7, #17
510: 1e18b8e7 fcvtzs w7, s7, #18
514: 9e18b8e7 fcvtzs x7, s7, #18
518: 1e19b8e7 fcvtzu w7, s7, #18
51c: 9e19b8e7 fcvtzu x7, s7, #18
520: 1e02b8e7 scvtf s7, w7, #18
524: 9e02b8e7 scvtf s7, x7, #18
528: 1e03b8e7 ucvtf s7, w7, #18
52c: 9e03b8e7 ucvtf s7, x7, #18
530: 1e58b8e7 fcvtzs w7, d7, #18
534: 9e58b8e7 fcvtzs x7, d7, #18
538: 1e59b8e7 fcvtzu w7, d7, #18
53c: 9e59b8e7 fcvtzu x7, d7, #18
540: 1e42b8e7 scvtf d7, w7, #18
544: 9e42b8e7 scvtf d7, x7, #18
548: 1e43b8e7 ucvtf d7, w7, #18
54c: 9e43b8e7 ucvtf d7, x7, #18
550: 1e18b4e7 fcvtzs w7, s7, #19
554: 9e18b4e7 fcvtzs x7, s7, #19
558: 1e19b4e7 fcvtzu w7, s7, #19
55c: 9e19b4e7 fcvtzu x7, s7, #19
560: 1e02b4e7 scvtf s7, w7, #19
564: 9e02b4e7 scvtf s7, x7, #19
568: 1e03b4e7 ucvtf s7, w7, #19
56c: 9e03b4e7 ucvtf s7, x7, #19
570: 1e58b4e7 fcvtzs w7, d7, #19
574: 9e58b4e7 fcvtzs x7, d7, #19
578: 1e59b4e7 fcvtzu w7, d7, #19
57c: 9e59b4e7 fcvtzu x7, d7, #19
580: 1e42b4e7 scvtf d7, w7, #19
584: 9e42b4e7 scvtf d7, x7, #19
588: 1e43b4e7 ucvtf d7, w7, #19
58c: 9e43b4e7 ucvtf d7, x7, #19
590: 1e18b0e7 fcvtzs w7, s7, #20
594: 9e18b0e7 fcvtzs x7, s7, #20
598: 1e19b0e7 fcvtzu w7, s7, #20
59c: 9e19b0e7 fcvtzu x7, s7, #20
5a0: 1e02b0e7 scvtf s7, w7, #20
5a4: 9e02b0e7 scvtf s7, x7, #20
5a8: 1e03b0e7 ucvtf s7, w7, #20
5ac: 9e03b0e7 ucvtf s7, x7, #20
5b0: 1e58b0e7 fcvtzs w7, d7, #20
5b4: 9e58b0e7 fcvtzs x7, d7, #20
5b8: 1e59b0e7 fcvtzu w7, d7, #20
5bc: 9e59b0e7 fcvtzu x7, d7, #20
5c0: 1e42b0e7 scvtf d7, w7, #20
5c4: 9e42b0e7 scvtf d7, x7, #20
5c8: 1e43b0e7 ucvtf d7, w7, #20
5cc: 9e43b0e7 ucvtf d7, x7, #20
5d0: 1e18ace7 fcvtzs w7, s7, #21
5d4: 9e18ace7 fcvtzs x7, s7, #21
5d8: 1e19ace7 fcvtzu w7, s7, #21
5dc: 9e19ace7 fcvtzu x7, s7, #21
5e0: 1e02ace7 scvtf s7, w7, #21
5e4: 9e02ace7 scvtf s7, x7, #21
5e8: 1e03ace7 ucvtf s7, w7, #21
5ec: 9e03ace7 ucvtf s7, x7, #21
5f0: 1e58ace7 fcvtzs w7, d7, #21
5f4: 9e58ace7 fcvtzs x7, d7, #21
5f8: 1e59ace7 fcvtzu w7, d7, #21
5fc: 9e59ace7 fcvtzu x7, d7, #21
600: 1e42ace7 scvtf d7, w7, #21
604: 9e42ace7 scvtf d7, x7, #21
608: 1e43ace7 ucvtf d7, w7, #21
60c: 9e43ace7 ucvtf d7, x7, #21
610: 1e18a8e7 fcvtzs w7, s7, #22
614: 9e18a8e7 fcvtzs x7, s7, #22
618: 1e19a8e7 fcvtzu w7, s7, #22
61c: 9e19a8e7 fcvtzu x7, s7, #22
620: 1e02a8e7 scvtf s7, w7, #22
624: 9e02a8e7 scvtf s7, x7, #22
628: 1e03a8e7 ucvtf s7, w7, #22
62c: 9e03a8e7 ucvtf s7, x7, #22
630: 1e58a8e7 fcvtzs w7, d7, #22
634: 9e58a8e7 fcvtzs x7, d7, #22
638: 1e59a8e7 fcvtzu w7, d7, #22
63c: 9e59a8e7 fcvtzu x7, d7, #22
640: 1e42a8e7 scvtf d7, w7, #22
644: 9e42a8e7 scvtf d7, x7, #22
648: 1e43a8e7 ucvtf d7, w7, #22
64c: 9e43a8e7 ucvtf d7, x7, #22
650: 1e18a4e7 fcvtzs w7, s7, #23
654: 9e18a4e7 fcvtzs x7, s7, #23
658: 1e19a4e7 fcvtzu w7, s7, #23
65c: 9e19a4e7 fcvtzu x7, s7, #23
660: 1e02a4e7 scvtf s7, w7, #23
664: 9e02a4e7 scvtf s7, x7, #23
668: 1e03a4e7 ucvtf s7, w7, #23
66c: 9e03a4e7 ucvtf s7, x7, #23
670: 1e58a4e7 fcvtzs w7, d7, #23
674: 9e58a4e7 fcvtzs x7, d7, #23
678: 1e59a4e7 fcvtzu w7, d7, #23
67c: 9e59a4e7 fcvtzu x7, d7, #23
680: 1e42a4e7 scvtf d7, w7, #23
684: 9e42a4e7 scvtf d7, x7, #23
688: 1e43a4e7 ucvtf d7, w7, #23
68c: 9e43a4e7 ucvtf d7, x7, #23
690: 1e18a0e7 fcvtzs w7, s7, #24
694: 9e18a0e7 fcvtzs x7, s7, #24
698: 1e19a0e7 fcvtzu w7, s7, #24
69c: 9e19a0e7 fcvtzu x7, s7, #24
6a0: 1e02a0e7 scvtf s7, w7, #24
6a4: 9e02a0e7 scvtf s7, x7, #24
6a8: 1e03a0e7 ucvtf s7, w7, #24
6ac: 9e03a0e7 ucvtf s7, x7, #24
6b0: 1e58a0e7 fcvtzs w7, d7, #24
6b4: 9e58a0e7 fcvtzs x7, d7, #24
6b8: 1e59a0e7 fcvtzu w7, d7, #24
6bc: 9e59a0e7 fcvtzu x7, d7, #24
6c0: 1e42a0e7 scvtf d7, w7, #24
6c4: 9e42a0e7 scvtf d7, x7, #24
6c8: 1e43a0e7 ucvtf d7, w7, #24
6cc: 9e43a0e7 ucvtf d7, x7, #24
6d0: 1e189ce7 fcvtzs w7, s7, #25
6d4: 9e189ce7 fcvtzs x7, s7, #25
6d8: 1e199ce7 fcvtzu w7, s7, #25
6dc: 9e199ce7 fcvtzu x7, s7, #25
6e0: 1e029ce7 scvtf s7, w7, #25
6e4: 9e029ce7 scvtf s7, x7, #25
6e8: 1e039ce7 ucvtf s7, w7, #25
6ec: 9e039ce7 ucvtf s7, x7, #25
6f0: 1e589ce7 fcvtzs w7, d7, #25
6f4: 9e589ce7 fcvtzs x7, d7, #25
6f8: 1e599ce7 fcvtzu w7, d7, #25
6fc: 9e599ce7 fcvtzu x7, d7, #25
700: 1e429ce7 scvtf d7, w7, #25
704: 9e429ce7 scvtf d7, x7, #25
708: 1e439ce7 ucvtf d7, w7, #25
70c: 9e439ce7 ucvtf d7, x7, #25
710: 1e1898e7 fcvtzs w7, s7, #26
714: 9e1898e7 fcvtzs x7, s7, #26
718: 1e1998e7 fcvtzu w7, s7, #26
71c: 9e1998e7 fcvtzu x7, s7, #26
720: 1e0298e7 scvtf s7, w7, #26
724: 9e0298e7 scvtf s7, x7, #26
728: 1e0398e7 ucvtf s7, w7, #26
72c: 9e0398e7 ucvtf s7, x7, #26
730: 1e5898e7 fcvtzs w7, d7, #26
734: 9e5898e7 fcvtzs x7, d7, #26
738: 1e5998e7 fcvtzu w7, d7, #26
73c: 9e5998e7 fcvtzu x7, d7, #26
740: 1e4298e7 scvtf d7, w7, #26
744: 9e4298e7 scvtf d7, x7, #26
748: 1e4398e7 ucvtf d7, w7, #26
74c: 9e4398e7 ucvtf d7, x7, #26
750: 1e1894e7 fcvtzs w7, s7, #27
754: 9e1894e7 fcvtzs x7, s7, #27
758: 1e1994e7 fcvtzu w7, s7, #27
75c: 9e1994e7 fcvtzu x7, s7, #27
760: 1e0294e7 scvtf s7, w7, #27
764: 9e0294e7 scvtf s7, x7, #27
768: 1e0394e7 ucvtf s7, w7, #27
76c: 9e0394e7 ucvtf s7, x7, #27
770: 1e5894e7 fcvtzs w7, d7, #27
774: 9e5894e7 fcvtzs x7, d7, #27
778: 1e5994e7 fcvtzu w7, d7, #27
77c: 9e5994e7 fcvtzu x7, d7, #27
780: 1e4294e7 scvtf d7, w7, #27
784: 9e4294e7 scvtf d7, x7, #27
788: 1e4394e7 ucvtf d7, w7, #27
78c: 9e4394e7 ucvtf d7, x7, #27
790: 1e1890e7 fcvtzs w7, s7, #28
794: 9e1890e7 fcvtzs x7, s7, #28
798: 1e1990e7 fcvtzu w7, s7, #28
79c: 9e1990e7 fcvtzu x7, s7, #28
7a0: 1e0290e7 scvtf s7, w7, #28
7a4: 9e0290e7 scvtf s7, x7, #28
7a8: 1e0390e7 ucvtf s7, w7, #28
7ac: 9e0390e7 ucvtf s7, x7, #28
7b0: 1e5890e7 fcvtzs w7, d7, #28
7b4: 9e5890e7 fcvtzs x7, d7, #28
7b8: 1e5990e7 fcvtzu w7, d7, #28
7bc: 9e5990e7 fcvtzu x7, d7, #28
7c0: 1e4290e7 scvtf d7, w7, #28
7c4: 9e4290e7 scvtf d7, x7, #28
7c8: 1e4390e7 ucvtf d7, w7, #28
7cc: 9e4390e7 ucvtf d7, x7, #28
7d0: 1e188ce7 fcvtzs w7, s7, #29
7d4: 9e188ce7 fcvtzs x7, s7, #29
7d8: 1e198ce7 fcvtzu w7, s7, #29
7dc: 9e198ce7 fcvtzu x7, s7, #29
7e0: 1e028ce7 scvtf s7, w7, #29
7e4: 9e028ce7 scvtf s7, x7, #29
7e8: 1e038ce7 ucvtf s7, w7, #29
7ec: 9e038ce7 ucvtf s7, x7, #29
7f0: 1e588ce7 fcvtzs w7, d7, #29
7f4: 9e588ce7 fcvtzs x7, d7, #29
7f8: 1e598ce7 fcvtzu w7, d7, #29
7fc: 9e598ce7 fcvtzu x7, d7, #29
800: 1e428ce7 scvtf d7, w7, #29
804: 9e428ce7 scvtf d7, x7, #29
808: 1e438ce7 ucvtf d7, w7, #29
80c: 9e438ce7 ucvtf d7, x7, #29
810: 1e1888e7 fcvtzs w7, s7, #30
814: 9e1888e7 fcvtzs x7, s7, #30
818: 1e1988e7 fcvtzu w7, s7, #30
81c: 9e1988e7 fcvtzu x7, s7, #30
820: 1e0288e7 scvtf s7, w7, #30
824: 9e0288e7 scvtf s7, x7, #30
828: 1e0388e7 ucvtf s7, w7, #30
82c: 9e0388e7 ucvtf s7, x7, #30
830: 1e5888e7 fcvtzs w7, d7, #30
834: 9e5888e7 fcvtzs x7, d7, #30
838: 1e5988e7 fcvtzu w7, d7, #30
83c: 9e5988e7 fcvtzu x7, d7, #30
840: 1e4288e7 scvtf d7, w7, #30
844: 9e4288e7 scvtf d7, x7, #30
848: 1e4388e7 ucvtf d7, w7, #30
84c: 9e4388e7 ucvtf d7, x7, #30
850: 1e1884e7 fcvtzs w7, s7, #31
854: 9e1884e7 fcvtzs x7, s7, #31
858: 1e1984e7 fcvtzu w7, s7, #31
85c: 9e1984e7 fcvtzu x7, s7, #31
860: 1e0284e7 scvtf s7, w7, #31
864: 9e0284e7 scvtf s7, x7, #31
868: 1e0384e7 ucvtf s7, w7, #31
86c: 9e0384e7 ucvtf s7, x7, #31
870: 1e5884e7 fcvtzs w7, d7, #31
874: 9e5884e7 fcvtzs x7, d7, #31
878: 1e5984e7 fcvtzu w7, d7, #31
87c: 9e5984e7 fcvtzu x7, d7, #31
880: 1e4284e7 scvtf d7, w7, #31
884: 9e4284e7 scvtf d7, x7, #31
888: 1e4384e7 ucvtf d7, w7, #31
88c: 9e4384e7 ucvtf d7, x7, #31
890: 1e1880e7 fcvtzs w7, s7, #32
894: 9e1880e7 fcvtzs x7, s7, #32
898: 1e1980e7 fcvtzu w7, s7, #32
89c: 9e1980e7 fcvtzu x7, s7, #32
8a0: 1e0280e7 scvtf s7, w7, #32
8a4: 9e0280e7 scvtf s7, x7, #32
8a8: 1e0380e7 ucvtf s7, w7, #32
8ac: 9e0380e7 ucvtf s7, x7, #32
8b0: 1e5880e7 fcvtzs w7, d7, #32
8b4: 9e5880e7 fcvtzs x7, d7, #32
8b8: 1e5980e7 fcvtzu w7, d7, #32
8bc: 9e5980e7 fcvtzu x7, d7, #32
8c0: 1e4280e7 scvtf d7, w7, #32
8c4: 9e4280e7 scvtf d7, x7, #32
8c8: 1e4380e7 ucvtf d7, w7, #32
8cc: 9e4380e7 ucvtf d7, x7, #32
8d0: 9e187ce7 fcvtzs x7, s7, #33
8d4: 9e197ce7 fcvtzu x7, s7, #33
8d8: 9e027ce7 scvtf s7, x7, #33
8dc: 9e037ce7 ucvtf s7, x7, #33
8e0: 9e587ce7 fcvtzs x7, d7, #33
8e4: 9e597ce7 fcvtzu x7, d7, #33
8e8: 9e427ce7 scvtf d7, x7, #33
8ec: 9e437ce7 ucvtf d7, x7, #33
8f0: 9e1878e7 fcvtzs x7, s7, #34
8f4: 9e1978e7 fcvtzu x7, s7, #34
8f8: 9e0278e7 scvtf s7, x7, #34
8fc: 9e0378e7 ucvtf s7, x7, #34
900: 9e5878e7 fcvtzs x7, d7, #34
904: 9e5978e7 fcvtzu x7, d7, #34
908: 9e4278e7 scvtf d7, x7, #34
90c: 9e4378e7 ucvtf d7, x7, #34
910: 9e1874e7 fcvtzs x7, s7, #35
914: 9e1974e7 fcvtzu x7, s7, #35
918: 9e0274e7 scvtf s7, x7, #35
91c: 9e0374e7 ucvtf s7, x7, #35
920: 9e5874e7 fcvtzs x7, d7, #35
924: 9e5974e7 fcvtzu x7, d7, #35
928: 9e4274e7 scvtf d7, x7, #35
92c: 9e4374e7 ucvtf d7, x7, #35
930: 9e1870e7 fcvtzs x7, s7, #36
934: 9e1970e7 fcvtzu x7, s7, #36
938: 9e0270e7 scvtf s7, x7, #36
93c: 9e0370e7 ucvtf s7, x7, #36
940: 9e5870e7 fcvtzs x7, d7, #36
944: 9e5970e7 fcvtzu x7, d7, #36
948: 9e4270e7 scvtf d7, x7, #36
94c: 9e4370e7 ucvtf d7, x7, #36
950: 9e186ce7 fcvtzs x7, s7, #37
954: 9e196ce7 fcvtzu x7, s7, #37
958: 9e026ce7 scvtf s7, x7, #37
95c: 9e036ce7 ucvtf s7, x7, #37
960: 9e586ce7 fcvtzs x7, d7, #37
964: 9e596ce7 fcvtzu x7, d7, #37
968: 9e426ce7 scvtf d7, x7, #37
96c: 9e436ce7 ucvtf d7, x7, #37
970: 9e1868e7 fcvtzs x7, s7, #38
974: 9e1968e7 fcvtzu x7, s7, #38
978: 9e0268e7 scvtf s7, x7, #38
97c: 9e0368e7 ucvtf s7, x7, #38
980: 9e5868e7 fcvtzs x7, d7, #38
984: 9e5968e7 fcvtzu x7, d7, #38
988: 9e4268e7 scvtf d7, x7, #38
98c: 9e4368e7 ucvtf d7, x7, #38
990: 9e1864e7 fcvtzs x7, s7, #39
994: 9e1964e7 fcvtzu x7, s7, #39
998: 9e0264e7 scvtf s7, x7, #39
99c: 9e0364e7 ucvtf s7, x7, #39
9a0: 9e5864e7 fcvtzs x7, d7, #39
9a4: 9e5964e7 fcvtzu x7, d7, #39
9a8: 9e4264e7 scvtf d7, x7, #39
9ac: 9e4364e7 ucvtf d7, x7, #39
9b0: 9e1860e7 fcvtzs x7, s7, #40
9b4: 9e1960e7 fcvtzu x7, s7, #40
9b8: 9e0260e7 scvtf s7, x7, #40
9bc: 9e0360e7 ucvtf s7, x7, #40
9c0: 9e5860e7 fcvtzs x7, d7, #40
9c4: 9e5960e7 fcvtzu x7, d7, #40
9c8: 9e4260e7 scvtf d7, x7, #40
9cc: 9e4360e7 ucvtf d7, x7, #40
9d0: 9e185ce7 fcvtzs x7, s7, #41
9d4: 9e195ce7 fcvtzu x7, s7, #41
9d8: 9e025ce7 scvtf s7, x7, #41
9dc: 9e035ce7 ucvtf s7, x7, #41
9e0: 9e585ce7 fcvtzs x7, d7, #41
9e4: 9e595ce7 fcvtzu x7, d7, #41
9e8: 9e425ce7 scvtf d7, x7, #41
9ec: 9e435ce7 ucvtf d7, x7, #41
9f0: 9e1858e7 fcvtzs x7, s7, #42
9f4: 9e1958e7 fcvtzu x7, s7, #42
9f8: 9e0258e7 scvtf s7, x7, #42
9fc: 9e0358e7 ucvtf s7, x7, #42
a00: 9e5858e7 fcvtzs x7, d7, #42
a04: 9e5958e7 fcvtzu x7, d7, #42
a08: 9e4258e7 scvtf d7, x7, #42
a0c: 9e4358e7 ucvtf d7, x7, #42
a10: 9e1854e7 fcvtzs x7, s7, #43
a14: 9e1954e7 fcvtzu x7, s7, #43
a18: 9e0254e7 scvtf s7, x7, #43
a1c: 9e0354e7 ucvtf s7, x7, #43
a20: 9e5854e7 fcvtzs x7, d7, #43
a24: 9e5954e7 fcvtzu x7, d7, #43
a28: 9e4254e7 scvtf d7, x7, #43
a2c: 9e4354e7 ucvtf d7, x7, #43
a30: 9e1850e7 fcvtzs x7, s7, #44
a34: 9e1950e7 fcvtzu x7, s7, #44
a38: 9e0250e7 scvtf s7, x7, #44
a3c: 9e0350e7 ucvtf s7, x7, #44
a40: 9e5850e7 fcvtzs x7, d7, #44
a44: 9e5950e7 fcvtzu x7, d7, #44
a48: 9e4250e7 scvtf d7, x7, #44
a4c: 9e4350e7 ucvtf d7, x7, #44
a50: 9e184ce7 fcvtzs x7, s7, #45
a54: 9e194ce7 fcvtzu x7, s7, #45
a58: 9e024ce7 scvtf s7, x7, #45
a5c: 9e034ce7 ucvtf s7, x7, #45
a60: 9e584ce7 fcvtzs x7, d7, #45
a64: 9e594ce7 fcvtzu x7, d7, #45
a68: 9e424ce7 scvtf d7, x7, #45
a6c: 9e434ce7 ucvtf d7, x7, #45
a70: 9e1848e7 fcvtzs x7, s7, #46
a74: 9e1948e7 fcvtzu x7, s7, #46
a78: 9e0248e7 scvtf s7, x7, #46
a7c: 9e0348e7 ucvtf s7, x7, #46
a80: 9e5848e7 fcvtzs x7, d7, #46
a84: 9e5948e7 fcvtzu x7, d7, #46
a88: 9e4248e7 scvtf d7, x7, #46
a8c: 9e4348e7 ucvtf d7, x7, #46
a90: 9e1844e7 fcvtzs x7, s7, #47
a94: 9e1944e7 fcvtzu x7, s7, #47
a98: 9e0244e7 scvtf s7, x7, #47
a9c: 9e0344e7 ucvtf s7, x7, #47
aa0: 9e5844e7 fcvtzs x7, d7, #47
aa4: 9e5944e7 fcvtzu x7, d7, #47
aa8: 9e4244e7 scvtf d7, x7, #47
aac: 9e4344e7 ucvtf d7, x7, #47
ab0: 9e1840e7 fcvtzs x7, s7, #48
ab4: 9e1940e7 fcvtzu x7, s7, #48
ab8: 9e0240e7 scvtf s7, x7, #48
abc: 9e0340e7 ucvtf s7, x7, #48
ac0: 9e5840e7 fcvtzs x7, d7, #48
ac4: 9e5940e7 fcvtzu x7, d7, #48
ac8: 9e4240e7 scvtf d7, x7, #48
acc: 9e4340e7 ucvtf d7, x7, #48
ad0: 9e183ce7 fcvtzs x7, s7, #49
ad4: 9e193ce7 fcvtzu x7, s7, #49
ad8: 9e023ce7 scvtf s7, x7, #49
adc: 9e033ce7 ucvtf s7, x7, #49
ae0: 9e583ce7 fcvtzs x7, d7, #49
ae4: 9e593ce7 fcvtzu x7, d7, #49
ae8: 9e423ce7 scvtf d7, x7, #49
aec: 9e433ce7 ucvtf d7, x7, #49
af0: 9e1838e7 fcvtzs x7, s7, #50
af4: 9e1938e7 fcvtzu x7, s7, #50
af8: 9e0238e7 scvtf s7, x7, #50
afc: 9e0338e7 ucvtf s7, x7, #50
b00: 9e5838e7 fcvtzs x7, d7, #50
b04: 9e5938e7 fcvtzu x7, d7, #50
b08: 9e4238e7 scvtf d7, x7, #50
b0c: 9e4338e7 ucvtf d7, x7, #50
b10: 9e1834e7 fcvtzs x7, s7, #51
b14: 9e1934e7 fcvtzu x7, s7, #51
b18: 9e0234e7 scvtf s7, x7, #51
b1c: 9e0334e7 ucvtf s7, x7, #51
b20: 9e5834e7 fcvtzs x7, d7, #51
b24: 9e5934e7 fcvtzu x7, d7, #51
b28: 9e4234e7 scvtf d7, x7, #51
b2c: 9e4334e7 ucvtf d7, x7, #51
b30: 9e1830e7 fcvtzs x7, s7, #52
b34: 9e1930e7 fcvtzu x7, s7, #52
b38: 9e0230e7 scvtf s7, x7, #52
b3c: 9e0330e7 ucvtf s7, x7, #52
b40: 9e5830e7 fcvtzs x7, d7, #52
b44: 9e5930e7 fcvtzu x7, d7, #52
b48: 9e4230e7 scvtf d7, x7, #52
b4c: 9e4330e7 ucvtf d7, x7, #52
b50: 9e182ce7 fcvtzs x7, s7, #53
b54: 9e192ce7 fcvtzu x7, s7, #53
b58: 9e022ce7 scvtf s7, x7, #53
b5c: 9e032ce7 ucvtf s7, x7, #53
b60: 9e582ce7 fcvtzs x7, d7, #53
b64: 9e592ce7 fcvtzu x7, d7, #53
b68: 9e422ce7 scvtf d7, x7, #53
b6c: 9e432ce7 ucvtf d7, x7, #53
b70: 9e1828e7 fcvtzs x7, s7, #54
b74: 9e1928e7 fcvtzu x7, s7, #54
b78: 9e0228e7 scvtf s7, x7, #54
b7c: 9e0328e7 ucvtf s7, x7, #54
b80: 9e5828e7 fcvtzs x7, d7, #54
b84: 9e5928e7 fcvtzu x7, d7, #54
b88: 9e4228e7 scvtf d7, x7, #54
b8c: 9e4328e7 ucvtf d7, x7, #54
b90: 9e1824e7 fcvtzs x7, s7, #55
b94: 9e1924e7 fcvtzu x7, s7, #55
b98: 9e0224e7 scvtf s7, x7, #55
b9c: 9e0324e7 ucvtf s7, x7, #55
ba0: 9e5824e7 fcvtzs x7, d7, #55
ba4: 9e5924e7 fcvtzu x7, d7, #55
ba8: 9e4224e7 scvtf d7, x7, #55
bac: 9e4324e7 ucvtf d7, x7, #55
bb0: 9e1820e7 fcvtzs x7, s7, #56
bb4: 9e1920e7 fcvtzu x7, s7, #56
bb8: 9e0220e7 scvtf s7, x7, #56
bbc: 9e0320e7 ucvtf s7, x7, #56
bc0: 9e5820e7 fcvtzs x7, d7, #56
bc4: 9e5920e7 fcvtzu x7, d7, #56
bc8: 9e4220e7 scvtf d7, x7, #56
bcc: 9e4320e7 ucvtf d7, x7, #56
bd0: 9e181ce7 fcvtzs x7, s7, #57
bd4: 9e191ce7 fcvtzu x7, s7, #57
bd8: 9e021ce7 scvtf s7, x7, #57
bdc: 9e031ce7 ucvtf s7, x7, #57
be0: 9e581ce7 fcvtzs x7, d7, #57
be4: 9e591ce7 fcvtzu x7, d7, #57
be8: 9e421ce7 scvtf d7, x7, #57
bec: 9e431ce7 ucvtf d7, x7, #57
bf0: 9e1818e7 fcvtzs x7, s7, #58
bf4: 9e1918e7 fcvtzu x7, s7, #58
bf8: 9e0218e7 scvtf s7, x7, #58
bfc: 9e0318e7 ucvtf s7, x7, #58
c00: 9e5818e7 fcvtzs x7, d7, #58
c04: 9e5918e7 fcvtzu x7, d7, #58
c08: 9e4218e7 scvtf d7, x7, #58
c0c: 9e4318e7 ucvtf d7, x7, #58
c10: 9e1814e7 fcvtzs x7, s7, #59
c14: 9e1914e7 fcvtzu x7, s7, #59
c18: 9e0214e7 scvtf s7, x7, #59
c1c: 9e0314e7 ucvtf s7, x7, #59
c20: 9e5814e7 fcvtzs x7, d7, #59
c24: 9e5914e7 fcvtzu x7, d7, #59
c28: 9e4214e7 scvtf d7, x7, #59
c2c: 9e4314e7 ucvtf d7, x7, #59
c30: 9e1810e7 fcvtzs x7, s7, #60
c34: 9e1910e7 fcvtzu x7, s7, #60
c38: 9e0210e7 scvtf s7, x7, #60
c3c: 9e0310e7 ucvtf s7, x7, #60
c40: 9e5810e7 fcvtzs x7, d7, #60
c44: 9e5910e7 fcvtzu x7, d7, #60
c48: 9e4210e7 scvtf d7, x7, #60
c4c: 9e4310e7 ucvtf d7, x7, #60
c50: 9e180ce7 fcvtzs x7, s7, #61
c54: 9e190ce7 fcvtzu x7, s7, #61
c58: 9e020ce7 scvtf s7, x7, #61
c5c: 9e030ce7 ucvtf s7, x7, #61
c60: 9e580ce7 fcvtzs x7, d7, #61
c64: 9e590ce7 fcvtzu x7, d7, #61
c68: 9e420ce7 scvtf d7, x7, #61
c6c: 9e430ce7 ucvtf d7, x7, #61
c70: 9e1808e7 fcvtzs x7, s7, #62
c74: 9e1908e7 fcvtzu x7, s7, #62
c78: 9e0208e7 scvtf s7, x7, #62
c7c: 9e0308e7 ucvtf s7, x7, #62
c80: 9e5808e7 fcvtzs x7, d7, #62
c84: 9e5908e7 fcvtzu x7, d7, #62
c88: 9e4208e7 scvtf d7, x7, #62
c8c: 9e4308e7 ucvtf d7, x7, #62
c90: 9e1804e7 fcvtzs x7, s7, #63
c94: 9e1904e7 fcvtzu x7, s7, #63
c98: 9e0204e7 scvtf s7, x7, #63
c9c: 9e0304e7 ucvtf s7, x7, #63
ca0: 9e5804e7 fcvtzs x7, d7, #63
ca4: 9e5904e7 fcvtzu x7, d7, #63
ca8: 9e4204e7 scvtf d7, x7, #63
cac: 9e4304e7 ucvtf d7, x7, #63
cb0: 9e1800e7 fcvtzs x7, s7, #64
cb4: 9e1900e7 fcvtzu x7, s7, #64
cb8: 9e0200e7 scvtf s7, x7, #64
cbc: 9e0300e7 ucvtf s7, x7, #64
cc0: 9e5800e7 fcvtzs x7, d7, #64
cc4: 9e5900e7 fcvtzu x7, d7, #64
cc8: 9e4200e7 scvtf d7, x7, #64
ccc: 9e4300e7 ucvtf d7, x7, #64
cd0: 9eae00e7 fmov x7, v7.d\[1\]
cd4: 9eaf00e7 fmov v7.d\[1\], x7

117
gas/testsuite/gas/aarch64/fp_cvt_int.s Normal file
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/* fp_cvt_ins.s Test file for AArch64 floating-point<->fixed-point
conversion and floating-point<->integer conversion instructions.
Copyright 2011, 2012 Free Software Foundation, Inc.
Contributed by ARM Ltd.
This file is part of GAS.
GAS is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the license, or
(at your option) any later version.
GAS is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; see the file COPYING3. If not,
see <http://www.gnu.org/licenses/>. */
// SCVTF & UCVTF
.macro do_cvtf fbits, reg
.ifc \fbits, 0
// Floating-point<->integer conversions
SCVTF \reg\()7, W7
SCVTF \reg\()7, X7
UCVTF \reg\()7, W7
UCVTF \reg\()7, X7
.else
// Floating-point<->fixed-point conversions
.ifle \fbits-32
SCVTF \reg\()7, W7, #\fbits
.endif
SCVTF \reg\()7, X7, #\fbits
.ifle \fbits-32
UCVTF \reg\()7, W7, #\fbits
.endif
UCVTF \reg\()7, X7, #\fbits
.endif
.endm
// FMOV
.macro do_fmov type
.ifc \type, S
// 32-bit
FMOV W7, S7
FMOV S7, W7
.elseif \type == D
// 64-bit
FMOV X7, D7
FMOV D7, X7
.else
// 64-bit with V reg element
FMOV X7, V7.D[1]
FMOV V7.D[1], X7
.endif
.endm
.macro do_fcvt suffix, fbits, reg
.ifc \fbits, 0
// Floating-point<->integer conversions
FCVT\suffix W7, \reg\()7
FCVT\suffix X7, \reg\()7
.else
// Floating-point<->fixed-point conversions
.ifle \fbits-32
FCVT\suffix W7, \reg\()7, #\fbits
.endif
FCVT\suffix X7, \reg\()7, #\fbits
.endif
.endm
.macro fcvts_with_fbits fbits
.ifc \fbits, 0
// fp <-> integer
.irp reg, S, D
// single-precision and double precision
do_fcvt NS, \fbits, \reg
do_fcvt NU, \fbits, \reg
do_fcvt PS, \fbits, \reg
do_fcvt PU, \fbits, \reg
do_fcvt MS, \fbits, \reg
do_fcvt MU, \fbits, \reg
do_fcvt ZS, \fbits, \reg
do_fcvt ZU, \fbits, \reg
do_cvtf \fbits, \reg
do_fcvt AS, \fbits, \reg
do_fcvt AU, \fbits, \reg
do_fmov S
.endr
.else
// fp <-> fixed-point
// After ISA 2.06, only FCVTZ[US] and [US]CVTF are available
.irp reg, S, D
// single-precision and double precision
do_fcvt ZS, \fbits, \reg
do_fcvt ZU, \fbits, \reg
do_cvtf \fbits, \reg
.endr
.endif
.endm
.macro fcvts_with_fbits_wrapper from=0, to=64
fcvts_with_fbits \from
.if \to-\from
fcvts_with_fbits_wrapper "(\from+1)", \to
.endif
.endm
func:
// Generate fcvt instructions without fbits and
// with fbits from 1 to 64, also generate [us]cvtf
// and fmov.
fcvts_with_fbits_wrapper from=0, to=64
do_fmov V

4
gas/testsuite/gas/aarch64/illegal-2.d Normal file
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@ -0,0 +1,4 @@
#name: Illegal Instructions - 2
#as:
#source: illegal-2.s
#error-output: illegal-2.l

8
gas/testsuite/gas/aarch64/illegal-2.l Normal file
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@ -0,0 +1,8 @@
[^:]*: Assembler messages:
[^:]*:10: Error: .*$
[^:]*:13: Error: .*$
[^:]*:14: Error: .*$
[^:]*:15: Error: .*$
[^:]*:16: Error: .*$
[^:]*:19: Error: .*$
[^:]*:20: Error: .*$

22
gas/testsuite/gas/aarch64/illegal-2.s Normal file
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@ -0,0 +1,22 @@
// illegal-2.s Test file for AArch64 instructions that should be rejected
// by the assembler. This test is a complement to the illegal.s test.
// md_apply_fix will not run if there is any error occurred in an earlier
// stage, which means errors should be reported by md_apply_fix will not
// be issued. This test hosts instructions that will only incur error
// report from md_apply_fix.
.text
mov x0, #deliberately_undefined_symbol
// immediate out of range
add wsp, w0, #0xfff0, LSL #12
add wsp, w0, #0xfff0, LSL #0
add wsp, w0, u16, LSL #12
add wsp, w0, u16, LSL #0
// immediate cannot be moved by a single instruction
mov wzr, #0x0f0f0f0f
mov wsp, #0x33030000
.set u16, 0xfff0

4
gas/testsuite/gas/aarch64/illegal.d Normal file
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@ -0,0 +1,4 @@
#name: Illegal Instructions
#as:
#source: illegal.s
#error-output: illegal.l

549
gas/testsuite/gas/aarch64/illegal.l Normal file
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@ -0,0 +1,549 @@
[^:]*: Assembler messages:
[^:]*:24: Error: .*`urecpe v0.1d,v7.1d'
[^:]*:25: Error: .*`urecpe v0.2d,v7.2d'
[^:]*:26: Error: .*`ursqrte v0.1d,v7.1d'
[^:]*:27: Error: .*`ursqrte v0.2d,v7.2d'
[^:]*:30: Error: .*`saddlv b7,v31.8b'
[^:]*:31: Error: .*`saddlv d7,v31.2s'
[^:]*:32: Error: .*`saddlv q7,v31.2d'
[^:]*:33: Error: .*`smaxv s7,v31.2s'
[^:]*:34: Error: .*`sminv d7,v31.2d'
[^:]*:35: Error: .*`fmaxv h7,v31.8h'
[^:]*:36: Error: .*`fmaxv h7,v31.4h'
[^:]*:37: Error: .*`fminv d7,v31.2d'
[^:]*:39: Error: .*`abs b0,b31'
[^:]*:40: Error: .*`neg b0,b31'
[^:]*:41: Error: .*`abs h0,h31'
[^:]*:42: Error: .*`neg h0,h31'
[^:]*:43: Error: .*`abs s0,s31'
[^:]*:44: Error: .*`neg s0,s31'
[^:]*:46: Error: .*`fcvt s0,s0'
[^:]*:48: Error: .*`bfm w0,w1,8,43'
[^:]*:49: Error: .*`ubfm w0,x1,8,31'
[^:]*:51: Error: .*`aese v1.8b,v2.8b'
[^:]*:52: Error: .*`sha1h s7,d31'
[^:]*:53: Error: .*`sha1h q7,d31'
[^:]*:54: Error: .*`sha1su1 v7.4s,v7.2s'
[^:]*:55: Error: .*`sha256su0 v7.2d,v7.2d'
[^:]*:56: Error: .*`sha1c q7,q3,v7.4s'
[^:]*:57: Error: .*`sha1p s7,q8,v9.4s'
[^:]*:58: Error: .*`sha1m v8.4s,v7.4s,q8'
[^:]*:59: Error: .*`sha1su0 v0.2d,v1.2d,v2.2d'
[^:]*:60: Error: .*`sha256h q7,s2,v8.4s'
[^:]*:62: Error: .*`pmull v7.8b,v15.8b,v31.8b'
[^:]*:63: Error: .*`pmull v7.1q,v15.1q,v31.1d'
[^:]*:64: Error: .*`pmull2 v7.8h,v15.8b,v31.8b'
[^:]*:65: Error: .*`pmull2 v7.1q,v15.2d,v31.1q'
[^:]*:67: Error: .*`ld2 {v1.4h,v0.4h},\[x1\]'
[^:]*:68: Error: .*`strb x0,\[sp,x1,lsl#0\]'
[^:]*:69: Error: .*`strb w7,\[x30,x0,lsl\]'
[^:]*:70: Error: .*`strb w7,\[x30,x0,lsl#1\]'
[^:]*:71: Error: .*`ldtr x7,\[x15,266\]'
[^:]*:72: Error: .*`sttr x7,\[x15,#1\]!'
[^:]*:73: Error: .*`stxrb x2,w1,\[sp\]'
[^:]*:74: Error: .*`stxp w2,x3,w4,\[x0\]'
[^:]*:75: Error: .*`ldxp w3,x4,\[x30\]'
[^:]*:77: Error: .*`st2 {v4.2d,v5.2d},\[x3,#3\]'
[^:]*:78: Error: .*`st2 {v4.2d,v5.2d,v6.2d},\[x3\]'
[^:]*:79: Error: .*`st1 {v4.2d,v6.2d,v8.2d},\[x3\]'
[^:]*:80: Error: .*`st3 {v4.2d,v6.2d},\[x3\]'
[^:]*:81: Error: .*`st4 {v4.2d,v6.2d},\[x3\]'
[^:]*:82: Error: .*`st2 {v4.2d,v6.2d,v8.2d,v10.2d},\[x3\]'
[^:]*:83: Error: .*`st2 {v4.2d,v6.2d,v8.2d,v10.2d},\[x3\],48'
[^:]*:85: Error: .*`ext v0.8b,v1.8b,v2.8b,8'
[^:]*:86: Error: .*`ext v0.16b,v1.16b,v2.16b,20'
[^:]*:88: Error: .*`tbz w0,#40,0x17c'
[^:]*:90: Error: .*`svc'
[^:]*:92: Error: .*`fmov v1.D\[0\],x0'
[^:]*:93: Error: .*`fmov v2.S\[2\],x0'
[^:]*:94: Error: .*`fmov v2.S\[1\],x0'
[^:]*:95: Error: .*`fmov v2.D\[1\],w0'
[^:]*:97: Error: .*`smaddl w0,w1,w2,x3'
[^:]*:98: Error: .*`smaddl x0,x1,w2,x3'
[^:]*:99: Error: .*`smaddl x0,w1,x2,x3'
[^:]*:100: Error: .*`smaddl x0,w1,w2,w3'
[^:]*:102: Error: .*`ld1 {v1.s,v2.s}\[1\],\[x3\]'
[^:]*:103: Error: .*`st1 {v2.s,v3.s}\[1\],\[x4\]'
[^:]*:104: Error: .*`ld2 {v1.s,v2.s,v3.s}\[1\],\[x3\]'
[^:]*:105: Error: .*`st2 {v2.s,v2.s,v3.s}\[1\],\[x4\]'
[^:]*:106: Error: .*`ld3 {v1.s,v2.s,v3.s,v4.s}\[1\],\[x3\]'
[^:]*:107: Error: .*`st3 {v2.s,v3.s,v4.s,v5.s}\[1\],\[x4\]'
[^:]*:108: Error: .*`ld4 {v1.s}\[1\],\[x3\]'
[^:]*:109: Error: .*`st4 {v2.s}\[1\],\[x4\]'
[^:]*:111: Error: .*`ld2 {v1.b,v3.b}\[1\],\[x3\]'
[^:]*:112: Error: .*`st2 {v2.b,v4.b}\[1\],\[x4\]'
[^:]*:113: Error: .*`ld3 {v1.b,v3.b,v5.b}\[1\],\[x3\]'
[^:]*:114: Error: .*`st3 {v2.b,v4.b,v6.b}\[1\],\[x4\]'
[^:]*:115: Error: .*`ld4 {v1.b,v3.b,v5.b,v7.b}\[1\],\[x3\]'
[^:]*:116: Error: .*`st4 {v2.b,v4.b,v6.b,v8.b}\[1\],\[x4\]'
[^:]*:118: Error: .*`ld1 {v1.q}\[1\],\[x3\]'
[^:]*:120: Error: .*`ld1r {v1.4s,v3.4s},\[x3\]'
[^:]*:121: Error: .*`ld1r {v1.4s,v2.4s,v3.4s},\[x3\]'
[^:]*:122: Error: .*`ld2r {v1.4s,v2.4s,v3.4s},\[x3\]'
[^:]*:123: Error: .*`ld3r {v1.4s,v2.4s,v3.4s,v4.4s},\[x3\]'
[^:]*:124: Error: .*`ld4r {v1.4s},\[x3\]'
[^:]*:126: Error: .*`ld1r {v1.4s,v3.4s},\[x3\],x4'
[^:]*:127: Error: .*`ld1r {v1.4s,v2.4s,v3.4s},\[x3\],x4'
[^:]*:128: Error: .*`ld2r {v1.4s,v2.4s,v3.4s},\[x3\],x4'
[^:]*:129: Error: .*`ld3r {v1.4s,v2.4s,v3.4s,v4.4s},\[x3\],x4'
[^:]*:130: Error: .*`ld4r {v1.4s},\[x3\],x4'
[^:]*:132: Error: .*`ld1r {v1.4s},\[x3\],#1'
[^:]*:133: Error: .*`ld1r {v1.4s,v2.4s},\[x3\],#8'
[^:]*:134: Error: .*`ld2r {v1.4s,v2.4s},\[x3\],#4'
[^:]*:135: Error: .*`ld3r {v1.4s,v2.4s,v3.4s},\[x3\],#16'
[^:]*:136: Error: .*`ld4r {v1.4s,v2.4s,v3.4s,v4.4s},\[x3\],#32'
[^:]*:138: Error: .*`addp s1,v2.2s'
[^:]*:139: Error: .*`addp s1,v2.2d'
[^:]*:140: Error: .*`addp d1,v2.2s'
[^:]*:141: Error: .*`fmaxp s1,v2.4s'
[^:]*:143: Error: .*`add s1,s2,s3'
[^:]*:144: Error: .*`cmhi d1,d2,s3'
[^:]*:146: Error: .*`shll v0.8h,v1.8b,16'
[^:]*:147: Error: .*`shll2 v0.2d,v1.4s,16'
[^:]*:149: Error: .*`dup s1,v2.d\[1\]'
[^:]*:150: Error: .*`dup s1,v2.s\[4\]'
[^:]*:151: Error: .*`mov s1,v2.h\[1\]'
[^:]*:153: Error: .*`clrex #16'
[^:]*:155: Error: .*`msr daif,w5'
[^:]*:156: Error: .*`mrs w15,midr_el1'
[^:]*:157: Error: .*`mrs x0,dummy'
[^:]*:159: Error: .*`sshr v0.4s,v1.4s,#0'
[^:]*:160: Error: .*`sshr v0.4s,v1.4s,#33'
[^:]*:161: Error: .*`sshr v0.4h,v1.4h,#20'
[^:]*:163: Error: .*`shl v0.4s,v1.4s,#32'
[^:]*:164: Error: .*`fcvtzs v0.4h,v1.4h,#2'
[^:]*:165: Error: .*`uqshrn v0.2s,v1.2d,33'
[^:]*:166: Error: .*`uqrshrn v0.2s,v1.2s,32'
[^:]*:167: Error: .*`sshll v8.8h,v2.8b,#8'
[^:]*:169: Error: .*`sysl x7,#10,C15,C7,#11'
[^:]*:170: Error: .*`sysl w7,#1,C15,C7,#1'
[^:]*:172: Error: .*`dsb dummy'
[^:]*:173: Error: .*`dmb #16'
[^:]*:174: Error: .*`isb osh'
[^:]*:176: Error: .*`prfm 0x2f,LABEL1'
[^:]*:177: Error: .*`prfm pldl3strm,\[sp,#8\]!'
[^:]*:178: Error: .*`prfm pldl3strm,\[sp\],#8'
[^:]*:179: Error: .*`prfm pldl3strm,\[sp,w0,sxtw#3\]!'
[^:]*:180: Error: .*`prfm pldl3strm,=0x100'
[^:]*:182: Error: .*`sttr x0,LABEL1'
[^:]*:183: Error: .*`sttr x0,\[sp,#16\]!'
[^:]*:184: Error: .*`sttr x0,\[sp\],#16'
[^:]*:185: Error: .*`sttr x0,\[sp,x1\]'
[^:]*:187: Error: .*`ldur x0,LABEL1'
[^:]*:188: Error: .*`ldur x0,\[sp,#16\]!'
[^:]*:189: Error: .*`ldur x0,\[sp\],#16'
[^:]*:190: Error: .*`ldur x0,\[sp,x1\]'
[^:]*:192: Error: .*`ldr b0,=0x100'
[^:]*:193: Error: .*`ldr h0,LABEL1'
[^:]*:195: Error: .*`ic ivau'
[^:]*:196: Error: .*`ic ivau,w0'
[^:]*:197: Error: .*`ic ialluis,xzr'
[^:]*:198: Error: .*`ic ialluis,x0'
[^:]*:199: Error: .*`sys #0,c0,c0,0,w0'
[^:]*:200: Error: .*`msr spsel,#16'
[^:]*:201: Error: .*`msr cptr_el2,#15'
[^:]*:203: Error: .*`movz x1,#:abs_g2:u48,lsl#16'
[^:]*:204: Error: .*`movz x1,0xddee,lsl#8'
[^:]*:205: Error: .*`movz w1,#:abs_g2:u48'
[^:]*:206: Error: .*`movz w1,#:abs_g3:u48'
[^:]*:207: Error: .*`movk x1,#:abs_g1_s:s12'
[^:]*:209: Error: .*`movi v0.4s,#256'
[^:]*:210: Error: .*`movi v0.2d,#0xabcdef'
[^:]*:212: Error: .*`bic v0.4s,#255,msl#8'
[^:]*:213: Error: .*`bic v0.4s,#512'
[^:]*:214: Error: .*`bic v0.4s,#1,lsl#31'
[^:]*:217: Error: .*`orr v0.4s,#255,msl#8'
[^:]*:218: Error: .*`orr v0.4s,#512'
[^:]*:220: Error: .*`movi v0.4s,#127,lsl#4'
[^:]*:221: Error: .*`movi v0.4s,#127,msl#24'
[^:]*:224: Error: .*`mvni v0.4s,#127,lsl#4'
[^:]*:225: Error: .*`mvni v0.4s,#127,msl#24'
[^:]*:228: Error: .*`fmov v0.2s,#3.1415926'
[^:]*:229: Error: .*`fmov v0.4s,#3.1415926'
[^:]*:230: Error: .*`fmov v0.2d,#3.1415926'
[^:]*:231: Error: .*`fmov x0,#1.0'
[^:]*:232: Error: .*`fmov w0,w1'
[^:]*:234: Error: .*`msr #5,#0'
[^:]*:235: Error: .*`msr SPSel,#2'
[^:]*:237: Error: .*`tbl v0.16b,{v1.16b,v3.16b,v5.16b},v2.16b'
[^:]*:238: Error: .*`tbx v0.8b,{v1.16b,v3.16b,v5.16b,v7.16b},v2.8b'
[^:]*:264: Error: .*`ld2 {v0.8b,v2.8b},\[x0\],#16'
[^:]*:264: Error: .*`ld2 {v0.8b,v1.8b,v2.8b,v3.8b},\[x0\],#32'
[^:]*:264: Error: .*`ld2 {v0.8b,v2.8b},\[x0\],x7'
[^:]*:264: Error: .*`ld2 {v0.8b,v1.8b,v2.8b,v3.8b},\[x0\],x7'
[^:]*:264: Error: .*`ld2 {v0.4h,v2.4h},\[x0\],#16'
[^:]*:264: Error: .*`ld2 {v0.4h,v1.4h,v2.4h,v3.4h},\[x0\],#32'
[^:]*:264: Error: .*`ld2 {v0.4h,v2.4h},\[x0\],x7'
[^:]*:264: Error: .*`ld2 {v0.4h,v1.4h,v2.4h,v3.4h},\[x0\],x7'
[^:]*:264: Error: .*`ld2 {v0.2s,v2.2s},\[x0\],#16'
[^:]*:264: Error: .*`ld2 {v0.2s,v1.2s,v2.2s,v3.2s},\[x0\],#32'
[^:]*:264: Error: .*`ld2 {v0.2s,v2.2s},\[x0\],x7'
[^:]*:264: Error: .*`ld2 {v0.2s,v1.2s,v2.2s,v3.2s},\[x0\],x7'
[^:]*:264: Error: .*`st2 {v0.8b,v2.8b},\[x0\],#16'
[^:]*:264: Error: .*`st2 {v0.8b,v1.8b,v2.8b,v3.8b},\[x0\],#32'
[^:]*:264: Error: .*`st2 {v0.8b,v2.8b},\[x0\],x7'
[^:]*:264: Error: .*`st2 {v0.8b,v1.8b,v2.8b,v3.8b},\[x0\],x7'
[^:]*:264: Error: .*`st2 {v0.4h,v2.4h},\[x0\],#16'
[^:]*:264: Error: .*`st2 {v0.4h,v1.4h,v2.4h,v3.4h},\[x0\],#32'
[^:]*:264: Error: .*`st2 {v0.4h,v2.4h},\[x0\],x7'
[^:]*:264: Error: .*`st2 {v0.4h,v1.4h,v2.4h,v3.4h},\[x0\],x7'
[^:]*:264: Error: .*`st2 {v0.2s,v2.2s},\[x0\],#16'
[^:]*:264: Error: .*`st2 {v0.2s,v1.2s,v2.2s,v3.2s},\[x0\],#32'
[^:]*:264: Error: .*`st2 {v0.2s,v2.2s},\[x0\],x7'
[^:]*:264: Error: .*`st2 {v0.2s,v1.2s,v2.2s,v3.2s},\[x0\],x7'
[^:]*:270: Error: .*`ld2 {v0.16b,v2.16b},\[x0\],#32'
[^:]*:270: Error: .*`ld2 {v0.16b,v1.16b,v2.16b,v3.16b},\[x0\],#64'
[^:]*:270: Error: .*`ld2 {v0.16b,v2.16b},\[x0\],x7'
[^:]*:270: Error: .*`ld2 {v0.16b,v1.16b,v2.16b,v3.16b},\[x0\],x7'
[^:]*:270: Error: .*`ld2 {v0.8h,v2.8h},\[x0\],#32'
[^:]*:270: Error: .*`ld2 {v0.8h,v1.8h,v2.8h,v3.8h},\[x0\],#64'
[^:]*:270: Error: .*`ld2 {v0.8h,v2.8h},\[x0\],x7'
[^:]*:270: Error: .*`ld2 {v0.8h,v1.8h,v2.8h,v3.8h},\[x0\],x7'
[^:]*:270: Error: .*`ld2 {v0.4s,v2.4s},\[x0\],#32'
[^:]*:270: Error: .*`ld2 {v0.4s,v1.4s,v2.4s,v3.4s},\[x0\],#64'
[^:]*:270: Error: .*`ld2 {v0.4s,v2.4s},\[x0\],x7'
[^:]*:270: Error: .*`ld2 {v0.4s,v1.4s,v2.4s,v3.4s},\[x0\],x7'
[^:]*:270: Error: .*`ld2 {v0.2d,v2.2d},\[x0\],#32'
[^:]*:270: Error: .*`ld2 {v0.2d,v1.2d,v2.2d,v3.2d},\[x0\],#64'
[^:]*:270: Error: .*`ld2 {v0.2d,v2.2d},\[x0\],x7'
[^:]*:270: Error: .*`ld2 {v0.2d,v1.2d,v2.2d,v3.2d},\[x0\],x7'
[^:]*:270: Error: .*`st2 {v0.16b,v2.16b},\[x0\],#32'
[^:]*:270: Error: .*`st2 {v0.16b,v1.16b,v2.16b,v3.16b},\[x0\],#64'
[^:]*:270: Error: .*`st2 {v0.16b,v2.16b},\[x0\],x7'
[^:]*:270: Error: .*`st2 {v0.16b,v1.16b,v2.16b,v3.16b},\[x0\],x7'
[^:]*:270: Error: .*`st2 {v0.8h,v2.8h},\[x0\],#32'
[^:]*:270: Error: .*`st2 {v0.8h,v1.8h,v2.8h,v3.8h},\[x0\],#64'
[^:]*:270: Error: .*`st2 {v0.8h,v2.8h},\[x0\],x7'
[^:]*:270: Error: .*`st2 {v0.8h,v1.8h,v2.8h,v3.8h},\[x0\],x7'
[^:]*:270: Error: .*`st2 {v0.4s,v2.4s},\[x0\],#32'
[^:]*:270: Error: .*`st2 {v0.4s,v1.4s,v2.4s,v3.4s},\[x0\],#64'
[^:]*:270: Error: .*`st2 {v0.4s,v2.4s},\[x0\],x7'
[^:]*:270: Error: .*`st2 {v0.4s,v1.4s,v2.4s,v3.4s},\[x0\],x7'
[^:]*:270: Error: .*`st2 {v0.2d,v2.2d},\[x0\],#32'
[^:]*:270: Error: .*`st2 {v0.2d,v1.2d,v2.2d,v3.2d},\[x0\],#64'
[^:]*:270: Error: .*`st2 {v0.2d,v2.2d},\[x0\],x7'
[^:]*:270: Error: .*`st2 {v0.2d,v1.2d,v2.2d,v3.2d},\[x0\],x7'
[^:]*:290: Error: .*`ld3 {v0.8b,v2.8b,v4.8b},\[x0\],#24'
[^:]*:290: Error: .*`ld4 {v0.8b,v2.8b,v4.8b,v6.8b},\[x0\],#32'
[^:]*:290: Error: .*`ld3 {v0.8b,v2.8b,v4.8b},\[x0\],x7'
[^:]*:290: Error: .*`ld4 {v0.8b,v2.8b,v4.8b,v6.8b},\[x0\],x7'
[^:]*:290: Error: .*`ld3 {v0.4h,v2.4h,v4.4h},\[x0\],#24'
[^:]*:290: Error: .*`ld4 {v0.4h,v2.4h,v4.4h,v6.4h},\[x0\],#32'
[^:]*:290: Error: .*`ld3 {v0.4h,v2.4h,v4.4h},\[x0\],x7'
[^:]*:290: Error: .*`ld4 {v0.4h,v2.4h,v4.4h,v6.4h},\[x0\],x7'
[^:]*:290: Error: .*`ld3 {v0.2s,v2.2s,v4.2s},\[x0\],#24'
[^:]*:290: Error: .*`ld4 {v0.2s,v2.2s,v4.2s,v6.2s},\[x0\],#32'
[^:]*:290: Error: .*`ld3 {v0.2s,v2.2s,v4.2s},\[x0\],x7'
[^:]*:290: Error: .*`ld4 {v0.2s,v2.2s,v4.2s,v6.2s},\[x0\],x7'
[^:]*:290: Error: .*`st3 {v0.8b,v2.8b,v4.8b},\[x0\],#24'
[^:]*:290: Error: .*`st4 {v0.8b,v2.8b,v4.8b,v6.8b},\[x0\],#32'
[^:]*:290: Error: .*`st3 {v0.8b,v2.8b,v4.8b},\[x0\],x7'
[^:]*:290: Error: .*`st4 {v0.8b,v2.8b,v4.8b,v6.8b},\[x0\],x7'
[^:]*:290: Error: .*`st3 {v0.4h,v2.4h,v4.4h},\[x0\],#24'
[^:]*:290: Error: .*`st4 {v0.4h,v2.4h,v4.4h,v6.4h},\[x0\],#32'
[^:]*:290: Error: .*`st3 {v0.4h,v2.4h,v4.4h},\[x0\],x7'
[^:]*:290: Error: .*`st4 {v0.4h,v2.4h,v4.4h,v6.4h},\[x0\],x7'
[^:]*:290: Error: .*`st3 {v0.2s,v2.2s,v4.2s},\[x0\],#24'
[^:]*:290: Error: .*`st4 {v0.2s,v2.2s,v4.2s,v6.2s},\[x0\],#32'
[^:]*:290: Error: .*`st3 {v0.2s,v2.2s,v4.2s},\[x0\],x7'
[^:]*:290: Error: .*`st4 {v0.2s,v2.2s,v4.2s,v6.2s},\[x0\],x7'
[^:]*:296: Error: .*`ld3 {v0.16b,v2.16b,v4.16b},\[x0\],#48'
[^:]*:296: Error: .*`ld4 {v0.16b,v2.16b,v4.16b,v6.16b},\[x0\],#64'
[^:]*:296: Error: .*`ld3 {v0.16b,v2.16b,v4.16b},\[x0\],x7'
[^:]*:296: Error: .*`ld4 {v0.16b,v2.16b,v4.16b,v6.16b},\[x0\],x7'
[^:]*:296: Error: .*`ld3 {v0.8h,v2.8h,v4.8h},\[x0\],#48'
[^:]*:296: Error: .*`ld4 {v0.8h,v2.8h,v4.8h,v6.8h},\[x0\],#64'
[^:]*:296: Error: .*`ld3 {v0.8h,v2.8h,v4.8h},\[x0\],x7'
[^:]*:296: Error: .*`ld4 {v0.8h,v2.8h,v4.8h,v6.8h},\[x0\],x7'
[^:]*:296: Error: .*`ld3 {v0.4s,v2.4s,v4.4s},\[x0\],#48'
[^:]*:296: Error: .*`ld4 {v0.4s,v2.4s,v4.4s,v6.4s},\[x0\],#64'
[^:]*:296: Error: .*`ld3 {v0.4s,v2.4s,v4.4s},\[x0\],x7'
[^:]*:296: Error: .*`ld4 {v0.4s,v2.4s,v4.4s,v6.4s},\[x0\],x7'
[^:]*:296: Error: .*`ld3 {v0.2d,v2.2d,v4.2d},\[x0\],#48'
[^:]*:296: Error: .*`ld4 {v0.2d,v2.2d,v4.2d,v6.2d},\[x0\],#64'
[^:]*:296: Error: .*`ld3 {v0.2d,v2.2d,v4.2d},\[x0\],x7'
[^:]*:296: Error: .*`ld4 {v0.2d,v2.2d,v4.2d,v6.2d},\[x0\],x7'
[^:]*:296: Error: .*`st3 {v0.16b,v2.16b,v4.16b},\[x0\],#48'
[^:]*:296: Error: .*`st4 {v0.16b,v2.16b,v4.16b,v6.16b},\[x0\],#64'
[^:]*:296: Error: .*`st3 {v0.16b,v2.16b,v4.16b},\[x0\],x7'
[^:]*:296: Error: .*`st4 {v0.16b,v2.16b,v4.16b,v6.16b},\[x0\],x7'
[^:]*:296: Error: .*`st3 {v0.8h,v2.8h,v4.8h},\[x0\],#48'
[^:]*:296: Error: .*`st4 {v0.8h,v2.8h,v4.8h,v6.8h},\[x0\],#64'
[^:]*:296: Error: .*`st3 {v0.8h,v2.8h,v4.8h},\[x0\],x7'
[^:]*:296: Error: .*`st4 {v0.8h,v2.8h,v4.8h,v6.8h},\[x0\],x7'
[^:]*:296: Error: .*`st3 {v0.4s,v2.4s,v4.4s},\[x0\],#48'
[^:]*:296: Error: .*`st4 {v0.4s,v2.4s,v4.4s,v6.4s},\[x0\],#64'
[^:]*:296: Error: .*`st3 {v0.4s,v2.4s,v4.4s},\[x0\],x7'
[^:]*:296: Error: .*`st4 {v0.4s,v2.4s,v4.4s,v6.4s},\[x0\],x7'
[^:]*:296: Error: .*`st3 {v0.2d,v2.2d,v4.2d},\[x0\],#48'
[^:]*:296: Error: .*`st4 {v0.2d,v2.2d,v4.2d,v6.2d},\[x0\],#64'
[^:]*:296: Error: .*`st3 {v0.2d,v2.2d,v4.2d},\[x0\],x7'
[^:]*:296: Error: .*`st4 {v0.2d,v2.2d,v4.2d,v6.2d},\[x0\],x7'
[^:]*:300: Error: .*`ld1r {v0.8b,v1.8b},\[x0\],#1'
[^:]*:301: Error: .*`ld1r {v0.16b,v1.16b},\[x0\],#1'
[^:]*:302: Error: .*`ld1r {v0.4h,v1.4h},\[x0\],#2'
[^:]*:303: Error: .*`ld1r {v0.8h,v1.8h},\[x0\],#2'
[^:]*:304: Error: .*`ld1r {v0.2s,v1.2s},\[x0\],#4'
[^:]*:305: Error: .*`ld1r {v0.4s,v1.4s},\[x0\],#4'
[^:]*:306: Error: .*`ld1r {v0.1d,v1.1d},\[x0\],#8'
[^:]*:307: Error: .*`ld1r {v0.2d,v1.2d},\[x0\],#8'
[^:]*:322: Error: .*`ld2 {v0.h,v2.h}\[1\],\[x0\],#4'
[^:]*:322: Error: .*`ld3 {v0.h,v2.h,v4.h}\[1\],\[x0\],#6'
[^:]*:322: Error: .*`ld4 {v0.h,v2.h,v4.h,v6.h}\[1\],\[x0\],#8'
[^:]*:322: Error: .*`ld2r {v0.4h,v2.4h},\[x0\],#4'
[^:]*:322: Error: .*`ld3r {v0.4h,v2.4h,v4.4h},\[x0\],#6'
[^:]*:322: Error: .*`ld4r {v0.4h,v2.4h,v4.4h,v6.4h},\[x0\],#8'
[^:]*:322: Error: .*`ld2r {v0.8h,v2.8h},\[x0\],#4'
[^:]*:322: Error: .*`ld3r {v0.8h,v2.8h,v4.8h},\[x0\],#6'
[^:]*:322: Error: .*`ld4r {v0.8h,v2.8h,v4.8h,v6.8h},\[x0\],#8'
[^:]*:322: Error: .*`st2 {v0.h,v2.h}\[1\],\[x0\],#4'
[^:]*:322: Error: .*`st3 {v0.h,v2.h,v4.h}\[1\],\[x0\],#6'
[^:]*:322: Error: .*`st4 {v0.h,v2.h,v4.h,v6.h}\[1\],\[x0\],#8'
[^:]*:337: Error: .*`ld2 {v0.s,v2.s}\[1\],\[x0\],#8'
[^:]*:337: Error: .*`ld3 {v0.s,v2.s,v4.s}\[1\],\[x0\],#12'
[^:]*:337: Error: .*`ld4 {v0.s,v2.s,v4.s,v6.s}\[1\],\[x0\],#16'
[^:]*:337: Error: .*`ld2r {v0.2s,v2.2s},\[x0\],#8'
[^:]*:337: Error: .*`ld3r {v0.2s,v2.2s,v4.2s},\[x0\],#12'
[^:]*:337: Error: .*`ld4r {v0.2s,v2.2s,v4.2s,v6.2s},\[x0\],#16'
[^:]*:337: Error: .*`ld2r {v0.4s,v2.4s},\[x0\],#8'
[^:]*:337: Error: .*`ld3r {v0.4s,v2.4s,v4.4s},\[x0\],#12'
[^:]*:337: Error: .*`ld4r {v0.4s,v2.4s,v4.4s,v6.4s},\[x0\],#16'
[^:]*:337: Error: .*`st2 {v0.s,v2.s}\[1\],\[x0\],#8'
[^:]*:337: Error: .*`st3 {v0.s,v2.s,v4.s}\[1\],\[x0\],#12'
[^:]*:337: Error: .*`st4 {v0.s,v2.s,v4.s,v6.s}\[1\],\[x0\],#16'
[^:]*:352: Error: .*`ld2 {v0.d,v2.d}\[1\],\[x0\],#16'
[^:]*:352: Error: .*`ld3 {v0.d,v2.d,v4.d}\[1\],\[x0\],#24'
[^:]*:352: Error: .*`ld4 {v0.d,v2.d,v4.d,v6.d}\[1\],\[x0\],#32'
[^:]*:352: Error: .*`ld2r {v0.1d,v2.1d},\[x0\],#16'
[^:]*:352: Error: .*`ld3r {v0.1d,v2.1d,v4.1d},\[x0\],#24'
[^:]*:352: Error: .*`ld4r {v0.1d,v2.1d,v4.1d,v6.1d},\[x0\],#32'
[^:]*:352: Error: .*`ld2r {v0.2d,v2.2d},\[x0\],#16'
[^:]*:352: Error: .*`ld3r {v0.2d,v2.2d,v4.2d},\[x0\],#24'
[^:]*:352: Error: .*`ld4r {v0.2d,v2.2d,v4.2d,v6.2d},\[x0\],#32'
[^:]*:352: Error: .*`st2 {v0.d,v2.d}\[1\],\[x0\],#16'
[^:]*:352: Error: .*`st3 {v0.d,v2.d,v4.d}\[1\],\[x0\],#24'
[^:]*:352: Error: .*`st4 {v0.d,v2.d,v4.d,v6.d}\[1\],\[x0\],#32'
[^:]*:356: Error: .*`ld1r {v0.8b,v1.8b},\[x0\],x7'
[^:]*:356: Error: .*`ld1r {v0.16b,v1.16b},\[x0\],x7'
[^:]*:356: Error: .*`ld1r {v0.4h,v1.4h},\[x0\],x7'
[^:]*:356: Error: .*`ld1r {v0.8h,v1.8h},\[x0\],x7'
[^:]*:356: Error: .*`ld1r {v0.2s,v1.2s},\[x0\],x7'
[^:]*:356: Error: .*`ld1r {v0.4s,v1.4s},\[x0\],x7'
[^:]*:356: Error: .*`ld1r {v0.1d,v1.1d},\[x0\],x7'
[^:]*:356: Error: .*`ld1r {v0.2d,v1.2d},\[x0\],x7'
[^:]*:373: Error: .*`ld2 {v0.b,v2.b}\[1\],\[x0\],x7'
[^:]*:373: Error: .*`ld3 {v0.b,v2.b,v4.b}\[1\],\[x0\],x7'
[^:]*:373: Error: .*`ld4 {v0.b,v2.b,v4.b,v6.b}\[1\],\[x0\],x7'
[^:]*:373: Error: .*`ld2 {v0.h,v2.h}\[1\],\[x0\],x7'
[^:]*:373: Error: .*`ld3 {v0.h,v2.h,v4.h}\[1\],\[x0\],x7'
[^:]*:373: Error: .*`ld4 {v0.h,v2.h,v4.h,v6.h}\[1\],\[x0\],x7'
[^:]*:373: Error: .*`ld2 {v0.s,v2.s}\[1\],\[x0\],x7'
[^:]*:373: Error: .*`ld3 {v0.s,v2.s,v4.s}\[1\],\[x0\],x7'
[^:]*:373: Error: .*`ld4 {v0.s,v2.s,v4.s,v6.s}\[1\],\[x0\],x7'
[^:]*:373: Error: .*`ld2 {v0.d,v2.d}\[1\],\[x0\],x7'
[^:]*:373: Error: .*`ld3 {v0.d,v2.d,v4.d}\[1\],\[x0\],x7'
[^:]*:373: Error: .*`ld4 {v0.d,v2.d,v4.d,v6.d}\[1\],\[x0\],x7'
[^:]*:373: Error: .*`ld2r {v0.8b,v2.8b},\[x0\],x7'
[^:]*:373: Error: .*`ld3r {v0.8b,v2.8b,v4.8b},\[x0\],x7'
[^:]*:373: Error: .*`ld4r {v0.8b,v2.8b,v4.8b,v6.8b},\[x0\],x7'
[^:]*:373: Error: .*`ld2r {v0.16b,v2.16b},\[x0\],x7'
[^:]*:373: Error: .*`ld3r {v0.16b,v2.16b,v4.16b},\[x0\],x7'
[^:]*:373: Error: .*`ld4r {v0.16b,v2.16b,v4.16b,v6.16b},\[x0\],x7'
[^:]*:373: Error: .*`ld2r {v0.4h,v2.4h},\[x0\],x7'
[^:]*:373: Error: .*`ld3r {v0.4h,v2.4h,v4.4h},\[x0\],x7'
[^:]*:373: Error: .*`ld4r {v0.4h,v2.4h,v4.4h,v6.4h},\[x0\],x7'
[^:]*:373: Error: .*`ld2r {v0.8h,v2.8h},\[x0\],x7'
[^:]*:373: Error: .*`ld3r {v0.8h,v2.8h,v4.8h},\[x0\],x7'
[^:]*:373: Error: .*`ld4r {v0.8h,v2.8h,v4.8h,v6.8h},\[x0\],x7'
[^:]*:373: Error: .*`ld2r {v0.2s,v2.2s},\[x0\],x7'
[^:]*:373: Error: .*`ld3r {v0.2s,v2.2s,v4.2s},\[x0\],x7'
[^:]*:373: Error: .*`ld4r {v0.2s,v2.2s,v4.2s,v6.2s},\[x0\],x7'
[^:]*:373: Error: .*`ld2r {v0.4s,v2.4s},\[x0\],x7'
[^:]*:373: Error: .*`ld3r {v0.4s,v2.4s,v4.4s},\[x0\],x7'
[^:]*:373: Error: .*`ld4r {v0.4s,v2.4s,v4.4s,v6.4s},\[x0\],x7'
[^:]*:373: Error: .*`ld2r {v0.1d,v2.1d},\[x0\],x7'
[^:]*:373: Error: .*`ld3r {v0.1d,v2.1d,v4.1d},\[x0\],x7'
[^:]*:373: Error: .*`ld4r {v0.1d,v2.1d,v4.1d,v6.1d},\[x0\],x7'
[^:]*:373: Error: .*`ld2r {v0.2d,v2.2d},\[x0\],x7'
[^:]*:373: Error: .*`ld3r {v0.2d,v2.2d,v4.2d},\[x0\],x7'
[^:]*:373: Error: .*`ld4r {v0.2d,v2.2d,v4.2d,v6.2d},\[x0\],x7'
[^:]*:373: Error: .*`st2 {v0.b,v2.b}\[1\],\[x0\],x7'
[^:]*:373: Error: .*`st3 {v0.b,v2.b,v4.b}\[1\],\[x0\],x7'
[^:]*:373: Error: .*`st4 {v0.b,v2.b,v4.b,v6.b}\[1\],\[x0\],x7'
[^:]*:373: Error: .*`st2 {v0.h,v2.h}\[1\],\[x0\],x7'
[^:]*:373: Error: .*`st3 {v0.h,v2.h,v4.h}\[1\],\[x0\],x7'
[^:]*:373: Error: .*`st4 {v0.h,v2.h,v4.h,v6.h}\[1\],\[x0\],x7'
[^:]*:373: Error: .*`st2 {v0.s,v2.s}\[1\],\[x0\],x7'
[^:]*:373: Error: .*`st3 {v0.s,v2.s,v4.s}\[1\],\[x0\],x7'
[^:]*:373: Error: .*`st4 {v0.s,v2.s,v4.s,v6.s}\[1\],\[x0\],x7'
[^:]*:373: Error: .*`st2 {v0.d,v2.d}\[1\],\[x0\],x7'
[^:]*:373: Error: .*`st3 {v0.d,v2.d,v4.d}\[1\],\[x0\],x7'
[^:]*:373: Error: .*`st4 {v0.d,v2.d,v4.d,v6.d}\[1\],\[x0\],x7'
[^:]*:396: Error: .*`ld2 {v0.8B,v2.8B},\[x0\]'
[^:]*:396: Error: .*`ld3 {v0.8B,v2.8B,v4.8B},\[x0\]'
[^:]*:396: Error: .*`ld4 {v0.8B,v2.8B,v4.8B,v6.8B},\[x0\]'
[^:]*:397: Error: .*`st2 {v0.8B,v2.8B},\[x0\]'
[^:]*:397: Error: .*`st3 {v0.8B,v2.8B,v4.8B},\[x0\]'
[^:]*:397: Error: .*`st4 {v0.8B,v2.8B,v4.8B,v6.8B},\[x0\]'
[^:]*:399: Error: .*`ld2 {v0.16B,v2.16B},\[x0\]'
[^:]*:399: Error: .*`ld3 {v0.16B,v2.16B,v4.16B},\[x0\]'
[^:]*:399: Error: .*`ld4 {v0.16B,v2.16B,v4.16B,v6.16B},\[x0\]'
[^:]*:400: Error: .*`st2 {v0.16B,v2.16B},\[x0\]'
[^:]*:400: Error: .*`st3 {v0.16B,v2.16B,v4.16B},\[x0\]'
[^:]*:400: Error: .*`st4 {v0.16B,v2.16B,v4.16B,v6.16B},\[x0\]'
[^:]*:402: Error: .*`ld2 {v0.4H,v2.4H},\[x0\]'
[^:]*:402: Error: .*`ld3 {v0.4H,v2.4H,v4.4H},\[x0\]'
[^:]*:402: Error: .*`ld4 {v0.4H,v2.4H,v4.4H,v6.4H},\[x0\]'
[^:]*:403: Error: .*`st2 {v0.4H,v2.4H},\[x0\]'
[^:]*:403: Error: .*`st3 {v0.4H,v2.4H,v4.4H},\[x0\]'
[^:]*:403: Error: .*`st4 {v0.4H,v2.4H,v4.4H,v6.4H},\[x0\]'
[^:]*:405: Error: .*`ld2 {v0.8H,v2.8H},\[x0\]'
[^:]*:405: Error: .*`ld3 {v0.8H,v2.8H,v4.8H},\[x0\]'
[^:]*:405: Error: .*`ld4 {v0.8H,v2.8H,v4.8H,v6.8H},\[x0\]'
[^:]*:406: Error: .*`st2 {v0.8H,v2.8H},\[x0\]'
[^:]*:406: Error: .*`st3 {v0.8H,v2.8H,v4.8H},\[x0\]'
[^:]*:406: Error: .*`st4 {v0.8H,v2.8H,v4.8H,v6.8H},\[x0\]'
[^:]*:408: Error: .*`ld2 {v0.2S,v2.2S},\[x0\]'
[^:]*:408: Error: .*`ld3 {v0.2S,v2.2S,v4.2S},\[x0\]'
[^:]*:408: Error: .*`ld4 {v0.2S,v2.2S,v4.2S,v6.2S},\[x0\]'
[^:]*:409: Error: .*`st2 {v0.2S,v2.2S},\[x0\]'
[^:]*:409: Error: .*`st3 {v0.2S,v2.2S,v4.2S},\[x0\]'
[^:]*:409: Error: .*`st4 {v0.2S,v2.2S,v4.2S,v6.2S},\[x0\]'
[^:]*:411: Error: .*`ld2 {v0.4S,v2.4S},\[x0\]'
[^:]*:411: Error: .*`ld3 {v0.4S,v2.4S,v4.4S},\[x0\]'
[^:]*:411: Error: .*`ld4 {v0.4S,v2.4S,v4.4S,v6.4S},\[x0\]'
[^:]*:412: Error: .*`st2 {v0.4S,v2.4S},\[x0\]'
[^:]*:412: Error: .*`st3 {v0.4S,v2.4S,v4.4S},\[x0\]'
[^:]*:412: Error: .*`st4 {v0.4S,v2.4S,v4.4S,v6.4S},\[x0\]'
[^:]*:414: Error: .*`ld2 {v0.2D,v2.2D},\[x0\]'
[^:]*:414: Error: .*`ld3 {v0.2D,v2.2D,v4.2D},\[x0\]'
[^:]*:414: Error: .*`ld4 {v0.2D,v2.2D,v4.2D,v6.2D},\[x0\]'
[^:]*:415: Error: .*`st2 {v0.2D,v2.2D},\[x0\]'
[^:]*:415: Error: .*`st3 {v0.2D,v2.2D,v4.2D},\[x0\]'
[^:]*:415: Error: .*`st4 {v0.2D,v2.2D,v4.2D,v6.2D},\[x0\]'
[^:]*:423: Error: .*`ld2 {v0.H,v2.H}\[1\],\[x0\]'
[^:]*:423: Error: .*`ld3 {v0.H,v2.H,v4.H}\[1\],\[x0\]'
[^:]*:423: Error: .*`ld4 {v0.H,v2.H,v4.H,v6.H}\[1\],\[x0\]'
[^:]*:424: Error: .*`st2 {v0.H,v2.H}\[1\],\[x0\]'
[^:]*:424: Error: .*`st3 {v0.H,v2.H,v4.H}\[1\],\[x0\]'
[^:]*:424: Error: .*`st4 {v0.H,v2.H,v4.H,v6.H}\[1\],\[x0\]'
[^:]*:426: Error: .*`ld2 {v0.H,v2.H}\[1\],\[x0\]'
[^:]*:426: Error: .*`ld3 {v0.H,v2.H,v4.H}\[1\],\[x0\]'
[^:]*:426: Error: .*`ld4 {v0.H,v2.H,v4.H,v6.H}\[1\],\[x0\]'
[^:]*:427: Error: .*`st2 {v0.H,v2.H}\[1\],\[x0\]'
[^:]*:427: Error: .*`st3 {v0.H,v2.H,v4.H}\[1\],\[x0\]'
[^:]*:427: Error: .*`st4 {v0.H,v2.H,v4.H,v6.H}\[1\],\[x0\]'
[^:]*:429: Error: .*`ld2 {v0.S,v2.S}\[1\],\[x0\]'
[^:]*:429: Error: .*`ld3 {v0.S,v2.S,v4.S}\[1\],\[x0\]'
[^:]*:429: Error: .*`ld4 {v0.S,v2.S,v4.S,v6.S}\[1\],\[x0\]'
[^:]*:430: Error: .*`st2 {v0.S,v2.S}\[1\],\[x0\]'
[^:]*:430: Error: .*`st3 {v0.S,v2.S,v4.S}\[1\],\[x0\]'
[^:]*:430: Error: .*`st4 {v0.S,v2.S,v4.S,v6.S}\[1\],\[x0\]'
[^:]*:432: Error: .*`ld2 {v0.S,v2.S}\[1\],\[x0\]'
[^:]*:432: Error: .*`ld3 {v0.S,v2.S,v4.S}\[1\],\[x0\]'
[^:]*:432: Error: .*`ld4 {v0.S,v2.S,v4.S,v6.S}\[1\],\[x0\]'
[^:]*:433: Error: .*`st2 {v0.S,v2.S}\[1\],\[x0\]'
[^:]*:433: Error: .*`st3 {v0.S,v2.S,v4.S}\[1\],\[x0\]'
[^:]*:433: Error: .*`st4 {v0.S,v2.S,v4.S,v6.S}\[1\],\[x0\]'
[^:]*:435: Error: .*`ld2 {v0.D,v2.D}\[1\],\[x0\]'
[^:]*:435: Error: .*`ld3 {v0.D,v2.D,v4.D}\[1\],\[x0\]'
[^:]*:435: Error: .*`ld4 {v0.D,v2.D,v4.D,v6.D}\[1\],\[x0\]'
[^:]*:436: Error: .*`st2 {v0.D,v2.D}\[1\],\[x0\]'
[^:]*:436: Error: .*`st3 {v0.D,v2.D,v4.D}\[1\],\[x0\]'
[^:]*:436: Error: .*`st4 {v0.D,v2.D,v4.D,v6.D}\[1\],\[x0\]'
[^:]*:438: Error: .*`ld1r {v0.8B,v1.8B},\[x0\]'
[^:]*:438: Error: .*`ld2r {v0.8B,v2.8B},\[x0\]'
[^:]*:438: Error: .*`ld3r {v0.8B,v2.8B,v4.8B},\[x0\]'
[^:]*:438: Error: .*`ld4r {v0.8B,v2.8B,v4.8B,v6.8B},\[x0\]'
[^:]*:440: Error: .*`ld1r {v0.16B,v1.16B},\[x0\]'
[^:]*:440: Error: .*`ld2r {v0.16B,v2.16B},\[x0\]'
[^:]*:440: Error: .*`ld3r {v0.16B,v2.16B,v4.16B},\[x0\]'
[^:]*:440: Error: .*`ld4r {v0.16B,v2.16B,v4.16B,v6.16B},\[x0\]'
[^:]*:442: Error: .*`ld1r {v0.4H,v1.4H},\[x0\]'
[^:]*:442: Error: .*`ld2r {v0.4H,v2.4H},\[x0\]'
[^:]*:442: Error: .*`ld3r {v0.4H,v2.4H,v4.4H},\[x0\]'
[^:]*:442: Error: .*`ld4r {v0.4H,v2.4H,v4.4H,v6.4H},\[x0\]'
[^:]*:444: Error: .*`ld1r {v0.8H,v1.8H},\[x0\]'
[^:]*:444: Error: .*`ld2r {v0.8H,v2.8H},\[x0\]'
[^:]*:444: Error: .*`ld3r {v0.8H,v2.8H,v4.8H},\[x0\]'
[^:]*:444: Error: .*`ld4r {v0.8H,v2.8H,v4.8H,v6.8H},\[x0\]'
[^:]*:446: Error: .*`ld1r {v0.2S,v1.2S},\[x0\]'
[^:]*:446: Error: .*`ld2r {v0.2S,v2.2S},\[x0\]'
[^:]*:446: Error: .*`ld3r {v0.2S,v2.2S,v4.2S},\[x0\]'
[^:]*:446: Error: .*`ld4r {v0.2S,v2.2S,v4.2S,v6.2S},\[x0\]'
[^:]*:448: Error: .*`ld1r {v0.4S,v1.4S},\[x0\]'
[^:]*:448: Error: .*`ld2r {v0.4S,v2.4S},\[x0\]'
[^:]*:448: Error: .*`ld3r {v0.4S,v2.4S,v4.4S},\[x0\]'
[^:]*:448: Error: .*`ld4r {v0.4S,v2.4S,v4.4S,v6.4S},\[x0\]'
[^:]*:450: Error: .*`ld1r {v0.1D,v1.1D},\[x0\]'
[^:]*:450: Error: .*`ld2r {v0.1D,v2.1D},\[x0\]'
[^:]*:450: Error: .*`ld3r {v0.1D,v2.1D,v4.1D},\[x0\]'
[^:]*:450: Error: .*`ld4r {v0.1D,v2.1D,v4.1D,v6.1D},\[x0\]'
[^:]*:452: Error: .*`ld1r {v0.2D,v1.2D},\[x0\]'
[^:]*:452: Error: .*`ld2r {v0.2D,v2.2D},\[x0\]'
[^:]*:452: Error: .*`ld3r {v0.2D,v2.2D,v4.2D},\[x0\]'
[^:]*:452: Error: .*`ld4r {v0.2D,v2.2D,v4.2D,v6.2D},\[x0\]'
[^:]*:454: Error: .*`pmull v0.1q,v1.1d,v2.1d'
[^:]*:455: Error: .*`pmull2 v0.1q,v1.2d,v2.2d'
[^:]*:463: Error: .*`scvtf d0,w1,33'
[^:]*:463: Error: .*`scvtf s0,w0,33'
[^:]*:463: Error: .*`scvtf d0,x1,65'
[^:]*:463: Error: .*`scvtf s0,x1,65'
[^:]*:463: Error: .*`ucvtf d0,w1,33'
[^:]*:463: Error: .*`ucvtf s0,w0,33'
[^:]*:463: Error: .*`ucvtf d0,x1,65'
[^:]*:463: Error: .*`ucvtf s0,x1,65'
[^:]*:469: Error: .*`fcvtzs w1,d0,33'
[^:]*:469: Error: .*`fcvtzs w0,s0,33'
[^:]*:469: Error: .*`fcvtzs x1,d0,65'
[^:]*:469: Error: .*`fcvtzs x1,s0,65'
[^:]*:469: Error: .*`fcvtzu w1,d0,33'
[^:]*:469: Error: .*`fcvtzu w0,s0,33'
[^:]*:469: Error: .*`fcvtzu x1,d0,65'
[^:]*:469: Error: .*`fcvtzu x1,s0,65'
[^:]*:472: Error: .*
[^:]*:475: Error: .*`ldrh w0,\[x1,x2,lsr#1\]'
[^:]*:477: Error: .*`add w0,w1,w2,ror#1'
[^:]*:478: Error: .*`sub w0,w1,w2,asr#32'
[^:]*:479: Error: .*`eor w0,w1,w2,ror#32'
[^:]*:481: Error: .*`add x0,x1,#20,LSL#16'
[^:]*:482: Error: .*`add x0,x1,#20,UXTX#12'
[^:]*:483: Error: .*`add x0,x1,#20,LSR'
[^:]*:484: Error: .*`add x0,x1,#20,LSL'
[^:]*:486: Error: .*`ldnp h7,h15,\[x0,#2\]'
[^:]*:487: Error: .*`ldnp b15,b31,\[x0\],#4'
[^:]*:488: Error: .*`ldnp h0,h1,\[x0,#6\]!'
[^:]*:490: Error: .*`uqrshrn h0,s1,#63'
[^:]*:491: Error: .*`sqshl b7,b15,#8'
[^:]*:493: Error: .*`bfxil w7,w15,#15,#30'
[^:]*:494: Error: .*`bfi x3,x7,#31,#48'
[^:]*:496: Error: .*`str x1,page_table_count'
[^:]*:498: Error: .*`prfm PLDL3KEEP,\[x9,x15,sxtx#2\]'
[^:]*:500: Error: .*`mrs x5,S1_0_C13_C8_0'
[^:]*:501: Error: .*`msr S3_1_C13_C15_1,x7'
[^:]*:502: Error: .*`msr S3_1_C11_C15_-1,x7'
[^:]*:503: Error: .*`msr S3_1_11_15_1,x7'
[^:]*:506: Error: .*`movi w1,#15'
[^:]*:509: Error: .*`uxtb x7,x15'
[^:]*:510: Error: .*`uxth x7,x15'
[^:]*:511: Error: .*`uxtw x7,x15'
[^:]*:512: Error: .*`sxtb w15,xzr'
[^:]*:513: Error: .*`sxth w15,xzr'
[^:]*:514: Error: .*`sxtw w15,xzr'
[^:]*:516: Error: .*`mov w0,v0.b\[0\]'
[^:]*:517: Error: .*`mov w0,v0.h\[0\]'
[^:]*:518: Error: .*`mov w0,v0.d\[0\]'
[^:]*:519: Error: .*`mov x0,v0.b\[0\]'
[^:]*:520: Error: .*`mov x0,v0.h\[0\]'
[^:]*:521: Error: .*`mov x0,v0.s\[0\]'
[^:]*:523: Error: .*`uabdl2 v20\.4S,v12\.8H,v29\.8'
[^:]*:525: Error: .*`movi d1,0xffff,lsl#16'
[^:]*:527: Error: .*`st3 {v18.D-v20.D}\[0\],\[x28\],x'
[^:]*:528: Error: .*`st1 {v7.B}\[2\],\[x4\],x'
[^:]*:529: Error: .*`st1 {v22.1D-v25.1D},\[x10\],x'
[^:]*:531: Error: .*`ldr w0,\[x0\]!'
[^:]*:532: Error: .*`ldr w0,\[x0\],\{127\}'
[^:]*:534: Error: .*`orr x0,x0,#0xff,lsl#1'
[^:]*:535: Error: .*`orr x0. x0,#0xff,lsl#1'
[^:]*:536: Error: .*`orr x0,x0,#0xff lsl#1'
[^:]*:538: Error: .*`mov x0,##5'

538
gas/testsuite/gas/aarch64/illegal.s Normal file
View File

@ -0,0 +1,538 @@
/* illegal.s Test file for AArch64 instructions that should be rejected
by the assembler.
Copyright 2011, 2012 Free Software Foundation, Inc. Contributed by ARM Ltd.
This file is part of GAS.
GAS is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the license, or
(at your option) any later version.
GAS is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; see the file COPYING3. If not,
see <http://www.gnu.org/licenses/>. */
.text
// For urecpe and ursqrte, only 2s and 4s are accepted qualifiers.
urecpe v0.1d, v7.1d
urecpe v0.2d, v7.2d
ursqrte v0.1d, v7.1d
ursqrte v0.2d, v7.2d
// For AdvSIMD (across) instructions, there are restraints on the register type and qualifiers.
saddlv b7, v31.8b
saddlv d7, v31.2s
saddlv q7, v31.2d
smaxv s7, v31.2s
sminv d7, v31.2d
fmaxv h7, v31.8h
fmaxv h7, v31.4h
fminv d7, v31.2d
abs b0, b31
neg b0, b31
abs h0, h31
neg h0, h31
abs s0, s31
neg s0, s31
fcvt s0, s0
bfm w0, w1, 8, 43
ubfm w0, x1, 8, 31
aese v1.8b, v2.8b
sha1h s7, d31
sha1h q7, d31
sha1su1 v7.4s, v7.2s
sha256su0 v7.2d, v7.2d
sha1c q7, q3, v7.4s
sha1p s7, q8, v9.4s
sha1m v8.4s, v7.4s, q8
sha1su0 v0.2d, v1.2d, v2.2d
sha256h q7, s2, v8.4s
pmull v7.8b, v15.8b, v31.8b
pmull v7.1q, v15.1q, v31.1d
pmull2 v7.8h, v15.8b, v31.8b
pmull2 v7.1q, v15.2d, v31.1q
ld2 {v1.4h, v0.4h}, [x1]
strb x0, [sp, x1, lsl #0]
strb w7, [x30, x0, lsl]
strb w7, [x30, x0, lsl #1]
ldtr x7, [x15, 266]
sttr x7, [x15, #1]!
stxrb x2, w1, [sp]
stxp w2, x3, w4, [x0]
ldxp w3, x4, [x30]
st2 {v4.2d, v5.2d}, [x3, #3]
st2 {v4.2d, v5.2d, v6.2d}, [x3]
st1 {v4.2d, v6.2d, v8.2d}, [x3]
st3 {v4.2d, v6.2d}, [x3]
st4 {v4.2d, v6.2d}, [x3]
st2 {v4.2d, v6.2d, v8.2d, v10.2d}, [x3]
st2 {v4.2d, v6.2d, v8.2d, v10.2d}, [x3], 48
ext v0.8b, v1.8b, v2.8b, 8
ext v0.16b, v1.16b, v2.16b, 20
tbz w0, #40, 0x17c
svc
fmov v1.D[0], x0
fmov v2.S[2], x0
fmov v2.S[1], x0
fmov v2.D[1], w0
smaddl w0, w1, w2, x3
smaddl x0, x1, w2, x3
smaddl x0, w1, x2, x3
smaddl x0, w1, w2, w3
ld1 {v1.s, v2.s}[1], [x3]
st1 {v2.s, v3.s}[1], [x4]
ld2 {v1.s, v2.s, v3.s}[1], [x3]
st2 {v2.s, v2.s, v3.s}[1], [x4]
ld3 {v1.s, v2.s, v3.s, v4.s}[1], [x3]
st3 {v2.s, v3.s, v4.s, v5.s}[1], [x4]
ld4 {v1.s}[1], [x3]
st4 {v2.s}[1], [x4]
ld2 {v1.b, v3.b}[1], [x3]
st2 {v2.b, v4.b}[1], [x4]
ld3 {v1.b, v3.b, v5.b}[1], [x3]
st3 {v2.b, v4.b, v6.b}[1], [x4]
ld4 {v1.b, v3.b, v5.b, v7.b}[1], [x3]
st4 {v2.b, v4.b, v6.b, v8.b}[1], [x4]
ld1 {v1.q}[1], [x3]
ld1r {v1.4s, v3.4s}, [x3]
ld1r {v1.4s, v2.4s, v3.4s}, [x3]
ld2r {v1.4s, v2.4s, v3.4s}, [x3]
ld3r {v1.4s, v2.4s, v3.4s, v4.4s}, [x3]
ld4r {v1.4s}, [x3]
ld1r {v1.4s, v3.4s}, [x3], x4
ld1r {v1.4s, v2.4s, v3.4s}, [x3], x4
ld2r {v1.4s, v2.4s, v3.4s}, [x3], x4
ld3r {v1.4s, v2.4s, v3.4s, v4.4s}, [x3], x4
ld4r {v1.4s}, [x3], x4
ld1r {v1.4s}, [x3], #1
ld1r {v1.4s, v2.4s}, [x3], #8
ld2r {v1.4s, v2.4s}, [x3], #4
ld3r {v1.4s, v2.4s, v3.4s}, [x3], #16
ld4r {v1.4s, v2.4s, v3.4s, v4.4s}, [x3], #32
addp s1, v2.2s
addp s1, v2.2d
addp d1, v2.2s
fmaxp s1, v2.4s
add s1, s2, s3
cmhi d1, d2, s3
shll v0.8h, v1.8b, 16
shll2 v0.2d, v1.4s, 16
dup s1, v2.d[1]
dup s1, v2.s[4]
mov s1, v2.h[1]
clrex #16
msr daif, w5
mrs w15, midr_el1
mrs x0, dummy
sshr v0.4s, v1.4s, #0
sshr v0.4s, v1.4s, #33
sshr v0.4h, v1.4h, #20
shl v0.4s, v1.4s, #32
fcvtzs v0.4h, v1.4h, #2
uqshrn v0.2s, v1.2d, 33
uqrshrn v0.2s, v1.2s, 32
sshll v8.8h, v2.8b, #8
sysl x7, #10, C15, C7, #11
sysl w7, #1, C15, C7, #1
dsb dummy
dmb #16
isb osh
prfm 0x2f, LABEL1
prfm pldl3strm, [sp, #8]!
prfm pldl3strm, [sp], #8
prfm pldl3strm, [sp, w0, sxtw #3]!
prfm pldl3strm, =0x100
sttr x0, LABEL1
sttr x0, [sp, #16]!
sttr x0, [sp], #16
sttr x0, [sp, x1]
ldur x0, LABEL1
ldur x0, [sp, #16]!
ldur x0, [sp], #16
ldur x0, [sp, x1]
ldr b0, =0x100
ldr h0, LABEL1
ic ivau
ic ivau, w0
ic ialluis, xzr
ic ialluis, x0
sys #0, c0, c0, 0, w0
msr spsel, #16
msr cptr_el2, #15
movz x1,#:abs_g2:u48, lsl #16
movz x1, 0xddee, lsl #8
movz w1,#:abs_g2:u48
movz w1,#:abs_g3:u48
movk x1,#:abs_g1_s:s12
movi v0.4s, #256
movi v0.2d, #0xabcdef
bic v0.4s, #255, msl #8
bic v0.4s, #512
bic v0.4s, #1, lsl #31
// bic v0.4h, #1, lsl #16
orr v0.4s, #255, msl #8
orr v0.4s, #512
movi v0.4s, #127, lsl #4
movi v0.4s, #127, msl #24
// movi v0.4h, #127, lsl #16
mvni v0.4s, #127, lsl #4
mvni v0.4s, #127, msl #24
// mvni v0.4h, #127, lsl #16
fmov v0.2s, #3.1415926
fmov v0.4s, #3.1415926
fmov v0.2d, #3.1415926
fmov x0, #1.0
fmov w0, w1
msr #5, #0
msr SPSel, #2
tbl v0.16b, {v1.16b, v3.16b, v5.16b}, v2.16b
tbx v0.8b, {v1.16b, v3.16b, v5.16b, v7.16b}, v2.8b
// Alternating register list forms are no longer available A64 ISA
.macro ldst2_reg_list_post_imm_reg_64 inst type postreg
\inst\()2 {v0.\type, v2.\type}, [x0], #16
\inst\()2 {v0.\type, v1.\type, v2.\type, v3.\type}, [x0], #32
.ifnb \postreg
\inst\()2 {v0.\type, v2.\type}, [x0], \postreg
\inst\()2 {v0.\type, v1.\type, v2.\type, v3.\type}, [x0], \postreg
.endif
.endm
.macro ldst2_reg_list_post_imm_reg_128 inst type postreg
\inst\()2 {v0.\type, v2.\type}, [x0], #32
\inst\()2 {v0.\type, v1.\type, v2.\type, v3.\type}, [x0], #64
.ifnb \postreg
\inst\()2 {v0.\type, v2.\type}, [x0], \postreg
\inst\()2 {v0.\type, v1.\type, v2.\type, v3.\type}, [x0], \postreg
.endif
.endm
.irp instr ld,st
.irp bits_64 8b, 4h, 2s
ldst2_reg_list_post_imm_reg_64 \instr \bits_64 x7
.endr
.endr
.irp instr ld,st
.irp bits_128 16b, 8h, 4s, 2d
ldst2_reg_list_post_imm_reg_128 \instr \bits_128 x7
.endr
.endr
.macro ldst34_reg_list_post_imm_reg_64 inst type postreg
\inst\()3 {v0.\type, v2.\type, v4.\type}, [x0], #24
\inst\()4 {v0.\type, v2.\type, v4.\type, v6.\type}, [x0], #32
\inst\()3 {v0.\type, v2.\type, v4.\type}, [x0], \postreg
\inst\()4 {v0.\type, v2.\type, v4.\type, v6.\type}, [x0], \postreg
.endm
.macro ldst34_reg_list_post_imm_reg_128 inst type postreg
\inst\()3 {v0.\type, v2.\type, v4.\type}, [x0], #48
\inst\()4 {v0.\type, v2.\type, v4.\type, v6.\type}, [x0], #64
\inst\()3 {v0.\type, v2.\type, v4.\type}, [x0], \postreg
\inst\()4 {v0.\type, v2.\type, v4.\type, v6.\type}, [x0], \postreg
.endm
.irp instr ld,st
.irp bits_64 8b, 4h, 2s
ldst34_reg_list_post_imm_reg_64 \instr \bits_64 x7
.endr
.endr
.irp instr ld,st
.irp bits_128 16b, 8h, 4s, 2d
ldst34_reg_list_post_imm_reg_128 \instr \bits_128 x7
.endr
.endr
// LD1R expects one register only.
ld1r {v0.8b, v1.8b}, [x0], #1
ld1r {v0.16b, v1.16b}, [x0], #1
ld1r {v0.4h, v1.4h}, [x0], #2
ld1r {v0.8h, v1.8h}, [x0], #2
ld1r {v0.2s, v1.2s}, [x0], #4
ld1r {v0.4s, v1.4s}, [x0], #4
ld1r {v0.1d, v1.1d}, [x0], #8
ld1r {v0.2d, v1.2d}, [x0], #8
.macro ldstn_index_rep_H_altreg_imm inst index type rep
\inst\()2\rep {v0.\type, v2.\type}\index, [x0], #4
\inst\()3\rep {v0.\type, v2.\type, v4.\type}\index, [x0], #6
\inst\()4\rep {v0.\type, v2.\type, v4.\type, v6.\type}\index, [x0], #8
.endm
.irp instr, ld, st
ldstn_index_rep_H_altreg_imm \instr index="[1]" type=h rep=""
.ifnc \instr, st
.irp types 4h, 8h
ldstn_index_rep_H_altreg_imm \instr index="" type=\types rep="r"
.endr
.endif
.endr
.macro ldstn_index_rep_S_altreg_imm inst index type rep
\inst\()2\rep {v0.\type, v2.\type}\index, [x0], #8
\inst\()3\rep {v0.\type, v2.\type, v4.\type}\index, [x0], #12
\inst\()4\rep {v0.\type, v2.\type, v4.\type, v6.\type}\index, [x0], #16
.endm
.irp instr, ld, st
ldstn_index_rep_S_altreg_imm \instr index="[1]" type=s rep=""
.ifnc \instr, st
.irp types 2s, 4s
ldstn_index_rep_S_altreg_imm \instr index="" type=\types rep="r"
.endr
.endif
.endr
.macro ldstn_index_rep_D_altreg_imm inst index type rep
\inst\()2\rep {v0.\type, v2.\type}\index, [x0], #16
\inst\()3\rep {v0.\type, v2.\type, v4.\type}\index, [x0], #24
\inst\()4\rep {v0.\type, v2.\type, v4.\type, v6.\type}\index, [x0], #32
.endm
.irp instr, ld, st
ldstn_index_rep_D_altreg_imm \instr index="[1]" type=d rep=""
.ifnc \instr, st
.irp types 1d, 2d
ldstn_index_rep_D_altreg_imm \instr index="" type=\types rep="r"
.endr
.endif
.endr
.irp type 8b, 16b, 4h, 8h, 2s, 4s, 1d, 2d
ld1r {v0.\type, v1.\type}, [x0], x7
.endr
.macro ldstn_index_rep_reg_altreg inst index type rep postreg
\inst\()2\rep {v0.\type, v2.\type}\index, [x0], \postreg
\inst\()3\rep {v0.\type, v2.\type, v4.\type}\index, [x0], \postreg
\inst\()4\rep {v0.\type, v2.\type, v4.\type, v6.\type}\index, [x0], \postreg
.endm
.irp instr, ld, st
.irp itypes b,h,s,d
ldstn_index_rep_reg_altreg \instr index="[1]" type=\itypes rep="" postreg=x7
.endr
.ifnc \instr, st
.irp types 8b, 16b, 4h, 8h, 2s, 4s, 1d, 2d
ldstn_index_rep_reg_altreg \instr index="" type=\types rep="r" postreg=x7
.endr
.endif
.endr
.macro ldnstn_reg_list type inst index rep
.ifb \index
.ifnb \rep
\inst\()1\rep {v0.\type, v1.\type}\index, [x0]
.endif
.endif
.ifnc \type, B
\inst\()2\rep {v0.\type, v2.\type}\index, [x0]
.endif
.ifnc \type, B
\inst\()3\rep {v0.\type, v2.\type, v4.\type}\index, [x0]
.endif
.ifnc \type, B
\inst\()4\rep {v0.\type, v2.\type, v4.\type, v6.\type}\index, [x0]
.endif
.endm
ldnstn_reg_list type="8B", inst="ld" index="" rep=""
ldnstn_reg_list type="8B", inst="st" index="" rep=""
ldnstn_reg_list type="16B", inst="ld" index="" rep=""
ldnstn_reg_list type="16B", inst="st" index="" rep=""
ldnstn_reg_list type="4H", inst="ld" index="" rep=""
ldnstn_reg_list type="4H", inst="st" index="" rep=""
ldnstn_reg_list type="8H", inst="ld" index="" rep=""
ldnstn_reg_list type="8H", inst="st" index="" rep=""
ldnstn_reg_list type="2S", inst="ld" index="" rep=""
ldnstn_reg_list type="2S", inst="st" index="" rep=""
ldnstn_reg_list type="4S", inst="ld" index="" rep=""
ldnstn_reg_list type="4S", inst="st" index="" rep=""
ldnstn_reg_list type="2D", inst="ld" index="" rep=""
ldnstn_reg_list type="2D", inst="st" index="" rep=""
ldnstn_reg_list type="B", inst="ld" index="[1]" rep=""
ldnstn_reg_list type="B", inst="st" index="[1]" rep=""
ldnstn_reg_list type="B", inst="ld" index="[1]" rep=""
ldnstn_reg_list type="B", inst="st" index="[1]" rep=""
ldnstn_reg_list type="H", inst="ld" index="[1]" rep=""
ldnstn_reg_list type="H", inst="st" index="[1]" rep=""
ldnstn_reg_list type="H", inst="ld" index="[1]" rep=""
ldnstn_reg_list type="H", inst="st" index="[1]" rep=""
ldnstn_reg_list type="S", inst="ld" index="[1]" rep=""
ldnstn_reg_list type="S", inst="st" index="[1]" rep=""
ldnstn_reg_list type="S", inst="ld" index="[1]" rep=""
ldnstn_reg_list type="S", inst="st" index="[1]" rep=""
ldnstn_reg_list type="D", inst="ld" index="[1]" rep=""
ldnstn_reg_list type="D", inst="st" index="[1]" rep=""
ldnstn_reg_list type="8B", inst="ld" index="" rep="r"
ldnstn_reg_list type="16B", inst="ld" index="" rep="r"
ldnstn_reg_list type="4H", inst="ld" index="" rep="r"
ldnstn_reg_list type="8H", inst="ld" index="" rep="r"
ldnstn_reg_list type="2S", inst="ld" index="" rep="r"
ldnstn_reg_list type="4S", inst="ld" index="" rep="r"
ldnstn_reg_list type="1D", inst="ld" index="" rep="r"
ldnstn_reg_list type="2D", inst="ld" index="" rep="r"
pmull v0.1q, v1.1d, v2.1d
pmull2 v0.1q, v1.2d, v2.2d
// #<fbits> out of range
.irp instr, scvtf, ucvtf
\instr d0, w1, 33
\instr s0, w0, 33
\instr d0, x1, 65
\instr s0, x1, 65
.endr
.irp instr, fcvtzs, fcvtzu
\instr w1, d0, 33
\instr w0, s0, 33
\instr x1, d0, 65
\instr x1, s0, 65
.endr
// Invalid instruction.
mockup-op
ldrh w0, [x1, x2, lsr #1]
add w0, w1, w2, ror #1
sub w0, w1, w2, asr #32
eor w0, w1, w2, ror #32
add x0, x1, #20, LSL #16
add x0, x1, #20, UXTX #12
add x0, x1, #20, LSR
add x0, x1, #20, LSL
ldnp h7, h15, [x0, #2]
ldnp b15, b31, [x0], #4
ldnp h0, h1, [x0, #6]!
uqrshrn h0, s1, #63
sqshl b7, b15, #8
bfxil w7, w15, #15, #30
bfi x3, x7, #31, #48
str x1,page_table_count
prfm PLDL3KEEP, [x9, x15, sxtx #2]
mrs x5, S1_0_C13_C8_0
msr S3_1_C13_C15_1, x7
msr S3_1_C11_C15_-1, x7
msr S3_1_11_15_1, x7
// MOVI (alias of ORR immediate) is no longer supported.
movi w1, #15
.set u48, 0xaabbccddeeff
uxtb x7, x15
uxth x7, x15
uxtw x7, x15
sxtb w15, xzr
sxth w15, xzr
sxtw w15, xzr
mov w0, v0.b[0]
mov w0, v0.h[0]
mov w0, v0.d[0]
mov x0, v0.b[0]
mov x0, v0.h[0]
mov x0, v0.s[0]
uabdl2 v20.4S, v12.8H, v29.8
movi d1, 0xffff, lsl #16
ST3 {v18.D-v20.D}[0],[x28],x
ST1 {v7.B}[2],[x4],x
ST1 {v22.1D-v25.1D},[x10],x
ldr w0, [x0]!
ldr w0, [x0], {127}
orr x0, x0, #0xff, lsl #1
orr x0. x0, #0xff, lsl #1
orr x0, x0, #0xff lsl #1
mov x0, ##5

8
gas/testsuite/gas/aarch64/inst-directive.d Normal file
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@ -0,0 +1,8 @@
#objdump: -dr
.*: file format .*
Disassembly of section \.text:
0000000000000000 <.*>:
0: 3619194c tbz w12, #3, 2328 <\.text\+0x2328>

5
gas/testsuite/gas/aarch64/inst-directive.s Normal file
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@ -0,0 +1,5 @@
// inst-directive.s Test file for AArch64 .inst directive.
// This test file is also useful in testing the disassembler.
.text
.inst 0x3619194c

80
gas/testsuite/gas/aarch64/int-insns.d Normal file
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@ -0,0 +1,80 @@
#objdump: -dr
#as: -march=armv8
.*: file format .*
Disassembly of section .text:
0000000000000000 <.*>:
0: 9ac32041 lsl x1, x2, x3
4: d340fc41 lsr x1, x2, #0
8: d37ff841 lsl x1, x2, #1
c: 93c30441 extr x1, x2, x3, #1
10: 93c3fc41 extr x1, x2, x3, #63
14: 93c30041 extr x1, x2, x3, #0
18: 13837c41 extr w1, w2, w3, #31
1c: 9a9f17e1 cset x1, eq
20: da9f13e1 csetm x1, eq
24: 71000021 subs w1, w1, #0x0
28: 7100003f cmp w1, #0x0
2c: 4b0203e1 neg w1, w2
30: 51000041 sub w1, w2, #0x0
34: f100003f cmp x1, #0x0
38: f1000021 subs x1, x1, #0x0
3c: 32000fe1 orr w1, wzr, #0xf
40: aa0203e1 mov x1, x2
44: 18000061 ldr w1, 50 <sp>
48: 18000621 ldr w1, 10c <sp\+0xbc>
4c: 58000621 ldr x1, 110 <sp\+0xc0>
0000000000000050 <sp>:
50: 12345678 .word 0x12345678
54: d65f03c0 ret
58: d65f03c0 ret
5c: d65f0040 ret x2
60: 8b22603f add sp, x1, x2
64: 91401ca5 add x5, x5, #0x7, lsl #12
68: 8b430441 add x1, x2, x3, lsr #1
6c: 91001ca5 add x5, x5, #0x7
70: 71000421 subs w1, w1, #0x1
74: d2800c82 movz x2, #0x64
78: d2800c82 movz x2, #0x64
7c: d2800c82 movz x2, #0x64
80: d2a00c82 movz x2, #0x64, lsl #16
84: d2a00c82 movz x2, #0x64, lsl #16
88: d2c00c82 movz x2, #0x64, lsl #32
8c: d2c00c82 movz x2, #0x64, lsl #32
90: d2e00c82 movz x2, #0x64, lsl #48
94: d2e00c82 movz x2, #0x64, lsl #48
98: 52800c81 movz w1, #0x64
9c: 52800c81 movz w1, #0x64
a0: 52a00c81 movz w1, #0x64, lsl #16
a4: 8a030041 and x1, x2, x3
a8: 0a0f015e and w30, w10, w15
ac: 12000041 and w1, w2, #0x1
b0: 8a430441 and x1, x2, x3, lsr #1
b4: 32000021 orr w1, w1, #0x1
b8: 32000021 orr w1, w1, #0x1
bc: b2400021 orr x1, x1, #0x1
c0: 92400c41 and x1, x2, #0xf
c4: 12000c41 and w1, w2, #0xf
c8: 92610041 and x1, x2, #0x80000000
cc: 12010041 and w1, w2, #0x80000000
d0: 925d0041 and x1, x2, #0x800000000
d4: 92400c85 and x5, x4, #0xf
d8: 0a230041 bic w1, w2, w3
dc: 8a230041 bic x1, x2, x3
e0: 54000001 b.ne e0 <sp\+0x90>
e4: 17ffffff b e0 <sp\+0x90>
e8: 14000001 b ec <sp\+0x9c>
ec: 54ffffa0 b.eq e0 <sp\+0x90>
f0: 54000001 b.ne f0 <sp\+0xa0>
f4: 17ffffff b f0 <sp\+0xa0>
f8: 14000001 b fc <sp\+0xac>
fc: 54ffffa0 b.eq f0 <sp\+0xa0>
100: d61f0040 br x2
104: 54ffffc2 b.cs fc <sp\+0xac>
108: 54ffffa3 b.cc fc <sp\+0xac>
...
10c: R_AARCH64_ABS32 .text\+0x50
110: R_AARCH64_ABS64 .text\+0x50

151
gas/testsuite/gas/aarch64/int-insns.s Normal file
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@ -0,0 +1,151 @@
// Test file for AArch64 GAS -- basic integer instructions
func:
lsl x1, x2, x3
lsl x1, x2, #0
lsl x1, x2, #1
extr x1, x2, x3, #1
extr x1, x2, x3, #63
extr x1, x2, x3, #0
extr w1, w2, w3, #31
CSET x1, eq
CSETM x1, eq
subs w1,w1,#0
cmp w1,#0
neg w1,w2
sub w1,w2,#0
cmp x1,#0
subs x1,x1,#0
orr w1,wzr,#15
mov x1,x2
ldr w1, sp
ldr w1, =sp
ldr x1, =sp
sp: .word 0x12345678
ret x30
ret
ret x2
add sp,x1,x2
add x5,x5,#0x7, lsl #12
add x1,x2,x3, lsr #1
add x5,x5,#0x7
subs w1,w1,#1
movz x2,#0x64
movz x2,#0x64, lsl #0
movz x2,#:abs_g0:0x64
movz x2,#0x64, lsl #16
movz x2,#:abs_g1:(0x64 << 16)
movz x2,#0x64, lsl #32
movz x2,#:abs_g2:(0x64 << 32)
movz x2,#0x64, lsl #48
movz x2,#:abs_g3:(0x64 << 48)
movz w1,#0x64
movz w1,#0x64, lsl #0
movz w1,#0x64, lsl #16
and x1,x2,x3
and w30,w10,w15
and w1,w2,#1
and x1,x2,x3, lsr #1
orr w1,w1,#1
orr w1,w1,#1
orr x1,x1,#1
and x1,x2,#0xf
and w1,w2,#0xf
and x1,x2,#0x80000000
and w1,w2,#0x80000000
and x1,x2,#0x800000000
// 00010010000101000000010100000011
// 1 2 1 4 0 5 0 3
and x5,x4,#0xf
bic w1,w2,w3
bic x1,x2,x3
1: b.ne 1b
b 1b
b 2f
2: b.eq 1b
3: bne 3b
b 3b
b 4f
4: beq 3b
br x2
bcs 4b
bcc 4b
.if 0
lsl x1, #0, #1
ext x1, x2, x3, #64
ext w1, w2, w3, #63
ext w1, w2, w3, #32
mov w1,#10
neg w1,#1
ldm {x1},[sp]
ldm {x1-x2},[sp]
ldm {x1,x2,x3,x4},sp
ldm {x1-x3},[x1,w2]
subs #0,#1
add x5,x5,#0x7, lsl #1
add x5,x5,#0x7, lsr #1
movz x0,#0x64, lsl #1
movz x0,#0x64, lsl #2
movz x0,#0x64, lsl #3
movz x0,#0x64, lsl #4
movz x0,#0x64, lsl #64
movz w1,#0x64, lsl #32
movz w1,#0x64, lsl #48
orr #0,w1
and sp,x1,x2
and x1,sp,x2
and x1,x2,sp
and w1,#0,x2
and x1,#0,w2
and x1,x2,w3
and x1,w2,x3
and x1,w2,w3
and w1,x2,x3
and w1,x2,w3
and w1,w2,x3
and w1,w2,w3
and x1,x2,#0
and w1,w2,#0x800000000
bic x1,x2,#1
br w2
br sp
.endif
.equ sh,2

103
gas/testsuite/gas/aarch64/ldst-exclusive.d Normal file
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@ -0,0 +1,103 @@
#objdump: -dr
.*: file format .*
Disassembly of section \.text:
0000000000000000 <.*>:
0: 080f7ce1 stxrb w15, w1, \[x7\]
4: 080f7ce1 stxrb w15, w1, \[x7\]
8: 080f7ce1 stxrb w15, w1, \[x7\]
c: 480f7ce1 stxrh w15, w1, \[x7\]
10: 480f7ce1 stxrh w15, w1, \[x7\]
14: 480f7ce1 stxrh w15, w1, \[x7\]
18: 880f7ce1 stxr w15, w1, \[x7\]
1c: 880f7ce1 stxr w15, w1, \[x7\]
20: 880f7ce1 stxr w15, w1, \[x7\]
24: c80f7ce1 stxr w15, x1, \[x7\]
28: c80f7ce1 stxr w15, x1, \[x7\]
2c: c80f7ce1 stxr w15, x1, \[x7\]
30: 085f7ce1 ldxrb w1, \[x7\]
34: 085f7ce1 ldxrb w1, \[x7\]
38: 085f7ce1 ldxrb w1, \[x7\]
3c: 485f7ce1 ldxrh w1, \[x7\]
40: 485f7ce1 ldxrh w1, \[x7\]
44: 485f7ce1 ldxrh w1, \[x7\]
48: 885f7ce1 ldxr w1, \[x7\]
4c: 885f7ce1 ldxr w1, \[x7\]
50: 885f7ce1 ldxr w1, \[x7\]
54: c85f7ce1 ldxr x1, \[x7\]
58: c85f7ce1 ldxr x1, \[x7\]
5c: c85f7ce1 ldxr x1, \[x7\]
60: 882f08e1 stxp w15, w1, w2, \[x7\]
64: 882f08e1 stxp w15, w1, w2, \[x7\]
68: 882f08e1 stxp w15, w1, w2, \[x7\]
6c: c82f08e1 stxp w15, x1, x2, \[x7\]
70: c82f08e1 stxp w15, x1, x2, \[x7\]
74: c82f08e1 stxp w15, x1, x2, \[x7\]
78: 887f08e1 ldxp w1, w2, \[x7\]
7c: 887f08e1 ldxp w1, w2, \[x7\]
80: 887f08e1 ldxp w1, w2, \[x7\]
84: c87f08e1 ldxp x1, x2, \[x7\]
88: c87f08e1 ldxp x1, x2, \[x7\]
8c: c87f08e1 ldxp x1, x2, \[x7\]
90: 080ffce1 stlxrb w15, w1, \[x7\]
94: 080ffce1 stlxrb w15, w1, \[x7\]
98: 080ffce1 stlxrb w15, w1, \[x7\]
9c: 480ffce1 stlxrh w15, w1, \[x7\]
a0: 480ffce1 stlxrh w15, w1, \[x7\]
a4: 480ffce1 stlxrh w15, w1, \[x7\]
a8: 880ffce1 stlxr w15, w1, \[x7\]
ac: 880ffce1 stlxr w15, w1, \[x7\]
b0: 880ffce1 stlxr w15, w1, \[x7\]
b4: c80ffce1 stlxr w15, x1, \[x7\]
b8: c80ffce1 stlxr w15, x1, \[x7\]
bc: c80ffce1 stlxr w15, x1, \[x7\]
c0: 085ffce1 ldaxrb w1, \[x7\]
c4: 085ffce1 ldaxrb w1, \[x7\]
c8: 085ffce1 ldaxrb w1, \[x7\]
cc: 485ffce1 ldaxrh w1, \[x7\]
d0: 485ffce1 ldaxrh w1, \[x7\]
d4: 485ffce1 ldaxrh w1, \[x7\]
d8: 885ffce1 ldaxr w1, \[x7\]
dc: 885ffce1 ldaxr w1, \[x7\]
e0: 885ffce1 ldaxr w1, \[x7\]
e4: c85ffce1 ldaxr x1, \[x7\]
e8: c85ffce1 ldaxr x1, \[x7\]
ec: c85ffce1 ldaxr x1, \[x7\]
f0: 882f88e1 stlxp w15, w1, w2, \[x7\]
f4: 882f88e1 stlxp w15, w1, w2, \[x7\]
f8: 882f88e1 stlxp w15, w1, w2, \[x7\]
fc: c82f88e1 stlxp w15, x1, x2, \[x7\]
100: c82f88e1 stlxp w15, x1, x2, \[x7\]
104: c82f88e1 stlxp w15, x1, x2, \[x7\]
108: 887f88e1 ldaxp w1, w2, \[x7\]
10c: 887f88e1 ldaxp w1, w2, \[x7\]
110: 887f88e1 ldaxp w1, w2, \[x7\]
114: c87f88e1 ldaxp x1, x2, \[x7\]
118: c87f88e1 ldaxp x1, x2, \[x7\]
11c: c87f88e1 ldaxp x1, x2, \[x7\]
120: 089ffce1 stlrb w1, \[x7\]
124: 089ffce1 stlrb w1, \[x7\]
128: 089ffce1 stlrb w1, \[x7\]
12c: 489ffce1 stlrh w1, \[x7\]
130: 489ffce1 stlrh w1, \[x7\]
134: 489ffce1 stlrh w1, \[x7\]
138: 889ffce1 stlr w1, \[x7\]
13c: 889ffce1 stlr w1, \[x7\]
140: 889ffce1 stlr w1, \[x7\]
144: c89ffce1 stlr x1, \[x7\]
148: c89ffce1 stlr x1, \[x7\]
14c: c89ffce1 stlr x1, \[x7\]
150: 08dffce1 ldarb w1, \[x7\]
154: 08dffce1 ldarb w1, \[x7\]
158: 08dffce1 ldarb w1, \[x7\]
15c: 48dffce1 ldarh w1, \[x7\]
160: 48dffce1 ldarh w1, \[x7\]
164: 48dffce1 ldarh w1, \[x7\]
168: 88dffce1 ldar w1, \[x7\]
16c: 88dffce1 ldar w1, \[x7\]
170: 88dffce1 ldar w1, \[x7\]
174: c8dffce1 ldar x1, \[x7\]
178: c8dffce1 ldar x1, \[x7\]
17c: c8dffce1 ldar x1, \[x7\]

139
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/* ldst-exclusive.s Test file for AArch64 load-store exclusive
instructions.
Copyright 2011, 2012 Free Software Foundation, Inc.
Contributed by ARM Ltd.
This file is part of GAS.
GAS is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the license, or
(at your option) any later version.
GAS is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; see the file COPYING3. If not,
see <http://www.gnu.org/licenses/>. */
/* <mnemonic> <Wt>, [<Xn|SP>]{,#0}] */
.macro LR32 op
\op w1, [x7]
\op w1, [x7, #0]
\op w1, [x7, 0]
.endm
/* <mnemonic> <Xt>, [<Xn|SP>]{,#0}] */
.macro LR64 op
\op x1, [x7]
\op x1, [x7, #0]
\op x1, [x7, 0]
.endm
/* <mnemonic> <Ws>, <Wt>, [<Xn|SP>]{,#0}] */
.macro SR32 op
\op w15, w1, [x7]
\op w15, w1, [x7, #0]
\op w15, w1, [x7, 0]
.endm
/* <mnemonic> <Ws>, <Xt>, [<Xn|SP>]{,#0}] */
.macro SR64 op
\op w15, x1, [x7]
\op w15, x1, [x7, #0]
\op w15, x1, [x7, 0]
.endm
/* <mnemonic> <Wt1>, <Wt2>, [<Xn|SP>]{,#0}] */
.macro LP32 op
\op w1, w2, [x7]
\op w1, w2, [x7, #0]
\op w1, w2, [x7, 0]
.endm
/* <mnemonic> <Xt1>, <Xt2>, [<Xn|SP>]{,#0}] */
.macro LP64 op
\op x1, x2, [x7]
\op x1, x2, [x7, #0]
\op x1, x2, [x7, 0]
.endm
/* <mnemonic> <Ws>, <Wt1>, <Wt2>, [<Xn|SP>]{,#0}] */
.macro SP32 op
\op w15, w1, w2, [x7]
\op w15, w1, w2, [x7, #0]
\op w15, w1, w2, [x7, 0]
.endm
/* <mnemonic> <Ws>, <Xt1>, <Xt2>, [<Xn|SP>]{,#0}] */
.macro SP64 op
\op w15, x1, x2, [x7]
\op w15, x1, x2, [x7, #0]
\op w15, x1, x2, [x7, 0]
.endm
/* <mnemonic> <Wt>, [<Xn|SP>]{,#0}] */
.macro SL32 op
\op w1, [x7]
\op w1, [x7, #0]
\op w1, [x7, 0]
.endm
/* <mnemonic> <Xt>, [<Xn|SP>]{,#0}] */
.macro SL64 op
\op x1, [x7]
\op x1, [x7, #0]
\op x1, [x7, 0]
.endm
func:
.irp op, stxrb, stxrh, stxr
SR32 \op
.endr
SR64 stxr
.irp op, ldxrb, ldxrh, ldxr
LR32 \op
.endr
LR64 ldxr
SP32 stxp
SP64 stxp
LP32 ldxp
LP64 ldxp
.irp op, stlxrb, stlxrh, stlxr
SR32 \op
.endr
SR64 stlxr
.irp op, ldaxrb, ldaxrh, ldaxr
LR32 \op
.endr
LR64 ldaxr
SP32 stlxp
SP64 stlxp
LP32 ldaxp
LP64 ldaxp
.irp op, stlrb, stlrh, stlr
SL32 \op
.endr
SL64 stlr
.irp op, ldarb, ldarh, ldar
LR32 \op
.endr
LR64 ldar

214
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#objdump: -dr
.*: file format .*
Disassembly of section \.text:
0000000000000000 <.*>:
0: 3c1007e7 str b7, \[sp\],#-256
4: 3c1557e7 str b7, \[sp\],#-171
8: 3c0007e7 str b7, \[sp\],#0
c: 3c0027e7 str b7, \[sp\],#2
10: 3c0047e7 str b7, \[sp\],#4
14: 3c0087e7 str b7, \[sp\],#8
18: 3c0107e7 str b7, \[sp\],#16
1c: 3c0557e7 str b7, \[sp\],#85
20: 3c0ff7e7 str b7, \[sp\],#255
24: 7c1007e7 str h7, \[sp\],#-256
28: 7c1557e7 str h7, \[sp\],#-171
2c: 7c0007e7 str h7, \[sp\],#0
30: 7c0027e7 str h7, \[sp\],#2
34: 7c0047e7 str h7, \[sp\],#4
38: 7c0087e7 str h7, \[sp\],#8
3c: 7c0107e7 str h7, \[sp\],#16
40: 7c0557e7 str h7, \[sp\],#85
44: 7c0ff7e7 str h7, \[sp\],#255
48: bc1007e7 str s7, \[sp\],#-256
4c: bc1557e7 str s7, \[sp\],#-171
50: bc0007e7 str s7, \[sp\],#0
54: bc0027e7 str s7, \[sp\],#2
58: bc0047e7 str s7, \[sp\],#4
5c: bc0087e7 str s7, \[sp\],#8
60: bc0107e7 str s7, \[sp\],#16
64: bc0557e7 str s7, \[sp\],#85
68: bc0ff7e7 str s7, \[sp\],#255
6c: fc1007e7 str d7, \[sp\],#-256
70: fc1557e7 str d7, \[sp\],#-171
74: fc0007e7 str d7, \[sp\],#0
78: fc0027e7 str d7, \[sp\],#2
7c: fc0047e7 str d7, \[sp\],#4
80: fc0087e7 str d7, \[sp\],#8
84: fc0107e7 str d7, \[sp\],#16
88: fc0557e7 str d7, \[sp\],#85
8c: fc0ff7e7 str d7, \[sp\],#255
90: 3c9007e7 str q7, \[sp\],#-256
94: 3c9557e7 str q7, \[sp\],#-171
98: 3c8007e7 str q7, \[sp\],#0
9c: 3c8027e7 str q7, \[sp\],#2
a0: 3c8047e7 str q7, \[sp\],#4
a4: 3c8087e7 str q7, \[sp\],#8
a8: 3c8107e7 str q7, \[sp\],#16
ac: 3c8557e7 str q7, \[sp\],#85
b0: 3c8ff7e7 str q7, \[sp\],#255
b4: 3c5007e7 ldr b7, \[sp\],#-256
b8: 3c5557e7 ldr b7, \[sp\],#-171
bc: 3c4007e7 ldr b7, \[sp\],#0
c0: 3c4027e7 ldr b7, \[sp\],#2
c4: 3c4047e7 ldr b7, \[sp\],#4
c8: 3c4087e7 ldr b7, \[sp\],#8
cc: 3c4107e7 ldr b7, \[sp\],#16
d0: 3c4557e7 ldr b7, \[sp\],#85
d4: 3c4ff7e7 ldr b7, \[sp\],#255
d8: 7c5007e7 ldr h7, \[sp\],#-256
dc: 7c5557e7 ldr h7, \[sp\],#-171
e0: 7c4007e7 ldr h7, \[sp\],#0
e4: 7c4027e7 ldr h7, \[sp\],#2
e8: 7c4047e7 ldr h7, \[sp\],#4
ec: 7c4087e7 ldr h7, \[sp\],#8
f0: 7c4107e7 ldr h7, \[sp\],#16
f4: 7c4557e7 ldr h7, \[sp\],#85
f8: 7c4ff7e7 ldr h7, \[sp\],#255
fc: bc5007e7 ldr s7, \[sp\],#-256
100: bc5557e7 ldr s7, \[sp\],#-171
104: bc4007e7 ldr s7, \[sp\],#0
108: bc4027e7 ldr s7, \[sp\],#2
10c: bc4047e7 ldr s7, \[sp\],#4
110: bc4087e7 ldr s7, \[sp\],#8
114: bc4107e7 ldr s7, \[sp\],#16
118: bc4557e7 ldr s7, \[sp\],#85
11c: bc4ff7e7 ldr s7, \[sp\],#255
120: fc5007e7 ldr d7, \[sp\],#-256
124: fc5557e7 ldr d7, \[sp\],#-171
128: fc4007e7 ldr d7, \[sp\],#0
12c: fc4027e7 ldr d7, \[sp\],#2
130: fc4047e7 ldr d7, \[sp\],#4
134: fc4087e7 ldr d7, \[sp\],#8
138: fc4107e7 ldr d7, \[sp\],#16
13c: fc4557e7 ldr d7, \[sp\],#85
140: fc4ff7e7 ldr d7, \[sp\],#255
144: 3cd007e7 ldr q7, \[sp\],#-256
148: 3cd557e7 ldr q7, \[sp\],#-171
14c: 3cc007e7 ldr q7, \[sp\],#0
150: 3cc027e7 ldr q7, \[sp\],#2
154: 3cc047e7 ldr q7, \[sp\],#4
158: 3cc087e7 ldr q7, \[sp\],#8
15c: 3cc107e7 ldr q7, \[sp\],#16
160: 3cc557e7 ldr q7, \[sp\],#85
164: 3ccff7e7 ldr q7, \[sp\],#255
168: 381007e7 strb w7, \[sp\],#-256
16c: 381557e7 strb w7, \[sp\],#-171
170: 380007e7 strb w7, \[sp\],#0
174: 380027e7 strb w7, \[sp\],#2
178: 380047e7 strb w7, \[sp\],#4
17c: 380087e7 strb w7, \[sp\],#8
180: 380107e7 strb w7, \[sp\],#16
184: 380557e7 strb w7, \[sp\],#85
188: 380ff7e7 strb w7, \[sp\],#255
18c: 781007e7 strh w7, \[sp\],#-256
190: 781557e7 strh w7, \[sp\],#-171
194: 780007e7 strh w7, \[sp\],#0
198: 780027e7 strh w7, \[sp\],#2
19c: 780047e7 strh w7, \[sp\],#4
1a0: 780087e7 strh w7, \[sp\],#8
1a4: 780107e7 strh w7, \[sp\],#16
1a8: 780557e7 strh w7, \[sp\],#85
1ac: 780ff7e7 strh w7, \[sp\],#255
1b0: b81007e7 str w7, \[sp\],#-256
1b4: b81557e7 str w7, \[sp\],#-171
1b8: b80007e7 str w7, \[sp\],#0
1bc: b80027e7 str w7, \[sp\],#2
1c0: b80047e7 str w7, \[sp\],#4
1c4: b80087e7 str w7, \[sp\],#8
1c8: b80107e7 str w7, \[sp\],#16
1cc: b80557e7 str w7, \[sp\],#85
1d0: b80ff7e7 str w7, \[sp\],#255
1d4: f81007e7 str x7, \[sp\],#-256
1d8: f81557e7 str x7, \[sp\],#-171
1dc: f80007e7 str x7, \[sp\],#0
1e0: f80027e7 str x7, \[sp\],#2
1e4: f80047e7 str x7, \[sp\],#4
1e8: f80087e7 str x7, \[sp\],#8
1ec: f80107e7 str x7, \[sp\],#16
1f0: f80557e7 str x7, \[sp\],#85
1f4: f80ff7e7 str x7, \[sp\],#255
1f8: 385007e7 ldrb w7, \[sp\],#-256
1fc: 385557e7 ldrb w7, \[sp\],#-171
200: 384007e7 ldrb w7, \[sp\],#0
204: 384027e7 ldrb w7, \[sp\],#2
208: 384047e7 ldrb w7, \[sp\],#4
20c: 384087e7 ldrb w7, \[sp\],#8
210: 384107e7 ldrb w7, \[sp\],#16
214: 384557e7 ldrb w7, \[sp\],#85
218: 384ff7e7 ldrb w7, \[sp\],#255
21c: 785007e7 ldrh w7, \[sp\],#-256
220: 785557e7 ldrh w7, \[sp\],#-171
224: 784007e7 ldrh w7, \[sp\],#0
228: 784027e7 ldrh w7, \[sp\],#2
22c: 784047e7 ldrh w7, \[sp\],#4
230: 784087e7 ldrh w7, \[sp\],#8
234: 784107e7 ldrh w7, \[sp\],#16
238: 784557e7 ldrh w7, \[sp\],#85
23c: 784ff7e7 ldrh w7, \[sp\],#255
240: b85007e7 ldr w7, \[sp\],#-256
244: b85557e7 ldr w7, \[sp\],#-171
248: b84007e7 ldr w7, \[sp\],#0
24c: b84027e7 ldr w7, \[sp\],#2
250: b84047e7 ldr w7, \[sp\],#4
254: b84087e7 ldr w7, \[sp\],#8
258: b84107e7 ldr w7, \[sp\],#16
25c: b84557e7 ldr w7, \[sp\],#85
260: b84ff7e7 ldr w7, \[sp\],#255
264: f85007e7 ldr x7, \[sp\],#-256
268: f85557e7 ldr x7, \[sp\],#-171
26c: f84007e7 ldr x7, \[sp\],#0
270: f84027e7 ldr x7, \[sp\],#2
274: f84047e7 ldr x7, \[sp\],#4
278: f84087e7 ldr x7, \[sp\],#8
27c: f84107e7 ldr x7, \[sp\],#16
280: f84557e7 ldr x7, \[sp\],#85
284: f84ff7e7 ldr x7, \[sp\],#255
288: 389007e7 ldrsb x7, \[sp\],#-256
28c: 389557e7 ldrsb x7, \[sp\],#-171
290: 388007e7 ldrsb x7, \[sp\],#0
294: 388027e7 ldrsb x7, \[sp\],#2
298: 388047e7 ldrsb x7, \[sp\],#4
29c: 388087e7 ldrsb x7, \[sp\],#8
2a0: 388107e7 ldrsb x7, \[sp\],#16
2a4: 388557e7 ldrsb x7, \[sp\],#85
2a8: 388ff7e7 ldrsb x7, \[sp\],#255
2ac: 789007e7 ldrsh x7, \[sp\],#-256
2b0: 789557e7 ldrsh x7, \[sp\],#-171
2b4: 788007e7 ldrsh x7, \[sp\],#0
2b8: 788027e7 ldrsh x7, \[sp\],#2
2bc: 788047e7 ldrsh x7, \[sp\],#4
2c0: 788087e7 ldrsh x7, \[sp\],#8
2c4: 788107e7 ldrsh x7, \[sp\],#16
2c8: 788557e7 ldrsh x7, \[sp\],#85
2cc: 788ff7e7 ldrsh x7, \[sp\],#255
2d0: b89007e7 ldrsw x7, \[sp\],#-256
2d4: b89557e7 ldrsw x7, \[sp\],#-171
2d8: b88007e7 ldrsw x7, \[sp\],#0
2dc: b88027e7 ldrsw x7, \[sp\],#2
2e0: b88047e7 ldrsw x7, \[sp\],#4
2e4: b88087e7 ldrsw x7, \[sp\],#8
2e8: b88107e7 ldrsw x7, \[sp\],#16
2ec: b88557e7 ldrsw x7, \[sp\],#85
2f0: b88ff7e7 ldrsw x7, \[sp\],#255
2f4: 38d007e7 ldrsb w7, \[sp\],#-256
2f8: 38d557e7 ldrsb w7, \[sp\],#-171
2fc: 38c007e7 ldrsb w7, \[sp\],#0
300: 38c027e7 ldrsb w7, \[sp\],#2
304: 38c047e7 ldrsb w7, \[sp\],#4
308: 38c087e7 ldrsb w7, \[sp\],#8
30c: 38c107e7 ldrsb w7, \[sp\],#16
310: 38c557e7 ldrsb w7, \[sp\],#85
314: 38cff7e7 ldrsb w7, \[sp\],#255
318: 78d007e7 ldrsh w7, \[sp\],#-256
31c: 78d557e7 ldrsh w7, \[sp\],#-171
320: 78c007e7 ldrsh w7, \[sp\],#0
324: 78c027e7 ldrsh w7, \[sp\],#2
328: 78c047e7 ldrsh w7, \[sp\],#4
32c: 78c087e7 ldrsh w7, \[sp\],#8
330: 78c107e7 ldrsh w7, \[sp\],#16
334: 78c557e7 ldrsh w7, \[sp\],#85
338: 78cff7e7 ldrsh w7, \[sp\],#255

62
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/* ldst-reg-imm-post-ind.s Test file for AArch64
load-store reg. (imm.post-ind.) instructions.
Copyright 2011, 2012 Free Software Foundation, Inc.
Contributed by ARM Ltd.
This file is part of GAS.
GAS is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the license, or
(at your option) any later version.
GAS is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; see the file COPYING3. If not,
see <http://www.gnu.org/licenses/>. */
.macro op2 op, reg, simm
\op \reg\()7, [sp], #\simm
.endm
// load to or store from core register
.macro ld_or_st op, suffix, reg
.irp simm, -256, -171, 0, 2, 4, 8, 16, 85, 255
op2 \op\suffix, \reg, \simm
.endr
.endm
// load to or store from FP/SIMD register
.macro ld_or_st_v op
.irp reg, b, h, s, d, q
.irp simm, -256, -171, 0, 2, 4, 8, 16, 85, 255
op2 \op, \reg, \simm
.endr
.endr
.endm
func:
// load to or store from FP/SIMD register
ld_or_st_v str
ld_or_st_v ldr
// load to or store from core register
// op, suffix, reg
ld_or_st str, b, w
ld_or_st str, h, w
ld_or_st str, , w
ld_or_st str, , x
ld_or_st ldr, b, w
ld_or_st ldr, h, w
ld_or_st ldr, , w
ld_or_st ldr, , x
ld_or_st ldr, sb, x
ld_or_st ldr, sh, x
ld_or_st ldr, sw, x
ld_or_st ldr, sb, w
ld_or_st ldr, sh, w

214
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#objdump: -dr
.*: file format .*
Disassembly of section \.text:
0000000000000000 <.*>:
0: 3c100fe7 str b7, \[sp,#-256\]!
4: 3c155fe7 str b7, \[sp,#-171\]!
8: 3c000fe7 str b7, \[sp,#0\]!
c: 3c002fe7 str b7, \[sp,#2\]!
10: 3c004fe7 str b7, \[sp,#4\]!
14: 3c008fe7 str b7, \[sp,#8\]!
18: 3c010fe7 str b7, \[sp,#16\]!
1c: 3c055fe7 str b7, \[sp,#85\]!
20: 3c0fffe7 str b7, \[sp,#255\]!
24: 7c100fe7 str h7, \[sp,#-256\]!
28: 7c155fe7 str h7, \[sp,#-171\]!
2c: 7c000fe7 str h7, \[sp,#0\]!
30: 7c002fe7 str h7, \[sp,#2\]!
34: 7c004fe7 str h7, \[sp,#4\]!
38: 7c008fe7 str h7, \[sp,#8\]!
3c: 7c010fe7 str h7, \[sp,#16\]!
40: 7c055fe7 str h7, \[sp,#85\]!
44: 7c0fffe7 str h7, \[sp,#255\]!
48: bc100fe7 str s7, \[sp,#-256\]!
4c: bc155fe7 str s7, \[sp,#-171\]!
50: bc000fe7 str s7, \[sp,#0\]!
54: bc002fe7 str s7, \[sp,#2\]!
58: bc004fe7 str s7, \[sp,#4\]!
5c: bc008fe7 str s7, \[sp,#8\]!
60: bc010fe7 str s7, \[sp,#16\]!
64: bc055fe7 str s7, \[sp,#85\]!
68: bc0fffe7 str s7, \[sp,#255\]!
6c: fc100fe7 str d7, \[sp,#-256\]!
70: fc155fe7 str d7, \[sp,#-171\]!
74: fc000fe7 str d7, \[sp,#0\]!
78: fc002fe7 str d7, \[sp,#2\]!
7c: fc004fe7 str d7, \[sp,#4\]!
80: fc008fe7 str d7, \[sp,#8\]!
84: fc010fe7 str d7, \[sp,#16\]!
88: fc055fe7 str d7, \[sp,#85\]!
8c: fc0fffe7 str d7, \[sp,#255\]!
90: 3c900fe7 str q7, \[sp,#-256\]!
94: 3c955fe7 str q7, \[sp,#-171\]!
98: 3c800fe7 str q7, \[sp,#0\]!
9c: 3c802fe7 str q7, \[sp,#2\]!
a0: 3c804fe7 str q7, \[sp,#4\]!
a4: 3c808fe7 str q7, \[sp,#8\]!
a8: 3c810fe7 str q7, \[sp,#16\]!
ac: 3c855fe7 str q7, \[sp,#85\]!
b0: 3c8fffe7 str q7, \[sp,#255\]!
b4: 3c500fe7 ldr b7, \[sp,#-256\]!
b8: 3c555fe7 ldr b7, \[sp,#-171\]!
bc: 3c400fe7 ldr b7, \[sp,#0\]!
c0: 3c402fe7 ldr b7, \[sp,#2\]!
c4: 3c404fe7 ldr b7, \[sp,#4\]!
c8: 3c408fe7 ldr b7, \[sp,#8\]!
cc: 3c410fe7 ldr b7, \[sp,#16\]!
d0: 3c455fe7 ldr b7, \[sp,#85\]!
d4: 3c4fffe7 ldr b7, \[sp,#255\]!
d8: 7c500fe7 ldr h7, \[sp,#-256\]!
dc: 7c555fe7 ldr h7, \[sp,#-171\]!
e0: 7c400fe7 ldr h7, \[sp,#0\]!
e4: 7c402fe7 ldr h7, \[sp,#2\]!
e8: 7c404fe7 ldr h7, \[sp,#4\]!
ec: 7c408fe7 ldr h7, \[sp,#8\]!
f0: 7c410fe7 ldr h7, \[sp,#16\]!
f4: 7c455fe7 ldr h7, \[sp,#85\]!
f8: 7c4fffe7 ldr h7, \[sp,#255\]!
fc: bc500fe7 ldr s7, \[sp,#-256\]!
100: bc555fe7 ldr s7, \[sp,#-171\]!
104: bc400fe7 ldr s7, \[sp,#0\]!
108: bc402fe7 ldr s7, \[sp,#2\]!
10c: bc404fe7 ldr s7, \[sp,#4\]!
110: bc408fe7 ldr s7, \[sp,#8\]!
114: bc410fe7 ldr s7, \[sp,#16\]!
118: bc455fe7 ldr s7, \[sp,#85\]!
11c: bc4fffe7 ldr s7, \[sp,#255\]!
120: fc500fe7 ldr d7, \[sp,#-256\]!
124: fc555fe7 ldr d7, \[sp,#-171\]!
128: fc400fe7 ldr d7, \[sp,#0\]!
12c: fc402fe7 ldr d7, \[sp,#2\]!
130: fc404fe7 ldr d7, \[sp,#4\]!
134: fc408fe7 ldr d7, \[sp,#8\]!
138: fc410fe7 ldr d7, \[sp,#16\]!
13c: fc455fe7 ldr d7, \[sp,#85\]!
140: fc4fffe7 ldr d7, \[sp,#255\]!
144: 3cd00fe7 ldr q7, \[sp,#-256\]!
148: 3cd55fe7 ldr q7, \[sp,#-171\]!
14c: 3cc00fe7 ldr q7, \[sp,#0\]!
150: 3cc02fe7 ldr q7, \[sp,#2\]!
154: 3cc04fe7 ldr q7, \[sp,#4\]!
158: 3cc08fe7 ldr q7, \[sp,#8\]!
15c: 3cc10fe7 ldr q7, \[sp,#16\]!
160: 3cc55fe7 ldr q7, \[sp,#85\]!
164: 3ccfffe7 ldr q7, \[sp,#255\]!
168: 38100fe7 strb w7, \[sp,#-256\]!
16c: 38155fe7 strb w7, \[sp,#-171\]!
170: 38000fe7 strb w7, \[sp,#0\]!
174: 38002fe7 strb w7, \[sp,#2\]!
178: 38004fe7 strb w7, \[sp,#4\]!
17c: 38008fe7 strb w7, \[sp,#8\]!
180: 38010fe7 strb w7, \[sp,#16\]!
184: 38055fe7 strb w7, \[sp,#85\]!
188: 380fffe7 strb w7, \[sp,#255\]!
18c: 78100fe7 strh w7, \[sp,#-256\]!
190: 78155fe7 strh w7, \[sp,#-171\]!
194: 78000fe7 strh w7, \[sp,#0\]!
198: 78002fe7 strh w7, \[sp,#2\]!
19c: 78004fe7 strh w7, \[sp,#4\]!
1a0: 78008fe7 strh w7, \[sp,#8\]!
1a4: 78010fe7 strh w7, \[sp,#16\]!
1a8: 78055fe7 strh w7, \[sp,#85\]!
1ac: 780fffe7 strh w7, \[sp,#255\]!
1b0: b8100fe7 str w7, \[sp,#-256\]!
1b4: b8155fe7 str w7, \[sp,#-171\]!
1b8: b8000fe7 str w7, \[sp,#0\]!
1bc: b8002fe7 str w7, \[sp,#2\]!
1c0: b8004fe7 str w7, \[sp,#4\]!
1c4: b8008fe7 str w7, \[sp,#8\]!
1c8: b8010fe7 str w7, \[sp,#16\]!
1cc: b8055fe7 str w7, \[sp,#85\]!
1d0: b80fffe7 str w7, \[sp,#255\]!
1d4: f8100fe7 str x7, \[sp,#-256\]!
1d8: f8155fe7 str x7, \[sp,#-171\]!
1dc: f8000fe7 str x7, \[sp,#0\]!
1e0: f8002fe7 str x7, \[sp,#2\]!
1e4: f8004fe7 str x7, \[sp,#4\]!
1e8: f8008fe7 str x7, \[sp,#8\]!
1ec: f8010fe7 str x7, \[sp,#16\]!
1f0: f8055fe7 str x7, \[sp,#85\]!
1f4: f80fffe7 str x7, \[sp,#255\]!
1f8: 38500fe7 ldrb w7, \[sp,#-256\]!
1fc: 38555fe7 ldrb w7, \[sp,#-171\]!
200: 38400fe7 ldrb w7, \[sp,#0\]!
204: 38402fe7 ldrb w7, \[sp,#2\]!
208: 38404fe7 ldrb w7, \[sp,#4\]!
20c: 38408fe7 ldrb w7, \[sp,#8\]!
210: 38410fe7 ldrb w7, \[sp,#16\]!
214: 38455fe7 ldrb w7, \[sp,#85\]!
218: 384fffe7 ldrb w7, \[sp,#255\]!
21c: 78500fe7 ldrh w7, \[sp,#-256\]!
220: 78555fe7 ldrh w7, \[sp,#-171\]!
224: 78400fe7 ldrh w7, \[sp,#0\]!
228: 78402fe7 ldrh w7, \[sp,#2\]!
22c: 78404fe7 ldrh w7, \[sp,#4\]!
230: 78408fe7 ldrh w7, \[sp,#8\]!
234: 78410fe7 ldrh w7, \[sp,#16\]!
238: 78455fe7 ldrh w7, \[sp,#85\]!
23c: 784fffe7 ldrh w7, \[sp,#255\]!
240: b8500fe7 ldr w7, \[sp,#-256\]!
244: b8555fe7 ldr w7, \[sp,#-171\]!
248: b8400fe7 ldr w7, \[sp,#0\]!
24c: b8402fe7 ldr w7, \[sp,#2\]!
250: b8404fe7 ldr w7, \[sp,#4\]!
254: b8408fe7 ldr w7, \[sp,#8\]!
258: b8410fe7 ldr w7, \[sp,#16\]!
25c: b8455fe7 ldr w7, \[sp,#85\]!
260: b84fffe7 ldr w7, \[sp,#255\]!
264: f8500fe7 ldr x7, \[sp,#-256\]!
268: f8555fe7 ldr x7, \[sp,#-171\]!
26c: f8400fe7 ldr x7, \[sp,#0\]!
270: f8402fe7 ldr x7, \[sp,#2\]!
274: f8404fe7 ldr x7, \[sp,#4\]!
278: f8408fe7 ldr x7, \[sp,#8\]!
27c: f8410fe7 ldr x7, \[sp,#16\]!
280: f8455fe7 ldr x7, \[sp,#85\]!
284: f84fffe7 ldr x7, \[sp,#255\]!
288: 38900fe7 ldrsb x7, \[sp,#-256\]!
28c: 38955fe7 ldrsb x7, \[sp,#-171\]!
290: 38800fe7 ldrsb x7, \[sp,#0\]!
294: 38802fe7 ldrsb x7, \[sp,#2\]!
298: 38804fe7 ldrsb x7, \[sp,#4\]!
29c: 38808fe7 ldrsb x7, \[sp,#8\]!
2a0: 38810fe7 ldrsb x7, \[sp,#16\]!
2a4: 38855fe7 ldrsb x7, \[sp,#85\]!
2a8: 388fffe7 ldrsb x7, \[sp,#255\]!
2ac: 78900fe7 ldrsh x7, \[sp,#-256\]!
2b0: 78955fe7 ldrsh x7, \[sp,#-171\]!
2b4: 78800fe7 ldrsh x7, \[sp,#0\]!
2b8: 78802fe7 ldrsh x7, \[sp,#2\]!
2bc: 78804fe7 ldrsh x7, \[sp,#4\]!
2c0: 78808fe7 ldrsh x7, \[sp,#8\]!
2c4: 78810fe7 ldrsh x7, \[sp,#16\]!
2c8: 78855fe7 ldrsh x7, \[sp,#85\]!
2cc: 788fffe7 ldrsh x7, \[sp,#255\]!
2d0: b8900fe7 ldrsw x7, \[sp,#-256\]!
2d4: b8955fe7 ldrsw x7, \[sp,#-171\]!
2d8: b8800fe7 ldrsw x7, \[sp,#0\]!
2dc: b8802fe7 ldrsw x7, \[sp,#2\]!
2e0: b8804fe7 ldrsw x7, \[sp,#4\]!
2e4: b8808fe7 ldrsw x7, \[sp,#8\]!
2e8: b8810fe7 ldrsw x7, \[sp,#16\]!
2ec: b8855fe7 ldrsw x7, \[sp,#85\]!
2f0: b88fffe7 ldrsw x7, \[sp,#255\]!
2f4: 38d00fe7 ldrsb w7, \[sp,#-256\]!
2f8: 38d55fe7 ldrsb w7, \[sp,#-171\]!
2fc: 38c00fe7 ldrsb w7, \[sp,#0\]!
300: 38c02fe7 ldrsb w7, \[sp,#2\]!
304: 38c04fe7 ldrsb w7, \[sp,#4\]!
308: 38c08fe7 ldrsb w7, \[sp,#8\]!
30c: 38c10fe7 ldrsb w7, \[sp,#16\]!
310: 38c55fe7 ldrsb w7, \[sp,#85\]!
314: 38cfffe7 ldrsb w7, \[sp,#255\]!
318: 78d00fe7 ldrsh w7, \[sp,#-256\]!
31c: 78d55fe7 ldrsh w7, \[sp,#-171\]!
320: 78c00fe7 ldrsh w7, \[sp,#0\]!
324: 78c02fe7 ldrsh w7, \[sp,#2\]!
328: 78c04fe7 ldrsh w7, \[sp,#4\]!
32c: 78c08fe7 ldrsh w7, \[sp,#8\]!
330: 78c10fe7 ldrsh w7, \[sp,#16\]!
334: 78c55fe7 ldrsh w7, \[sp,#85\]!
338: 78cfffe7 ldrsh w7, \[sp,#255\]!

62
gas/testsuite/gas/aarch64/ldst-reg-imm-pre-ind.s Normal file
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/* ldst-reg-imm-pre-ind.s Test file for AArch64
load-store reg. (imm.pre-ind.) instructions.
Copyright 2011, 2012 Free Software Foundation, Inc.
Contributed by ARM Ltd.
This file is part of GAS.
GAS is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the license, or
(at your option) any later version.
GAS is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; see the file COPYING3. If not,
see <http://www.gnu.org/licenses/>. */
.macro op2 op, reg, simm
\op \reg\()7, [sp, #\simm]!
.endm
// load to or store from core register
.macro ld_or_st op, suffix, reg
.irp simm, -256, -171, 0, 2, 4, 8, 16, 85, 255
op2 \op\suffix, \reg, \simm
.endr
.endm
// load to or store from FP/SIMD register
.macro ld_or_st_v op
.irp reg, b, h, s, d, q
.irp simm, -256, -171, 0, 2, 4, 8, 16, 85, 255
op2 \op, \reg, \simm
.endr
.endr
.endm
func:
// load to or store from FP/SIMD register
ld_or_st_v str
ld_or_st_v ldr
// load to or store from core register
// op, suffix, reg
ld_or_st str, b, w
ld_or_st str, h, w
ld_or_st str, , w
ld_or_st str, , x
ld_or_st ldr, b, w
ld_or_st ldr, h, w
ld_or_st ldr, , w
ld_or_st ldr, , x
ld_or_st ldr, sb, x
ld_or_st ldr, sh, x
ld_or_st ldr, sw, x
ld_or_st ldr, sb, w
ld_or_st ldr, sh, w

265
gas/testsuite/gas/aarch64/ldst-reg-pair.d Normal file
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#objdump: -dr
.*: file format .*
Disassembly of section \.text:
0000000000000000 <.*>:
0: 29203fe7 stp w7, w15, \[sp,#-256\]
4: 2930bfe7 stp w7, w15, \[sp,#-124\]
8: 293fbfe7 stp w7, w15, \[sp,#-4\]
c: 29003fe7 stp w7, w15, \[sp\]
10: 2907bfe7 stp w7, w15, \[sp,#60\]
14: 291fbfe7 stp w7, w15, \[sp,#252\]
18: 29603fe7 ldp w7, w15, \[sp,#-256\]
1c: 2970bfe7 ldp w7, w15, \[sp,#-124\]
20: 297fbfe7 ldp w7, w15, \[sp,#-4\]
24: 29403fe7 ldp w7, w15, \[sp\]
28: 2947bfe7 ldp w7, w15, \[sp,#60\]
2c: 295fbfe7 ldp w7, w15, \[sp,#252\]
30: 69603fe7 ldpsw x7, x15, \[sp,#-256\]
34: 6970bfe7 ldpsw x7, x15, \[sp,#-124\]
38: 697fbfe7 ldpsw x7, x15, \[sp,#-4\]
3c: 69403fe7 ldpsw x7, x15, \[sp\]
40: 6947bfe7 ldpsw x7, x15, \[sp,#60\]
44: 695fbfe7 ldpsw x7, x15, \[sp,#252\]
48: a9203fe7 stp x7, x15, \[sp,#-512\]
4c: a930bfe7 stp x7, x15, \[sp,#-248\]
50: a93fbfe7 stp x7, x15, \[sp,#-8\]
54: a9003fe7 stp x7, x15, \[sp\]
58: a907bfe7 stp x7, x15, \[sp,#120\]
5c: a91fbfe7 stp x7, x15, \[sp,#504\]
60: a9603fe7 ldp x7, x15, \[sp,#-512\]
64: a970bfe7 ldp x7, x15, \[sp,#-248\]
68: a97fbfe7 ldp x7, x15, \[sp,#-8\]
6c: a9403fe7 ldp x7, x15, \[sp\]
70: a947bfe7 ldp x7, x15, \[sp,#120\]
74: a95fbfe7 ldp x7, x15, \[sp,#504\]
78: 2d203fe7 stp s7, s15, \[sp,#-256\]
7c: 2d30bfe7 stp s7, s15, \[sp,#-124\]
80: 2d3fbfe7 stp s7, s15, \[sp,#-4\]
84: 2d003fe7 stp s7, s15, \[sp\]
88: 2d07bfe7 stp s7, s15, \[sp,#60\]
8c: 2d1fbfe7 stp s7, s15, \[sp,#252\]
90: 2d603fe7 ldp s7, s15, \[sp,#-256\]
94: 2d70bfe7 ldp s7, s15, \[sp,#-124\]
98: 2d7fbfe7 ldp s7, s15, \[sp,#-4\]
9c: 2d403fe7 ldp s7, s15, \[sp\]
a0: 2d47bfe7 ldp s7, s15, \[sp,#60\]
a4: 2d5fbfe7 ldp s7, s15, \[sp,#252\]
a8: 6d203fe7 stp d7, d15, \[sp,#-512\]
ac: 6d30bfe7 stp d7, d15, \[sp,#-248\]
b0: 6d3fbfe7 stp d7, d15, \[sp,#-8\]
b4: 6d003fe7 stp d7, d15, \[sp\]
b8: 6d07bfe7 stp d7, d15, \[sp,#120\]
bc: 6d1fbfe7 stp d7, d15, \[sp,#504\]
c0: 6d603fe7 ldp d7, d15, \[sp,#-512\]
c4: 6d70bfe7 ldp d7, d15, \[sp,#-248\]
c8: 6d7fbfe7 ldp d7, d15, \[sp,#-8\]
cc: 6d403fe7 ldp d7, d15, \[sp\]
d0: 6d47bfe7 ldp d7, d15, \[sp,#120\]
d4: 6d5fbfe7 ldp d7, d15, \[sp,#504\]
d8: ad203fe7 stp q7, q15, \[sp,#-1024\]
dc: ad30bfe7 stp q7, q15, \[sp,#-496\]
e0: ad3fbfe7 stp q7, q15, \[sp,#-16\]
e4: ad003fe7 stp q7, q15, \[sp\]
e8: ad07bfe7 stp q7, q15, \[sp,#240\]
ec: ad1fbfe7 stp q7, q15, \[sp,#1008\]
f0: ad603fe7 ldp q7, q15, \[sp,#-1024\]
f4: ad70bfe7 ldp q7, q15, \[sp,#-496\]
f8: ad7fbfe7 ldp q7, q15, \[sp,#-16\]
fc: ad403fe7 ldp q7, q15, \[sp\]
100: ad47bfe7 ldp q7, q15, \[sp,#240\]
104: ad5fbfe7 ldp q7, q15, \[sp,#1008\]
108: 28a03fe7 stp w7, w15, \[sp\],#-256
10c: 28b0bfe7 stp w7, w15, \[sp\],#-124
110: 28bfbfe7 stp w7, w15, \[sp\],#-4
114: 28803fe7 stp w7, w15, \[sp\],#0
118: 2887bfe7 stp w7, w15, \[sp\],#60
11c: 289fbfe7 stp w7, w15, \[sp\],#252
120: 28e03fe7 ldp w7, w15, \[sp\],#-256
124: 28f0bfe7 ldp w7, w15, \[sp\],#-124
128: 28ffbfe7 ldp w7, w15, \[sp\],#-4
12c: 28c03fe7 ldp w7, w15, \[sp\],#0
130: 28c7bfe7 ldp w7, w15, \[sp\],#60
134: 28dfbfe7 ldp w7, w15, \[sp\],#252
138: 68e03fe7 ldpsw x7, x15, \[sp\],#-256
13c: 68f0bfe7 ldpsw x7, x15, \[sp\],#-124
140: 68ffbfe7 ldpsw x7, x15, \[sp\],#-4
144: 68c03fe7 ldpsw x7, x15, \[sp\],#0
148: 68c7bfe7 ldpsw x7, x15, \[sp\],#60
14c: 68dfbfe7 ldpsw x7, x15, \[sp\],#252
150: a8a03fe7 stp x7, x15, \[sp\],#-512
154: a8b0bfe7 stp x7, x15, \[sp\],#-248
158: a8bfbfe7 stp x7, x15, \[sp\],#-8
15c: a8803fe7 stp x7, x15, \[sp\],#0
160: a887bfe7 stp x7, x15, \[sp\],#120
164: a89fbfe7 stp x7, x15, \[sp\],#504
168: a8e03fe7 ldp x7, x15, \[sp\],#-512
16c: a8f0bfe7 ldp x7, x15, \[sp\],#-248
170: a8ffbfe7 ldp x7, x15, \[sp\],#-8
174: a8c03fe7 ldp x7, x15, \[sp\],#0
178: a8c7bfe7 ldp x7, x15, \[sp\],#120
17c: a8dfbfe7 ldp x7, x15, \[sp\],#504
180: 2ca03fe7 stp s7, s15, \[sp\],#-256
184: 2cb0bfe7 stp s7, s15, \[sp\],#-124
188: 2cbfbfe7 stp s7, s15, \[sp\],#-4
18c: 2c803fe7 stp s7, s15, \[sp\],#0
190: 2c87bfe7 stp s7, s15, \[sp\],#60
194: 2c9fbfe7 stp s7, s15, \[sp\],#252
198: 2ce03fe7 ldp s7, s15, \[sp\],#-256
19c: 2cf0bfe7 ldp s7, s15, \[sp\],#-124
1a0: 2cffbfe7 ldp s7, s15, \[sp\],#-4
1a4: 2cc03fe7 ldp s7, s15, \[sp\],#0
1a8: 2cc7bfe7 ldp s7, s15, \[sp\],#60
1ac: 2cdfbfe7 ldp s7, s15, \[sp\],#252
1b0: 6ca03fe7 stp d7, d15, \[sp\],#-512
1b4: 6cb0bfe7 stp d7, d15, \[sp\],#-248
1b8: 6cbfbfe7 stp d7, d15, \[sp\],#-8
1bc: 6c803fe7 stp d7, d15, \[sp\],#0
1c0: 6c87bfe7 stp d7, d15, \[sp\],#120
1c4: 6c9fbfe7 stp d7, d15, \[sp\],#504
1c8: 6ce03fe7 ldp d7, d15, \[sp\],#-512
1cc: 6cf0bfe7 ldp d7, d15, \[sp\],#-248
1d0: 6cffbfe7 ldp d7, d15, \[sp\],#-8
1d4: 6cc03fe7 ldp d7, d15, \[sp\],#0
1d8: 6cc7bfe7 ldp d7, d15, \[sp\],#120
1dc: 6cdfbfe7 ldp d7, d15, \[sp\],#504
1e0: aca03fe7 stp q7, q15, \[sp\],#-1024
1e4: acb0bfe7 stp q7, q15, \[sp\],#-496
1e8: acbfbfe7 stp q7, q15, \[sp\],#-16
1ec: ac803fe7 stp q7, q15, \[sp\],#0
1f0: ac87bfe7 stp q7, q15, \[sp\],#240
1f4: ac9fbfe7 stp q7, q15, \[sp\],#1008
1f8: ace03fe7 ldp q7, q15, \[sp\],#-1024
1fc: acf0bfe7 ldp q7, q15, \[sp\],#-496
200: acffbfe7 ldp q7, q15, \[sp\],#-16
204: acc03fe7 ldp q7, q15, \[sp\],#0
208: acc7bfe7 ldp q7, q15, \[sp\],#240
20c: acdfbfe7 ldp q7, q15, \[sp\],#1008
210: 29a03fe7 stp w7, w15, \[sp,#-256\]!
214: 29b0bfe7 stp w7, w15, \[sp,#-124\]!
218: 29bfbfe7 stp w7, w15, \[sp,#-4\]!
21c: 29803fe7 stp w7, w15, \[sp,#0\]!
220: 2987bfe7 stp w7, w15, \[sp,#60\]!
224: 299fbfe7 stp w7, w15, \[sp,#252\]!
228: 29e03fe7 ldp w7, w15, \[sp,#-256\]!
22c: 29f0bfe7 ldp w7, w15, \[sp,#-124\]!
230: 29ffbfe7 ldp w7, w15, \[sp,#-4\]!
234: 29c03fe7 ldp w7, w15, \[sp,#0\]!
238: 29c7bfe7 ldp w7, w15, \[sp,#60\]!
23c: 29dfbfe7 ldp w7, w15, \[sp,#252\]!
240: 69e03fe7 ldpsw x7, x15, \[sp,#-256\]!
244: 69f0bfe7 ldpsw x7, x15, \[sp,#-124\]!
248: 69ffbfe7 ldpsw x7, x15, \[sp,#-4\]!
24c: 69c03fe7 ldpsw x7, x15, \[sp,#0\]!
250: 69c7bfe7 ldpsw x7, x15, \[sp,#60\]!
254: 69dfbfe7 ldpsw x7, x15, \[sp,#252\]!
258: a9a03fe7 stp x7, x15, \[sp,#-512\]!
25c: a9b0bfe7 stp x7, x15, \[sp,#-248\]!
260: a9bfbfe7 stp x7, x15, \[sp,#-8\]!
264: a9803fe7 stp x7, x15, \[sp,#0\]!
268: a987bfe7 stp x7, x15, \[sp,#120\]!
26c: a99fbfe7 stp x7, x15, \[sp,#504\]!
270: a9e03fe7 ldp x7, x15, \[sp,#-512\]!
274: a9f0bfe7 ldp x7, x15, \[sp,#-248\]!
278: a9ffbfe7 ldp x7, x15, \[sp,#-8\]!
27c: a9c03fe7 ldp x7, x15, \[sp,#0\]!
280: a9c7bfe7 ldp x7, x15, \[sp,#120\]!
284: a9dfbfe7 ldp x7, x15, \[sp,#504\]!
288: 2da03fe7 stp s7, s15, \[sp,#-256\]!
28c: 2db0bfe7 stp s7, s15, \[sp,#-124\]!
290: 2dbfbfe7 stp s7, s15, \[sp,#-4\]!
294: 2d803fe7 stp s7, s15, \[sp,#0\]!
298: 2d87bfe7 stp s7, s15, \[sp,#60\]!
29c: 2d9fbfe7 stp s7, s15, \[sp,#252\]!
2a0: 2de03fe7 ldp s7, s15, \[sp,#-256\]!
2a4: 2df0bfe7 ldp s7, s15, \[sp,#-124\]!
2a8: 2dffbfe7 ldp s7, s15, \[sp,#-4\]!
2ac: 2dc03fe7 ldp s7, s15, \[sp,#0\]!
2b0: 2dc7bfe7 ldp s7, s15, \[sp,#60\]!
2b4: 2ddfbfe7 ldp s7, s15, \[sp,#252\]!
2b8: 6da03fe7 stp d7, d15, \[sp,#-512\]!
2bc: 6db0bfe7 stp d7, d15, \[sp,#-248\]!
2c0: 6dbfbfe7 stp d7, d15, \[sp,#-8\]!
2c4: 6d803fe7 stp d7, d15, \[sp,#0\]!
2c8: 6d87bfe7 stp d7, d15, \[sp,#120\]!
2cc: 6d9fbfe7 stp d7, d15, \[sp,#504\]!
2d0: 6de03fe7 ldp d7, d15, \[sp,#-512\]!
2d4: 6df0bfe7 ldp d7, d15, \[sp,#-248\]!
2d8: 6dffbfe7 ldp d7, d15, \[sp,#-8\]!
2dc: 6dc03fe7 ldp d7, d15, \[sp,#0\]!
2e0: 6dc7bfe7 ldp d7, d15, \[sp,#120\]!
2e4: 6ddfbfe7 ldp d7, d15, \[sp,#504\]!
2e8: ada03fe7 stp q7, q15, \[sp,#-1024\]!
2ec: adb0bfe7 stp q7, q15, \[sp,#-496\]!
2f0: adbfbfe7 stp q7, q15, \[sp,#-16\]!
2f4: ad803fe7 stp q7, q15, \[sp,#0\]!
2f8: ad87bfe7 stp q7, q15, \[sp,#240\]!
2fc: ad9fbfe7 stp q7, q15, \[sp,#1008\]!
300: ade03fe7 ldp q7, q15, \[sp,#-1024\]!
304: adf0bfe7 ldp q7, q15, \[sp,#-496\]!
308: adffbfe7 ldp q7, q15, \[sp,#-16\]!
30c: adc03fe7 ldp q7, q15, \[sp,#0\]!
310: adc7bfe7 ldp q7, q15, \[sp,#240\]!
314: addfbfe7 ldp q7, q15, \[sp,#1008\]!
318: 28203fe7 stnp w7, w15, \[sp,#-256\]
31c: 2830bfe7 stnp w7, w15, \[sp,#-124\]
320: 283fbfe7 stnp w7, w15, \[sp,#-4\]
324: 28003fe7 stnp w7, w15, \[sp\]
328: 2807bfe7 stnp w7, w15, \[sp,#60\]
32c: 281fbfe7 stnp w7, w15, \[sp,#252\]
330: 28603fe7 ldnp w7, w15, \[sp,#-256\]
334: 2870bfe7 ldnp w7, w15, \[sp,#-124\]
338: 287fbfe7 ldnp w7, w15, \[sp,#-4\]
33c: 28403fe7 ldnp w7, w15, \[sp\]
340: 2847bfe7 ldnp w7, w15, \[sp,#60\]
344: 285fbfe7 ldnp w7, w15, \[sp,#252\]
348: a8203fe7 stnp x7, x15, \[sp,#-512\]
34c: a830bfe7 stnp x7, x15, \[sp,#-248\]
350: a83fbfe7 stnp x7, x15, \[sp,#-8\]
354: a8003fe7 stnp x7, x15, \[sp\]
358: a807bfe7 stnp x7, x15, \[sp,#120\]
35c: a81fbfe7 stnp x7, x15, \[sp,#504\]
360: a8603fe7 ldnp x7, x15, \[sp,#-512\]
364: a870bfe7 ldnp x7, x15, \[sp,#-248\]
368: a87fbfe7 ldnp x7, x15, \[sp,#-8\]
36c: a8403fe7 ldnp x7, x15, \[sp\]
370: a847bfe7 ldnp x7, x15, \[sp,#120\]
374: a85fbfe7 ldnp x7, x15, \[sp,#504\]
378: 2c203fe7 stnp s7, s15, \[sp,#-256\]
37c: 2c30bfe7 stnp s7, s15, \[sp,#-124\]
380: 2c3fbfe7 stnp s7, s15, \[sp,#-4\]
384: 2c003fe7 stnp s7, s15, \[sp\]
388: 2c07bfe7 stnp s7, s15, \[sp,#60\]
38c: 2c1fbfe7 stnp s7, s15, \[sp,#252\]
390: 2c603fe7 ldnp s7, s15, \[sp,#-256\]
394: 2c70bfe7 ldnp s7, s15, \[sp,#-124\]
398: 2c7fbfe7 ldnp s7, s15, \[sp,#-4\]
39c: 2c403fe7 ldnp s7, s15, \[sp\]
3a0: 2c47bfe7 ldnp s7, s15, \[sp,#60\]
3a4: 2c5fbfe7 ldnp s7, s15, \[sp,#252\]
3a8: 6c203fe7 stnp d7, d15, \[sp,#-512\]
3ac: 6c30bfe7 stnp d7, d15, \[sp,#-248\]
3b0: 6c3fbfe7 stnp d7, d15, \[sp,#-8\]
3b4: 6c003fe7 stnp d7, d15, \[sp\]
3b8: 6c07bfe7 stnp d7, d15, \[sp,#120\]
3bc: 6c1fbfe7 stnp d7, d15, \[sp,#504\]
3c0: 6c603fe7 ldnp d7, d15, \[sp,#-512\]
3c4: 6c70bfe7 ldnp d7, d15, \[sp,#-248\]
3c8: 6c7fbfe7 ldnp d7, d15, \[sp,#-8\]
3cc: 6c403fe7 ldnp d7, d15, \[sp\]
3d0: 6c47bfe7 ldnp d7, d15, \[sp,#120\]
3d4: 6c5fbfe7 ldnp d7, d15, \[sp,#504\]
3d8: ac203fe7 stnp q7, q15, \[sp,#-1024\]
3dc: ac30bfe7 stnp q7, q15, \[sp,#-496\]
3e0: ac3fbfe7 stnp q7, q15, \[sp,#-16\]
3e4: ac003fe7 stnp q7, q15, \[sp\]
3e8: ac07bfe7 stnp q7, q15, \[sp,#240\]
3ec: ac1fbfe7 stnp q7, q15, \[sp,#1008\]
3f0: ac603fe7 ldnp q7, q15, \[sp,#-1024\]
3f4: ac70bfe7 ldnp q7, q15, \[sp,#-496\]
3f8: ac7fbfe7 ldnp q7, q15, \[sp,#-16\]
3fc: ac403fe7 ldnp q7, q15, \[sp\]
400: ac47bfe7 ldnp q7, q15, \[sp,#240\]
404: ac5fbfe7 ldnp q7, q15, \[sp,#1008\]

111
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/* ldst-reg-pair.s Test file for AArch64 load-store reg.pair instructions.
Copyright 2011, 2012 Free Software Foundation, Inc.
Contributed by ARM Ltd.
This file is part of GAS.
GAS is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the license, or
(at your option) any later version.
GAS is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; see the file COPYING3. If not,
see <http://www.gnu.org/licenses/>. */
/* Includes:
* Load-store reg.pair (offset)
* Load-store reg.pair (post-ind.)
* Load-store reg.pair (pre-ind.)
* Load-store na.pair (pre-ind.)
*/
// offset format
.macro op3_offset op, reg, imm
\op \reg\()7, \reg\()15, [sp, #\imm]
.endm
// post-ind. format
.macro op3_post_ind op, reg, imm
\op \reg\()7, \reg\()15, [sp], #\imm
.endm
// pre-ind. format
.macro op3_pre_ind op, reg, imm
\op \reg\()7, \reg\()15, [sp, #\imm]!
.endm
.macro op3 op, reg, size, type
// a variety of values for the imm7 field
.irp imm7, -64, -31, -1, 0, 15, 63
// offset format
.ifc \type, 1
op3_offset \op, \reg, "(\imm7*\size)"
.endif
// post-ind. format
.ifc \type, 2
op3_post_ind \op, \reg, "(\imm7*\size)"
.endif
// pre-ind. format
.ifc \type, 3
op3_pre_ind \op, \reg, "(\imm7*\size)"
.endif
.endr
.endm
.macro ldst_reg_pair type
// op, reg, size(in byte) of one of the pair, type
op3 stp, w, 4, \type
op3 ldp, w, 4, \type
op3 ldpsw, x, 4, \type
op3 stp, x, 8, \type
op3 ldp, x, 8, \type
op3 stp, s, 4, \type
op3 ldp, s, 4, \type
op3 stp, d, 8, \type
op3 ldp, d, 8, \type
op3 stp, q, 16, \type
op3 ldp, q, 16, \type
.endm
.macro ldst_reg_na_pair type
// op, reg, size(in byte) of one of the pair, type
op3 stnp, w, 4, \type
op3 ldnp, w, 4, \type
op3 stnp, x, 8, \type
op3 ldnp, x, 8, \type
op3 stnp, s, 4, \type
op3 ldnp, s, 4, \type
op3 stnp, d, 8, \type
op3 ldnp, d, 8, \type
op3 stnp, q, 16, \type
op3 ldnp, q, 16, \type
.endm
func:
// Load-store reg.pair (offset)
ldst_reg_pair 1
// Load-store reg.pair (post-ind.)
ldst_reg_pair 2
// Load-store reg.pair (pre-ind.)
ldst_reg_pair 3
// Load-store na.pair (offset)
ldst_reg_na_pair 1

87
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#objdump: -dr
.*: file format .*
Disassembly of section \.text:
0000000000000000 <.*>:
0: 3c274be7 str b7, \[sp,w7,uxtw\]
4: 3c275be7 str b7, \[sp,w7,uxtw #0\]
8: 7c274be7 str h7, \[sp,w7,uxtw\]
c: 7c275be7 str h7, \[sp,w7,uxtw #1\]
10: bc274be7 str s7, \[sp,w7,uxtw\]
14: bc275be7 str s7, \[sp,w7,uxtw #2\]
18: fc274be7 str d7, \[sp,w7,uxtw\]
1c: fc275be7 str d7, \[sp,w7,uxtw #3\]
20: 3ca74be7 str q7, \[sp,w7,uxtw\]
24: 3ca75be7 str q7, \[sp,w7,uxtw #4\]
28: 3c276be7 str b7, \[sp,x7\]
2c: 3c277be7 str b7, \[sp,x7,lsl #0\]
30: 7c276be7 str h7, \[sp,x7\]
34: 7c277be7 str h7, \[sp,x7,lsl #1\]
38: bc276be7 str s7, \[sp,x7\]
3c: bc277be7 str s7, \[sp,x7,lsl #2\]
40: fc276be7 str d7, \[sp,x7\]
44: fc277be7 str d7, \[sp,x7,lsl #3\]
48: 3ca76be7 str q7, \[sp,x7\]
4c: 3ca77be7 str q7, \[sp,x7,lsl #4\]
50: 3c27cbe7 str b7, \[sp,w7,sxtw\]
54: 3c27dbe7 str b7, \[sp,w7,sxtw #0\]
58: 7c27cbe7 str h7, \[sp,w7,sxtw\]
5c: 7c27dbe7 str h7, \[sp,w7,sxtw #1\]
60: bc27cbe7 str s7, \[sp,w7,sxtw\]
64: bc27dbe7 str s7, \[sp,w7,sxtw #2\]
68: fc27cbe7 str d7, \[sp,w7,sxtw\]
6c: fc27dbe7 str d7, \[sp,w7,sxtw #3\]
70: 3ca7cbe7 str q7, \[sp,w7,sxtw\]
74: 3ca7dbe7 str q7, \[sp,w7,sxtw #4\]
78: 3c27ebe7 str b7, \[sp,x7,sxtx\]
7c: 3c27fbe7 str b7, \[sp,x7,sxtx #0\]
80: 7c27ebe7 str h7, \[sp,x7,sxtx\]
84: 7c27fbe7 str h7, \[sp,x7,sxtx #1\]
88: bc27ebe7 str s7, \[sp,x7,sxtx\]
8c: bc27fbe7 str s7, \[sp,x7,sxtx #2\]
90: fc27ebe7 str d7, \[sp,x7,sxtx\]
94: fc27fbe7 str d7, \[sp,x7,sxtx #3\]
98: 3ca7ebe7 str q7, \[sp,x7,sxtx\]
9c: 3ca7fbe7 str q7, \[sp,x7,sxtx #4\]
a0: 3c674be7 ldr b7, \[sp,w7,uxtw\]
a4: 3c675be7 ldr b7, \[sp,w7,uxtw #0\]
a8: 7c674be7 ldr h7, \[sp,w7,uxtw\]
ac: 7c675be7 ldr h7, \[sp,w7,uxtw #1\]
b0: bc674be7 ldr s7, \[sp,w7,uxtw\]
b4: bc675be7 ldr s7, \[sp,w7,uxtw #2\]
b8: fc674be7 ldr d7, \[sp,w7,uxtw\]
bc: fc675be7 ldr d7, \[sp,w7,uxtw #3\]
c0: 3ce74be7 ldr q7, \[sp,w7,uxtw\]
c4: 3ce75be7 ldr q7, \[sp,w7,uxtw #4\]
c8: 3c676be7 ldr b7, \[sp,x7\]
cc: 3c677be7 ldr b7, \[sp,x7,lsl #0\]
d0: 7c676be7 ldr h7, \[sp,x7\]
d4: 7c677be7 ldr h7, \[sp,x7,lsl #1\]
d8: bc676be7 ldr s7, \[sp,x7\]
dc: bc677be7 ldr s7, \[sp,x7,lsl #2\]
e0: fc676be7 ldr d7, \[sp,x7\]
e4: fc677be7 ldr d7, \[sp,x7,lsl #3\]
e8: 3ce76be7 ldr q7, \[sp,x7\]
ec: 3ce77be7 ldr q7, \[sp,x7,lsl #4\]
f0: 3c67cbe7 ldr b7, \[sp,w7,sxtw\]
f4: 3c67dbe7 ldr b7, \[sp,w7,sxtw #0\]
f8: 7c67cbe7 ldr h7, \[sp,w7,sxtw\]
fc: 7c67dbe7 ldr h7, \[sp,w7,sxtw #1\]
100: bc67cbe7 ldr s7, \[sp,w7,sxtw\]
104: bc67dbe7 ldr s7, \[sp,w7,sxtw #2\]
108: fc67cbe7 ldr d7, \[sp,w7,sxtw\]
10c: fc67dbe7 ldr d7, \[sp,w7,sxtw #3\]
110: 3ce7cbe7 ldr q7, \[sp,w7,sxtw\]
114: 3ce7dbe7 ldr q7, \[sp,w7,sxtw #4\]
118: 3c67ebe7 ldr b7, \[sp,x7,sxtx\]
11c: 3c67fbe7 ldr b7, \[sp,x7,sxtx #0\]
120: 7c67ebe7 ldr h7, \[sp,x7,sxtx\]
124: 7c67fbe7 ldr h7, \[sp,x7,sxtx #1\]
128: bc67ebe7 ldr s7, \[sp,x7,sxtx\]
12c: bc67fbe7 ldr s7, \[sp,x7,sxtx #2\]
130: fc67ebe7 ldr d7, \[sp,x7,sxtx\]
134: fc67fbe7 ldr d7, \[sp,x7,sxtx #3\]
138: 3ce7ebe7 ldr q7, \[sp,x7,sxtx\]
13c: 3ce7fbe7 ldr q7, \[sp,x7,sxtx #4\]

88
gas/testsuite/gas/aarch64/ldst-reg-reg-offset.s Normal file
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/* ldst-reg-reg-offset.s Test file for AArch64 load-store reg. (reg.offset)
instructions.
Copyright 2011, 2012 Free Software Foundation, Inc.
Contributed by ARM Ltd.
This file is part of GAS.
GAS is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the license, or
(at your option) any later version.
GAS is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; see the file COPYING3. If not,
see <http://www.gnu.org/licenses/>. */
/* Only instructions loading from/storing to FP/SIMD register are
tested here. */
.macro op3_32 op, reg, ext, imm
.ifc \imm, -1
\op \reg\()7, [sp, w7, \ext]
.else
\op \reg\()7, [sp, w7, \ext #\imm]
.endif
.endm
.macro op3_64 op, reg, ext, imm
.ifc \imm, -1
\op \reg\()7, [sp, x7, \ext]
.else
\op \reg\()7, [sp, x7, \ext #\imm]
.endif
.endm
.macro op3 op, reg, ext, imm=-1
.ifc \ext, uxtw
op3_32 \op, \reg, \ext, \imm
.endif
.ifc \ext, sxtw
op3_32 \op, \reg, \ext, \imm
.endif
.ifc \ext, lsl
.ifnc \imm, -1
// shift <amount> is mandatory when 'lsl' is used
op3_64 \op, \reg, \ext, \imm
.else
// absent shift; lsl by default
\op \reg\()7, [sp, x7]
.endif
.endif
.ifc \ext, sxtx
op3_64 \op, \reg, \ext, \imm
.endif
.endm
.macro shift op, ext
op3 \op, b, \ext
op3 \op, b, \ext, 0
op3 \op, h, \ext, 0
op3 \op, h, \ext, 1
op3 \op, s, \ext, 0
op3 \op, s, \ext, 2
op3 \op, d, \ext, 0
op3 \op, d, \ext, 3
op3 \op, q, \ext, 0
op3 \op, q, \ext, 4
.endm
.macro extend op
.irp ext, uxtw, lsl, sxtw, sxtx
shift \op, \ext
.endr
.endm
.macro ld_or_st op
extend \op
.endm
func:
ld_or_st str
ld_or_st ldr

260
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#objdump: -dr
.*: file format .*
Disassembly of section \.text:
0000000000000000 <.*>:
0: 3c1003e7 str b7, \[sp,#-256\]
4: 3c1553e7 str b7, \[sp,#-171\]
8: 3d0003e7 str b7, \[sp\]
c: 3d0003e7 str b7, \[sp\]
10: 3d000be7 str b7, \[sp,#2\]
14: 3d0013e7 str b7, \[sp,#4\]
18: 3d0023e7 str b7, \[sp,#8\]
1c: 3d0043e7 str b7, \[sp,#16\]
20: 3d0157e7 str b7, \[sp,#85\]
24: 3d03ffe7 str b7, \[sp,#255\]
28: 3d3fffe7 str b7, \[sp,#4095\]
2c: 7c1003e7 str h7, \[sp,#-256\]
30: 7c1553e7 str h7, \[sp,#-171\]
34: 7d0003e7 str h7, \[sp\]
38: 7d0003e7 str h7, \[sp\]
3c: 7d0007e7 str h7, \[sp,#2\]
40: 7d000be7 str h7, \[sp,#4\]
44: 7d0013e7 str h7, \[sp,#8\]
48: 7d0023e7 str h7, \[sp,#16\]
4c: 7c0553e7 str h7, \[sp,#85\]
50: 7c0ff3e7 str h7, \[sp,#255\]
54: 7d3fffe7 str h7, \[sp,#8190\]
58: bc1003e7 str s7, \[sp,#-256\]
5c: bc1553e7 str s7, \[sp,#-171\]
60: bd0003e7 str s7, \[sp\]
64: bd0003e7 str s7, \[sp\]
68: bc0023e7 str s7, \[sp,#2\]
6c: bd0007e7 str s7, \[sp,#4\]
70: bd000be7 str s7, \[sp,#8\]
74: bd0013e7 str s7, \[sp,#16\]
78: bc0553e7 str s7, \[sp,#85\]
7c: bc0ff3e7 str s7, \[sp,#255\]
80: bd3fffe7 str s7, \[sp,#16380\]
84: fc1003e7 str d7, \[sp,#-256\]
88: fc1553e7 str d7, \[sp,#-171\]
8c: fd0003e7 str d7, \[sp\]
90: fd0003e7 str d7, \[sp\]
94: fc0023e7 str d7, \[sp,#2\]
98: fc0043e7 str d7, \[sp,#4\]
9c: fd0007e7 str d7, \[sp,#8\]
a0: fd000be7 str d7, \[sp,#16\]
a4: fc0553e7 str d7, \[sp,#85\]
a8: fc0ff3e7 str d7, \[sp,#255\]
ac: fd3fffe7 str d7, \[sp,#32760\]
b0: 3c9003e7 str q7, \[sp,#-256\]
b4: 3c9553e7 str q7, \[sp,#-171\]
b8: 3d8003e7 str q7, \[sp\]
bc: 3d8003e7 str q7, \[sp\]
c0: 3c8023e7 str q7, \[sp,#2\]
c4: 3c8043e7 str q7, \[sp,#4\]
c8: 3c8083e7 str q7, \[sp,#8\]
cc: 3d8007e7 str q7, \[sp,#16\]
d0: 3c8553e7 str q7, \[sp,#85\]
d4: 3c8ff3e7 str q7, \[sp,#255\]
d8: 3dbfffe7 str q7, \[sp,#65520\]
dc: 3c5003e7 ldr b7, \[sp,#-256\]
e0: 3c5553e7 ldr b7, \[sp,#-171\]
e4: 3d4003e7 ldr b7, \[sp\]
e8: 3d4003e7 ldr b7, \[sp\]
ec: 3d400be7 ldr b7, \[sp,#2\]
f0: 3d4013e7 ldr b7, \[sp,#4\]
f4: 3d4023e7 ldr b7, \[sp,#8\]
f8: 3d4043e7 ldr b7, \[sp,#16\]
fc: 3d4157e7 ldr b7, \[sp,#85\]
100: 3d43ffe7 ldr b7, \[sp,#255\]
104: 3d7fffe7 ldr b7, \[sp,#4095\]
108: 7c5003e7 ldr h7, \[sp,#-256\]
10c: 7c5553e7 ldr h7, \[sp,#-171\]
110: 7d4003e7 ldr h7, \[sp\]
114: 7d4003e7 ldr h7, \[sp\]
118: 7d4007e7 ldr h7, \[sp,#2\]
11c: 7d400be7 ldr h7, \[sp,#4\]
120: 7d4013e7 ldr h7, \[sp,#8\]
124: 7d4023e7 ldr h7, \[sp,#16\]
128: 7c4553e7 ldr h7, \[sp,#85\]
12c: 7c4ff3e7 ldr h7, \[sp,#255\]
130: 7d7fffe7 ldr h7, \[sp,#8190\]
134: bc5003e7 ldr s7, \[sp,#-256\]
138: bc5553e7 ldr s7, \[sp,#-171\]
13c: bd4003e7 ldr s7, \[sp\]
140: bd4003e7 ldr s7, \[sp\]
144: bc4023e7 ldr s7, \[sp,#2\]
148: bd4007e7 ldr s7, \[sp,#4\]
14c: bd400be7 ldr s7, \[sp,#8\]
150: bd4013e7 ldr s7, \[sp,#16\]
154: bc4553e7 ldr s7, \[sp,#85\]
158: bc4ff3e7 ldr s7, \[sp,#255\]
15c: bd7fffe7 ldr s7, \[sp,#16380\]
160: fc5003e7 ldr d7, \[sp,#-256\]
164: fc5553e7 ldr d7, \[sp,#-171\]
168: fd4003e7 ldr d7, \[sp\]
16c: fd4003e7 ldr d7, \[sp\]
170: fc4023e7 ldr d7, \[sp,#2\]
174: fc4043e7 ldr d7, \[sp,#4\]
178: fd4007e7 ldr d7, \[sp,#8\]
17c: fd400be7 ldr d7, \[sp,#16\]
180: fc4553e7 ldr d7, \[sp,#85\]
184: fc4ff3e7 ldr d7, \[sp,#255\]
188: fd7fffe7 ldr d7, \[sp,#32760\]
18c: 3cd003e7 ldr q7, \[sp,#-256\]
190: 3cd553e7 ldr q7, \[sp,#-171\]
194: 3dc003e7 ldr q7, \[sp\]
198: 3dc003e7 ldr q7, \[sp\]
19c: 3cc023e7 ldr q7, \[sp,#2\]
1a0: 3cc043e7 ldr q7, \[sp,#4\]
1a4: 3cc083e7 ldr q7, \[sp,#8\]
1a8: 3dc007e7 ldr q7, \[sp,#16\]
1ac: 3cc553e7 ldr q7, \[sp,#85\]
1b0: 3ccff3e7 ldr q7, \[sp,#255\]
1b4: 3dffffe7 ldr q7, \[sp,#65520\]
1b8: 381003e7 strb w7, \[sp,#-256\]
1bc: 381553e7 strb w7, \[sp,#-171\]
1c0: 390003e7 strb w7, \[sp\]
1c4: 390003e7 strb w7, \[sp\]
1c8: 39000be7 strb w7, \[sp,#2\]
1cc: 390013e7 strb w7, \[sp,#4\]
1d0: 390023e7 strb w7, \[sp,#8\]
1d4: 390043e7 strb w7, \[sp,#16\]
1d8: 390157e7 strb w7, \[sp,#85\]
1dc: 3903ffe7 strb w7, \[sp,#255\]
1e0: 393fffe7 strb w7, \[sp,#4095\]
1e4: 781003e7 strh w7, \[sp,#-256\]
1e8: 781553e7 strh w7, \[sp,#-171\]
1ec: 790003e7 strh w7, \[sp\]
1f0: 790003e7 strh w7, \[sp\]
1f4: 790007e7 strh w7, \[sp,#2\]
1f8: 79000be7 strh w7, \[sp,#4\]
1fc: 790013e7 strh w7, \[sp,#8\]
200: 790023e7 strh w7, \[sp,#16\]
204: 780553e7 strh w7, \[sp,#85\]
208: 780ff3e7 strh w7, \[sp,#255\]
20c: 793fffe7 strh w7, \[sp,#8190\]
210: b81003e7 str w7, \[sp,#-256\]
214: b81553e7 str w7, \[sp,#-171\]
218: b90003e7 str w7, \[sp\]
21c: b90003e7 str w7, \[sp\]
220: b80023e7 str w7, \[sp,#2\]
224: b90007e7 str w7, \[sp,#4\]
228: b9000be7 str w7, \[sp,#8\]
22c: b90013e7 str w7, \[sp,#16\]
230: b80553e7 str w7, \[sp,#85\]
234: b80ff3e7 str w7, \[sp,#255\]
238: b93fffe7 str w7, \[sp,#16380\]
23c: f81003e7 str x7, \[sp,#-256\]
240: f81553e7 str x7, \[sp,#-171\]
244: f90003e7 str x7, \[sp\]
248: f90003e7 str x7, \[sp\]
24c: f80023e7 str x7, \[sp,#2\]
250: f80043e7 str x7, \[sp,#4\]
254: f90007e7 str x7, \[sp,#8\]
258: f9000be7 str x7, \[sp,#16\]
25c: f80553e7 str x7, \[sp,#85\]
260: f80ff3e7 str x7, \[sp,#255\]
264: f93fffe7 str x7, \[sp,#32760\]
268: 385003e7 ldrb w7, \[sp,#-256\]
26c: 385553e7 ldrb w7, \[sp,#-171\]
270: 394003e7 ldrb w7, \[sp\]
274: 394003e7 ldrb w7, \[sp\]
278: 39400be7 ldrb w7, \[sp,#2\]
27c: 394013e7 ldrb w7, \[sp,#4\]
280: 394023e7 ldrb w7, \[sp,#8\]
284: 394043e7 ldrb w7, \[sp,#16\]
288: 394157e7 ldrb w7, \[sp,#85\]
28c: 3943ffe7 ldrb w7, \[sp,#255\]
290: 397fffe7 ldrb w7, \[sp,#4095\]
294: 785003e7 ldrh w7, \[sp,#-256\]
298: 785553e7 ldrh w7, \[sp,#-171\]
29c: 794003e7 ldrh w7, \[sp\]
2a0: 794003e7 ldrh w7, \[sp\]
2a4: 794007e7 ldrh w7, \[sp,#2\]
2a8: 79400be7 ldrh w7, \[sp,#4\]
2ac: 794013e7 ldrh w7, \[sp,#8\]
2b0: 794023e7 ldrh w7, \[sp,#16\]
2b4: 784553e7 ldrh w7, \[sp,#85\]
2b8: 784ff3e7 ldrh w7, \[sp,#255\]
2bc: 797fffe7 ldrh w7, \[sp,#8190\]
2c0: b85003e7 ldr w7, \[sp,#-256\]
2c4: b85553e7 ldr w7, \[sp,#-171\]
2c8: b94003e7 ldr w7, \[sp\]
2cc: b94003e7 ldr w7, \[sp\]
2d0: b84023e7 ldr w7, \[sp,#2\]
2d4: b94007e7 ldr w7, \[sp,#4\]
2d8: b9400be7 ldr w7, \[sp,#8\]
2dc: b94013e7 ldr w7, \[sp,#16\]
2e0: b84553e7 ldr w7, \[sp,#85\]
2e4: b84ff3e7 ldr w7, \[sp,#255\]
2e8: b97fffe7 ldr w7, \[sp,#16380\]
2ec: f85003e7 ldr x7, \[sp,#-256\]
2f0: f85553e7 ldr x7, \[sp,#-171\]
2f4: f94003e7 ldr x7, \[sp\]
2f8: f94003e7 ldr x7, \[sp\]
2fc: f84023e7 ldr x7, \[sp,#2\]
300: f84043e7 ldr x7, \[sp,#4\]
304: f94007e7 ldr x7, \[sp,#8\]
308: f9400be7 ldr x7, \[sp,#16\]
30c: f84553e7 ldr x7, \[sp,#85\]
310: f84ff3e7 ldr x7, \[sp,#255\]
314: f97fffe7 ldr x7, \[sp,#32760\]
318: 389003e7 ldrsb x7, \[sp,#-256\]
31c: 389553e7 ldrsb x7, \[sp,#-171\]
320: 398003e7 ldrsb x7, \[sp\]
324: 398003e7 ldrsb x7, \[sp\]
328: 39800be7 ldrsb x7, \[sp,#2\]
32c: 398013e7 ldrsb x7, \[sp,#4\]
330: 398023e7 ldrsb x7, \[sp,#8\]
334: 398043e7 ldrsb x7, \[sp,#16\]
338: 398157e7 ldrsb x7, \[sp,#85\]
33c: 3983ffe7 ldrsb x7, \[sp,#255\]
340: 39bfffe7 ldrsb x7, \[sp,#4095\]
344: 789003e7 ldrsh x7, \[sp,#-256\]
348: 789553e7 ldrsh x7, \[sp,#-171\]
34c: 798003e7 ldrsh x7, \[sp\]
350: 798003e7 ldrsh x7, \[sp\]
354: 798007e7 ldrsh x7, \[sp,#2\]
358: 79800be7 ldrsh x7, \[sp,#4\]
35c: 798013e7 ldrsh x7, \[sp,#8\]
360: 798023e7 ldrsh x7, \[sp,#16\]
364: 788553e7 ldrsh x7, \[sp,#85\]
368: 788ff3e7 ldrsh x7, \[sp,#255\]
36c: 79bfffe7 ldrsh x7, \[sp,#8190\]
370: b89003e7 ldrsw x7, \[sp,#-256\]
374: b89553e7 ldrsw x7, \[sp,#-171\]
378: b98003e7 ldrsw x7, \[sp\]
37c: b98003e7 ldrsw x7, \[sp\]
380: b88023e7 ldrsw x7, \[sp,#2\]
384: b98007e7 ldrsw x7, \[sp,#4\]
388: b9800be7 ldrsw x7, \[sp,#8\]
38c: b98013e7 ldrsw x7, \[sp,#16\]
390: b88553e7 ldrsw x7, \[sp,#85\]
394: b88ff3e7 ldrsw x7, \[sp,#255\]
398: b9bfffe7 ldrsw x7, \[sp,#16380\]
39c: 38d003e7 ldrsb w7, \[sp,#-256\]
3a0: 38d553e7 ldrsb w7, \[sp,#-171\]
3a4: 39c003e7 ldrsb w7, \[sp\]
3a8: 39c003e7 ldrsb w7, \[sp\]
3ac: 39c00be7 ldrsb w7, \[sp,#2\]
3b0: 39c013e7 ldrsb w7, \[sp,#4\]
3b4: 39c023e7 ldrsb w7, \[sp,#8\]
3b8: 39c043e7 ldrsb w7, \[sp,#16\]
3bc: 39c157e7 ldrsb w7, \[sp,#85\]
3c0: 39c3ffe7 ldrsb w7, \[sp,#255\]
3c4: 39ffffe7 ldrsb w7, \[sp,#4095\]
3c8: 78d003e7 ldrsh w7, \[sp,#-256\]
3cc: 78d553e7 ldrsh w7, \[sp,#-171\]
3d0: 79c003e7 ldrsh w7, \[sp\]
3d4: 79c003e7 ldrsh w7, \[sp\]
3d8: 79c007e7 ldrsh w7, \[sp,#2\]
3dc: 79c00be7 ldrsh w7, \[sp,#4\]
3e0: 79c013e7 ldrsh w7, \[sp,#8\]
3e4: 79c023e7 ldrsh w7, \[sp,#16\]
3e8: 78c553e7 ldrsh w7, \[sp,#85\]
3ec: 78cff3e7 ldrsh w7, \[sp,#255\]
3f0: 79ffffe7 ldrsh w7, \[sp,#8190\]

102
gas/testsuite/gas/aarch64/ldst-reg-uns-imm.s Normal file
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@ -0,0 +1,102 @@
/* ld-reg-uns-imm.s Test file for AArch64 load-store reg. (uns.imm)
instructions.
Copyright 2011, 2012 Free Software Foundation, Inc.
Contributed by ARM Ltd.
This file is part of GAS.
GAS is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the license, or
(at your option) any later version.
GAS is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; see the file COPYING3. If not,
see <http://www.gnu.org/licenses/>. */
/* Prefetch memory instruction is not tested here.
Also note that as a programmer-friendly assembler, GAS generates
LDUR/STUR instructions in response to the standard LDR/STR mnemonics
when the immediate offset is unambiguous, i.e. when it is negative
or unaligned. Similarly a disassembler could display these
instructions using the standard LDR/STR mnemonics when the encoded
immediate is negative or unaligned. However this behaviour is not
required by the architectural assembly language. */
.macro op2_no_imm op, reg
\op \reg\()7, [sp]
.endm
.macro op2 op, reg, simm
\op \reg\()7, [sp, #\simm]
.endm
// load to or store from core register
// size is the access size in byte
.macro ld_or_st op, suffix, reg, size
.irp simm, -256, -171
op2 \op\suffix, \reg, \simm
.endr
op2_no_imm \op\suffix, \reg
.irp simm, 0, 2, 4, 8, 16, 85, 255
op2 \op\suffix, \reg, \simm
.endr
op2 \op\suffix, \reg, "(4095*\size)"
.endm
// load to or store from FP/SIMD register
.macro ld_or_st_v op
.irp reg, b, h, s, d, q
.irp simm, -256, -171
op2 \op, \reg, \simm
.endr
op2_no_imm \op, \reg
.irp simm, 0, 2, 4, 8, 16, 85, 255
op2 \op, \reg, \simm
.endr
.ifc \reg, b
op2 \op, \reg, 4095
.endif
.ifc \reg, h
op2 \op, \reg, 8190
.endif
.ifc \reg, s
op2 \op, \reg, 16380
.endif
.ifc \reg, d
op2 \op, \reg, 32760
.endif
.ifc \reg, q
op2 \op, \reg, 65520
.endif
.endr
.endm
func:
// load to or store from FP/SIMD register
ld_or_st_v str
ld_or_st_v ldr
// load to or store from core register
// op, suffix, reg, size(in byte)
ld_or_st str, b, w, 1
ld_or_st str, h, w, 2
ld_or_st str, , w, 4
ld_or_st str, , x, 8
ld_or_st ldr, b, w, 1
ld_or_st ldr, h, w, 2
ld_or_st ldr, , w, 4
ld_or_st ldr, , x, 8
ld_or_st ldr, sb, x, 1
ld_or_st ldr, sh, x, 2
ld_or_st ldr, sw, x, 4
ld_or_st ldr, sb, w, 1
ld_or_st ldr, sh, w, 2

237
gas/testsuite/gas/aarch64/ldst-reg-unscaled-imm.d Normal file
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#objdump: -dr
.*: file format .*
Disassembly of section \.text:
0000000000000000 <.*>:
0: 3c1003e7 str b7, \[sp,#-256\]
4: 3c1553e7 str b7, \[sp,#-171\]
8: 3c0003e7 stur b7, \[sp\]
c: 3c0003e7 stur b7, \[sp\]
10: 3c0023e7 stur b7, \[sp,#2\]
14: 3c0043e7 stur b7, \[sp,#4\]
18: 3c0083e7 stur b7, \[sp,#8\]
1c: 3c0103e7 stur b7, \[sp,#16\]
20: 3c0553e7 stur b7, \[sp,#85\]
24: 3c0ff3e7 stur b7, \[sp,#255\]
28: 7c1003e7 str h7, \[sp,#-256\]
2c: 7c1553e7 str h7, \[sp,#-171\]
30: 7c0003e7 stur h7, \[sp\]
34: 7c0003e7 stur h7, \[sp\]
38: 7c0023e7 stur h7, \[sp,#2\]
3c: 7c0043e7 stur h7, \[sp,#4\]
40: 7c0083e7 stur h7, \[sp,#8\]
44: 7c0103e7 stur h7, \[sp,#16\]
48: 7c0553e7 str h7, \[sp,#85\]
4c: 7c0ff3e7 str h7, \[sp,#255\]
50: bc1003e7 str s7, \[sp,#-256\]
54: bc1553e7 str s7, \[sp,#-171\]
58: bc0003e7 stur s7, \[sp\]
5c: bc0003e7 stur s7, \[sp\]
60: bc0023e7 str s7, \[sp,#2\]
64: bc0043e7 stur s7, \[sp,#4\]
68: bc0083e7 stur s7, \[sp,#8\]
6c: bc0103e7 stur s7, \[sp,#16\]
70: bc0553e7 str s7, \[sp,#85\]
74: bc0ff3e7 str s7, \[sp,#255\]
78: fc1003e7 str d7, \[sp,#-256\]
7c: fc1553e7 str d7, \[sp,#-171\]
80: fc0003e7 stur d7, \[sp\]
84: fc0003e7 stur d7, \[sp\]
88: fc0023e7 str d7, \[sp,#2\]
8c: fc0043e7 str d7, \[sp,#4\]
90: fc0083e7 stur d7, \[sp,#8\]
94: fc0103e7 stur d7, \[sp,#16\]
98: fc0553e7 str d7, \[sp,#85\]
9c: fc0ff3e7 str d7, \[sp,#255\]
a0: 3c9003e7 str q7, \[sp,#-256\]
a4: 3c9553e7 str q7, \[sp,#-171\]
a8: 3c8003e7 stur q7, \[sp\]
ac: 3c8003e7 stur q7, \[sp\]
b0: 3c8023e7 str q7, \[sp,#2\]
b4: 3c8043e7 str q7, \[sp,#4\]
b8: 3c8083e7 str q7, \[sp,#8\]
bc: 3c8103e7 stur q7, \[sp,#16\]
c0: 3c8553e7 str q7, \[sp,#85\]
c4: 3c8ff3e7 str q7, \[sp,#255\]
c8: 3c5003e7 ldr b7, \[sp,#-256\]
cc: 3c5553e7 ldr b7, \[sp,#-171\]
d0: 3c4003e7 ldur b7, \[sp\]
d4: 3c4003e7 ldur b7, \[sp\]
d8: 3c4023e7 ldur b7, \[sp,#2\]
dc: 3c4043e7 ldur b7, \[sp,#4\]
e0: 3c4083e7 ldur b7, \[sp,#8\]
e4: 3c4103e7 ldur b7, \[sp,#16\]
e8: 3c4553e7 ldur b7, \[sp,#85\]
ec: 3c4ff3e7 ldur b7, \[sp,#255\]
f0: 7c5003e7 ldr h7, \[sp,#-256\]
f4: 7c5553e7 ldr h7, \[sp,#-171\]
f8: 7c4003e7 ldur h7, \[sp\]
fc: 7c4003e7 ldur h7, \[sp\]
100: 7c4023e7 ldur h7, \[sp,#2\]
104: 7c4043e7 ldur h7, \[sp,#4\]
108: 7c4083e7 ldur h7, \[sp,#8\]
10c: 7c4103e7 ldur h7, \[sp,#16\]
110: 7c4553e7 ldr h7, \[sp,#85\]
114: 7c4ff3e7 ldr h7, \[sp,#255\]
118: bc5003e7 ldr s7, \[sp,#-256\]
11c: bc5553e7 ldr s7, \[sp,#-171\]
120: bc4003e7 ldur s7, \[sp\]
124: bc4003e7 ldur s7, \[sp\]
128: bc4023e7 ldr s7, \[sp,#2\]
12c: bc4043e7 ldur s7, \[sp,#4\]
130: bc4083e7 ldur s7, \[sp,#8\]
134: bc4103e7 ldur s7, \[sp,#16\]
138: bc4553e7 ldr s7, \[sp,#85\]
13c: bc4ff3e7 ldr s7, \[sp,#255\]
140: fc5003e7 ldr d7, \[sp,#-256\]
144: fc5553e7 ldr d7, \[sp,#-171\]
148: fc4003e7 ldur d7, \[sp\]
14c: fc4003e7 ldur d7, \[sp\]
150: fc4023e7 ldr d7, \[sp,#2\]
154: fc4043e7 ldr d7, \[sp,#4\]
158: fc4083e7 ldur d7, \[sp,#8\]
15c: fc4103e7 ldur d7, \[sp,#16\]
160: fc4553e7 ldr d7, \[sp,#85\]
164: fc4ff3e7 ldr d7, \[sp,#255\]
168: 3cd003e7 ldr q7, \[sp,#-256\]
16c: 3cd553e7 ldr q7, \[sp,#-171\]
170: 3cc003e7 ldur q7, \[sp\]
174: 3cc003e7 ldur q7, \[sp\]
178: 3cc023e7 ldr q7, \[sp,#2\]
17c: 3cc043e7 ldr q7, \[sp,#4\]
180: 3cc083e7 ldr q7, \[sp,#8\]
184: 3cc103e7 ldur q7, \[sp,#16\]
188: 3cc553e7 ldr q7, \[sp,#85\]
18c: 3ccff3e7 ldr q7, \[sp,#255\]
190: 381003e7 strb w7, \[sp,#-256\]
194: 381553e7 strb w7, \[sp,#-171\]
198: 380003e7 sturb w7, \[sp\]
19c: 380003e7 sturb w7, \[sp\]
1a0: 380023e7 sturb w7, \[sp,#2\]
1a4: 380043e7 sturb w7, \[sp,#4\]
1a8: 380083e7 sturb w7, \[sp,#8\]
1ac: 380103e7 sturb w7, \[sp,#16\]
1b0: 380553e7 sturb w7, \[sp,#85\]
1b4: 380ff3e7 sturb w7, \[sp,#255\]
1b8: 781003e7 strh w7, \[sp,#-256\]
1bc: 781553e7 strh w7, \[sp,#-171\]
1c0: 780003e7 sturh w7, \[sp\]
1c4: 780003e7 sturh w7, \[sp\]
1c8: 780023e7 sturh w7, \[sp,#2\]
1cc: 780043e7 sturh w7, \[sp,#4\]
1d0: 780083e7 sturh w7, \[sp,#8\]
1d4: 780103e7 sturh w7, \[sp,#16\]
1d8: 780553e7 strh w7, \[sp,#85\]
1dc: 780ff3e7 strh w7, \[sp,#255\]
1e0: b81003e7 str w7, \[sp,#-256\]
1e4: b81553e7 str w7, \[sp,#-171\]
1e8: b80003e7 stur w7, \[sp\]
1ec: b80003e7 stur w7, \[sp\]
1f0: b80023e7 str w7, \[sp,#2\]
1f4: b80043e7 stur w7, \[sp,#4\]
1f8: b80083e7 stur w7, \[sp,#8\]
1fc: b80103e7 stur w7, \[sp,#16\]
200: b80553e7 str w7, \[sp,#85\]
204: b80ff3e7 str w7, \[sp,#255\]
208: f81003e7 str x7, \[sp,#-256\]
20c: f81553e7 str x7, \[sp,#-171\]
210: f80003e7 stur x7, \[sp\]
214: f80003e7 stur x7, \[sp\]
218: f80023e7 str x7, \[sp,#2\]
21c: f80043e7 str x7, \[sp,#4\]
220: f80083e7 stur x7, \[sp,#8\]
224: f80103e7 stur x7, \[sp,#16\]
228: f80553e7 str x7, \[sp,#85\]
22c: f80ff3e7 str x7, \[sp,#255\]
230: 385003e7 ldrb w7, \[sp,#-256\]
234: 385553e7 ldrb w7, \[sp,#-171\]
238: 384003e7 ldurb w7, \[sp\]
23c: 384003e7 ldurb w7, \[sp\]
240: 384023e7 ldurb w7, \[sp,#2\]
244: 384043e7 ldurb w7, \[sp,#4\]
248: 384083e7 ldurb w7, \[sp,#8\]
24c: 384103e7 ldurb w7, \[sp,#16\]
250: 384553e7 ldurb w7, \[sp,#85\]
254: 384ff3e7 ldurb w7, \[sp,#255\]
258: 785003e7 ldrh w7, \[sp,#-256\]
25c: 785553e7 ldrh w7, \[sp,#-171\]
260: 784003e7 ldurh w7, \[sp\]
264: 784003e7 ldurh w7, \[sp\]
268: 784023e7 ldurh w7, \[sp,#2\]
26c: 784043e7 ldurh w7, \[sp,#4\]
270: 784083e7 ldurh w7, \[sp,#8\]
274: 784103e7 ldurh w7, \[sp,#16\]
278: 784553e7 ldrh w7, \[sp,#85\]
27c: 784ff3e7 ldrh w7, \[sp,#255\]
280: b85003e7 ldr w7, \[sp,#-256\]
284: b85553e7 ldr w7, \[sp,#-171\]
288: b84003e7 ldur w7, \[sp\]
28c: b84003e7 ldur w7, \[sp\]
290: b84023e7 ldr w7, \[sp,#2\]
294: b84043e7 ldur w7, \[sp,#4\]
298: b84083e7 ldur w7, \[sp,#8\]
29c: b84103e7 ldur w7, \[sp,#16\]
2a0: b84553e7 ldr w7, \[sp,#85\]
2a4: b84ff3e7 ldr w7, \[sp,#255\]
2a8: f85003e7 ldr x7, \[sp,#-256\]
2ac: f85553e7 ldr x7, \[sp,#-171\]
2b0: f84003e7 ldur x7, \[sp\]
2b4: f84003e7 ldur x7, \[sp\]
2b8: f84023e7 ldr x7, \[sp,#2\]
2bc: f84043e7 ldr x7, \[sp,#4\]
2c0: f84083e7 ldur x7, \[sp,#8\]
2c4: f84103e7 ldur x7, \[sp,#16\]
2c8: f84553e7 ldr x7, \[sp,#85\]
2cc: f84ff3e7 ldr x7, \[sp,#255\]
2d0: 389003e7 ldrsb x7, \[sp,#-256\]
2d4: 389553e7 ldrsb x7, \[sp,#-171\]
2d8: 388003e7 ldursb x7, \[sp\]
2dc: 388003e7 ldursb x7, \[sp\]
2e0: 388023e7 ldursb x7, \[sp,#2\]
2e4: 388043e7 ldursb x7, \[sp,#4\]
2e8: 388083e7 ldursb x7, \[sp,#8\]
2ec: 388103e7 ldursb x7, \[sp,#16\]
2f0: 388553e7 ldursb x7, \[sp,#85\]
2f4: 388ff3e7 ldursb x7, \[sp,#255\]
2f8: 789003e7 ldrsh x7, \[sp,#-256\]
2fc: 789553e7 ldrsh x7, \[sp,#-171\]
300: 788003e7 ldursh x7, \[sp\]
304: 788003e7 ldursh x7, \[sp\]
308: 788023e7 ldursh x7, \[sp,#2\]
30c: 788043e7 ldursh x7, \[sp,#4\]
310: 788083e7 ldursh x7, \[sp,#8\]
314: 788103e7 ldursh x7, \[sp,#16\]
318: 788553e7 ldrsh x7, \[sp,#85\]
31c: 788ff3e7 ldrsh x7, \[sp,#255\]
320: b89003e7 ldrsw x7, \[sp,#-256\]
324: b89553e7 ldrsw x7, \[sp,#-171\]
328: b88003e7 ldursw x7, \[sp\]
32c: b88003e7 ldursw x7, \[sp\]
330: b88023e7 ldrsw x7, \[sp,#2\]
334: b88043e7 ldursw x7, \[sp,#4\]
338: b88083e7 ldursw x7, \[sp,#8\]
33c: b88103e7 ldursw x7, \[sp,#16\]
340: b88553e7 ldrsw x7, \[sp,#85\]
344: b88ff3e7 ldrsw x7, \[sp,#255\]
348: 38d003e7 ldrsb w7, \[sp,#-256\]
34c: 38d553e7 ldrsb w7, \[sp,#-171\]
350: 38c003e7 ldursb w7, \[sp\]
354: 38c003e7 ldursb w7, \[sp\]
358: 38c023e7 ldursb w7, \[sp,#2\]
35c: 38c043e7 ldursb w7, \[sp,#4\]
360: 38c083e7 ldursb w7, \[sp,#8\]
364: 38c103e7 ldursb w7, \[sp,#16\]
368: 38c553e7 ldursb w7, \[sp,#85\]
36c: 38cff3e7 ldursb w7, \[sp,#255\]
370: 78d003e7 ldrsh w7, \[sp,#-256\]
374: 78d553e7 ldrsh w7, \[sp,#-171\]
378: 78c003e7 ldursh w7, \[sp\]
37c: 78c003e7 ldursh w7, \[sp\]
380: 78c023e7 ldursh w7, \[sp,#2\]
384: 78c043e7 ldursh w7, \[sp,#4\]
388: 78c083e7 ldursh w7, \[sp,#8\]
38c: 78c103e7 ldursh w7, \[sp,#16\]
390: 78c553e7 ldrsh w7, \[sp,#85\]
394: 78cff3e7 ldrsh w7, \[sp,#255\]

82
gas/testsuite/gas/aarch64/ldst-reg-unscaled-imm.s Normal file
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/* ldst-reg-unscaled-imm.s Test file for AArch64
load-store reg. (unscaled imm.) instructions.
Copyright 2011, 2012 Free Software Foundation, Inc.
Contributed by ARM Ltd.
This file is part of GAS.
GAS is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the license, or
(at your option) any later version.
GAS is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; see the file COPYING3. If not,
see <http://www.gnu.org/licenses/>. */
/* Prefetch memory instruction is not tested here.
Also note that a programmer-friendly disassembler could display
LDUR/STUR instructions using the standard LDR/STR mnemonics when
the encoded immediate is negative or unaligned. However this behaviour
is not required by the architectural assembly language. */
.macro op2_no_imm op, reg
\op \reg\()7, [sp]
.endm
.macro op2 op, reg, simm
\op \reg\()7, [sp, #\simm]
.endm
// load to or store from core register
.macro ld_or_st op, suffix, reg
.irp simm, -256, -171
op2 \op\suffix, \reg, \simm
.endr
op2_no_imm \op\suffix, \reg
.irp simm, 0, 2, 4, 8, 16, 85, 255
op2 \op\suffix, \reg, \simm
.endr
.endm
// load to or store from FP/SIMD register
.macro ld_or_st_v op
.irp reg, b, h, s, d, q
.irp simm, -256, -171
op2 \op, \reg, \simm
.endr
op2_no_imm \op, \reg
.irp simm, 0, 2, 4, 8, 16, 85, 255
op2 \op, \reg, \simm
.endr
.endr
.endm
func:
// load to or store from FP/SIMD register
ld_or_st_v stur
ld_or_st_v ldur
// load to or store from core register
// op, suffix, reg
ld_or_st stur, b, w
ld_or_st stur, h, w
ld_or_st stur, , w
ld_or_st stur, , x
ld_or_st ldur, b, w
ld_or_st ldur, h, w
ld_or_st ldur, , w
ld_or_st ldur, , x
ld_or_st ldur, sb, x
ld_or_st ldur, sh, x
ld_or_st ldur, sw, x
ld_or_st ldur, sb, w
ld_or_st ldur, sh, w

2
gas/testsuite/gas/aarch64/legacy_reg_names.d Normal file
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#name: Legacy register names errors
#error-output: legacy_reg_names.l

4
gas/testsuite/gas/aarch64/legacy_reg_names.l Normal file
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[^:]*: Assembler messages:
[^:]*:5: Error: indexed vector register expected at operand 1 -- `dup v0.b,v1.b\[7\]'
[^:]*:6: Error: operand 1 should be an integer register -- `mov r0.w,r1.w'
[^:]*:7: Error: operand 2 should be a SIMD vector element -- `dup s0,s1\[3\]'

7
gas/testsuite/gas/aarch64/legacy_reg_names.s Normal file
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.text
.arch armv8
dup v0.b, v1.b[7]
mov r0.w, r1.w
dup s0, s1[3]

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gas/testsuite/gas/aarch64/mapmisc.d Normal file
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#as: -EL -I$srcdir/$subdir
#objdump: --syms --special-syms -d
#name: AArch64 Mapping Symbols for miscellaneous directives
#source: mapmisc.s
# This test is only valid on ELF based ports.
#not-target: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix*
.*: +file format .*aarch64.*
SYMBOL TABLE:
0+00 l d .text 0000000000000000 .text
0+00 l d .data 0000000000000000 .data
0+00 l d .bss 0000000000000000 .bss
0+00 l F .text 0000000000000000 foo
0+00 l .text 0000000000000000 \$x
0+04 l .text 0000000000000000 \$d
0+08 l .text 0000000000000000 \$x
0+0c l .text 0000000000000000 \$d
0+10 l .text 0000000000000000 \$x
0+14 l .text 0000000000000000 \$d
0+18 l .text 0000000000000000 \$x
0+1c l .text 0000000000000000 \$d
0+20 l .text 0000000000000000 \$x
0+24 l .text 0000000000000000 \$d
0+28 l .text 0000000000000000 \$x
0+2c l .text 0000000000000000 \$d
0+34 l .text 0000000000000000 \$x
0+38 l .text 0000000000000000 \$d
0+48 l .text 0000000000000000 \$x
0+4c l .text 0000000000000000 \$d
0+50 l .text 0000000000000000 \$x
0+54 l .text 0000000000000000 \$d
0+58 l .text 0000000000000000 \$x
0+5c l .text 0000000000000000 \$d
0+64 l .text 0000000000000000 \$x
0+68 l .text 0000000000000000 \$d
0+70 l .text 0000000000000000 \$x
0+74 l .text 0000000000000000 \$d
0+84 l .text 0000000000000000 \$x
0+88 l .text 0000000000000000 \$d
0+8c l .text 0000000000000000 \$x
0+90 l .text 0000000000000000 \$d
0+94 l .text 0000000000000000 \$x
0+98 l .text 0000000000000000 \$d
0+9c l .text 0000000000000000 \$x
0+a0 l .text 0000000000000000 \$d
0+a4 l .text 0000000000000000 \$x
0+a8 l .text 0000000000000000 \$x
Disassembly of section .text:
0000000000000000 <foo>:
0: d503201f nop
4: 64636261 .word 0x64636261
8: d503201f nop
c: 00636261 .word 0x00636261
10: d503201f nop
14: 00676665 .word 0x00676665
18: d503201f nop
1c: 006a6968 .word 0x006a6968
20: d503201f nop
24: 0000006b .word 0x0000006b
28: d503201f nop
2c: 0000006c .word 0x0000006c
30: 00000000 .word 0x00000000
34: d503201f nop
38: 0000006d .word 0x0000006d
...
48: d503201f nop
4c: 3fc00000 .word 0x3fc00000
50: d503201f nop
54: 40200000 .word 0x40200000
58: d503201f nop
5c: 00000000 .word 0x00000000
60: 400c0000 .word 0x400c0000
64: d503201f nop
68: 00000000 .word 0x00000000
6c: 40120000 .word 0x40120000
70: d503201f nop
74: 00000004 .word 0x00000004
78: 00000004 .word 0x00000004
7c: 00000004 .word 0x00000004
80: 00000004 .word 0x00000004
84: d503201f nop
88: 00000000 .word 0x00000000
8c: d503201f nop
90: 00000000 .word 0x00000000
94: d503201f nop
98: 00000000 .word 0x00000000
9c: d503201f nop
a0: 7778797a .word 0x7778797a
a4: d503201f nop
a8: d503201f nop

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gas/testsuite/gas/aarch64/mapmisc.dat Normal file
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zyxw

40
gas/testsuite/gas/aarch64/mapmisc.s Normal file
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.text
.type foo, %function
foo:
.align 2
.fill 0, 0, 0
nop
.ascii "abcd"
nop
.asciz "abc"
nop
.string "efg"
nop
.string8 "hij"
nop
.string16 "k"
nop
.string32 "l"
nop
.string64 "m"
nop
.float 0e1.5
nop
.single 0e2.5
nop
.double 0e3.5
nop
.dcb.d 1, 4.5
nop
.fill 4, 4, 4
nop
.space 4
nop
.skip 4
nop
.zero 4
nop
.incbin "mapmisc.dat"
nop
.fill 0, 0, 0
nop

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gas/testsuite/gas/aarch64/mapping.d Normal file
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#objdump: --syms --special-syms
#name: AArch64 Mapping Symbols
# This test is only valid on ELF based ports.
#not-target: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix*
# Test the generation of AArch64 ELF Mapping Symbols
.*: +file format.*aarch64.*
SYMBOL TABLE:
0+00 l d .text 0+0 (|.text)
0+00 l d .data 0+0 (|.data)
0+00 l d .bss 0+0 (|.bss)
0+00 l .text 0+0 \$x
0+00 l d foo 0+0 (|foo)
0+00 l foo 0+0 \$x
#Maybe section symbol for .ARM.attributes
#...
0+00 g .text 0+0 mapping
0+08 g .text 0+0 another_mapping

16
gas/testsuite/gas/aarch64/mapping.s Normal file
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.text
.global mapping
mapping:
nop
bl mapping
.global another_mapping
another_mapping:
nop
bl another_mapping
.data
.word 0x123456
.section foo,"ax"
nop

17
gas/testsuite/gas/aarch64/mapping2.d Normal file
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#objdump: --syms --special-syms
#name: AArch64 Mapping Symbols Test 2
# This test is only valid on ELF based ports.
#not-target: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix*
.*: +file format.*aarch64.*
SYMBOL TABLE:
[0]+00 l d .text 0[0]+00 .text
[0]+00 l d .data 0[0]+00 .data
[0]+00 l d .bss 0[0]+00 .bss
[0]+00 l .text 0[0]+00 \$x
[0]+04 l .text 0[0]+00 foo
[0]+00 l d .comment 0[0]+00 .comment
[0]+00 g F .text 0[0]+0c main

13
gas/testsuite/gas/aarch64/mapping2.s Normal file
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.text
.align 2
.global main
.type main, %function
main:
nop
foo:
nop
nop
.size main, .-main
.ident ""
nop

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gas/testsuite/gas/aarch64/mapping3.d Normal file
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#objdump: --syms --special-syms
#name: AArch64 Mapping Symbols Test 3
# This test is only valid on ELF based ports.
#not-target: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix*
.*: +file format.*aarch64.*
SYMBOL TABLE:
0[0]+00 l d .text 0[0]+00 .text
0[0]+00 l d .data 0[0]+00 .data
0[0]+00 l d .bss 0[0]+00 .bss
0[0]+00 l .text 0[0]+00 \$d
0[0]+04 l .text 0[0]+00 \$x

3
gas/testsuite/gas/aarch64/mapping3.s Normal file
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.text
.word 0
nop

14
gas/testsuite/gas/aarch64/mapping4.d Normal file
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#objdump: --syms --special-syms
#name: AArch64 Mapping Symbols Test 4
# This test is only valid on ELF based ports.
#not-target: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix*
.*: +file format.*aarch64.*
SYMBOL TABLE:
0[0]+00 l d .text 0[0]+00 .text
0[0]+00 l d .data 0[0]+00 .data
0[0]+00 l d .bss 0[0]+00 .bss
0[0]+00 l .text 0[0]+00 \$x

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