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aarch64: Implement TLBIP 128-bit instruction

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The addition of 128-bit page table descriptors and, with it, the
addition of 128-bit system registers for these means that special
"invalidate translation table entry" instructions are needed to cope
with the new 128-bit model.  This is introduced with the `tlbpi'
instruction, implemented here.
This commit is contained in:
Victor Do Nascimento 2023-11-15 17:21:39 +00:00
parent 92d8946670
commit a9e2cefdf0
3 changed files with 5 additions and 0 deletions
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1
gas/config/tc-aarch64.c
View File

@ -7666,6 +7666,7 @@ parse_operands (char *str, const aarch64_opcode *opcode)
goto sys_reg_ins;
case AARCH64_OPND_SYSREG_TLBI:
case AARCH64_OPND_SYSREG_TLBIP:
inst.base.operands[i].sysins_op =
parse_sys_ins_reg (&str, aarch64_sys_regs_tlbi_hsh);
sys_reg_ins:

1
include/opcode/aarch64.h
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@ -566,6 +566,7 @@ enum aarch64_opnd
AARCH64_OPND_SYSREG_DC, /* System register <dc_op> operand. */
AARCH64_OPND_SYSREG_IC, /* System register <ic_op> operand. */
AARCH64_OPND_SYSREG_TLBI, /* System register <tlbi_op> operand. */
AARCH64_OPND_SYSREG_TLBIP, /* System register <tlbip_op> operand. */
AARCH64_OPND_SYSREG_SR, /* System register RCTX operand. */
AARCH64_OPND_BARRIER, /* Barrier operand. */
AARCH64_OPND_BARRIER_DSB_NXS, /* Barrier operand for DSB nXS variant. */

3
opcodes/aarch64-tbl.h
View File

@ -4218,6 +4218,7 @@ const struct aarch64_opcode aarch64_opcode_table[] =
CORE_INSN ("dc", 0xd5080000, 0xfff80000, ic_system, 0, OP2 (SYSREG_DC, Rt), QL_SRC_X, F_ALIAS),
CORE_INSN ("ic", 0xd5080000, 0xfff80000, ic_system, 0, OP2 (SYSREG_IC, Rt_SYS), QL_SRC_X, F_ALIAS | F_OPD1_OPT | F_DEFAULT (0x1F)),
CORE_INSN ("tlbi",0xd5080000, 0xfff80000, ic_system, 0, OP2 (SYSREG_TLBI, Rt_SYS), QL_SRC_X, F_ALIAS | F_OPD1_OPT | F_DEFAULT (0x1F)),
D128_INSN ("tlbip",0xd5480000, 0xfff80000, OP3 (SYSREG_TLBIP, Rt_SYS, PAIRREG_OR_XZR), QL_SRC_X2, F_ALIAS| F_OPD1_OPT | F_OPD_PAIR_OPT | F_DEFAULT (0x1f)),
V8_7A_INSN ("wfet", 0xd5031000, 0xffffffe0, ic_system, OP1 (Rd), QL_I1X, F_HAS_ALIAS),
V8_7A_INSN ("wfit", 0xd5031020, 0xffffffe0, ic_system, OP1 (Rd), QL_I1X, F_HAS_ALIAS),
PREDRES_INSN ("cfp", 0xd50b7380, 0xffffffe0, ic_system, OP2 (SYSREG_SR, Rt), QL_SRC_X, F_ALIAS),
@ -6351,6 +6352,8 @@ const struct aarch64_opcode aarch64_opcode_table[] =
"an instruction cache maintenance operation specifier") \
Y(SYSTEM, sysins_op, "SYSREG_TLBI", 0, F(), \
"a TBL invalidation operation specifier") \
Y(SYSTEM, sysins_op, "SYSREG_TLBIP", 0, F(), \
"a 128-bit TBL invalidation operation specifier") \
Y(SYSTEM, sysins_op, "SYSREG_SR", 0, F(), \
"a Speculation Restriction option name (RCTX)") \
Y(SYSTEM, barrier, "BARRIER", 0, F(), \