X86: Ignore REX_B bit for 32-bit XOP instructions
While decoding 32-bit XOP instructions, 64 bit registers names are printed. This patch fixes this by ignoring REX_B bit in 32-bit mode. opcodes/ PR binutils/20637 * i386-dis.c (get_valid_dis386): Ignore REX_B for 32-bit XOP instructions. gas/ PR binutils/20637 * testsuite/gas/i386/xop32reg.d: New file. * testsuite/gas/i386/xop32reg.s: New file. * testsuite/gas/i386/i386.exp: Run new test.
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@ -1,3 +1,11 @@
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2016-11-28 Ramiro Polla <ramiro@hex-rays.com>
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Amit Pawar <amit.pawar@amd.com>
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PR binutils/20637
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* testsuite/gas/i386/xop32reg.d: New file.
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* testsuite/gas/i386/xop32reg.s: New file.
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* testsuite/gas/i386/i386.exp: Run new test.
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2016-11-27 Ambrogino Modigliani <ambrogino.modigliani@gmail.com>
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* arparse.y: Fix spelling in comments.
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@ -261,6 +261,7 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_32_check]]
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run_dump_test "fma4"
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run_dump_test "lwp"
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run_dump_test "xop"
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run_dump_test "xop32reg"
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run_dump_test "bmi"
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run_dump_test "bmi-intel"
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run_dump_test "tbm"
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15
gas/testsuite/gas/i386/xop32reg.d
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15
gas/testsuite/gas/i386/xop32reg.d
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#source: xop32reg.s
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#objdump: -dw
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#name: i386 ignore rex_b in case of 32 bit decoding
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.*: +file format .*
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Disassembly of section \.text:
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0+ <_start>:
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[ ]*[a-f0-9]+: 8f e9 78 e1 4d c2[ ]+vphsubbw -0x3e\(%ebp\),%xmm1
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[ ]*[a-f0-9]+: 8f c9 78 e1 4d c2[ ]+vphsubbw -0x3e\(%ebp\),%xmm1
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[ ]*[a-f0-9]+: 8f e8 40 cd 04 08 07[ ]+vpcomw \$0x7,\(%eax,%ecx,1\),%xmm7,%xmm0
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[ ]*[a-f0-9]+: 8f c8 40 cd 04 08 07[ ]+vpcomw \$0x7,\(%eax,%ecx,1\),%xmm7,%xmm0
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#pass
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13
gas/testsuite/gas/i386/xop32reg.s
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13
gas/testsuite/gas/i386/xop32reg.s
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.text
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_start:
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.long 0xe178e98f
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.word 0xc24d
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.long 0xe178c98f
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.word 0xc24d
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.long 0xcd40e88f
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.word 0x0804
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.byte 0x07
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.long 0xcd40c88f
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.word 0x0804
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.byte 0x07
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@ -1,3 +1,10 @@
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2016-11-28 Ramiro Polla <ramiro@hex-rays.com>
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Amit Pawar <amit.pawar@amd.com>
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PR binutils/20637
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* i386-dis.c (get_valid_dis386): Ignore REX_B for 32-bit XOP
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instructions.
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2016-11-22 Ambrogino Modigliani <ambrogino.modigliani@gmail.com>
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* configure: Regenerate.
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@ -12670,11 +12670,15 @@ get_valid_dis386 (const struct dis386 *dp, disassemble_info *info)
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rex |= REX_W;
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vex.register_specifier = (~(*codep >> 3)) & 0xf;
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if (address_mode != mode_64bit
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&& vex.register_specifier > 0x7)
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if (address_mode != mode_64bit)
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{
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dp = &bad_opcode;
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return dp;
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/* In 16/32-bit mode REX_B is silently ignored. */
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rex &= ~REX_B;
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if (vex.register_specifier > 0x7)
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{
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dp = &bad_opcode;
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return dp;
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}
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}
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vex.length = (*codep & 0x4) ? 256 : 128;
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