diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index 8409c0254e5..9f52bb545ac 100644
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -1562,7 +1562,9 @@ riscv_parse_add_subset (riscv_parse_subset_t *rps,
 	rps->error_handler
 	  (_("x ISA extension `%s' must be set with the versions"),
 	   subset);
-      else
+      /* Allow old ISA spec can recognize zicsr and zifencei.  */
+      else if (strcmp (subset, "zicsr") != 0
+	       && strcmp (subset, "zifencei") != 0)
 	rps->error_handler
 	  (_("cannot find default versions of the ISA extension `%s'"),
 	   subset);
diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
index 5f8e1181baa..1eed63cb38f 100644
--- a/gas/config/tc-riscv.c
+++ b/gas/config/tc-riscv.c
@@ -104,7 +104,7 @@ struct riscv_csr_extra
 
 /* Need to sync the version with RISC-V compiler.  */
 #ifndef DEFAULT_RISCV_ISA_SPEC
-#define DEFAULT_RISCV_ISA_SPEC "2.2"
+#define DEFAULT_RISCV_ISA_SPEC "20191213"
 #endif
 
 #ifndef DEFAULT_RISCV_PRIV_SPEC
diff --git a/gas/testsuite/gas/riscv/csr-version-1p10.d b/gas/testsuite/gas/riscv/csr-version-1p10.d
index ee56ae31f0c..88da7240a78 100644
--- a/gas/testsuite/gas/riscv/csr-version-1p10.d
+++ b/gas/testsuite/gas/riscv/csr-version-1p10.d
@@ -1,4 +1,4 @@
-#as: -march=rv64i -mcsr-check -mpriv-spec=1.10
+#as: -march=rv64i_zicsr -mcsr-check -mpriv-spec=1.10
 #source: csr.s
 #warning_output: csr-version-1p10.l
 #objdump: -dr -Mpriv-spec=1.10
diff --git a/gas/testsuite/gas/riscv/csr-version-1p11.d b/gas/testsuite/gas/riscv/csr-version-1p11.d
index a1d8169d7f7..b40c1d5d6b9 100644
--- a/gas/testsuite/gas/riscv/csr-version-1p11.d
+++ b/gas/testsuite/gas/riscv/csr-version-1p11.d
@@ -1,4 +1,4 @@
-#as: -march=rv64i -mcsr-check -mpriv-spec=1.11
+#as: -march=rv64i_zicsr -mcsr-check -mpriv-spec=1.11
 #source: csr.s
 #warning_output: csr-version-1p11.l
 #objdump: -dr -Mpriv-spec=1.11
diff --git a/gas/testsuite/gas/riscv/csr-version-1p12.d b/gas/testsuite/gas/riscv/csr-version-1p12.d
index c4c211829b2..fbc30ee2fcc 100644
--- a/gas/testsuite/gas/riscv/csr-version-1p12.d
+++ b/gas/testsuite/gas/riscv/csr-version-1p12.d
@@ -1,4 +1,4 @@
-#as: -march=rv64i -mcsr-check -mpriv-spec=1.12
+#as: -march=rv64i_zicsr -mcsr-check -mpriv-spec=1.12
 #source: csr.s
 #warning_output: csr-version-1p12.l
 #objdump: -dr -Mpriv-spec=1.12
diff --git a/gas/testsuite/gas/riscv/csr-version-1p9p1.d b/gas/testsuite/gas/riscv/csr-version-1p9p1.d
index 01e05ae4fbc..a96e8c9dbec 100644
--- a/gas/testsuite/gas/riscv/csr-version-1p9p1.d
+++ b/gas/testsuite/gas/riscv/csr-version-1p9p1.d
@@ -1,4 +1,4 @@
-#as: -march=rv64i -mcsr-check -mpriv-spec=1.9.1
+#as: -march=rv64i_zicsr -mcsr-check -mpriv-spec=1.9.1
 #source: csr.s
 #warning_output: csr-version-1p9p1.l
 #objdump: -dr -Mpriv-spec=1.9.1
diff --git a/gas/testsuite/gas/riscv/option-arch-03.d b/gas/testsuite/gas/riscv/option-arch-03.d
index b621d036c29..62d7f7d5ed2 100644
--- a/gas/testsuite/gas/riscv/option-arch-03.d
+++ b/gas/testsuite/gas/riscv/option-arch-03.d
@@ -4,5 +4,5 @@
 
 Attribute Section: riscv
 File Attributes
-  Tag_RISCV_arch: "rv32i2p0_c2p0"
+  Tag_RISCV_arch: "rv32i2p1_c2p0"
 #...
diff --git a/gas/testsuite/gas/riscv/option-arch-03.s b/gas/testsuite/gas/riscv/option-arch-03.s
index d982a0b0985..ccdb1c354b0 100644
--- a/gas/testsuite/gas/riscv/option-arch-03.s
+++ b/gas/testsuite/gas/riscv/option-arch-03.s
@@ -1,3 +1,3 @@
 .attribute arch, "rv64ic"
 .option arch, +d2p0, -c
-.option arch, rv32ic
+.option arch, rv32i2p1c2p0
diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-arch-01.d b/ld/testsuite/ld-riscv-elf/attr-merge-arch-01.d
index c148cdbc4f4..a4b0322a3d9 100644
--- a/ld/testsuite/ld-riscv-elf/attr-merge-arch-01.d
+++ b/ld/testsuite/ld-riscv-elf/attr-merge-arch-01.d
@@ -6,4 +6,4 @@
 
 Attribute Section: riscv
 File Attributes
-  Tag_RISCV_arch: "rv32i2p0_m2p0"
+  Tag_RISCV_arch: "rv32i2p1_m2p0"
diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-arch-01a.s b/ld/testsuite/ld-riscv-elf/attr-merge-arch-01a.s
index acc98a53cf5..ea097f99b04 100644
--- a/ld/testsuite/ld-riscv-elf/attr-merge-arch-01a.s
+++ b/ld/testsuite/ld-riscv-elf/attr-merge-arch-01a.s
@@ -1 +1 @@
-	.attribute arch, "rv32i2p0_m2p0"
+	.attribute arch, "rv32i2p1_m2p0"
diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-arch-01b.s b/ld/testsuite/ld-riscv-elf/attr-merge-arch-01b.s
index acc98a53cf5..ea097f99b04 100644
--- a/ld/testsuite/ld-riscv-elf/attr-merge-arch-01b.s
+++ b/ld/testsuite/ld-riscv-elf/attr-merge-arch-01b.s
@@ -1 +1 @@
-	.attribute arch, "rv32i2p0_m2p0"
+	.attribute arch, "rv32i2p1_m2p0"
diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-arch-02.d b/ld/testsuite/ld-riscv-elf/attr-merge-arch-02.d
index bc0e0fd1384..852fd55ae08 100644
--- a/ld/testsuite/ld-riscv-elf/attr-merge-arch-02.d
+++ b/ld/testsuite/ld-riscv-elf/attr-merge-arch-02.d
@@ -6,4 +6,4 @@
 
 Attribute Section: riscv
 File Attributes
-  Tag_RISCV_arch: "rv32i2p0_m2p0"
+  Tag_RISCV_arch: "rv32i2p1_m2p0"
diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-arch-02a.s b/ld/testsuite/ld-riscv-elf/attr-merge-arch-02a.s
index acc98a53cf5..ea097f99b04 100644
--- a/ld/testsuite/ld-riscv-elf/attr-merge-arch-02a.s
+++ b/ld/testsuite/ld-riscv-elf/attr-merge-arch-02a.s
@@ -1 +1 @@
-	.attribute arch, "rv32i2p0_m2p0"
+	.attribute arch, "rv32i2p1_m2p0"
diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-arch-02b.s b/ld/testsuite/ld-riscv-elf/attr-merge-arch-02b.s
index 65d0fefd5af..610c7e53c1a 100644
--- a/ld/testsuite/ld-riscv-elf/attr-merge-arch-02b.s
+++ b/ld/testsuite/ld-riscv-elf/attr-merge-arch-02b.s
@@ -1 +1 @@
-	.attribute arch, "rv32i2p0"
+	.attribute arch, "rv32i2p1"
diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-arch-03.d b/ld/testsuite/ld-riscv-elf/attr-merge-arch-03.d
index 374a043c69e..c1cf8081dc7 100644
--- a/ld/testsuite/ld-riscv-elf/attr-merge-arch-03.d
+++ b/ld/testsuite/ld-riscv-elf/attr-merge-arch-03.d
@@ -6,4 +6,4 @@
 
 Attribute Section: riscv
 File Attributes
-  Tag_RISCV_arch: "rv32i2p0_m2p0_xbar2p0_xfoo2p0"
+  Tag_RISCV_arch: "rv32i2p1_m2p0_xbar2p0_xfoo2p0"
diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-arch-03a.s b/ld/testsuite/ld-riscv-elf/attr-merge-arch-03a.s
index b86cc558fbf..3a9fb97ac4e 100644
--- a/ld/testsuite/ld-riscv-elf/attr-merge-arch-03a.s
+++ b/ld/testsuite/ld-riscv-elf/attr-merge-arch-03a.s
@@ -1 +1 @@
-	.attribute arch, "rv32i2p0_m2p0_xfoo2p0"
+	.attribute arch, "rv32i2p1_m2p0_xfoo2p0"
diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-arch-03b.s b/ld/testsuite/ld-riscv-elf/attr-merge-arch-03b.s
index 376e3737b2c..878f2de8e53 100644
--- a/ld/testsuite/ld-riscv-elf/attr-merge-arch-03b.s
+++ b/ld/testsuite/ld-riscv-elf/attr-merge-arch-03b.s
@@ -1 +1 @@
-	.attribute arch, "rv32i2p0_xbar2p0"
+	.attribute arch, "rv32i2p1_xbar2p0"
diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-arch-failed-02.d b/ld/testsuite/ld-riscv-elf/attr-merge-arch-failed-02.d
index 3f4935df54c..2f2638ace22 100644
--- a/ld/testsuite/ld-riscv-elf/attr-merge-arch-failed-02.d
+++ b/ld/testsuite/ld-riscv-elf/attr-merge-arch-failed-02.d
@@ -23,5 +23,5 @@
 
 Attribute Section: riscv
 File Attributes
-  Tag_RISCV_arch: "rv32i4p6_m4p7_a4p8_zicsr4p9_xunknown4p0"
+  Tag_RISCV_arch: "rv32i4p6_m4p7_a4p8_zicsr4p9_zifencei2p0_xunknown4p0"
 #..
diff --git a/ld/testsuite/ld-riscv-elf/call-relax.d b/ld/testsuite/ld-riscv-elf/call-relax.d
index c6022bec262..f8f02298232 100644
--- a/ld/testsuite/ld-riscv-elf/call-relax.d
+++ b/ld/testsuite/ld-riscv-elf/call-relax.d
@@ -3,7 +3,7 @@
 #source: call-relax-1.s
 #source: call-relax-2.s
 #source: call-relax-3.s
-#as: -march=rv32ic -mno-arch-attr
+#as: -march=rv32ic_zicsr -mno-arch-attr
 #ld: -m[riscv_choose_ilp32_emul]
 #objdump: -d
 #pass