yggdrasil/binutils-gdb
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

PATCH 5/6][Binutils] aarch64: Add SVE2.1 fmin and fmax instructions.

Browse Source 
Hi,

This patch add support for SVE2.1 instruction faddqv,
fmaxnmqv, fmaxqv, fminnmqv and fminqv.

Regression testing for aarch64-none-elf target and found no regressions.

Ok for binutils-master?

Regards,
Srinath.
This commit is contained in:
Srinath Parvathaneni 2024-01-15 09:38:39 +00:00 committed by Nick Clifton
parent 39092c7a1f
commit b34104edab
4 changed files with 91 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

25
gas/testsuite/gas/aarch64/sve2p1-1-bad.l
View File

@ -55,3 +55,28 @@
.*: Error: selected processor does not support `extq z4.b,z4.b,z12.b\[1\]'
.*: Error: selected processor does not support `extq z8.b,z8.b,z7.b\[4\]'
.*: Error: selected processor does not support `extq z16.b,z16.b,z1.b\[8\]'
.*: Error: selected processor does not support `faddqv v1.8h,p1,z8.h'
.*: Error: selected processor does not support `faddqv v2.4s,p2,z4.s'
.*: Error: selected processor does not support `faddqv v4.2d,p3,z2.d'
.*: Error: selected processor does not support `faddqv v8.2d,p4,z1.d'
.*: Error: selected processor does not support `faddqv v16.4s,p7,z0.s'
.*: Error: selected processor does not support `fmaxnmqv v1.8h,p1,z8.h'
.*: Error: selected processor does not support `fmaxnmqv v2.4s,p2,z4.s'
.*: Error: selected processor does not support `fmaxnmqv v4.2d,p3,z2.d'
.*: Error: selected processor does not support `fmaxnmqv v8.2d,p4,z1.d'
.*: Error: selected processor does not support `fmaxnmqv v16.4s,p7,z0.s'
.*: Error: selected processor does not support `fmaxqv v1.8h,p1,z8.h'
.*: Error: selected processor does not support `fmaxqv v2.4s,p2,z4.s'
.*: Error: selected processor does not support `fmaxqv v4.2d,p3,z2.d'
.*: Error: selected processor does not support `fmaxqv v8.2d,p4,z1.d'
.*: Error: selected processor does not support `fmaxqv v16.4s,p7,z0.s'
.*: Error: selected processor does not support `fminnmqv v1.8h,p1,z8.h'
.*: Error: selected processor does not support `fminnmqv v2.4s,p2,z4.s'
.*: Error: selected processor does not support `fminnmqv v4.2d,p3,z2.d'
.*: Error: selected processor does not support `fminnmqv v8.2d,p4,z1.d'
.*: Error: selected processor does not support `fminnmqv v16.4s,p7,z0.s'
.*: Error: selected processor does not support `fminqv v1.8h,p1,z8.h'
.*: Error: selected processor does not support `fminqv v2.4s,p2,z4.s'
.*: Error: selected processor does not support `fminqv v4.2d,p3,z2.d'
.*: Error: selected processor does not support `fminqv v8.2d,p4,z1.d'
.*: Error: selected processor does not support `fminqv v16.4s,p7,z0.s'

25
gas/testsuite/gas/aarch64/sve2p1-1.d
View File

@ -64,3 +64,28 @@
.*: 056c2444 extq z4.b, z4.b, z12.b\[1\]
.*: 05672508 extq z8.b, z8.b, z7.b\[4\]
.*: 05612610 extq z16.b, z16.b, z1.b\[8\]
.*: 6450a501 faddqv v1.8h, p1, z8.h
.*: 6490a882 faddqv v2.4s, p2, z4.s
.*: 64d0ac44 faddqv v4.2d, p3, z2.d
.*: 64d0b028 faddqv v8.2d, p4, z1.d
.*: 6490bc10 faddqv v16.4s, p7, z0.s
.*: 6454a501 fmaxnmqv v1.8h, p1, z8.h
.*: 6494a882 fmaxnmqv v2.4s, p2, z4.s
.*: 64d4ac44 fmaxnmqv v4.2d, p3, z2.d
.*: 64d4b028 fmaxnmqv v8.2d, p4, z1.d
.*: 6494bc10 fmaxnmqv v16.4s, p7, z0.s
.*: 6456a501 fmaxqv v1.8h, p1, z8.h
.*: 6496a882 fmaxqv v2.4s, p2, z4.s
.*: 64d6ac44 fmaxqv v4.2d, p3, z2.d
.*: 64d6b028 fmaxqv v8.2d, p4, z1.d
.*: 6496bc10 fmaxqv v16.4s, p7, z0.s
.*: 6455a501 fminnmqv v1.8h, p1, z8.h
.*: 6495a882 fminnmqv v2.4s, p2, z4.s
.*: 64d5ac44 fminnmqv v4.2d, p3, z2.d
.*: 64d5b028 fminnmqv v8.2d, p4, z1.d
.*: 6495bc10 fminnmqv v16.4s, p7, z0.s
.*: 6457a501 fminqv v1.8h, p1, z8.h
.*: 6497a882 fminqv v2.4s, p2, z4.s
.*: 64d7ac44 fminqv v4.2d, p3, z2.d
.*: 64d7b028 fminqv v8.2d, p4, z1.d
.*: 6497bc10 fminqv v16.4s, p7, z0.s

29
gas/testsuite/gas/aarch64/sve2p1-1.s
View File

@ -61,3 +61,32 @@ extq z2.b, z2.b, z5.b[3]
extq z4.b, z4.b, z12.b[1]
extq z8.b, z8.b, z7.b[4]
extq z16.b, z16.b, z1.b[8]
faddqv v1.8h, p1, z8.h
faddqv v2.4s, p2, z4.s
faddqv v4.2d, p3, z2.d
faddqv v8.2d, p4, z1.d
faddqv v16.4s, p7, z0.s
fmaxnmqv v1.8h, p1, z8.h
fmaxnmqv v2.4s, p2, z4.s
fmaxnmqv v4.2d, p3, z2.d
fmaxnmqv v8.2d, p4, z1.d
fmaxnmqv v16.4s, p7, z0.s
fmaxqv v1.8h, p1, z8.h
fmaxqv v2.4s, p2, z4.s
fmaxqv v4.2d, p3, z2.d
fmaxqv v8.2d, p4, z1.d
fmaxqv v16.4s, p7, z0.s
fminnmqv v1.8h, p1, z8.h
fminnmqv v2.4s, p2, z4.s
fminnmqv v4.2d, p3, z2.d
fminnmqv v8.2d, p4, z1.d
fminnmqv v16.4s, p7, z0.s
fminqv v1.8h, p1, z8.h
fminqv v2.4s, p2, z4.s
fminqv v4.2d, p3, z2.d
fminqv v8.2d, p4, z1.d
fminqv v16.4s, p7, z0.s

12
opcodes/aarch64-tbl.h
View File

@ -1922,6 +1922,12 @@
QLF3(V_4S,NIL,S_S), \
QLF3(V_2D,NIL,S_D), \
}
#define OP_SVE_vUS_HSD_HSD \
{ \
QLF3(V_8H,NIL,S_H), \
QLF3(V_4S,NIL,S_S), \
QLF3(V_2D,NIL,S_D), \
}
#define OP_SVE_VMV_SD \
{ \
QLF3(S_S,P_M,S_S), \
@ -6339,6 +6345,12 @@ const struct aarch64_opcode aarch64_opcode_table[] =
SVE2p1_INSNC("uminqv",0x040f2000, 0xff3fe000, sve2_urqvs, 0, OP3 (Vd, SVE_Pg3, SVE_Zn), OP_SVE_vUS_BHSD_BHSD, F_OPD_SIZE, C_SCAN_MOVPRFX, 0),
SVE2p1_INSNC("eorqv",0x041d2000, 0xff3fe000, sve2_urqvs, 0, OP3 (Vd, SVE_Pg3, SVE_Zn), OP_SVE_vUS_BHSD_BHSD, F_OPD_SIZE, C_SCAN_MOVPRFX, 0),
SVE2p1_INSNC("faddqv",0x6410a000, 0xff3fe000, sve2_urqvs, 0, OP3 (Vd, SVE_Pg3, SVE_Zn), OP_SVE_vUS_HSD_HSD, F_OPD_SIZE, C_SCAN_MOVPRFX, 0),
SVE2p1_INSNC("fmaxnmqv",0x6414a000, 0xff3fe000, sve2_urqvs, 0, OP3 (Vd, SVE_Pg3, SVE_Zn), OP_SVE_vUS_HSD_HSD, F_OPD_SIZE, C_SCAN_MOVPRFX, 0),
SVE2p1_INSNC("fmaxqv",0x6416a000, 0xff3fe000, sve2_urqvs, 0, OP3 (Vd, SVE_Pg3, SVE_Zn), OP_SVE_vUS_HSD_HSD, F_OPD_SIZE, C_SCAN_MOVPRFX, 0),
SVE2p1_INSNC("fminnmqv",0x6415a000, 0xff3fe000, sve2_urqvs, 0, OP3 (Vd, SVE_Pg3, SVE_Zn), OP_SVE_vUS_HSD_HSD, F_OPD_SIZE, C_SCAN_MOVPRFX, 0),
SVE2p1_INSNC("fminqv",0x6417a000, 0xff3fe000, sve2_urqvs, 0, OP3 (Vd, SVE_Pg3, SVE_Zn), OP_SVE_vUS_HSD_HSD, F_OPD_SIZE, C_SCAN_MOVPRFX, 0),
SVE2p1_INSN("dupq",0x05202400, 0xffe0fc00, sve_index1, 0, OP2 (SVE_Zd, SVE_Zn_5_INDEX), OP_SVE_VV_BHSD, 0, 0),
SVE2p1_INSN("extq",0x05602400, 0xfff0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zd, SVE_Zm_imm4), OP_SVE_BBB, 0, 0),