aarch64: Sort fields alphanumerically
This patch just sorts the field enum alphanumerically, which makes it easier to see if a particular field has already been defined.
This commit is contained in:
Richard Sandiford
parent
ccb6da7c82
commit
b5c36ad2e0
@ -202,74 +202,36 @@ aarch64_select_operand_for_sizeq_field_coding (const aarch64_opcode *opcode)
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const aarch64_field fields[] =
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{
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{ 0, 0 }, /* NIL. */
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{ 0, 4 }, /* cond2: condition in truly conditional-executed inst. */
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{ 0, 4 }, /* nzcv: flag bit specifier, encoded in the "nzcv" field. */
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{ 5, 5 }, /* defgh: d:e:f:g:h bits in AdvSIMD modified immediate. */
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{ 16, 3 }, /* abc: a:b:c bits in AdvSIMD modified immediate. */
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{ 5, 19 }, /* imm19: e.g. in CBZ. */
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{ 5, 19 }, /* immhi: e.g. in ADRP. */
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{ 29, 2 }, /* immlo: e.g. in ADRP. */
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{ 22, 2 }, /* size: in most AdvSIMD and floating-point instructions. */
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{ 10, 2 }, /* vldst_size: size field in the AdvSIMD load/store inst. */
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{ 29, 1 }, /* op: in AdvSIMD modified immediate instructions. */
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{ 30, 1 }, /* Q: in most AdvSIMD instructions. */
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{ 0, 5 }, /* Rt: in load/store instructions. */
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{ 0, 5 }, /* Rd: in many integer instructions. */
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{ 5, 5 }, /* Rn: in many integer instructions. */
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{ 10, 5 }, /* Rt2: in load/store pair instructions. */
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{ 10, 5 }, /* Ra: in fp instructions. */
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{ 5, 3 }, /* op2: in the system instructions. */
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{ 8, 4 }, /* CRm: in the system instructions. */
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{ 10, 2 }, /* CRm_dsb_nxs: 2-bit imm. encoded in CRm<3:2>. */
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{ 12, 4 }, /* CRn: in the system instructions. */
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{ 16, 3 }, /* op1: in the system instructions. */
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{ 19, 2 }, /* op0: in the system instructions. */
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{ 10, 3 }, /* imm3: in add/sub extended reg instructions. */
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{ 12, 4 }, /* cond: condition flags as a source operand. */
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{ 12, 4 }, /* opcode: in advsimd load/store instructions. */
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{ 12, 4 }, /* cmode: in advsimd modified immediate instructions. */
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{ 13, 3 }, /* asisdlso_opcode: opcode in advsimd ld/st single element. */
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{ 13, 2 }, /* len: in advsimd tbl/tbx instructions. */
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{ 16, 5 }, /* Rm: in ld/st reg offset and some integer inst. */
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{ 16, 5 }, /* Rs: in load/store exclusive instructions. */
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{ 13, 3 }, /* option: in ld/st reg offset + add/sub extended reg inst. */
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{ 12, 1 }, /* S: in load/store reg offset instructions. */
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{ 21, 2 }, /* hw: in move wide constant instructions. */
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{ 22, 2 }, /* opc: in load/store reg offset instructions. */
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{ 23, 1 }, /* opc1: in load/store reg offset instructions. */
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{ 22, 2 }, /* shift: in add/sub reg/imm shifted instructions. */
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{ 22, 2 }, /* type: floating point type field in fp data inst. */
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{ 30, 2 }, /* ldst_size: size field in ld/st reg offset inst. */
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{ 10, 6 }, /* imm6_10: in add/sub reg shifted instructions. */
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{ 15, 6 }, /* imm6_15: in rmif instructions. */
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{ 11, 4 }, /* imm4_11: in advsimd ext and advsimd ins instructions. */
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{ 0, 4 }, /* imm4_0: in rmif instructions. */
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{ 10, 4 }, /* imm4_10: in adddg/subg instructions. */
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{ 5, 4 }, /* imm4_5: in SME instructions. */
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{ 16, 5 }, /* imm5: in conditional compare (immediate) instructions. */
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{ 15, 7 }, /* imm7: in load/store pair pre/post index instructions. */
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{ 13, 8 }, /* imm8: in floating-point scalar move immediate inst. */
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{ 12, 9 }, /* imm9: in load/store pre/post index instructions. */
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{ 10, 12 }, /* imm12: in ld/st unsigned imm or add/sub shifted inst. */
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{ 5, 14 }, /* imm14: in test bit and branch instructions. */
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{ 5, 16 }, /* imm16_5: in exception instructions. */
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{ 0, 16 }, /* imm16_0: in udf instruction. */
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{ 0, 26 }, /* imm26: in unconditional branch instructions. */
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{ 10, 6 }, /* imms: in bitfield and logical immediate instructions. */
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{ 16, 6 }, /* immr: in bitfield and logical immediate instructions. */
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{ 16, 3 }, /* immb: in advsimd shift by immediate instructions. */
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{ 19, 4 }, /* immh: in advsimd shift by immediate instructions. */
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{ 22, 1 }, /* S_imm10: in LDRAA and LDRAB instructions. */
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{ 22, 1 }, /* N: in logical (immediate) instructions. */
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{ 11, 1 }, /* index: in ld/st inst deciding the pre/post-index. */
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{ 24, 1 }, /* index2: in ld/st pair inst deciding the pre/post-index. */
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{ 31, 1 }, /* sf: in integer data processing instructions. */
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{ 30, 1 }, /* lse_sz: in LSE extension atomic instructions. */
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{ 10, 8 }, /* CSSC_imm8. */
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{ 11, 1 }, /* H: in advsimd scalar x indexed element instructions. */
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{ 21, 1 }, /* L: in advsimd scalar x indexed element instructions. */
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{ 20, 1 }, /* M: in advsimd scalar x indexed element instructions. */
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{ 31, 1 }, /* b5: in the test bit and branch instructions. */
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{ 19, 5 }, /* b40: in the test bit and branch instructions. */
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{ 10, 6 }, /* scale: in the fixed-point scalar to fp converting inst. */
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{ 22, 1 }, /* N: in logical (immediate) instructions. */
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{ 30, 1 }, /* Q: in most AdvSIMD instructions. */
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{ 10, 5 }, /* Ra: in fp instructions. */
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{ 0, 5 }, /* Rd: in many integer instructions. */
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{ 16, 5 }, /* Rm: in ld/st reg offset and some integer inst. */
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{ 5, 5 }, /* Rn: in many integer instructions. */
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{ 16, 5 }, /* Rs: in load/store exclusive instructions. */
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{ 0, 5 }, /* Rt: in load/store instructions. */
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{ 10, 5 }, /* Rt2: in load/store pair instructions. */
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{ 12, 1 }, /* S: in load/store reg offset instructions. */
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{ 12, 2 }, /* SM3_imm2: Indexed element SM3 2 bits index immediate. */
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{ 13, 3 }, /* SME_Pm: second source scalable predicate register P0-P7. */
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{ 16, 1 }, /* SME_Q: Q class bit, bit 16. */
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{ 16, 2 }, /* SME_Rm: index base register W12-W15 [17:16]. */
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{ 13, 2 }, /* SME_Rv: vector select register W12-W15, bits [14:13]. */
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{ 15, 1 }, /* SME_V: (horizontal / vertical tiles), bit 15. */
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{ 0, 2 }, /* SME_ZAda_2b: tile ZA0-ZA3. */
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{ 0, 3 }, /* SME_ZAda_3b: tile ZA0-ZA7. */
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{ 23, 1 }, /* SME_i1: immediate field, bit 23. */
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{ 22, 2 }, /* SME_size_22: size<1>, size<0> class field, [23:22]. */
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{ 22, 1 }, /* SME_tszh: immediate and qualifier field, bit 22. */
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{ 18, 3 }, /* SME_tszl: immediate and qualifier field, bits [20:18]. */
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{ 0, 8 }, /* SME_zero_mask: list of up to 8 tile names separated by commas [7:0]. */
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{ 4, 1 }, /* SVE_M_4: Merge/zero select, bit 4. */
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{ 14, 1 }, /* SVE_M_14: Merge/zero select, bit 14. */
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{ 16, 1 }, /* SVE_M_16: Merge/zero select, bit 16. */
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@ -295,10 +257,10 @@ const aarch64_field fields[] =
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{ 5, 5 }, /* SVE_Zn: SVE vector register, bits [9,5]. */
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{ 0, 5 }, /* SVE_Zt: SVE vector register, bits [4,0]. */
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{ 5, 1 }, /* SVE_i1: single-bit immediate. */
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{ 22, 1 }, /* SVE_i3h: high bit of 3-bit immediate. */
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{ 11, 1 }, /* SVE_i3l: low bit of 3-bit immediate. */
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{ 19, 2 }, /* SVE_i3h2: two high bits of 3bit immediate, bits [20,19]. */
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{ 20, 1 }, /* SVE_i2h: high bit of 2bit immediate, bits. */
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{ 22, 1 }, /* SVE_i3h: high bit of 3-bit immediate. */
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{ 19, 2 }, /* SVE_i3h2: two high bits of 3bit immediate, bits [20,19]. */
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{ 11, 1 }, /* SVE_i3l: low bit of 3-bit immediate. */
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{ 16, 3 }, /* SVE_imm3: 3-bit immediate field. */
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{ 16, 4 }, /* SVE_imm4: 4-bit immediate field. */
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{ 5, 5 }, /* SVE_imm5: 5-bit immediate field. */
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@ -315,8 +277,8 @@ const aarch64_field fields[] =
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{ 16, 1 }, /* SVE_rot1: 1-bit rotation amount. */
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{ 10, 2 }, /* SVE_rot2: 2-bit rotation amount. */
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{ 10, 1 }, /* SVE_rot3: 1-bit rotation amount at bit 10. */
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{ 22, 1 }, /* SVE_sz: 1-bit element size select. */
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{ 17, 2 }, /* SVE_size: 2-bit element size, bits [18,17]. */
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{ 22, 1 }, /* SVE_sz: 1-bit element size select. */
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{ 30, 1 }, /* SVE_sz2: 1-bit element size select. */
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{ 16, 4 }, /* SVE_tsz: triangular size select. */
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{ 22, 2 }, /* SVE_tszh: triangular size select high, bits [23,22]. */
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@ -324,25 +286,63 @@ const aarch64_field fields[] =
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{ 19, 2 }, /* SVE_tszl_19: triangular size select low, bits [20,19]. */
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{ 14, 1 }, /* SVE_xs_14: UXTW/SXTW select (bit 14). */
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{ 22, 1 }, /* SVE_xs_22: UXTW/SXTW select (bit 22). */
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{ 0, 2 }, /* SME_ZAda_2b: tile ZA0-ZA3. */
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{ 0, 3 }, /* SME_ZAda_3b: tile ZA0-ZA7. */
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{ 22, 2 }, /* SME_size_22: size<1>, size<0> class field, [23:22]. */
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{ 16, 1 }, /* SME_Q: Q class bit, bit 16. */
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{ 15, 1 }, /* SME_V: (horizontal / vertical tiles), bit 15. */
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{ 13, 2 }, /* SME_Rv: vector select register W12-W15, bits [14:13]. */
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{ 13, 3 }, /* SME_Pm: second source scalable predicate register P0-P7. */
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{ 0, 8 }, /* SME_zero_mask: list of up to 8 tile names separated by commas [7:0]. */
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{ 16, 2 }, /* SME_Rm: index base register W12-W15 [17:16]. */
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{ 23, 1 }, /* SME_i1: immediate field, bit 23. */
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{ 22, 1 }, /* SME_tszh: immediate and qualifier field, bit 22. */
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{ 18, 3 }, /* SME_tszl: immediate and qualifier field, bits [20:18]. */
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{ 22, 1 }, /* S_imm10: in LDRAA and LDRAB instructions. */
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{ 16, 3 }, /* abc: a:b:c bits in AdvSIMD modified immediate. */
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{ 13, 3 }, /* asisdlso_opcode: opcode in advsimd ld/st single element. */
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{ 19, 5 }, /* b40: in the test bit and branch instructions. */
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{ 31, 1 }, /* b5: in the test bit and branch instructions. */
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{ 12, 4 }, /* cmode: in advsimd modified immediate instructions. */
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{ 12, 4 }, /* cond: condition flags as a source operand. */
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{ 0, 4 }, /* cond2: condition in truly conditional-executed inst. */
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{ 5, 5 }, /* defgh: d:e:f:g:h bits in AdvSIMD modified immediate. */
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{ 21, 2 }, /* hw: in move wide constant instructions. */
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{ 10, 3 }, /* imm3: in add/sub extended reg instructions. */
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{ 0, 4 }, /* imm4_0: in rmif instructions. */
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{ 5, 4 }, /* imm4_5: in SME instructions. */
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{ 10, 4 }, /* imm4_10: in adddg/subg instructions. */
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{ 11, 4 }, /* imm4_11: in advsimd ext and advsimd ins instructions. */
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{ 16, 5 }, /* imm5: in conditional compare (immediate) instructions. */
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{ 10, 6 }, /* imm6_10: in add/sub reg shifted instructions. */
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{ 15, 6 }, /* imm6_15: in rmif instructions. */
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{ 15, 7 }, /* imm7: in load/store pair pre/post index instructions. */
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{ 13, 8 }, /* imm8: in floating-point scalar move immediate inst. */
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{ 12, 9 }, /* imm9: in load/store pre/post index instructions. */
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{ 10, 12 }, /* imm12: in ld/st unsigned imm or add/sub shifted inst. */
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{ 5, 14 }, /* imm14: in test bit and branch instructions. */
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{ 0, 16 }, /* imm16_0: in udf instruction. */
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{ 5, 16 }, /* imm16_5: in exception instructions. */
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{ 5, 19 }, /* imm19: e.g. in CBZ. */
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{ 0, 26 }, /* imm26: in unconditional branch instructions. */
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{ 16, 3 }, /* immb: in advsimd shift by immediate instructions. */
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{ 19, 4 }, /* immh: in advsimd shift by immediate instructions. */
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{ 5, 19 }, /* immhi: e.g. in ADRP. */
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{ 29, 2 }, /* immlo: e.g. in ADRP. */
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{ 16, 6 }, /* immr: in bitfield and logical immediate instructions. */
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{ 10, 6 }, /* imms: in bitfield and logical immediate instructions. */
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{ 11, 1 }, /* index: in ld/st inst deciding the pre/post-index. */
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{ 24, 1 }, /* index2: in ld/st pair inst deciding the pre/post-index. */
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{ 30, 2 }, /* ldst_size: size field in ld/st reg offset inst. */
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{ 13, 2 }, /* len: in advsimd tbl/tbx instructions. */
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{ 30, 1 }, /* lse_sz: in LSE extension atomic instructions. */
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{ 0, 4 }, /* nzcv: flag bit specifier, encoded in the "nzcv" field. */
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{ 29, 1 }, /* op: in AdvSIMD modified immediate instructions. */
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{ 19, 2 }, /* op0: in the system instructions. */
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{ 16, 3 }, /* op1: in the system instructions. */
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{ 5, 3 }, /* op2: in the system instructions. */
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{ 22, 2 }, /* opc: in load/store reg offset instructions. */
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{ 23, 1 }, /* opc1: in load/store reg offset instructions. */
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{ 12, 4 }, /* opcode: in advsimd load/store instructions. */
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{ 13, 3 }, /* option: in ld/st reg offset + add/sub extended reg inst. */
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{ 11, 2 }, /* rotate1: FCMLA immediate rotate. */
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{ 13, 2 }, /* rotate2: Indexed element FCMLA immediate rotate. */
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{ 12, 1 }, /* rotate3: FCADD immediate rotate. */
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{ 12, 2 }, /* SM3_imm2: Indexed element SM3 2 bits index immediate. */
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{ 10, 6 }, /* scale: in the fixed-point scalar to fp converting inst. */
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{ 31, 1 }, /* sf: in integer data processing instructions. */
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{ 22, 2 }, /* shift: in add/sub reg/imm shifted instructions. */
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{ 22, 2 }, /* size: in most AdvSIMD and floating-point instructions. */
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{ 22, 1 }, /* sz: 1-bit element size select. */
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{ 10, 2 }, /* CRm_dsb_nxs: 2-bit imm. encoded in CRm<3:2>. */
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{ 10, 8 }, /* CSSC_imm8. */
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{ 22, 2 }, /* type: floating point type field in fp data inst. */
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{ 10, 2 }, /* vldst_size: size field in the AdvSIMD load/store inst. */
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};
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enum aarch64_operand_class
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@ -25,78 +25,41 @@
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#include "opcode/aarch64.h"
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/* Instruction fields.
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Keep synced with fields. */
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Keep this sorted alphanumerically and synced with the fields array
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in aarch64-opc.c. */
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enum aarch64_field_kind
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{
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FLD_NIL,
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FLD_cond2,
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FLD_nzcv,
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FLD_defgh,
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FLD_abc,
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FLD_imm19,
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FLD_immhi,
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FLD_immlo,
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FLD_size,
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FLD_vldst_size,
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FLD_op,
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FLD_Q,
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FLD_Rt,
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FLD_Rd,
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FLD_Rn,
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FLD_Rt2,
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FLD_Ra,
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FLD_op2,
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FLD_CRm,
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FLD_CRm_dsb_nxs,
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FLD_CRn,
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FLD_op1,
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FLD_op0,
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FLD_imm3,
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FLD_cond,
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FLD_opcode,
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FLD_cmode,
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FLD_asisdlso_opcode,
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FLD_len,
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FLD_Rm,
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FLD_Rs,
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FLD_option,
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FLD_S,
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FLD_hw,
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FLD_opc,
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FLD_opc1,
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FLD_shift,
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FLD_type,
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FLD_ldst_size,
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FLD_imm6_10,
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FLD_imm6_15,
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FLD_imm4_11,
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FLD_imm4_0,
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FLD_imm4_10,
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FLD_imm4_5,
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FLD_imm5,
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FLD_imm7,
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FLD_imm8,
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FLD_imm9,
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FLD_imm12,
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FLD_imm14,
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FLD_imm16_5,
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FLD_imm16_0,
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FLD_imm26,
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FLD_imms,
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FLD_immr,
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FLD_immb,
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FLD_immh,
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FLD_S_imm10,
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FLD_N,
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FLD_index,
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FLD_index2,
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FLD_sf,
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FLD_lse_sz,
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FLD_CSSC_imm8,
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FLD_H,
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FLD_L,
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FLD_M,
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FLD_b5,
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FLD_b40,
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FLD_scale,
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FLD_N,
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FLD_Q,
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FLD_Ra,
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FLD_Rd,
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FLD_Rm,
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FLD_Rn,
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FLD_Rs,
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FLD_Rt,
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FLD_Rt2,
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FLD_S,
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FLD_SM3_imm2,
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FLD_SME_Pm,
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FLD_SME_Q,
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FLD_SME_Rm,
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FLD_SME_Rv,
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FLD_SME_V,
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FLD_SME_ZAda_2b,
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FLD_SME_ZAda_3b,
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FLD_SME_i1,
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FLD_SME_size_22,
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FLD_SME_tszh,
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FLD_SME_tszl,
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FLD_SME_zero_mask,
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FLD_SVE_M_4,
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FLD_SVE_M_14,
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FLD_SVE_M_16,
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@ -122,10 +85,10 @@ enum aarch64_field_kind
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FLD_SVE_Zn,
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FLD_SVE_Zt,
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FLD_SVE_i1,
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FLD_SVE_i3h,
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FLD_SVE_i3l,
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FLD_SVE_i3h2,
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FLD_SVE_i2h,
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FLD_SVE_i3h,
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FLD_SVE_i3h2,
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FLD_SVE_i3l,
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FLD_SVE_imm3,
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FLD_SVE_imm4,
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FLD_SVE_imm5,
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@ -142,8 +105,8 @@ enum aarch64_field_kind
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FLD_SVE_rot1,
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FLD_SVE_rot2,
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FLD_SVE_rot3,
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FLD_SVE_sz,
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FLD_SVE_size,
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FLD_SVE_sz,
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FLD_SVE_sz2,
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FLD_SVE_tsz,
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FLD_SVE_tszh,
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@ -151,25 +114,63 @@ enum aarch64_field_kind
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FLD_SVE_tszl_19,
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FLD_SVE_xs_14,
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FLD_SVE_xs_22,
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FLD_SME_ZAda_2b,
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FLD_SME_ZAda_3b,
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FLD_SME_size_22,
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FLD_SME_Q,
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FLD_SME_V,
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FLD_SME_Rv,
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FLD_SME_Pm,
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FLD_SME_zero_mask,
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FLD_SME_Rm,
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FLD_SME_i1,
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FLD_SME_tszh,
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||||
FLD_SME_tszl,
|
||||
FLD_S_imm10,
|
||||
FLD_abc,
|
||||
FLD_asisdlso_opcode,
|
||||
FLD_b40,
|
||||
FLD_b5,
|
||||
FLD_cmode,
|
||||
FLD_cond,
|
||||
FLD_cond2,
|
||||
FLD_defgh,
|
||||
FLD_hw,
|
||||
FLD_imm3,
|
||||
FLD_imm4_0,
|
||||
FLD_imm4_5,
|
||||
FLD_imm4_10,
|
||||
FLD_imm4_11,
|
||||
FLD_imm5,
|
||||
FLD_imm6_10,
|
||||
FLD_imm6_15,
|
||||
FLD_imm7,
|
||||
FLD_imm8,
|
||||
FLD_imm9,
|
||||
FLD_imm12,
|
||||
FLD_imm14,
|
||||
FLD_imm16_0,
|
||||
FLD_imm16_5,
|
||||
FLD_imm19,
|
||||
FLD_imm26,
|
||||
FLD_immb,
|
||||
FLD_immh,
|
||||
FLD_immhi,
|
||||
FLD_immlo,
|
||||
FLD_immr,
|
||||
FLD_imms,
|
||||
FLD_index,
|
||||
FLD_index2,
|
||||
FLD_ldst_size,
|
||||
FLD_len,
|
||||
FLD_lse_sz,
|
||||
FLD_nzcv,
|
||||
FLD_op,
|
||||
FLD_op0,
|
||||
FLD_op1,
|
||||
FLD_op2,
|
||||
FLD_opc,
|
||||
FLD_opc1,
|
||||
FLD_opcode,
|
||||
FLD_option,
|
||||
FLD_rotate1,
|
||||
FLD_rotate2,
|
||||
FLD_rotate3,
|
||||
FLD_SM3_imm2,
|
||||
FLD_scale,
|
||||
FLD_sf,
|
||||
FLD_shift,
|
||||
FLD_size,
|
||||
FLD_sz,
|
||||
FLD_CRm_dsb_nxs,
|
||||
FLD_CSSC_imm8
|
||||
FLD_type,
|
||||
FLD_vldst_size,
|
||||
};
|
||||
|
||||
/* Field description. */
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user