RISC-V: Support Zicond extension

This implements the Zicond (conditional integer operations) extension,
    as of version 1.0-rc2.

    The Zicond extension acts as a building block for branchless sequences
    including conditional-arithmetic, conditional-logic and
    conditional-select/move.
    The following instructions constitute Zicond:
      - czero.eqz rd, rs1, rs2  =>  rd = (rs2 == 0) ? 0 : rs1
      - czero.nez rd, rs1, rs2  =>  rd = (rs2 != 0) ? 0 : rs1

    See
      https://github.com/riscv/riscv-zicond/releases/download/v1.0-rc2/riscv-zicond-v1.0-rc2.pdf
    for the proposed specification and usage details.

    bfd/ChangeLog:

            * elfxx-riscv.c (riscv_multi_subset_supports): Recognize
            INSN_CLASS_ZICOND.
            (riscv_multi_subset_supports_ext): Recognize INSN_CLASS_ZICOND.

    gas/ChangeLog:

            * testsuite/gas/riscv/zicond.d: New test.
            * testsuite/gas/riscv/zicond.s: New test.

    include/ChangeLog:

            * opcode/riscv-opc.h (MATCH_CZERO_EQZ): Define.
            (MASK_CZERO_EQZ): Define.
            (MATCH_CZERO_NEZ): Define,
            (MASK_CZERO_NEZ): Define.
            (DECLARE_INSN): Add czero.eqz and czero.nez.
            * opcode/riscv.h (enum riscv_insn_class): Add
            INSN_CLASS_ZICOND.

    opcodes/ChangeLog:

            * riscv-opc.c: Add czero.eqz and czero.nez.

    Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>

include/opcode/riscv-opc.h

@@ -2113,6 +2113,11 @@
 #define MASK_CBO_INVAL 0xfff07fff
 #define MATCH_CBO_ZERO 0x40200f
 #define MASK_CBO_ZERO 0xfff07fff
+/* Zicond instructions. */
+#define MATCH_CZERO_EQZ 0xe005033
+#define MASK_CZERO_EQZ 0xfe00707f
+#define MATCH_CZERO_NEZ 0xe007033
+#define MASK_CZERO_NEZ 0xfe00707f
 /* Zawrs intructions.  */
 #define MATCH_WRS_NTO 0x00d00073
 #define MASK_WRS_NTO 0xffffffff
@@ -3120,6 +3125,9 @@ DECLARE_INSN(cbo_clean, MATCH_CBO_CLEAN, MASK_CBO_CLEAN);
 DECLARE_INSN(cbo_flush, MATCH_CBO_FLUSH, MASK_CBO_FLUSH);
 DECLARE_INSN(cbo_inval, MATCH_CBO_INVAL, MASK_CBO_INVAL);
 DECLARE_INSN(cbo_zero, MATCH_CBO_ZERO, MASK_CBO_ZERO);
+/* Zicond instructions. */
+DECLARE_INSN(czero_eqz, MATCH_CZERO_EQZ, MASK_CZERO_EQZ)
+DECLARE_INSN(czero_nez, MATCH_CZERO_NEZ, MASK_CZERO_NEZ)
 /* Zawrs instructions.  */
 DECLARE_INSN(wrs_nto, MATCH_WRS_NTO, MASK_WRS_NTO)
 DECLARE_INSN(wrs_sto, MATCH_WRS_STO, MASK_WRS_STO)

include/opcode/riscv.h

@@ -375,6 +375,7 @@ enum riscv_insn_class
   INSN_CLASS_Q,
   INSN_CLASS_F_AND_C,
   INSN_CLASS_D_AND_C,
+  INSN_CLASS_ZICOND,
   INSN_CLASS_ZICSR,
   INSN_CLASS_ZIFENCEI,
   INSN_CLASS_ZIHINTPAUSE,