Split the ARM Crypto ISA extensions for AES and SHA1+2 into their own options (+aes and +sha2). The reason for the split is because with the introduction of Armv8.4-a the implementation of AES has explicitly been made independent of the implementation of the other crypto extensions.
gas * config/tc-aarch64.c (aarch64_arch_option_table): Add armv8.4-a. (aarch64_features): Added SM4 and SHA3. include * opcode/aarch64.h: (AARCH64_FEATURE_V8_4, AARCH64_FEATURE_SM4): New. (AARCH64_ARCH_V8_4, AARCH64_FEATURE_SHA3): New. opcodes * aarch64-tbl.h (aarch64_feature_v8_4, aarch64_feature_crypto_v8_2): New. (aarch64_feature_sm4, aarch64_feature_sha3): New. (aarch64_feature_fp_16_v8_2): New. (ARMV8_4, SHA3, SM4, CRYPTO_V8_2, FP_F16_V8_2): New. (V8_4_INSN, CRYPTO_V8_2_INSN): New. (SHA3_INSN, SM4_INSN, FP16_V8_2_INSN): New.
This commit is contained in:
Tamar Christina
Nick Clifton
parent
21b81e67c7
commit
b6b9ca0c3e
@ -1,3 +1,8 @@
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2017-11-09 Tamar Christina <tamar.christina@arm.com>
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* config/tc-aarch64.c (aarch64_arch_option_table): Add armv8.4-a.
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(aarch64_features): Add SM4 and SHA3.
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2017-11-08 Tamar Christina <tamar.christina@arm.com>
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* config/tc-aarch64.c
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@ -8455,6 +8455,7 @@ static const struct aarch64_arch_option_table aarch64_archs[] = {
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{"armv8.1-a", AARCH64_ARCH_V8_1},
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{"armv8.2-a", AARCH64_ARCH_V8_2},
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{"armv8.3-a", AARCH64_ARCH_V8_3},
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{"armv8.4-a", AARCH64_ARCH_V8_4},
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{NULL, AARCH64_ARCH_NONE}
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};
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@ -8506,6 +8507,11 @@ static const struct aarch64_option_cpu_value_table aarch64_features[] = {
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AARCH64_ARCH_NONE},
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{"aes", AARCH64_FEATURE (AARCH64_FEATURE_AES, 0),
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AARCH64_ARCH_NONE},
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{"sm4", AARCH64_FEATURE (AARCH64_FEATURE_SM4, 0),
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AARCH64_ARCH_NONE},
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{"sha3", AARCH64_FEATURE (AARCH64_FEATURE_SHA2
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| AARCH64_FEATURE_SHA3, 0),
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AARCH64_ARCH_NONE},
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{NULL, AARCH64_ARCH_NONE, AARCH64_ARCH_NONE},
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};
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@ -1,3 +1,9 @@
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2017-11-09 Tamar Christina <tamar.christina@arm.com>
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* opcode/aarch64.h:
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(AARCH64_FEATURE_V8_4, AARCH64_FEATURE_SM4): New.
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(AARCH64_ARCH_V8_4, AARCH64_FEATURE_SHA3): New.
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2017-11-09 Nick Clifton <nickc@redhat.com>
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* opcode/aarch64.h (aarch64_feature_set): Change type to unsigned
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@ -39,6 +39,9 @@ typedef uint32_t aarch64_insn;
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/* The following bitmasks control CPU features. */
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#define AARCH64_FEATURE_SHA2 0x200000000ULL /* SHA2 instructions. */
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#define AARCH64_FEATURE_AES 0x800000000ULL /* AES instructions. */
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#define AARCH64_FEATURE_V8_4 0x000000800ULL /* ARMv8.4 processors. */
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#define AARCH64_FEATURE_SM4 0x100000000ULL /* SM3 & SM4 instructions. */
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#define AARCH64_FEATURE_SHA3 0x400000000ULL /* SHA3 instructions. */
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#define AARCH64_FEATURE_V8 0x00000001 /* All processors. */
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#define AARCH64_FEATURE_V8_2 0x00000020 /* ARMv8.2 processors. */
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#define AARCH64_FEATURE_V8_3 0x00000040 /* ARMv8.3 processors. */
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@ -77,6 +80,8 @@ typedef uint32_t aarch64_insn;
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AARCH64_FEATURE_V8_3 \
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| AARCH64_FEATURE_RCPC \
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| AARCH64_FEATURE_COMPNUM)
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#define AARCH64_ARCH_V8_4 AARCH64_FEATURE (AARCH64_ARCH_V8_3, \
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AARCH64_FEATURE_V8_4)
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#define AARCH64_ARCH_NONE AARCH64_FEATURE (0, 0)
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#define AARCH64_ANY AARCH64_FEATURE (-1, 0) /* Any basic core. */
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@ -1,3 +1,13 @@
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2017-11-09 Tamar Christina <tamar.christina@arm.com>
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* aarch64-tbl.h
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(aarch64_feature_v8_4, aarch64_feature_crypto_v8_2): New.
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(aarch64_feature_sm4, aarch64_feature_sha3): New.
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(aarch64_feature_fp_16_v8_2): New.
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(ARMV8_4, SHA3, SM4, CRYPTO_V8_2, FP_F16_V8_2): New.
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(V8_4_INSN, CRYPTO_V8_2_INSN): New.
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(SHA3_INSN, SM4_INSN, FP16_V8_2_INSN): New.
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2017-11-08 Tamar Christina <tamar.christina@arm.com>
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* aarch64-tbl.h (aarch64_feature_crypto): Add AES and SHA2.
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@ -2041,6 +2041,18 @@ static const aarch64_feature_set aarch64_feature_sha2 =
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AARCH64_FEATURE (AARCH64_FEATURE_V8 | AARCH64_FEATURE_SHA2, 0);
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static const aarch64_feature_set aarch64_feature_aes =
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AARCH64_FEATURE (AARCH64_FEATURE_V8 | AARCH64_FEATURE_AES, 0);
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static const aarch64_feature_set aarch64_feature_v8_4 =
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AARCH64_FEATURE (AARCH64_FEATURE_V8_4, 0);
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static const aarch64_feature_set aarch64_feature_crypto_v8_2 =
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AARCH64_FEATURE (AARCH64_FEATURE_V8_2 | AARCH64_FEATURE_CRYPTO, 0);
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static const aarch64_feature_set aarch64_feature_sm4 =
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AARCH64_FEATURE (AARCH64_FEATURE_V8_2 | AARCH64_FEATURE_SM4, 0);
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static const aarch64_feature_set aarch64_feature_sha3 =
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AARCH64_FEATURE (AARCH64_FEATURE_V8_2 | AARCH64_FEATURE_SHA2
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| AARCH64_FEATURE_SHA3, 0);
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static const aarch64_feature_set aarch64_feature_fp_16_v8_2 =
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AARCH64_FEATURE (AARCH64_FEATURE_V8_2 | AARCH64_FEATURE_F16
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| AARCH64_FEATURE_FP, 0);
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#define CORE &aarch64_feature_v8
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#define FP &aarch64_feature_fp
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@ -2062,6 +2074,11 @@ static const aarch64_feature_set aarch64_feature_aes =
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#define RCPC &aarch64_feature_rcpc
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#define SHA2 &aarch64_feature_sha2
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#define AES &aarch64_feature_aes
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#define ARMV8_4 &aarch64_feature_v8_4
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#define SHA3 &aarch64_feature_sha3
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#define SM4 &aarch64_feature_sm4
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#define CRYPTO_V8_2 &aarch64_feature_crypto_v8_2
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#define FP_F16_V8_2 &aarch64_feature_fp_16_v8_2
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#define DOTPROD &aarch64_feature_dotprod
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#define CORE_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS) \
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@ -2099,6 +2116,16 @@ static const aarch64_feature_set aarch64_feature_aes =
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{ NAME, OPCODE, MASK, CLASS, 0, SHA2, OPS, QUALS, FLAGS, 0, NULL }
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#define AES_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \
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{ NAME, OPCODE, MASK, CLASS, 0, AES, OPS, QUALS, FLAGS, 0, NULL }
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#define V8_4_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \
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{ NAME, OPCODE, MASK, CLASS, 0, ARMV8_4, OPS, QUALS, FLAGS, 0, NULL }
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#define CRYPTO_V8_2_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \
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{ NAME, OPCODE, MASK, CLASS, 0, CRYPTO_V8_2, OPS, QUALS, FLAGS, 0, NULL }
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#define SHA3_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \
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{ NAME, OPCODE, MASK, CLASS, 0, SHA3, OPS, QUALS, FLAGS, 0, NULL }
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#define SM4_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \
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{ NAME, OPCODE, MASK, CLASS, 0, SM4, OPS, QUALS, FLAGS, 0, NULL }
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#define FP16_V8_2_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \
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{ NAME, OPCODE, MASK, CLASS, 0, FP_F16_V8_2, OPS, QUALS, FLAGS, 0, NULL }
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#define DOT_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \
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{ NAME, OPCODE, MASK, CLASS, 0, DOTPROD, OPS, QUALS, FLAGS, 0, NULL }
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