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sim/riscv: Complete tidying up with SBREAK

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This commit removes SBREAK-related references on the simulator as it's
renamed to EBREAK in 2016 (the RISC-V ISA, version 2.1).

sim/ChangeLog:

	* riscv/sim-main.c (execute_i): Use "ebreak" instead of "sbreak".
This commit is contained in:
Tsukasa OI 2022-09-04 07:45:06 +00:00 committed by Andrew Burgess
parent 06c00d5fea
commit b9593cb705
1 changed files with 3 additions and 3 deletions
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6
sim/riscv/sim-main.c
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@ -583,9 +583,9 @@ execute_i (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op)
case MATCH_FENCE_I:
TRACE_INSN (cpu, "fence.i;");
break;
case MATCH_SBREAK:
TRACE_INSN (cpu, "sbreak;");
/* GDB expects us to step over SBREAK. */
case MATCH_EBREAK:
TRACE_INSN (cpu, "ebreak;");
/* GDB expects us to step over EBREAK. */
sim_engine_halt (sd, cpu, NULL, cpu->pc + 4, sim_stopped, SIM_SIGTRAP);
break;
case MATCH_ECALL: