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opcodes: microblaze: Add new bit-field instructions

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This patches adds new bsefi and bsifi instructions.
BSEFI- The instruction shall extract a bit field from a
register and place it right-adjusted in the destination register.
The other bits in the destination register shall be set to zero.
BSIFI- The instruction shall insert a right-adjusted bit field
from a register at another position in the destination register.
The rest of the bits in the destination register shall be unchanged.

Further documentation of these instructions can be found here:
https://docs.xilinx.com/v/u/en-US/ug984-vivado-microblaze-ref

With version 6 of the patch, no new relocation types are added as
this was unnecessary for adding the bsefi and bsifi instructions.

FIXED: Segfault caused by incorrect termination of microblaze_opcodes.

Signed-off-by: nagaraju <nagaraju.mekala@amd.com>
Signed-off-by: Ibai Erkiaga <ibai.erkiaga-elorza@amd.com>
Signed-off-by: Neal Frager <neal.frager@amd.com>
Signed-off-by: Michael J. Eager <eager@eagercon.com>
This commit is contained in:
Neal Frager 2023-10-13 08:28:55 +01:00 committed by Michael J. Eager
parent 30ebc4310b
commit bb0d05ff74
4 changed files with 121 additions and 4 deletions
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83
gas/config/tc-microblaze.c
View File

@ -915,7 +915,7 @@ md_assemble (char * str)
unsigned reg2;
unsigned reg3;
unsigned isize;
unsigned int immed = 0, temp;
unsigned int immed = 0, immed2 = 0, temp;
expressionS exp;
char name[20];
@ -1177,6 +1177,87 @@ md_assemble (char * str)
inst |= (immed << IMM_LOW) & IMM5_MASK;
break;
case INST_TYPE_RD_R1_IMMW_IMMS:
if (strcmp (op_end, ""))
op_end = parse_reg (op_end + 1, &reg1); /* Get rd. */
else
{
as_fatal (_("Error in statement syntax"));
reg1 = 0;
}
if (strcmp (op_end, ""))
op_end = parse_reg (op_end + 1, &reg2); /* Get r1. */
else
{
as_fatal (_("Error in statement syntax"));
reg2 = 0;
}
/* Check for spl registers. */
if (check_spl_reg (&reg1))
as_fatal (_("Cannot use special register with this instruction"));
if (check_spl_reg (&reg2))
as_fatal (_("Cannot use special register with this instruction"));
/* Width immediate value. */
if (strcmp (op_end, ""))
op_end = parse_imm (op_end + 1, &exp, MIN_IMM_WIDTH, MAX_IMM_WIDTH);
else
as_fatal (_("Error in statement syntax"));
if (exp.X_op != O_constant)
{
as_warn (_(
"Symbol used as immediate width value for bit field instruction"));
immed = 1;
}
else
immed = exp.X_add_number;
if (opcode->instr == bsefi && immed > 31)
as_fatal (_("Width value must be less than 32"));
/* Shift immediate value. */
if (strcmp (op_end, ""))
op_end = parse_imm (op_end + 1, &exp, MIN_IMM, MAX_IMM);
else
as_fatal (_("Error in statement syntax"));
if (exp.X_op != O_constant)
{
as_warn (_(
"Symbol used as immediate shift value for bit field instruction"));
immed2 = 0;
}
else
{
output = frag_more (isize);
immed2 = exp.X_add_number;
}
if (immed2 != (immed2 % 32))
{
as_warn (_("Shift value greater than 32. using <value %% 32>"));
immed2 = immed2 % 32;
}
/* Check combined value. */
if (immed + immed2 > 32)
as_fatal (_("Width value + shift value must not be greater than 32"));
inst |= (reg1 << RD_LOW) & RD_MASK;
inst |= (reg2 << RA_LOW) & RA_MASK;
if (opcode->instr == bsefi)
inst |= (immed & IMM5_MASK) << IMM_WIDTH_LOW; /* bsefi */
else
inst |= ((immed + immed2 - 1) & IMM5_MASK)
<< IMM_WIDTH_LOW; /* bsifi */
inst |= (immed2 << IMM_LOW) & IMM5_MASK;
break;
case INST_TYPE_R1_R2:
if (strcmp (op_end, ""))
op_end = parse_reg (op_end + 1, &reg1); /* Get r1. */

23
opcodes/microblaze-dis.c
View File

@ -90,6 +90,21 @@ get_field_imm5_mbar (struct string_buf *buf, long instr)
return p;
}
static char *
get_field_immw (struct string_buf *buf, long instr)
{
char *p = strbuf (buf);
if (instr & 0x00004000)
sprintf (p, "%d", (short)(((instr & IMM5_WIDTH_MASK)
>> IMM_WIDTH_LOW))); /* bsefi */
else
sprintf (p, "%d", (short)(((instr & IMM5_WIDTH_MASK) >>
IMM_WIDTH_LOW) - ((instr & IMM5_MASK) >>
IMM_LOW) + 1)); /* bsifi */
return p;
}
static char *
get_field_rfsl (struct string_buf *buf, long instr)
{
@ -427,6 +442,14 @@ print_insn_microblaze (bfd_vma memaddr, struct disassemble_info * info)
/* For mbar 16 or sleep insn. */
case INST_TYPE_NONE:
break;
/* For bit field insns. */
case INST_TYPE_RD_R1_IMMW_IMMS:
print_func (stream, "\t%s, %s, %s, %s",
get_field_rd (&buf, inst),
get_field_r1 (&buf, inst),
get_field_immw (&buf, inst),
get_field_imm5 (&buf, inst));
break;
/* For tuqula instruction */
case INST_TYPE_RD:
print_func (stream, "\t%s", get_field_rd (&buf, inst));

13
opcodes/microblaze-opc.h
View File

@ -59,6 +59,9 @@
/* For mbar. */
#define INST_TYPE_IMM5 20
/* For bsefi and bsifi */
#define INST_TYPE_RD_R1_IMMW_IMMS 21
#define INST_TYPE_NONE 25
@ -90,6 +93,7 @@
#define OPCODE_MASK_H1234 0xFFFFFFFF /* All 32 bits. */
#define OPCODE_MASK_H3 0xFC000600 /* High 6 bits and bits 21, 22. */
#define OPCODE_MASK_H32 0xFC00FC00 /* High 6 bits and bit 16-21. */
#define OPCODE_MASK_H32B 0xFC00C000 /* High 6 bits and bit 16, 17. */
#define OPCODE_MASK_H34B 0xFC0000FF /* High 6 bits and low 8 bits. */
#define OPCODE_MASK_H35B 0xFC0004FF /* High 6 bits and low 9 bits. */
#define OPCODE_MASK_H34C 0xFC0007E0 /* High 6 bits and bits 21-26. */
@ -102,7 +106,7 @@
#define DELAY_SLOT 1
#define NO_DELAY_SLOT 0
#define MAX_OPCODES 300
#define MAX_OPCODES 291
const struct op_code_struct
{
@ -159,6 +163,8 @@ const struct op_code_struct
{"bslli", INST_TYPE_RD_R1_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64000400, OPCODE_MASK_H3, bslli, barrel_shift_inst },
{"bsrai", INST_TYPE_RD_R1_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64000200, OPCODE_MASK_H3, bsrai, barrel_shift_inst },
{"bsrli", INST_TYPE_RD_R1_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64000000, OPCODE_MASK_H3, bsrli, barrel_shift_inst },
{"bsefi", INST_TYPE_RD_R1_IMMW_IMMS, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64004000, OPCODE_MASK_H32B, bsefi, barrel_shift_inst },
{"bsifi", INST_TYPE_RD_R1_IMMW_IMMS, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64008000, OPCODE_MASK_H32B, bsifi, barrel_shift_inst },
{"or", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x80000000, OPCODE_MASK_H4, microblaze_or, logical_inst },
{"and", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x84000000, OPCODE_MASK_H4, microblaze_and, logical_inst },
{"xor", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x88000000, OPCODE_MASK_H4, microblaze_xor, logical_inst },
@ -418,7 +424,7 @@ const struct op_code_struct
{"suspend", INST_TYPE_NONE, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBB020004, OPCODE_MASK_HN, invalid_inst, special_inst }, /* translates to mbar 24. */
{"swapb", INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x900001E0, OPCODE_MASK_H4, swapb, arithmetic_inst },
{"swaph", INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x900001E2, OPCODE_MASK_H4, swaph, arithmetic_inst },
{"", 0, 0, 0, 0, 0, 0, 0, 0},
{NULL, 0, 0, 0, 0, 0, 0, 0, 0},
};
/* Prefix for register names. */
@ -438,5 +444,8 @@ char pvr_register_prefix[] = "rpvr";
#define MIN_IMM5 ((int) 0x00000000)
#define MAX_IMM5 ((int) 0x0000001f)
#define MIN_IMM_WIDTH ((int) 0x00000001)
#define MAX_IMM_WIDTH ((int) 0x00000020)
#endif /* MICROBLAZE_OPC */

6
opcodes/microblaze-opcm.h
View File

@ -29,7 +29,7 @@ enum microblaze_instr
addi, rsubi, addic, rsubic, addik, rsubik, addikc, rsubikc, mul,
mulh, mulhu, mulhsu, swapb, swaph,
idiv, idivu, bsll, bsra, bsrl, get, put, nget, nput, cget, cput,
ncget, ncput, muli, bslli, bsrai, bsrli, mului,
ncget, ncput, muli, bslli, bsrai, bsrli, bsefi, bsifi, mului,
/* 'or/and/xor' are C++ keywords. */
microblaze_or, microblaze_and, microblaze_xor,
andn, pcmpbf, pcmpbc, pcmpeq, pcmpne, sra, src, srl, sext8, sext16,
@ -130,6 +130,7 @@ enum microblaze_instr_type
#define RB_LOW 11 /* Low bit for RB. */
#define IMM_LOW 0 /* Low bit for immediate. */
#define IMM_MBAR 21 /* low bit for mbar instruction. */
#define IMM_WIDTH_LOW 6 /* Low bit for immediate width */
#define RD_MASK 0x03E00000
#define RA_MASK 0x001F0000
@ -142,6 +143,9 @@ enum microblaze_instr_type
/* Imm mask for mbar. */
#define IMM5_MBAR_MASK 0x03E00000
/* Imm mask for extract/insert width. */
#define IMM5_WIDTH_MASK 0x000007C0
/* FSL imm mask for get, put instructions. */
#define RFSL_MASK 0x000000F