[bfd]
* elf32-h8300.c (elf32_h8_relax_section): Relax MOVA opcodes. [gas] * tc-h8300.c (do_a_fix_imm): Pass the insn, force relocs for MOVA immediates. (build_bytes): Pass insn to do_a_fix_imm. [include/opcode] * h8300.h: Add relaxation attributes to MOVA opcodes.
This commit is contained in:
DJ Delorie
parent
6ce340f181
commit
bcb012d3f5
@ -1,3 +1,7 @@
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2009-04-06 DJ Delorie <dj@redhat.com>
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* elf32-h8300.c (elf32_h8_relax_section): Relax MOVA opcodes.
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2009-04-06 H.J. Lu <hongjiu.lu@intel.com>
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* coff-x86_64.c (bfd_pe_print_pdata): Defined to
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@ -722,6 +722,13 @@ elf32_h8_relax_section (bfd *abfd, asection *sec,
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{
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bfd_vma symval;
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{
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arelent bfd_reloc;
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reloc_howto_type *h;
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elf32_h8_info_to_howto (abfd, &bfd_reloc, irel);
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h = bfd_reloc.howto;
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}
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/* Keep track of the previous reloc so that we can delete
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some long jumps created by the compiler. */
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if (irel != internal_relocs)
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@ -994,7 +1001,8 @@ elf32_h8_relax_section (bfd *abfd, asection *sec,
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/* This is bsr. */
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bfd_put_8 (abfd, 0x55, contents + irel->r_offset - 2);
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else
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abort ();
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/* Might be MOVSD. */
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break;
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/* Fix the relocation's type. */
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irel->r_info = ELF32_R_INFO (ELF32_R_SYM (irel->r_info),
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@ -1207,6 +1215,8 @@ elf32_h8_relax_section (bfd *abfd, asection *sec,
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if (value <= 0x7fff || value >= 0xffff8000u)
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{
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unsigned char code;
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unsigned char op0, op1, op2, op3;
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unsigned char *op_ptr;
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/* Note that we've changed the relocs, section contents,
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etc. */
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@ -1214,6 +1224,87 @@ elf32_h8_relax_section (bfd *abfd, asection *sec,
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elf_section_data (sec)->this_hdr.contents = contents;
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symtab_hdr->contents = (unsigned char *) isymbuf;
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if (irel->r_offset >= 4)
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{
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/* Check for 4-byte MOVA relaxation. */
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int second_reloc = 0;
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op_ptr = contents + irel->r_offset - 4;
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if (last_reloc)
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{
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arelent bfd_reloc;
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reloc_howto_type *h;
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bfd_vma last_reloc_size;
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elf32_h8_info_to_howto (abfd, &bfd_reloc, last_reloc);
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h = bfd_reloc.howto;
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last_reloc_size = 1 << h->size;
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if (last_reloc->r_offset + last_reloc_size
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== irel->r_offset)
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{
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op_ptr -= last_reloc_size;
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second_reloc = 1;
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}
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}
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if (irel < irelend)
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{
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Elf_Internal_Rela *next_reloc = irel + 1;
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arelent bfd_reloc;
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reloc_howto_type *h;
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bfd_vma next_reloc_size;
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elf32_h8_info_to_howto (abfd, &bfd_reloc, next_reloc);
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h = bfd_reloc.howto;
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next_reloc_size = 1 << h->size;
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if (next_reloc->r_offset + next_reloc_size
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== irel->r_offset)
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{
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op_ptr -= next_reloc_size;
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second_reloc = 1;
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}
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}
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op0 = bfd_get_8 (abfd, op_ptr + 0);
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op1 = bfd_get_8 (abfd, op_ptr + 1);
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op2 = bfd_get_8 (abfd, op_ptr + 2);
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op3 = bfd_get_8 (abfd, op_ptr + 3);
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if (op0 == 0x01
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&& (op1 & 0xdf) == 0x5f
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&& (op2 & 0x40) == 0x40
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&& (op3 & 0x80) == 0x80)
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{
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if ((op2 & 0x08) == 0)
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second_reloc = 1;
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if (second_reloc)
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{
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op3 &= ~0x08;
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bfd_put_8 (abfd, op3, op_ptr + 3);
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}
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else
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{
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op2 &= ~0x08;
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bfd_put_8 (abfd, op2, op_ptr + 2);
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}
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goto r_h8_dir32a16_common;
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}
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}
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/* Now check for short version of MOVA. */
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op_ptr = contents + irel->r_offset - 2;
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op0 = bfd_get_8 (abfd, op_ptr + 0);
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op1 = bfd_get_8 (abfd, op_ptr + 1);
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if (op0 == 0x7a
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&& (op1 & 0x88) == 0x80)
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{
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op1 |= 0x08;
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bfd_put_8 (abfd, op1, op_ptr + 1);
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goto r_h8_dir32a16_common;
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}
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/* Get the opcode. */
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code = bfd_get_8 (abfd, contents + irel->r_offset - 1);
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@ -1224,6 +1315,7 @@ elf32_h8_relax_section (bfd *abfd, asection *sec,
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bfd_put_8 (abfd, code, contents + irel->r_offset - 1);
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r_h8_dir32a16_common:
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/* Fix the relocation's type. */
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irel->r_info = ELF32_R_INFO (ELF32_R_SYM (irel->r_info),
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R_H8_DIR16);
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@ -1,3 +1,9 @@
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2009-04-06 DJ Delorie <dj@redhat.com>
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* tc-h8300.c (do_a_fix_imm): Pass the insn, force relocs for MOVA
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immediates.
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(build_bytes): Pass insn to do_a_fix_imm.
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2009-04-02 Daniel Gutson <dgutson@codesourcery.com>
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* config/tc-arm.c (arm_cpus): Add entry for ARM Cortex-M0.
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@ -299,7 +299,7 @@ struct h8_op
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static void clever_message (const struct h8_instruction *, struct h8_op *);
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static void fix_operand_size (struct h8_op *, int);
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static void build_bytes (const struct h8_instruction *, struct h8_op *);
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static void do_a_fix_imm (int, int, struct h8_op *, int);
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static void do_a_fix_imm (int, int, struct h8_op *, int, const struct h8_instruction *);
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static void check_operand (struct h8_op *, unsigned int, char *);
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static const struct h8_instruction * get_specific (const struct h8_instruction *, struct h8_op *, int) ;
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static char *get_operands (unsigned, char *, struct h8_op *);
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@ -1273,7 +1273,7 @@ check_operand (struct h8_op *operand, unsigned int width, char *string)
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(may relax into an 8bit absolute address). */
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static void
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do_a_fix_imm (int offset, int nibble, struct h8_op *operand, int relaxmode)
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do_a_fix_imm (int offset, int nibble, struct h8_op *operand, int relaxmode, const struct h8_instruction *this_try)
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{
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int idx;
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int size;
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@ -1313,6 +1313,17 @@ do_a_fix_imm (int offset, int nibble, struct h8_op *operand, int relaxmode)
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check_operand (operand, 0xffff, t);
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bytes[0] |= operand->exp.X_add_number >> 8;
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bytes[1] |= operand->exp.X_add_number >> 0;
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#ifdef OBJ_ELF
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/* MOVA needs both relocs to relax the second operand properly. */
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if (relaxmode != 0
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&& (OP_KIND(this_try->opcode->how) == O_MOVAB
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|| OP_KIND(this_try->opcode->how) == O_MOVAW
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|| OP_KIND(this_try->opcode->how) == O_MOVAL))
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{
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idx = BFD_RELOC_16;
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fix_new_exp (frag_now, offset, 2, &operand->exp, 0, idx);
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}
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#endif
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break;
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case L_24:
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check_operand (operand, 0xffffff, t);
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@ -1576,12 +1587,14 @@ build_bytes (const struct h8_instruction *this_try, struct h8_op *operand)
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if (x_mode == IMM || x_mode == DISP)
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do_a_fix_imm (output - frag_now->fr_literal + op_at[i] / 2,
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op_at[i] & 1, operand + i, (x & MEMRELAX) != 0);
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op_at[i] & 1, operand + i, (x & MEMRELAX) != 0,
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this_try);
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else if (x_mode == ABS)
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do_a_fix_imm (output - frag_now->fr_literal + op_at[i] / 2,
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op_at[i] & 1, operand + i,
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(x & MEMRELAX) ? movb + 1 : 0);
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(x & MEMRELAX) ? movb + 1 : 0,
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this_try);
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else if (x_mode == PCREL)
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{
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@ -1,3 +1,7 @@
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2009-04-06 DJ Delorie <dj@redhat.com>
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* h8300.h: Add relaxation attributes to MOVA opcodes.
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2009-03-10 Alan Modra <amodra@bigpond.net.au>
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* ppc.h (ppc_parse_cpu): Declare.
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@ -1565,62 +1565,62 @@ struct h8_opcode h8_opcodes[] =
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MOVFROM_AD (O (O_MOV, SL), PREFIX_0108, "mov.l", ABS32SRC, FROM_ABS32, ABS32LIST),
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#define DO_MOVA1(TYPE, OP0, OP1) \
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{O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXB16, TYPE, R3_32}}, {{PREFIX_017F, OP0, OP1, 0x8, B30 | R3_32, DISP16LIST, E}}}, \
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{O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXW16, TYPE, R3_32}}, {{PREFIX_015F, OP0, OP1, 0x9, B30 | R3_32, DISP16LIST, E}}}, \
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{O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXB16, TYPE, R3_32}}, {{PREFIX_017F, OP0, OP1, 0xA, B30 | R3_32, DISP16LIST, E}}}, \
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{O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXW16, TYPE, R3_32}}, {{PREFIX_015F, OP0, OP1, 0xB, B30 | R3_32, DISP16LIST, E}}}, \
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{O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXB16, TYPE, R3_32}}, {{PREFIX_017F, OP0, OP1, 0xC, B30 | R3_32, DISP16LIST, E}}}, \
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{O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXW16, TYPE, R3_32}}, {{PREFIX_015F, OP0, OP1, 0xD, B30 | R3_32, DISP16LIST, E}}}, \
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{O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXB16, TYPE, R3_32}}, {{PREFIX_017F, OP0, OP1, 0x8, B30 | R3_32, MEMRELAX | DISP16LIST, E}}}, \
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{O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXW16, TYPE, R3_32}}, {{PREFIX_015F, OP0, OP1, 0x9, B30 | R3_32, MEMRELAX | DISP16LIST, E}}}, \
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{O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXB16, TYPE, R3_32}}, {{PREFIX_017F, OP0, OP1, 0xA, B30 | R3_32, MEMRELAX | DISP16LIST, E}}}, \
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{O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXW16, TYPE, R3_32}}, {{PREFIX_015F, OP0, OP1, 0xB, B30 | R3_32, MEMRELAX | DISP16LIST, E}}}, \
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{O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXB16, TYPE, R3_32}}, {{PREFIX_017F, OP0, OP1, 0xC, B30 | R3_32, MEMRELAX | DISP16LIST, E}}}, \
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{O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXW16, TYPE, R3_32}}, {{PREFIX_015F, OP0, OP1, 0xD, B30 | R3_32, MEMRELAX | DISP16LIST, E}}}, \
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\
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{O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXB32, TYPE, R3_32}}, {{PREFIX_017F, OP0, OP1, 0x8, B31 | R3_32, DISP32LIST, E}}}, \
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{O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXW32, TYPE, R3_32}}, {{PREFIX_015F, OP0, OP1, 0x9, B31 | R3_32, DISP32LIST, E}}}, \
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{O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXB32, TYPE, R3_32}}, {{PREFIX_017F, OP0, OP1, 0xA, B31 | R3_32, DISP32LIST, E}}}, \
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{O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXW32, TYPE, R3_32}}, {{PREFIX_015F, OP0, OP1, 0xB, B31 | R3_32, DISP32LIST, E}}}, \
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{O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXB32, TYPE, R3_32}}, {{PREFIX_017F, OP0, OP1, 0xC, B31 | R3_32, DISP32LIST, E}}}, \
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{O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXW32, TYPE, R3_32}}, {{PREFIX_015F, OP0, OP1, 0xD, B31 | R3_32, DISP32LIST, E}}}
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{O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXB32, TYPE, R3_32}}, {{PREFIX_017F, OP0, OP1, 0x8, B31 | R3_32, MEMRELAX | DISP32LIST, E}}}, \
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{O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXW32, TYPE, R3_32}}, {{PREFIX_015F, OP0, OP1, 0x9, B31 | R3_32, MEMRELAX | DISP32LIST, E}}}, \
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{O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXB32, TYPE, R3_32}}, {{PREFIX_017F, OP0, OP1, 0xA, B31 | R3_32, MEMRELAX | DISP32LIST, E}}}, \
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{O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXW32, TYPE, R3_32}}, {{PREFIX_015F, OP0, OP1, 0xB, B31 | R3_32, MEMRELAX | DISP32LIST, E}}}, \
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{O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXB32, TYPE, R3_32}}, {{PREFIX_017F, OP0, OP1, 0xC, B31 | R3_32, MEMRELAX | DISP32LIST, E}}}, \
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{O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXW32, TYPE, R3_32}}, {{PREFIX_015F, OP0, OP1, 0xD, B31 | R3_32, MEMRELAX | DISP32LIST, E}}}
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#define DO_MOVA2(TYPE, OP0, OP1, OP2) \
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{O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXB16, TYPE, R3_32}}, {{PREFIX_017F, OP0, OP1, 0x8, B30 | R3_32, OP2, DISP16LIST, E}}}, \
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{O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXW16, TYPE, R3_32}}, {{PREFIX_015F, OP0, OP1, 0x9, B30 | R3_32, OP2, DISP16LIST, E}}}, \
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{O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXB16, TYPE, R3_32}}, {{PREFIX_017F, OP0, OP1, 0xA, B30 | R3_32, OP2, DISP16LIST, E}}}, \
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{O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXW16, TYPE, R3_32}}, {{PREFIX_015F, OP0, OP1, 0xB, B30 | R3_32, OP2, DISP16LIST, E}}}, \
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{O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXB16, TYPE, R3_32}}, {{PREFIX_017F, OP0, OP1, 0xC, B30 | R3_32, OP2, DISP16LIST, E}}}, \
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{O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXW16, TYPE, R3_32}}, {{PREFIX_015F, OP0, OP1, 0xD, B30 | R3_32, OP2, DISP16LIST, E}}}, \
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{O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXB16, TYPE, R3_32}}, {{PREFIX_017F, OP0, OP1, 0x8, B30 | R3_32, OP2, MEMRELAX | DISP16LIST, E}}}, \
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{O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXW16, TYPE, R3_32}}, {{PREFIX_015F, OP0, OP1, 0x9, B30 | R3_32, OP2, MEMRELAX | DISP16LIST, E}}}, \
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{O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXB16, TYPE, R3_32}}, {{PREFIX_017F, OP0, OP1, 0xA, B30 | R3_32, OP2, MEMRELAX | DISP16LIST, E}}}, \
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{O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXW16, TYPE, R3_32}}, {{PREFIX_015F, OP0, OP1, 0xB, B30 | R3_32, OP2, MEMRELAX | DISP16LIST, E}}}, \
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{O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXB16, TYPE, R3_32}}, {{PREFIX_017F, OP0, OP1, 0xC, B30 | R3_32, OP2, MEMRELAX | DISP16LIST, E}}}, \
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{O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXW16, TYPE, R3_32}}, {{PREFIX_015F, OP0, OP1, 0xD, B30 | R3_32, OP2, MEMRELAX | DISP16LIST, E}}}, \
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\
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{O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXB32, TYPE, R3_32}}, {{PREFIX_017F, OP0, OP1, 0x8, B31 | R3_32, OP2, DISP32LIST, E}}}, \
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{O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXW32, TYPE, R3_32}}, {{PREFIX_015F, OP0, OP1, 0x9, B31 | R3_32, OP2, DISP32LIST, E}}}, \
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{O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXB32, TYPE, R3_32}}, {{PREFIX_017F, OP0, OP1, 0xA, B31 | R3_32, OP2, DISP32LIST, E}}}, \
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{O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXW32, TYPE, R3_32}}, {{PREFIX_015F, OP0, OP1, 0xB, B31 | R3_32, OP2, DISP32LIST, E}}}, \
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{O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXB32, TYPE, R3_32}}, {{PREFIX_017F, OP0, OP1, 0xC, B31 | R3_32, OP2, DISP32LIST, E}}}, \
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{O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXW32, TYPE, R3_32}}, {{PREFIX_015F, OP0, OP1, 0xD, B31 | R3_32, OP2, DISP32LIST, E}}}
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{O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXB32, TYPE, R3_32}}, {{PREFIX_017F, OP0, OP1, 0x8, B31 | R3_32, OP2, MEMRELAX | DISP32LIST, E}}}, \
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{O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXW32, TYPE, R3_32}}, {{PREFIX_015F, OP0, OP1, 0x9, B31 | R3_32, OP2, MEMRELAX | DISP32LIST, E}}}, \
|
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{O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXB32, TYPE, R3_32}}, {{PREFIX_017F, OP0, OP1, 0xA, B31 | R3_32, OP2, MEMRELAX | DISP32LIST, E}}}, \
|
||||
{O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXW32, TYPE, R3_32}}, {{PREFIX_015F, OP0, OP1, 0xB, B31 | R3_32, OP2, MEMRELAX | DISP32LIST, E}}}, \
|
||||
{O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXB32, TYPE, R3_32}}, {{PREFIX_017F, OP0, OP1, 0xC, B31 | R3_32, OP2, MEMRELAX | DISP32LIST, E}}}, \
|
||||
{O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXW32, TYPE, R3_32}}, {{PREFIX_015F, OP0, OP1, 0xD, B31 | R3_32, OP2, MEMRELAX | DISP32LIST, E}}}
|
||||
|
||||
{O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXB16, E}}, {{0x7, 0xA, 0x8, B31 | DISPREG, DISP16LIST, E}}},
|
||||
{O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXW16, E}}, {{0x7, 0xA, 0x9, B31 | DISPREG, DISP16LIST, E}}},
|
||||
{O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXB16, E}}, {{0x7, 0xA, 0xA, B31 | DISPREG, DISP16LIST, E}}},
|
||||
{O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXW16, E}}, {{0x7, 0xA, 0xB, B31 | DISPREG, DISP16LIST, E}}},
|
||||
{O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXB16, E}}, {{0x7, 0xA, 0xC, B31 | DISPREG, DISP16LIST, E}}},
|
||||
{O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXW16, E}}, {{0x7, 0xA, 0xD, B31 | DISPREG, DISP16LIST, E}}},
|
||||
{O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXB16, E}}, {{0x7, 0xA, 0x8, B31 | DISPREG, MEMRELAX | DISP16LIST, E}}},
|
||||
{O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXW16, E}}, {{0x7, 0xA, 0x9, B31 | DISPREG, MEMRELAX | DISP16LIST, E}}},
|
||||
{O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXB16, E}}, {{0x7, 0xA, 0xA, B31 | DISPREG, MEMRELAX | DISP16LIST, E}}},
|
||||
{O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXW16, E}}, {{0x7, 0xA, 0xB, B31 | DISPREG, MEMRELAX | DISP16LIST, E}}},
|
||||
{O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXB16, E}}, {{0x7, 0xA, 0xC, B31 | DISPREG, MEMRELAX | DISP16LIST, E}}},
|
||||
{O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXW16, E}}, {{0x7, 0xA, 0xD, B31 | DISPREG, MEMRELAX | DISP16LIST, E}}},
|
||||
|
||||
{O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXB32, E}}, {{0x7, 0xA, 0x8, B30 | DISPREG, DISP32LIST, E}}},
|
||||
{O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXW32, E}}, {{0x7, 0xA, 0x9, B30 | DISPREG, DISP32LIST, E}}},
|
||||
{O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXB32, E}}, {{0x7, 0xA, 0xA, B30 | DISPREG, DISP32LIST, E}}},
|
||||
{O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXW32, E}}, {{0x7, 0xA, 0xB, B30 | DISPREG, DISP32LIST, E}}},
|
||||
{O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXB32, E}}, {{0x7, 0xA, 0xC, B30 | DISPREG, DISP32LIST, E}}},
|
||||
{O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXW32, E}}, {{0x7, 0xA, 0xD, B30 | DISPREG, DISP32LIST, E}}},
|
||||
{O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXB32, E}}, {{0x7, 0xA, 0x8, B30 | DISPREG, MEMRELAX | DISP32LIST, E}}},
|
||||
{O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXW32, E}}, {{0x7, 0xA, 0x9, B30 | DISPREG, MEMRELAX | DISP32LIST, E}}},
|
||||
{O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXB32, E}}, {{0x7, 0xA, 0xA, B30 | DISPREG, MEMRELAX | DISP32LIST, E}}},
|
||||
{O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXW32, E}}, {{0x7, 0xA, 0xB, B30 | DISPREG, MEMRELAX | DISP32LIST, E}}},
|
||||
{O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXB32, E}}, {{0x7, 0xA, 0xC, B30 | DISPREG, MEMRELAX | DISP32LIST, E}}},
|
||||
{O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXW32, E}}, {{0x7, 0xA, 0xD, B30 | DISPREG, MEMRELAX | DISP32LIST, E}}},
|
||||
|
||||
{O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXB16, RD8, R3_32}}, {{0x7, 0x8, RD8, 0x8, 0x7, 0xA, 0x8, B31 | R3_32, DISP16LIST, E}}},
|
||||
{O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXW16, RD16, R3_32}}, {{0x7, 0x8, RD16, 0x9, 0x7, 0xA, 0x9, B31 | R3_32, DISP16LIST, E}}},
|
||||
{O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXB16, RD8, R3_32}}, {{0x7, 0x8, RD8, 0x8, 0x7, 0xA, 0xA, B31 | R3_32, DISP16LIST, E}}},
|
||||
{O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXW16, RD16, R3_32}}, {{0x7, 0x8, RD16, 0x9, 0x7, 0xA, 0xB, B31 | R3_32, DISP16LIST, E}}},
|
||||
{O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXB16, RD8, R3_32}}, {{0x7, 0x8, RD8, 0x8, 0x7, 0xA, 0xC, B31 | R3_32, DISP16LIST, E}}},
|
||||
{O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXW16, RD16, R3_32}}, {{0x7, 0x8, RD16, 0x9, 0x7, 0xA, 0xD, B31 | R3_32, DISP16LIST, E}}},
|
||||
{O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXB16, RD8, R3_32}}, {{0x7, 0x8, RD8, 0x8, 0x7, 0xA, 0x8, B31 | R3_32, MEMRELAX | DISP16LIST, E}}},
|
||||
{O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXW16, RD16, R3_32}}, {{0x7, 0x8, RD16, 0x9, 0x7, 0xA, 0x9, B31 | R3_32, MEMRELAX | DISP16LIST, E}}},
|
||||
{O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXB16, RD8, R3_32}}, {{0x7, 0x8, RD8, 0x8, 0x7, 0xA, 0xA, B31 | R3_32, MEMRELAX | DISP16LIST, E}}},
|
||||
{O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXW16, RD16, R3_32}}, {{0x7, 0x8, RD16, 0x9, 0x7, 0xA, 0xB, B31 | R3_32, MEMRELAX | DISP16LIST, E}}},
|
||||
{O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXB16, RD8, R3_32}}, {{0x7, 0x8, RD8, 0x8, 0x7, 0xA, 0xC, B31 | R3_32, MEMRELAX | DISP16LIST, E}}},
|
||||
{O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXW16, RD16, R3_32}}, {{0x7, 0x8, RD16, 0x9, 0x7, 0xA, 0xD, B31 | R3_32, MEMRELAX | DISP16LIST, E}}},
|
||||
|
||||
{O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXB32, RD8, R3_32}}, {{0x7, 0x8, RD8, 0x8, 0x7, 0xA, 0x8, B30 | R3_32, DISP32LIST, E}}},
|
||||
{O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXW32, RD16, R3_32}}, {{0x7, 0x8, RD16, 0x9, 0x7, 0xA, 0x9, B30 | R3_32, DISP32LIST, E}}},
|
||||
{O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXB32, RD8, R3_32}}, {{0x7, 0x8, RD8, 0x8, 0x7, 0xA, 0xA, B30 | R3_32, DISP32LIST, E}}},
|
||||
{O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXW32, RD16, R3_32}}, {{0x7, 0x8, RD16, 0x9, 0x7, 0xA, 0xB, B30 | R3_32, DISP32LIST, E}}},
|
||||
{O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXB32, RD8, R3_32}}, {{0x7, 0x8, RD8, 0x8, 0x7, 0xA, 0xC, B30 | R3_32, DISP32LIST, E}}},
|
||||
{O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXW32, RD16, R3_32}}, {{0x7, 0x8, RD16, 0x9, 0x7, 0xA, 0xD, B30 | R3_32, DISP32LIST, E}}},
|
||||
{O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXB32, RD8, R3_32}}, {{0x7, 0x8, RD8, 0x8, 0x7, 0xA, 0x8, B30 | R3_32, MEMRELAX | DISP32LIST, E}}},
|
||||
{O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXW32, RD16, R3_32}}, {{0x7, 0x8, RD16, 0x9, 0x7, 0xA, 0x9, B30 | R3_32, MEMRELAX | DISP32LIST, E}}},
|
||||
{O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXB32, RD8, R3_32}}, {{0x7, 0x8, RD8, 0x8, 0x7, 0xA, 0xA, B30 | R3_32, MEMRELAX | DISP32LIST, E}}},
|
||||
{O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXW32, RD16, R3_32}}, {{0x7, 0x8, RD16, 0x9, 0x7, 0xA, 0xB, B30 | R3_32, MEMRELAX | DISP32LIST, E}}},
|
||||
{O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXB32, RD8, R3_32}}, {{0x7, 0x8, RD8, 0x8, 0x7, 0xA, 0xC, B30 | R3_32, MEMRELAX | DISP32LIST, E}}},
|
||||
{O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXW32, RD16, R3_32}}, {{0x7, 0x8, RD16, 0x9, 0x7, 0xA, 0xD, B30 | R3_32, MEMRELAX | DISP32LIST, E}}},
|
||||
|
||||
DO_MOVA1 (RDIND, 0x0, B30 | RDIND),
|
||||
DO_MOVA1 (RDPOSTINC, 0x8, B30 | RDPOSTINC),
|
||||
@ -1628,16 +1628,16 @@ struct h8_opcode h8_opcodes[] =
|
||||
DO_MOVA1 (RDPREINC, 0x9, B30 | RDPREINC),
|
||||
DO_MOVA1 (RDPREDEC, 0xB, B30 | RDPREDEC),
|
||||
DO_MOVA1 (DISP2DST, B30 | B20 | DISP2DST, B30 | DSTDISPREG),
|
||||
DO_MOVA2 (DISP16DST, 0xC, B30 | DSTDISPREG, DSTDISP16LIST),
|
||||
DO_MOVA2 (DISP32DST, 0xC, B31 | DSTDISPREG, DSTDISP32LIST),
|
||||
DO_MOVA2 (INDEXB16D, 0xD, B30 | DSTDISPREG, DSTDISP16LIST),
|
||||
DO_MOVA2 (INDEXW16D, 0xE, B30 | DSTDISPREG, DSTDISP16LIST),
|
||||
DO_MOVA2 (INDEXL16D, 0xF, B30 | DSTDISPREG, DSTDISP16LIST),
|
||||
DO_MOVA2 (INDEXB32D, 0xD, B31 | DSTDISPREG, DSTDISP32LIST),
|
||||
DO_MOVA2 (INDEXW32D, 0xE, B31 | DSTDISPREG, DSTDISP32LIST),
|
||||
DO_MOVA2 (INDEXL32D, 0xF, B31 | DSTDISPREG, DSTDISP32LIST),
|
||||
DO_MOVA2 (ABS16DST, 0x4, 0x0, DSTABS16LIST),
|
||||
DO_MOVA2 (ABS32DST, 0x4, 0x8, DSTABS32LIST),
|
||||
DO_MOVA2 (DISP16DST, 0xC, B30 | DSTDISPREG, MEMRELAX | DSTDISP16LIST),
|
||||
DO_MOVA2 (DISP32DST, 0xC, B31 | DSTDISPREG, MEMRELAX | DSTDISP32LIST),
|
||||
DO_MOVA2 (INDEXB16D, 0xD, B30 | DSTDISPREG, MEMRELAX | DSTDISP16LIST),
|
||||
DO_MOVA2 (INDEXW16D, 0xE, B30 | DSTDISPREG, MEMRELAX | DSTDISP16LIST),
|
||||
DO_MOVA2 (INDEXL16D, 0xF, B30 | DSTDISPREG, MEMRELAX | DSTDISP16LIST),
|
||||
DO_MOVA2 (INDEXB32D, 0xD, B31 | DSTDISPREG, MEMRELAX | DSTDISP32LIST),
|
||||
DO_MOVA2 (INDEXW32D, 0xE, B31 | DSTDISPREG, MEMRELAX | DSTDISP32LIST),
|
||||
DO_MOVA2 (INDEXL32D, 0xF, B31 | DSTDISPREG, MEMRELAX | DSTDISP32LIST),
|
||||
DO_MOVA2 (ABS16DST, 0x4, 0x0, MEMRELAX | DSTABS16LIST),
|
||||
DO_MOVA2 (ABS32DST, 0x4, 0x8, MEMRELAX | DSTABS32LIST),
|
||||
|
||||
{O (O_MOV, SB), AV_H8, 10, "movfpe", {{ABS16SRC, RD8, E}}, {{0x6, 0xA, 0x4, RD8, ABS16SRC, DATA3, E}}},
|
||||
{O (O_MOV, SB), AV_H8, 10, "movtpe", {{RS8, ABS16DST, E}}, {{0x6, 0xA, 0xC, RS8, ABS16DST, DATA3, E}}},
|
||||
|
||||
Loading…
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Reference in New Issue
Block a user