gas/
2009-01-10 H.J. Lu <hongjiu.lu@intel.com> * gas/config/tc-i386.c (cpu_arch): Add corei7, .clflush and .syscall. (i386_align_code): Handle PROCESSOR_COREI7. (md_show_usage): Add corei7, clflush and syscall. (i386_target_format): Replace cpup4 with cpuclflush. * gas/config/tc-i386.h (processor_type): Add PROCESSOR_COREI7. * doc/c-i386.texi: Document corei7, clflush and syscall. gas/testsuite/ 2009-01-10 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/arch-10.s: Add clflush and syscall. * gas/i386/x86-64-arch-2.s: Likewise. * gas/i386/arch-10.d: Updated. * gas/i386/arch-10-1.l: Likewise. * gas/i386/arch-10-2.l: Likewise. * gas/i386/arch-10-3.l: Likewise. * gas/i386/arch-10-4.l: Likewise. * gas/i386/x86-64-arch-2.d: Likewise. opcodes/ 2009-01-10 H.J. Lu <hongjiu.lu@intel.com> * i386-gen.c (cpu_flag_init): Replace CpuP4 and CpuK6 with CpuClflush and CpuSYSCALL, respectively. Remove CpuK8. Add CPU_COREI7_FLAGS, CPU_CLFLUSH_FLAGS and CPU_SYSCALL_FLAGS. (cpu_flags): Remove CpuP4, CpuK6 and CpuK8. Add CpuClflush and CpuSYSCALL. (lineno): Removed. (set_bitfield): Take an argument, lineno. Don't report lineno on error if it is -1. (process_i386_cpu_flag): Take an argument, lineno. (process_i386_opcode_modifier): Likewise. (process_i386_operand_type): Likewise. (output_i386_opcode): Likewise. (opcode_hash_entry): Add lineno. (process_i386_opcodes): Updated. (process_i386_registers): Likewise. (process_i386_initializers): Likewise. * i386-opc.h (CpuP4): Removed. (CpuK6): Likewise. (CpuK8): Likewise. (CpuClflush): New. (CpuSYSCALL): Likewise. (CpuMMX): Updated. (i386_cpu_flags): Remove cpup4, cpuk6 and cpuk8. Add cpuclflush and cpusyscall. * i386-opc.tbl: Update movnti, clflush, lfence, mfence, pause, syscall and sysret. * i386-init.h: Regenerated. * i386-tbl.h: Likewise.
This commit is contained in:
H.J. Lu
parent
38788b66ed
commit
bd5295b282
@ -1,3 +1,15 @@
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2009-01-10 H.J. Lu <hongjiu.lu@intel.com>
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* gas/config/tc-i386.c (cpu_arch): Add corei7, .clflush and
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.syscall.
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(i386_align_code): Handle PROCESSOR_COREI7.
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(md_show_usage): Add corei7, clflush and syscall.
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(i386_target_format): Replace cpup4 with cpuclflush.
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* gas/config/tc-i386.h (processor_type): Add PROCESSOR_COREI7.
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* doc/c-i386.texi: Document corei7, clflush and syscall.
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2009-01-09 H.J. Lu <hongjiu.lu@intel.com>
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* config/tc-i386.c (cpu_arch): Add .rdtscp.
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@ -600,6 +600,8 @@ static const arch_entry cpu_arch[] =
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CPU_CORE2_FLAGS },
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{ "core2", PROCESSOR_CORE2,
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CPU_CORE2_FLAGS },
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{ "corei7", PROCESSOR_COREI7,
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CPU_COREI7_FLAGS },
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{ "k6", PROCESSOR_K6,
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CPU_K6_FLAGS },
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{ "k6_2", PROCESSOR_K6,
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@ -650,6 +652,10 @@ static const arch_entry cpu_arch[] =
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CPU_MOVBE_FLAGS },
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{ ".ept", PROCESSOR_UNKNOWN,
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CPU_EPT_FLAGS },
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{ ".clflush", PROCESSOR_UNKNOWN,
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CPU_CLFLUSH_FLAGS },
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{ ".syscall", PROCESSOR_UNKNOWN,
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CPU_SYSCALL_FLAGS },
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{ ".rdtscp", PROCESSOR_UNKNOWN,
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CPU_RDTSCP_FLAGS },
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{ ".3dnow", PROCESSOR_UNKNOWN,
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@ -950,8 +956,8 @@ i386_align_code (fragS *fragP, int count)
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1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
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PROCESSOR_GENERIC32, f32_patt will be used.
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2. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA,
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PROCESSOR_CORE, PROCESSOR_CORE2, and PROCESSOR_GENERIC64,
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alt_long_patt will be used.
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PROCESSOR_CORE, PROCESSOR_CORE2, PROCESSOR_COREI7, and
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PROCESSOR_GENERIC64, alt_long_patt will be used.
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3. For PROCESSOR_ATHLON, PROCESSOR_K6, PROCESSOR_K8 and
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PROCESSOR_AMDFAM10, alt_short_patt will be used.
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@ -997,6 +1003,7 @@ i386_align_code (fragS *fragP, int count)
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case PROCESSOR_NOCONA:
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case PROCESSOR_CORE:
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case PROCESSOR_CORE2:
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case PROCESSOR_COREI7:
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case PROCESSOR_GENERIC64:
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patt = alt_long_patt;
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break;
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@ -1044,6 +1051,7 @@ i386_align_code (fragS *fragP, int count)
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case PROCESSOR_NOCONA:
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case PROCESSOR_CORE:
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case PROCESSOR_CORE2:
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case PROCESSOR_COREI7:
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if (fragP->tc_frag_data.isa_flags.bitfield.cpui686)
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patt = alt_long_patt;
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else
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@ -8232,18 +8240,18 @@ md_show_usage (stream)
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generate code for CPU and EXTENSION, CPU is one of:\n\
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i8086, i186, i286, i386, i486, pentium, pentiumpro,\n\
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pentiumii, pentiumiii, pentium4, prescott, nocona,\n\
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core, core2, k6, k6_2, athlon, k8, amdfam10,\n\
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core, core2, corei7, k6, k6_2, athlon, k8, amdfam10,\n\
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generic32, generic64\n\
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EXTENSION is combination of:\n\
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mmx, sse, sse2, sse3, ssse3, sse4.1, sse4.2, sse4,\n\
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avx, vmx, smx, xsave, movbe, ept, aes, pclmul, fma,\n\
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rdtscp, 3dnow, 3dnowa, sse4a, sse5, svme, abm,\n\
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padlock\n"));
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clflush, syscall, rdtscp, 3dnow, 3dnowa, sse4a,\n\
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sse5, svme, abm, padlock\n"));
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fprintf (stream, _("\
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-mtune=CPU optimize for CPU, CPU is one of:\n\
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i8086, i186, i286, i386, i486, pentium, pentiumpro,\n\
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pentiumii, pentiumiii, pentium4, prescott, nocona,\n\
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core, core2, k6, k6_2, athlon, k8, amdfam10,\n\
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core, core2, corei7, k6, k6_2, athlon, k8, amdfam10,\n\
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generic32, generic64\n"));
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fprintf (stream, _("\
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-msse2avx encode SSE instructions with VEX prefix\n"));
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@ -8281,7 +8289,7 @@ i386_target_format (void)
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cpu_arch_isa_flags.bitfield.cpui486 = 1;
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cpu_arch_isa_flags.bitfield.cpui586 = 1;
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cpu_arch_isa_flags.bitfield.cpui686 = 1;
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cpu_arch_isa_flags.bitfield.cpup4 = 1;
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cpu_arch_isa_flags.bitfield.cpuclflush = 1;
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cpu_arch_isa_flags.bitfield.cpummx= 1;
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cpu_arch_isa_flags.bitfield.cpusse = 1;
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cpu_arch_isa_flags.bitfield.cpusse2 = 1;
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@ -8294,7 +8302,7 @@ i386_target_format (void)
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cpu_arch_tune_flags.bitfield.cpui486 = 1;
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cpu_arch_tune_flags.bitfield.cpui586 = 1;
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cpu_arch_tune_flags.bitfield.cpui686 = 1;
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cpu_arch_tune_flags.bitfield.cpup4 = 1;
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cpu_arch_tune_flags.bitfield.cpuclflush = 1;
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cpu_arch_tune_flags.bitfield.cpummx= 1;
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cpu_arch_tune_flags.bitfield.cpusse = 1;
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cpu_arch_tune_flags.bitfield.cpusse2 = 1;
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@ -198,6 +198,7 @@ enum processor_type
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PROCESSOR_NOCONA,
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PROCESSOR_CORE,
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PROCESSOR_CORE2,
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PROCESSOR_COREI7,
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PROCESSOR_K6,
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PROCESSOR_ATHLON,
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PROCESSOR_K8,
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@ -100,6 +100,7 @@ processor names are recognized:
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@code{nocona},
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@code{core},
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@code{core2},
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@code{corei7},
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@code{k6},
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@code{k6_2},
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@code{athlon},
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@ -130,6 +131,8 @@ accept various extension mnemonics. For example,
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@code{fma},
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@code{movbe},
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@code{ept},
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@code{clflush},
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@code{syscall},
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@code{rdtscp},
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@code{3dnow},
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@code{3dnowa},
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@ -873,14 +876,14 @@ supported on the CPU specified. The choices for @var{cpu_type} are:
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@item @samp{i486} @tab @samp{i586} @tab @samp{i686} @tab @samp{pentium}
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@item @samp{pentiumpro} @tab @samp{pentiumii} @tab @samp{pentiumiii} @tab @samp{pentium4}
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@item @samp{prescott} @tab @samp{nocona} @tab @samp{core} @tab @samp{core2}
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@item @samp{k6} @tab @samp{k6_2} @tab @samp{athlon} @tab @samp{k8}
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@item @samp{amdfam10}
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@item @samp{corei7} @tab @samp{k6} @tab @samp{k6_2} @tab @samp{athlon}
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@item @samp{k8} @tab @samp{amdfam10}
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@item @samp{generic32} @tab @samp{generic64}
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@item @samp{.mmx} @tab @samp{.sse} @tab @samp{.sse2} @tab @samp{.sse3}
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@item @samp{.ssse3} @tab @samp{.sse4.1} @tab @samp{.sse4.2} @tab @samp{.sse4}
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@item @samp{.avx} @tab @samp{.vmx} @tab @samp{.smx} @tab @samp{.xsave}
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@item @samp{.aes} @tab @samp{.pclmul} @tab @samp{.fma} @tab @samp{.movbe}
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@item @samp{.ept} @tab @samp{.rdtscp}
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@item @samp{.ept} @tab @samp{.clflush} @tab @samp{.syscall} @tab @samp{.rdtscp}
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@item @samp{.3dnow} @tab @samp{.3dnowa} @tab @samp{.sse4a} @tab @samp{.sse5}
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@item @samp{.svme} @tab @samp{.abm}
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@item @samp{.padlock}
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@ -1,3 +1,15 @@
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2009-01-10 H.J. Lu <hongjiu.lu@intel.com>
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* gas/i386/arch-10.s: Add clflush and syscall.
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* gas/i386/x86-64-arch-2.s: Likewise.
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* gas/i386/arch-10.d: Updated.
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* gas/i386/arch-10-1.l: Likewise.
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* gas/i386/arch-10-2.l: Likewise.
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* gas/i386/arch-10-3.l: Likewise.
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* gas/i386/arch-10-4.l: Likewise.
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* gas/i386/x86-64-arch-2.d: Likewise.
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2009-01-09 H.J. Lu <hongjiu.lu@intel.com>
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* gas/i386/arch-10.s: Add rdtscp.
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@ -25,6 +25,8 @@
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.*:50: Error: .*
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.*:52: Error: .*
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.*:54: Error: .*
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.*:56: Error: .*
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.*:58: Error: .*
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GAS LISTING .*
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@ -33,53 +35,60 @@ GAS LISTING .*
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[ ]*2[ ]+\.text
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[ ]*3[ ]+\# cmov feature
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[ ]*4[ ]+cmove %eax,%ebx
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[ ]*5[ ]+\# MMX
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[ ]*6[ ]+paddb %mm4,%mm3
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[ ]*7[ ]+\# SSE
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[ ]*8[ ]+addss %xmm4,%xmm3
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[ ]*9[ ]+\# SSE2
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[ ]*10[ ]+addsd %xmm4,%xmm3
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[ ]*11[ ]+\# SSE3
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[ ]*12[ ]+addsubpd %xmm4,%xmm3
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[ ]*13[ ]+\# SSSE3
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[ ]*14[ ]+phaddw %xmm4,%xmm3
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[ ]*15[ ]+\# SSE4\.1
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[ ]*16[ ]+phminposuw %xmm1,%xmm3
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[ ]*17[ ]+\# SSE4\.2
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[ ]*18[ ]+crc32 %ecx,%ebx
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[ ]*19[ ]+\# AVX
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[ ]*20[ ]+vzeroall
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[ ]*21[ ]+\# VMX
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[ ]*22[ ]+vmxoff
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[ ]*23[ ]+\# SMX
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[ ]*24[ ]+getsec
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[ ]*25[ ]+\# Xsave
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[ ]*26[ ]+xgetbv
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[ ]*27[ ]+\# AES
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[ ]*28[ ]+aesenc \(%ecx\),%xmm0
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[ ]*29[ ]+\# PCLMUL
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[ ]*30[ ]+pclmulqdq \$8,%xmm1,%xmm0
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[ ]*31[ ]+\# AES \+ AVX
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[ ]*32[ ]+vaesenc \(%ecx\),%xmm0,%xmm2
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[ ]*33[ ]+\# FMA
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[ ]*34[ ]+vfmadd132pd %xmm4,%xmm6,%xmm2
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[ ]*35[ ]+\# MOVBE
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[ ]*36[ ]+movbe \(%ecx\),%ebx
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[ ]*37[ ]+\# EPT
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[ ]*38[ ]+invept \(%ecx\),%ebx
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[ ]*39[ ]+\# RDTSCP
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[ ]*40[ ]+rdtscp
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[ ]*41[ ]+\# 3DNow
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[ ]*42[ ]+pmulhrw %mm4,%mm3
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[ ]*43[ ]+\# 3DNow Extensions
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[ ]*44[ ]+pswapd %mm4,%mm3
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[ ]*45[ ]+\# SSE4a
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[ ]*46[ ]+insertq %xmm2,%xmm1
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[ ]*47[ ]+\# SVME
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[ ]*48[ ]+vmload
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[ ]*49[ ]+\# ABM
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[ ]*50[ ]+lzcnt %ecx,%ebx
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[ ]*51[ ]+\# SSE5
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[ ]*52[ ]+frczss %xmm2, %xmm1
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[ ]*53[ ]+\# PadLock
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[ ]*54[ ]+xstorerng
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[ ]*5[ ]+\# clflush
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[ ]*6[ ]+clflush \(%eax\)
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[ ]*7[ ]+\# SYSCALL
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[ ]*8[ ]+syscall
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[ ]*9[ ]+\# MMX
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[ ]*10[ ]+paddb %mm4,%mm3
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[ ]*11[ ]+\# SSE
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[ ]*12[ ]+addss %xmm4,%xmm3
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[ ]*13[ ]+\# SSE2
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[ ]*14[ ]+addsd %xmm4,%xmm3
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[ ]*15[ ]+\# SSE3
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[ ]*16[ ]+addsubpd %xmm4,%xmm3
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[ ]*17[ ]+\# SSSE3
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[ ]*18[ ]+phaddw %xmm4,%xmm3
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[ ]*19[ ]+\# SSE4\.1
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[ ]*20[ ]+phminposuw %xmm1,%xmm3
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[ ]*21[ ]+\# SSE4\.2
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[ ]*22[ ]+crc32 %ecx,%ebx
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[ ]*23[ ]+\# AVX
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[ ]*24[ ]+vzeroall
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[ ]*25[ ]+\# VMX
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[ ]*26[ ]+vmxoff
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[ ]*27[ ]+\# SMX
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[ ]*28[ ]+getsec
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[ ]*29[ ]+\# Xsave
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[ ]*30[ ]+xgetbv
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[ ]*31[ ]+\# AES
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[ ]*32[ ]+aesenc \(%ecx\),%xmm0
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[ ]*33[ ]+\# PCLMUL
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[ ]*34[ ]+pclmulqdq \$8,%xmm1,%xmm0
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[ ]*35[ ]+\# AES \+ AVX
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[ ]*36[ ]+vaesenc \(%ecx\),%xmm0,%xmm2
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[ ]*37[ ]+\# FMA
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[ ]*38[ ]+vfmadd132pd %xmm4,%xmm6,%xmm2
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[ ]*39[ ]+\# MOVBE
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[ ]*40[ ]+movbe \(%ecx\),%ebx
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[ ]*41[ ]+\# EPT
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[ ]*42[ ]+invept \(%ecx\),%ebx
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[ ]*43[ ]+\# RDTSCP
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[ ]*44[ ]+rdtscp
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[ ]*45[ ]+\# 3DNow
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[ ]*46[ ]+pmulhrw %mm4,%mm3
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[ ]*47[ ]+\# 3DNow Extensions
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[ ]*48[ ]+pswapd %mm4,%mm3
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[ ]*49[ ]+\# SSE4a
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[ ]*50[ ]+insertq %xmm2,%xmm1
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[ ]*51[ ]+\# SVME
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[ ]*52[ ]+vmload
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[ ]*53[ ]+\# ABM
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[ ]*54[ ]+lzcnt %ecx,%ebx
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[ ]*55[ ]+\# SSE5
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[ ]*56[ ]+frczss %xmm2, %xmm1
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GAS LISTING .*
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[ ]*57[ ]+\# PadLock
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[ ]*58[ ]+xstorerng
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@ -24,6 +24,8 @@
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.*:50: Error: .*
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.*:52: Error: .*
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||||
.*:54: Error: .*
|
||||
.*:56: Error: .*
|
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.*:58: Error: .*
|
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GAS LISTING .*
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@ -32,53 +34,60 @@ GAS LISTING .*
|
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[ ]*2[ ]+\.text
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[ ]*3[ ]+\# cmov feature
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[ ]*4[ ]+\?\?\?\? 0F44D8 cmove %eax,%ebx
|
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[ ]*5[ ]+\# MMX
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[ ]*6[ ]+paddb %mm4,%mm3
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[ ]*7[ ]+\# SSE
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[ ]*8[ ]+addss %xmm4,%xmm3
|
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[ ]*9[ ]+\# SSE2
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[ ]*10[ ]+addsd %xmm4,%xmm3
|
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[ ]*11[ ]+\# SSE3
|
||||
[ ]*12[ ]+addsubpd %xmm4,%xmm3
|
||||
[ ]*13[ ]+\# SSSE3
|
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[ ]*14[ ]+phaddw %xmm4,%xmm3
|
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[ ]*15[ ]+\# SSE4\.1
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||||
[ ]*16[ ]+phminposuw %xmm1,%xmm3
|
||||
[ ]*17[ ]+\# SSE4\.2
|
||||
[ ]*18[ ]+crc32 %ecx,%ebx
|
||||
[ ]*19[ ]+\# AVX
|
||||
[ ]*20[ ]+vzeroall
|
||||
[ ]*21[ ]+\# VMX
|
||||
[ ]*22[ ]+vmxoff
|
||||
[ ]*23[ ]+\# SMX
|
||||
[ ]*24[ ]+getsec
|
||||
[ ]*25[ ]+\# Xsave
|
||||
[ ]*26[ ]+xgetbv
|
||||
[ ]*27[ ]+\# AES
|
||||
[ ]*28[ ]+aesenc \(%ecx\),%xmm0
|
||||
[ ]*29[ ]+\# PCLMUL
|
||||
[ ]*30[ ]+pclmulqdq \$8,%xmm1,%xmm0
|
||||
[ ]*31[ ]+\# AES \+ AVX
|
||||
[ ]*32[ ]+vaesenc \(%ecx\),%xmm0,%xmm2
|
||||
[ ]*33[ ]+\# FMA
|
||||
[ ]*34[ ]+vfmadd132pd %xmm4,%xmm6,%xmm2
|
||||
[ ]*35[ ]+\# MOVBE
|
||||
[ ]*36[ ]+movbe \(%ecx\),%ebx
|
||||
[ ]*37[ ]+\# EPT
|
||||
[ ]*38[ ]+invept \(%ecx\),%ebx
|
||||
[ ]*39[ ]+\# RDTSCP
|
||||
[ ]*40[ ]+rdtscp
|
||||
[ ]*41[ ]+\# 3DNow
|
||||
[ ]*42[ ]+pmulhrw %mm4,%mm3
|
||||
[ ]*43[ ]+\# 3DNow Extensions
|
||||
[ ]*44[ ]+pswapd %mm4,%mm3
|
||||
[ ]*45[ ]+\# SSE4a
|
||||
[ ]*46[ ]+insertq %xmm2,%xmm1
|
||||
[ ]*47[ ]+\# SVME
|
||||
[ ]*48[ ]+vmload
|
||||
[ ]*49[ ]+\# ABM
|
||||
[ ]*50[ ]+lzcnt %ecx,%ebx
|
||||
[ ]*51[ ]+\# SSE5
|
||||
[ ]*52[ ]+frczss %xmm2, %xmm1
|
||||
[ ]*53[ ]+\# PadLock
|
||||
[ ]*54[ ]+xstorerng
|
||||
[ ]*5[ ]+\# clflush
|
||||
[ ]*6[ ]+clflush \(%eax\)
|
||||
[ ]*7[ ]+\# SYSCALL
|
||||
[ ]*8[ ]+syscall
|
||||
[ ]*9[ ]+\# MMX
|
||||
[ ]*10[ ]+paddb %mm4,%mm3
|
||||
[ ]*11[ ]+\# SSE
|
||||
[ ]*12[ ]+addss %xmm4,%xmm3
|
||||
[ ]*13[ ]+\# SSE2
|
||||
[ ]*14[ ]+addsd %xmm4,%xmm3
|
||||
[ ]*15[ ]+\# SSE3
|
||||
[ ]*16[ ]+addsubpd %xmm4,%xmm3
|
||||
[ ]*17[ ]+\# SSSE3
|
||||
[ ]*18[ ]+phaddw %xmm4,%xmm3
|
||||
[ ]*19[ ]+\# SSE4\.1
|
||||
[ ]*20[ ]+phminposuw %xmm1,%xmm3
|
||||
[ ]*21[ ]+\# SSE4\.2
|
||||
[ ]*22[ ]+crc32 %ecx,%ebx
|
||||
[ ]*23[ ]+\# AVX
|
||||
[ ]*24[ ]+vzeroall
|
||||
[ ]*25[ ]+\# VMX
|
||||
[ ]*26[ ]+vmxoff
|
||||
[ ]*27[ ]+\# SMX
|
||||
[ ]*28[ ]+getsec
|
||||
[ ]*29[ ]+\# Xsave
|
||||
[ ]*30[ ]+xgetbv
|
||||
[ ]*31[ ]+\# AES
|
||||
[ ]*32[ ]+aesenc \(%ecx\),%xmm0
|
||||
[ ]*33[ ]+\# PCLMUL
|
||||
[ ]*34[ ]+pclmulqdq \$8,%xmm1,%xmm0
|
||||
[ ]*35[ ]+\# AES \+ AVX
|
||||
[ ]*36[ ]+vaesenc \(%ecx\),%xmm0,%xmm2
|
||||
[ ]*37[ ]+\# FMA
|
||||
[ ]*38[ ]+vfmadd132pd %xmm4,%xmm6,%xmm2
|
||||
[ ]*39[ ]+\# MOVBE
|
||||
[ ]*40[ ]+movbe \(%ecx\),%ebx
|
||||
[ ]*41[ ]+\# EPT
|
||||
[ ]*42[ ]+invept \(%ecx\),%ebx
|
||||
[ ]*43[ ]+\# RDTSCP
|
||||
[ ]*44[ ]+rdtscp
|
||||
[ ]*45[ ]+\# 3DNow
|
||||
[ ]*46[ ]+pmulhrw %mm4,%mm3
|
||||
[ ]*47[ ]+\# 3DNow Extensions
|
||||
[ ]*48[ ]+pswapd %mm4,%mm3
|
||||
[ ]*49[ ]+\# SSE4a
|
||||
[ ]*50[ ]+insertq %xmm2,%xmm1
|
||||
[ ]*51[ ]+\# SVME
|
||||
[ ]*52[ ]+vmload
|
||||
[ ]*53[ ]+\# ABM
|
||||
[ ]*54[ ]+lzcnt %ecx,%ebx
|
||||
[ ]*55[ ]+\# SSE5
|
||||
[ ]*56[ ]+frczss %xmm2, %xmm1
|
||||
GAS LISTING .*
|
||||
|
||||
|
||||
[ ]*57[ ]+\# PadLock
|
||||
[ ]*58[ ]+xstorerng
|
||||
|
||||
@ -1,6 +1,6 @@
|
||||
.*: Assembler messages:
|
||||
.*:20: Error: .*
|
||||
.*:22: Error: .*
|
||||
.*:6: Error: .*
|
||||
.*:8: Error: .*
|
||||
.*:24: Error: .*
|
||||
.*:26: Error: .*
|
||||
.*:28: Error: .*
|
||||
@ -17,6 +17,8 @@
|
||||
.*:50: Error: .*
|
||||
.*:52: Error: .*
|
||||
.*:54: Error: .*
|
||||
.*:56: Error: .*
|
||||
.*:58: Error: .*
|
||||
GAS LISTING .*
|
||||
|
||||
|
||||
@ -25,59 +27,63 @@ GAS LISTING .*
|
||||
[ ]*2[ ]+\.text
|
||||
[ ]*3[ ]+\# cmov feature
|
||||
[ ]*4[ ]+\?\?\?\? 0F44D8 cmove %eax,%ebx
|
||||
[ ]*5[ ]+\# MMX
|
||||
[ ]*6[ ]+\?\?\?\? 0FFCDC paddb %mm4,%mm3
|
||||
[ ]*7[ ]+\# SSE
|
||||
[ ]*8[ ]+\?\?\?\? F30F58DC addss %xmm4,%xmm3
|
||||
[ ]*9[ ]+\# SSE2
|
||||
[ ]*10[ ]+\?\?\?\? F20F58DC addsd %xmm4,%xmm3
|
||||
[ ]*11[ ]+\# SSE3
|
||||
[ ]*12[ ]+\?\?\?\? 660FD0DC addsubpd %xmm4,%xmm3
|
||||
[ ]*13[ ]+\# SSSE3
|
||||
[ ]*14[ ]+\?\?\?\? 660F3801 phaddw %xmm4,%xmm3
|
||||
[ ]*14[ ]+DC
|
||||
[ ]*15[ ]+\# SSE4\.1
|
||||
[ ]*16[ ]+\?\?\?\? 660F3841 phminposuw %xmm1,%xmm3
|
||||
[ ]*16[ ]+D9
|
||||
[ ]*17[ ]+\# SSE4\.2
|
||||
[ ]*18[ ]+\?\?\?\? F20F38F1 crc32 %ecx,%ebx
|
||||
[ ]*18[ ]+D9
|
||||
[ ]*19[ ]+\# AVX
|
||||
[ ]*20[ ]+vzeroall
|
||||
[ ]*21[ ]+\# VMX
|
||||
[ ]*22[ ]+vmxoff
|
||||
[ ]*23[ ]+\# SMX
|
||||
[ ]*24[ ]+getsec
|
||||
[ ]*25[ ]+\# Xsave
|
||||
[ ]*26[ ]+xgetbv
|
||||
[ ]*27[ ]+\# AES
|
||||
[ ]*28[ ]+aesenc \(%ecx\),%xmm0
|
||||
[ ]*29[ ]+\# PCLMUL
|
||||
[ ]*30[ ]+pclmulqdq \$8,%xmm1,%xmm0
|
||||
[ ]*31[ ]+\# AES \+ AVX
|
||||
[ ]*32[ ]+vaesenc \(%ecx\),%xmm0,%xmm2
|
||||
[ ]*33[ ]+\# FMA
|
||||
[ ]*34[ ]+vfmadd132pd %xmm4,%xmm6,%xmm2
|
||||
[ ]*35[ ]+\# MOVBE
|
||||
[ ]*36[ ]+movbe \(%ecx\),%ebx
|
||||
[ ]*37[ ]+\# EPT
|
||||
[ ]*38[ ]+invept \(%ecx\),%ebx
|
||||
[ ]*39[ ]+\# RDTSCP
|
||||
[ ]*40[ ]+rdtscp
|
||||
[ ]*41[ ]+\# 3DNow
|
||||
[ ]*42[ ]+pmulhrw %mm4,%mm3
|
||||
[ ]*43[ ]+\# 3DNow Extensions
|
||||
[ ]*44[ ]+pswapd %mm4,%mm3
|
||||
[ ]*45[ ]+\# SSE4a
|
||||
[ ]*46[ ]+insertq %xmm2,%xmm1
|
||||
[ ]*47[ ]+\# SVME
|
||||
[ ]*48[ ]+vmload
|
||||
[ ]*49[ ]+\# ABM
|
||||
[ ]*50[ ]+lzcnt %ecx,%ebx
|
||||
[ ]*51[ ]+\# SSE5
|
||||
[ ]*52[ ]+frczss %xmm2, %xmm1
|
||||
[ ]*53[ ]+\# PadLock
|
||||
[ ]*5[ ]+\# clflush
|
||||
[ ]*6[ ]+clflush \(%eax\)
|
||||
[ ]*7[ ]+\# SYSCALL
|
||||
[ ]*8[ ]+syscall
|
||||
[ ]*9[ ]+\# MMX
|
||||
[ ]*10[ ]+\?\?\?\? 0FFCDC paddb %mm4,%mm3
|
||||
[ ]*11[ ]+\# SSE
|
||||
[ ]*12[ ]+\?\?\?\? F30F58DC addss %xmm4,%xmm3
|
||||
[ ]*13[ ]+\# SSE2
|
||||
[ ]*14[ ]+\?\?\?\? F20F58DC addsd %xmm4,%xmm3
|
||||
[ ]*15[ ]+\# SSE3
|
||||
[ ]*16[ ]+\?\?\?\? 660FD0DC addsubpd %xmm4,%xmm3
|
||||
[ ]*17[ ]+\# SSSE3
|
||||
[ ]*18[ ]+\?\?\?\? 660F3801 phaddw %xmm4,%xmm3
|
||||
[ ]*18[ ]+DC
|
||||
[ ]*19[ ]+\# SSE4\.1
|
||||
[ ]*20[ ]+\?\?\?\? 660F3841 phminposuw %xmm1,%xmm3
|
||||
[ ]*20[ ]+D9
|
||||
[ ]*21[ ]+\# SSE4\.2
|
||||
[ ]*22[ ]+\?\?\?\? F20F38F1 crc32 %ecx,%ebx
|
||||
[ ]*22[ ]+D9
|
||||
[ ]*23[ ]+\# AVX
|
||||
[ ]*24[ ]+vzeroall
|
||||
[ ]*25[ ]+\# VMX
|
||||
[ ]*26[ ]+vmxoff
|
||||
[ ]*27[ ]+\# SMX
|
||||
[ ]*28[ ]+getsec
|
||||
[ ]*29[ ]+\# Xsave
|
||||
[ ]*30[ ]+xgetbv
|
||||
[ ]*31[ ]+\# AES
|
||||
[ ]*32[ ]+aesenc \(%ecx\),%xmm0
|
||||
[ ]*33[ ]+\# PCLMUL
|
||||
[ ]*34[ ]+pclmulqdq \$8,%xmm1,%xmm0
|
||||
[ ]*35[ ]+\# AES \+ AVX
|
||||
[ ]*36[ ]+vaesenc \(%ecx\),%xmm0,%xmm2
|
||||
[ ]*37[ ]+\# FMA
|
||||
[ ]*38[ ]+vfmadd132pd %xmm4,%xmm6,%xmm2
|
||||
[ ]*39[ ]+\# MOVBE
|
||||
[ ]*40[ ]+movbe \(%ecx\),%ebx
|
||||
[ ]*41[ ]+\# EPT
|
||||
[ ]*42[ ]+invept \(%ecx\),%ebx
|
||||
[ ]*43[ ]+\# RDTSCP
|
||||
[ ]*44[ ]+rdtscp
|
||||
[ ]*45[ ]+\# 3DNow
|
||||
[ ]*46[ ]+pmulhrw %mm4,%mm3
|
||||
[ ]*47[ ]+\# 3DNow Extensions
|
||||
[ ]*48[ ]+pswapd %mm4,%mm3
|
||||
[ ]*49[ ]+\# SSE4a
|
||||
[ ]*50[ ]+insertq %xmm2,%xmm1
|
||||
[ ]*51[ ]+\# SVME
|
||||
[ ]*52[ ]+vmload
|
||||
[ ]*53[ ]+\# ABM
|
||||
GAS LISTING .*
|
||||
|
||||
|
||||
[ ]*54[ ]+xstorerng
|
||||
[ ]*54[ ]+lzcnt %ecx,%ebx
|
||||
[ ]*55[ ]+\# SSE5
|
||||
[ ]*56[ ]+frczss %xmm2, %xmm1
|
||||
[ ]*57[ ]+\# PadLock
|
||||
[ ]*58[ ]+xstorerng
|
||||
|
||||
@ -1,7 +1,7 @@
|
||||
.*: Assembler messages:
|
||||
.*:20: Error: .*
|
||||
.*:26: Error: .*
|
||||
.*:28: Error: .*
|
||||
.*:6: Error: .*
|
||||
.*:8: Error: .*
|
||||
.*:24: Error: .*
|
||||
.*:30: Error: .*
|
||||
.*:32: Error: .*
|
||||
.*:34: Error: .*
|
||||
@ -15,6 +15,8 @@
|
||||
.*:50: Error: .*
|
||||
.*:52: Error: .*
|
||||
.*:54: Error: .*
|
||||
.*:56: Error: .*
|
||||
.*:58: Error: .*
|
||||
GAS LISTING .*
|
||||
|
||||
|
||||
@ -23,59 +25,63 @@ GAS LISTING .*
|
||||
[ ]*2[ ]+\.text
|
||||
[ ]*3[ ]+\# cmov feature
|
||||
[ ]*4[ ]+\?\?\?\? 0F44D8 cmove %eax,%ebx
|
||||
[ ]*5[ ]+\# MMX
|
||||
[ ]*6[ ]+\?\?\?\? 0FFCDC paddb %mm4,%mm3
|
||||
[ ]*7[ ]+\# SSE
|
||||
[ ]*8[ ]+\?\?\?\? F30F58DC addss %xmm4,%xmm3
|
||||
[ ]*9[ ]+\# SSE2
|
||||
[ ]*10[ ]+\?\?\?\? F20F58DC addsd %xmm4,%xmm3
|
||||
[ ]*11[ ]+\# SSE3
|
||||
[ ]*12[ ]+\?\?\?\? 660FD0DC addsubpd %xmm4,%xmm3
|
||||
[ ]*13[ ]+\# SSSE3
|
||||
[ ]*14[ ]+\?\?\?\? 660F3801 phaddw %xmm4,%xmm3
|
||||
[ ]*14[ ]+DC
|
||||
[ ]*15[ ]+\# SSE4\.1
|
||||
[ ]*16[ ]+\?\?\?\? 660F3841 phminposuw %xmm1,%xmm3
|
||||
[ ]*16[ ]+D9
|
||||
[ ]*17[ ]+\# SSE4\.2
|
||||
[ ]*18[ ]+\?\?\?\? F20F38F1 crc32 %ecx,%ebx
|
||||
[ ]*18[ ]+D9
|
||||
[ ]*19[ ]+\# AVX
|
||||
[ ]*20[ ]+vzeroall
|
||||
[ ]*21[ ]+\# VMX
|
||||
[ ]*22[ ]+\?\?\?\? 0F01C4 vmxoff
|
||||
[ ]*23[ ]+\# SMX
|
||||
[ ]*24[ ]+\?\?\?\? 0F37 getsec
|
||||
[ ]*25[ ]+\# Xsave
|
||||
[ ]*26[ ]+xgetbv
|
||||
[ ]*27[ ]+\# AES
|
||||
[ ]*28[ ]+aesenc \(%ecx\),%xmm0
|
||||
[ ]*29[ ]+\# PCLMUL
|
||||
[ ]*30[ ]+pclmulqdq \$8,%xmm1,%xmm0
|
||||
[ ]*31[ ]+\# AES \+ AVX
|
||||
[ ]*32[ ]+vaesenc \(%ecx\),%xmm0,%xmm2
|
||||
[ ]*33[ ]+\# FMA
|
||||
[ ]*34[ ]+vfmadd132pd %xmm4,%xmm6,%xmm2
|
||||
[ ]*35[ ]+\# MOVBE
|
||||
[ ]*36[ ]+movbe \(%ecx\),%ebx
|
||||
[ ]*37[ ]+\# EPT
|
||||
[ ]*38[ ]+invept \(%ecx\),%ebx
|
||||
[ ]*39[ ]+\# RDTSCP
|
||||
[ ]*40[ ]+rdtscp
|
||||
[ ]*41[ ]+\# 3DNow
|
||||
[ ]*42[ ]+pmulhrw %mm4,%mm3
|
||||
[ ]*43[ ]+\# 3DNow Extensions
|
||||
[ ]*44[ ]+pswapd %mm4,%mm3
|
||||
[ ]*45[ ]+\# SSE4a
|
||||
[ ]*46[ ]+insertq %xmm2,%xmm1
|
||||
[ ]*47[ ]+\# SVME
|
||||
[ ]*48[ ]+vmload
|
||||
[ ]*49[ ]+\# ABM
|
||||
[ ]*50[ ]+lzcnt %ecx,%ebx
|
||||
[ ]*51[ ]+\# SSE5
|
||||
[ ]*52[ ]+frczss %xmm2, %xmm1
|
||||
[ ]*53[ ]+\# PadLock
|
||||
[ ]*5[ ]+\# clflush
|
||||
[ ]*6[ ]+clflush \(%eax\)
|
||||
[ ]*7[ ]+\# SYSCALL
|
||||
[ ]*8[ ]+syscall
|
||||
[ ]*9[ ]+\# MMX
|
||||
[ ]*10[ ]+\?\?\?\? 0FFCDC paddb %mm4,%mm3
|
||||
[ ]*11[ ]+\# SSE
|
||||
[ ]*12[ ]+\?\?\?\? F30F58DC addss %xmm4,%xmm3
|
||||
[ ]*13[ ]+\# SSE2
|
||||
[ ]*14[ ]+\?\?\?\? F20F58DC addsd %xmm4,%xmm3
|
||||
[ ]*15[ ]+\# SSE3
|
||||
[ ]*16[ ]+\?\?\?\? 660FD0DC addsubpd %xmm4,%xmm3
|
||||
[ ]*17[ ]+\# SSSE3
|
||||
[ ]*18[ ]+\?\?\?\? 660F3801 phaddw %xmm4,%xmm3
|
||||
[ ]*18[ ]+DC
|
||||
[ ]*19[ ]+\# SSE4\.1
|
||||
[ ]*20[ ]+\?\?\?\? 660F3841 phminposuw %xmm1,%xmm3
|
||||
[ ]*20[ ]+D9
|
||||
[ ]*21[ ]+\# SSE4\.2
|
||||
[ ]*22[ ]+\?\?\?\? F20F38F1 crc32 %ecx,%ebx
|
||||
[ ]*22[ ]+D9
|
||||
[ ]*23[ ]+\# AVX
|
||||
[ ]*24[ ]+vzeroall
|
||||
[ ]*25[ ]+\# VMX
|
||||
[ ]*26[ ]+\?\?\?\? 0F01C4 vmxoff
|
||||
[ ]*27[ ]+\# SMX
|
||||
[ ]*28[ ]+\?\?\?\? 0F37 getsec
|
||||
[ ]*29[ ]+\# Xsave
|
||||
[ ]*30[ ]+xgetbv
|
||||
[ ]*31[ ]+\# AES
|
||||
[ ]*32[ ]+aesenc \(%ecx\),%xmm0
|
||||
[ ]*33[ ]+\# PCLMUL
|
||||
[ ]*34[ ]+pclmulqdq \$8,%xmm1,%xmm0
|
||||
[ ]*35[ ]+\# AES \+ AVX
|
||||
[ ]*36[ ]+vaesenc \(%ecx\),%xmm0,%xmm2
|
||||
[ ]*37[ ]+\# FMA
|
||||
[ ]*38[ ]+vfmadd132pd %xmm4,%xmm6,%xmm2
|
||||
[ ]*39[ ]+\# MOVBE
|
||||
[ ]*40[ ]+movbe \(%ecx\),%ebx
|
||||
[ ]*41[ ]+\# EPT
|
||||
[ ]*42[ ]+invept \(%ecx\),%ebx
|
||||
[ ]*43[ ]+\# RDTSCP
|
||||
[ ]*44[ ]+rdtscp
|
||||
[ ]*45[ ]+\# 3DNow
|
||||
[ ]*46[ ]+pmulhrw %mm4,%mm3
|
||||
[ ]*47[ ]+\# 3DNow Extensions
|
||||
[ ]*48[ ]+pswapd %mm4,%mm3
|
||||
[ ]*49[ ]+\# SSE4a
|
||||
[ ]*50[ ]+insertq %xmm2,%xmm1
|
||||
[ ]*51[ ]+\# SVME
|
||||
[ ]*52[ ]+vmload
|
||||
[ ]*53[ ]+\# ABM
|
||||
GAS LISTING .*
|
||||
|
||||
|
||||
[ ]*54[ ]+xstorerng
|
||||
[ ]*54[ ]+lzcnt %ecx,%ebx
|
||||
[ ]*55[ ]+\# SSE5
|
||||
[ ]*56[ ]+frczss %xmm2, %xmm1
|
||||
[ ]*57[ ]+\# PadLock
|
||||
[ ]*58[ ]+xstorerng
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
#as: -march=i686+avx+vmx+smx+xsave+aes+pclmul+fma+movbe+ept+rdtscp+sse5+3dnowa+svme+padlock
|
||||
#as: -march=i686+avx+vmx+smx+xsave+aes+pclmul+fma+movbe+ept+clflush+syscall+rdtscp+sse5+3dnowa+svme+padlock
|
||||
#objdump: -dw
|
||||
#name: i386 arch 10
|
||||
|
||||
@ -8,6 +8,8 @@ Disassembly of section .text:
|
||||
|
||||
0+ <.text>:
|
||||
[ ]*[a-f0-9]+: 0f 44 d8 cmove %eax,%ebx
|
||||
[ ]*[a-f0-9]+: 0f ae 38 clflush \(%eax\)
|
||||
[ ]*[a-f0-9]+: 0f 05 syscall
|
||||
[ ]*[a-f0-9]+: 0f fc dc paddb %mm4,%mm3
|
||||
[ ]*[a-f0-9]+: f3 0f 58 dc addss %xmm4,%xmm3
|
||||
[ ]*[a-f0-9]+: f2 0f 58 dc addsd %xmm4,%xmm3
|
||||
|
||||
@ -2,6 +2,10 @@
|
||||
.text
|
||||
# cmov feature
|
||||
cmove %eax,%ebx
|
||||
# clflush
|
||||
clflush (%eax)
|
||||
# SYSCALL
|
||||
syscall
|
||||
# MMX
|
||||
paddb %mm4,%mm3
|
||||
# SSE
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
#as: -march=generic64+avx+vmx+smx+xsave+aes+pclmul+fma+movbe+ept+rdtscp+sse5+3dnowa+svme+padlock
|
||||
#as: -march=generic64+avx+vmx+smx+xsave+aes+pclmul+fma+movbe+ept+clflush+syscall+rdtscp+sse5+3dnowa+svme+padlock
|
||||
#objdump: -dw
|
||||
#name: x86-64 arch 2
|
||||
|
||||
@ -8,6 +8,8 @@ Disassembly of section .text:
|
||||
|
||||
0+ <.text>:
|
||||
[ ]*[a-f0-9]+: 0f 44 d8 cmove %eax,%ebx
|
||||
[ ]*[a-f0-9]+: 0f ae 38 clflush \(%rax\)
|
||||
[ ]*[a-f0-9]+: 0f 05 syscall
|
||||
[ ]*[a-f0-9]+: 0f fc dc paddb %mm4,%mm3
|
||||
[ ]*[a-f0-9]+: f3 0f 58 dc addss %xmm4,%xmm3
|
||||
[ ]*[a-f0-9]+: f2 0f 58 dc addsd %xmm4,%xmm3
|
||||
|
||||
@ -2,6 +2,10 @@
|
||||
.text
|
||||
# cmov feature
|
||||
cmove %eax,%ebx
|
||||
# clflush
|
||||
clflush (%rax)
|
||||
# SYSCALL
|
||||
syscall
|
||||
# MMX
|
||||
paddb %mm4,%mm3
|
||||
# SSE
|
||||
|
||||
@ -1,3 +1,36 @@
|
||||
2009-01-10 H.J. Lu <hongjiu.lu@intel.com>
|
||||
|
||||
* i386-gen.c (cpu_flag_init): Replace CpuP4 and CpuK6 with
|
||||
CpuClflush and CpuSYSCALL, respectively. Remove CpuK8. Add
|
||||
CPU_COREI7_FLAGS, CPU_CLFLUSH_FLAGS and CPU_SYSCALL_FLAGS.
|
||||
(cpu_flags): Remove CpuP4, CpuK6 and CpuK8. Add CpuClflush
|
||||
and CpuSYSCALL.
|
||||
(lineno): Removed.
|
||||
(set_bitfield): Take an argument, lineno. Don't report lineno
|
||||
on error if it is -1.
|
||||
(process_i386_cpu_flag): Take an argument, lineno.
|
||||
(process_i386_opcode_modifier): Likewise.
|
||||
(process_i386_operand_type): Likewise.
|
||||
(output_i386_opcode): Likewise.
|
||||
(opcode_hash_entry): Add lineno.
|
||||
(process_i386_opcodes): Updated.
|
||||
(process_i386_registers): Likewise.
|
||||
(process_i386_initializers): Likewise.
|
||||
|
||||
* i386-opc.h (CpuP4): Removed.
|
||||
(CpuK6): Likewise.
|
||||
(CpuK8): Likewise.
|
||||
(CpuClflush): New.
|
||||
(CpuSYSCALL): Likewise.
|
||||
(CpuMMX): Updated.
|
||||
(i386_cpu_flags): Remove cpup4, cpuk6 and cpuk8. Add
|
||||
cpuclflush and cpusyscall.
|
||||
|
||||
* i386-opc.tbl: Update movnti, clflush, lfence, mfence, pause,
|
||||
syscall and sysret.
|
||||
* i386-init.h: Regenerated.
|
||||
* i386-tbl.h: Likewise.
|
||||
|
||||
2009-01-09 H.J. Lu <hongjiu.lu@intel.com>
|
||||
|
||||
* i386-gen.c (cpu_flag_init): Add CpuRdtscp to CPU_K8_FLAGS
|
||||
|
||||
@ -47,7 +47,7 @@ static initializer cpu_flag_init [] =
|
||||
{ "CPU_GENERIC32_FLAGS",
|
||||
"Cpu186|Cpu286|Cpu386" },
|
||||
{ "CPU_GENERIC64_FLAGS",
|
||||
"Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX|CpuSSE|CpuSSE2|CpuLM" },
|
||||
"Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuClflush|CpuMMX|CpuSSE|CpuSSE2|CpuLM" },
|
||||
{ "CPU_NONE_FLAGS",
|
||||
"0" },
|
||||
{ "CPU_I186_FLAGS",
|
||||
@ -67,23 +67,29 @@ static initializer cpu_flag_init [] =
|
||||
{ "CPU_P3_FLAGS",
|
||||
"Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX|CpuSSE" },
|
||||
{ "CPU_P4_FLAGS",
|
||||
"Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX|CpuSSE|CpuSSE2" },
|
||||
"Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuClflush|CpuMMX|CpuSSE|CpuSSE2" },
|
||||
{ "CPU_NOCONA_FLAGS",
|
||||
"Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX|CpuSSE|CpuSSE2|CpuSSE3|CpuLM" },
|
||||
"Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuClflush|CpuMMX|CpuSSE|CpuSSE2|CpuSSE3|CpuLM" },
|
||||
{ "CPU_CORE_FLAGS",
|
||||
"Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX|CpuSSE|CpuSSE2|CpuSSE3" },
|
||||
"Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuClflush|CpuMMX|CpuSSE|CpuSSE2|CpuSSE3" },
|
||||
{ "CPU_CORE2_FLAGS",
|
||||
"Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3|CpuLM" },
|
||||
"Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuClflush|CpuMMX|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3|CpuLM" },
|
||||
{ "CPU_COREI7_FLAGS",
|
||||
"Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuClflush|CpuMMX|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3|CpuSSE4_1|CpuSSE4_2|CpuRdtscp|CpuLM" },
|
||||
{ "CPU_K6_FLAGS",
|
||||
"Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuK6|CpuMMX" },
|
||||
"Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuSYSCALL|CpuMMX" },
|
||||
{ "CPU_K6_2_FLAGS",
|
||||
"Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuK6|CpuMMX|Cpu3dnow" },
|
||||
"Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuSYSCALL|CpuMMX|Cpu3dnow" },
|
||||
{ "CPU_ATHLON_FLAGS",
|
||||
"Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuMMX|Cpu3dnow|Cpu3dnowA" },
|
||||
"Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuSYSCALL|CpuMMX|Cpu3dnow|Cpu3dnowA" },
|
||||
{ "CPU_K8_FLAGS",
|
||||
"Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuK8|CpuMMX|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2|CpuRdtscp|CpuLM" },
|
||||
"Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuSYSCALL|CpuRdtscp|CpuMMX|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2|CpuLM" },
|
||||
{ "CPU_AMDFAM10_FLAGS",
|
||||
"Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuK8|CpuMMX|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2|CpuSSE3|CpuSSE4a|CpuABM|CpuRdtscp|CpuLM" },
|
||||
"Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuSYSCALL|CpuRdtscp|CpuMMX|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2|CpuSSE3|CpuSSE4a|CpuABM|CpuLM" },
|
||||
{ "CPU_CLFLUSH_FLAGS",
|
||||
"CpuClflush" },
|
||||
{ "CPU_SYSCALL_FLAGS",
|
||||
"CpuSYSCALL" },
|
||||
{ "CPU_MMX_FLAGS",
|
||||
"CpuMMX" },
|
||||
{ "CPU_SSE_FLAGS",
|
||||
@ -249,9 +255,8 @@ static bitfield cpu_flags[] =
|
||||
BITFIELD (Cpu486),
|
||||
BITFIELD (Cpu586),
|
||||
BITFIELD (Cpu686),
|
||||
BITFIELD (CpuP4),
|
||||
BITFIELD (CpuK6),
|
||||
BITFIELD (CpuK8),
|
||||
BITFIELD (CpuClflush),
|
||||
BITFIELD (CpuSYSCALL),
|
||||
BITFIELD (CpuMMX),
|
||||
BITFIELD (CpuSSE),
|
||||
BITFIELD (CpuSSE2),
|
||||
@ -397,7 +402,6 @@ static bitfield operand_types[] =
|
||||
#endif
|
||||
};
|
||||
|
||||
static int lineno;
|
||||
static const char *filename;
|
||||
|
||||
static int
|
||||
@ -499,7 +503,7 @@ next_field (char *str, char sep, char **next, char *last)
|
||||
}
|
||||
|
||||
static void
|
||||
set_bitfield (const char *f, bitfield *array, unsigned int size)
|
||||
set_bitfield (const char *f, bitfield *array, unsigned int size, int lineno)
|
||||
{
|
||||
unsigned int i;
|
||||
|
||||
@ -515,7 +519,10 @@ set_bitfield (const char *f, bitfield *array, unsigned int size)
|
||||
return;
|
||||
}
|
||||
|
||||
fail (_("%s: %d: Unknown bitfield: %s\n"), filename, lineno, f);
|
||||
if (lineno != -1)
|
||||
fail (_("%s: %d: Unknown bitfield: %s\n"), filename, lineno, f);
|
||||
else
|
||||
fail (_("Unknown bitfield: %s\n"), f);
|
||||
}
|
||||
|
||||
static void
|
||||
@ -544,7 +551,8 @@ output_cpu_flags (FILE *table, bitfield *flags, unsigned int size,
|
||||
|
||||
static void
|
||||
process_i386_cpu_flag (FILE *table, char *flag, int macro,
|
||||
const char *comma, const char *indent)
|
||||
const char *comma, const char *indent,
|
||||
int lineno)
|
||||
{
|
||||
char *str, *next, *last;
|
||||
bitfield flags [ARRAY_SIZE (cpu_flags)];
|
||||
@ -569,7 +577,7 @@ process_i386_cpu_flag (FILE *table, char *flag, int macro,
|
||||
{
|
||||
str = next_field (next, '|', &next, last);
|
||||
if (str)
|
||||
set_bitfield (str, flags, ARRAY_SIZE (flags));
|
||||
set_bitfield (str, flags, ARRAY_SIZE (flags), lineno);
|
||||
}
|
||||
}
|
||||
|
||||
@ -595,7 +603,7 @@ output_opcode_modifier (FILE *table, bitfield *modifier, unsigned int size)
|
||||
}
|
||||
|
||||
static void
|
||||
process_i386_opcode_modifier (FILE *table, char *mod)
|
||||
process_i386_opcode_modifier (FILE *table, char *mod, int lineno)
|
||||
{
|
||||
char *str, *next, *last;
|
||||
bitfield modifiers [ARRAY_SIZE (opcode_modifiers)];
|
||||
@ -610,7 +618,7 @@ process_i386_opcode_modifier (FILE *table, char *mod)
|
||||
{
|
||||
str = next_field (next, '|', &next, last);
|
||||
if (str)
|
||||
set_bitfield (str, modifiers, ARRAY_SIZE (modifiers));
|
||||
set_bitfield (str, modifiers, ARRAY_SIZE (modifiers), lineno);
|
||||
}
|
||||
}
|
||||
output_opcode_modifier (table, modifiers, ARRAY_SIZE (modifiers));
|
||||
@ -642,7 +650,7 @@ output_operand_type (FILE *table, bitfield *types, unsigned int size,
|
||||
|
||||
static void
|
||||
process_i386_operand_type (FILE *table, char *op, int macro,
|
||||
const char *indent)
|
||||
const char *indent, int lineno)
|
||||
{
|
||||
char *str, *next, *last;
|
||||
bitfield types [ARRAY_SIZE (operand_types)];
|
||||
@ -657,7 +665,7 @@ process_i386_operand_type (FILE *table, char *op, int macro,
|
||||
{
|
||||
str = next_field (next, '|', &next, last);
|
||||
if (str)
|
||||
set_bitfield (str, types, ARRAY_SIZE (types));
|
||||
set_bitfield (str, types, ARRAY_SIZE (types), lineno);
|
||||
}
|
||||
}
|
||||
output_operand_type (table, types, ARRAY_SIZE (types), macro,
|
||||
@ -666,7 +674,7 @@ process_i386_operand_type (FILE *table, char *op, int macro,
|
||||
|
||||
static void
|
||||
output_i386_opcode (FILE *table, const char *name, char *str,
|
||||
char *last)
|
||||
char *last, int lineno)
|
||||
{
|
||||
unsigned int i;
|
||||
char *operands, *base_opcode, *extension_opcode, *opcode_length;
|
||||
@ -737,9 +745,9 @@ output_i386_opcode (FILE *table, const char *name, char *str,
|
||||
name, operands, base_opcode, extension_opcode,
|
||||
opcode_length);
|
||||
|
||||
process_i386_cpu_flag (table, cpu_flags, 0, ",", " ");
|
||||
process_i386_cpu_flag (table, cpu_flags, 0, ",", " ", lineno);
|
||||
|
||||
process_i386_opcode_modifier (table, opcode_modifier);
|
||||
process_i386_opcode_modifier (table, opcode_modifier, lineno);
|
||||
|
||||
fprintf (table, " { ");
|
||||
|
||||
@ -748,7 +756,7 @@ output_i386_opcode (FILE *table, const char *name, char *str,
|
||||
if (operand_types[i] == NULL || *operand_types[i] == '0')
|
||||
{
|
||||
if (i == 0)
|
||||
process_i386_operand_type (table, "0", 0, "\t ");
|
||||
process_i386_operand_type (table, "0", 0, "\t ", lineno);
|
||||
break;
|
||||
}
|
||||
|
||||
@ -756,7 +764,7 @@ output_i386_opcode (FILE *table, const char *name, char *str,
|
||||
fprintf (table, ",\n ");
|
||||
|
||||
process_i386_operand_type (table, operand_types[i], 0,
|
||||
"\t ");
|
||||
"\t ", lineno);
|
||||
}
|
||||
fprintf (table, " } },\n");
|
||||
}
|
||||
@ -766,6 +774,7 @@ struct opcode_hash_entry
|
||||
struct opcode_hash_entry *next;
|
||||
char *name;
|
||||
char *opcode;
|
||||
int lineno;
|
||||
};
|
||||
|
||||
/* Calculate the hash value of an opcode hash entry P. */
|
||||
@ -798,6 +807,7 @@ process_i386_opcodes (FILE *table)
|
||||
htab_t opcode_hash_table;
|
||||
struct opcode_hash_entry **opcode_array;
|
||||
unsigned int opcode_array_size = 1024;
|
||||
int lineno = 0;
|
||||
|
||||
filename = "i386-opc.tbl";
|
||||
fp = fopen (filename, "r");
|
||||
@ -874,6 +884,7 @@ process_i386_opcodes (FILE *table)
|
||||
opcode_array[i]->next = NULL;
|
||||
opcode_array[i]->name = xstrdup (name);
|
||||
opcode_array[i]->opcode = xstrdup (str);
|
||||
opcode_array[i]->lineno = lineno;
|
||||
*hash_slot = opcode_array[i];
|
||||
i++;
|
||||
}
|
||||
@ -888,6 +899,7 @@ process_i386_opcodes (FILE *table)
|
||||
(*entry)->next = NULL;
|
||||
(*entry)->name = (*hash_slot)->name;
|
||||
(*entry)->opcode = xstrdup (str);
|
||||
(*entry)->lineno = lineno;
|
||||
}
|
||||
}
|
||||
|
||||
@ -898,8 +910,9 @@ process_i386_opcodes (FILE *table)
|
||||
{
|
||||
name = next->name;
|
||||
str = next->opcode;
|
||||
lineno = next->lineno;
|
||||
last = str + strlen (str);
|
||||
output_i386_opcode (table, name, str, last);
|
||||
output_i386_opcode (table, name, str, last, lineno);
|
||||
}
|
||||
}
|
||||
|
||||
@ -907,12 +920,12 @@ process_i386_opcodes (FILE *table)
|
||||
|
||||
fprintf (table, " { NULL, 0, 0, 0, 0,\n");
|
||||
|
||||
process_i386_cpu_flag (table, "0", 0, ",", " ");
|
||||
process_i386_cpu_flag (table, "0", 0, ",", " ", -1);
|
||||
|
||||
process_i386_opcode_modifier (table, "0");
|
||||
process_i386_opcode_modifier (table, "0", -1);
|
||||
|
||||
fprintf (table, " { ");
|
||||
process_i386_operand_type (table, "0", 0, "\t ");
|
||||
process_i386_operand_type (table, "0", 0, "\t ", -1);
|
||||
fprintf (table, " } }\n");
|
||||
|
||||
fprintf (table, "};\n");
|
||||
@ -926,6 +939,7 @@ process_i386_registers (FILE *table)
|
||||
char *str, *p, *last;
|
||||
char *reg_name, *reg_type, *reg_flags, *reg_num;
|
||||
char *dw2_32_num, *dw2_64_num;
|
||||
int lineno = 0;
|
||||
|
||||
filename = "i386-reg.tbl";
|
||||
fp = fopen (filename, "r");
|
||||
@ -980,7 +994,7 @@ process_i386_registers (FILE *table)
|
||||
|
||||
fprintf (table, " { \"%s\",\n ", reg_name);
|
||||
|
||||
process_i386_operand_type (table, reg_type, 0, "\t");
|
||||
process_i386_operand_type (table, reg_type, 0, "\t", lineno);
|
||||
|
||||
/* Find 32-bit Dwarf2 register number. */
|
||||
dw2_32_num = next_field (str, ',', &str, last);
|
||||
@ -1016,7 +1030,7 @@ process_i386_initializers (void)
|
||||
{
|
||||
fprintf (fp, "\n#define %s \\\n", cpu_flag_init[i].name);
|
||||
init = xstrdup (cpu_flag_init[i].init);
|
||||
process_i386_cpu_flag (fp, init, 1, "", " ");
|
||||
process_i386_cpu_flag (fp, init, 1, "", " ", -1);
|
||||
free (init);
|
||||
}
|
||||
|
||||
@ -1024,7 +1038,7 @@ process_i386_initializers (void)
|
||||
{
|
||||
fprintf (fp, "\n\n#define %s \\\n ", operand_type_init[i].name);
|
||||
init = xstrdup (operand_type_init[i].init);
|
||||
process_i386_operand_type (fp, init, 1, " ");
|
||||
process_i386_operand_type (fp, init, 1, " ", -1);
|
||||
free (init);
|
||||
}
|
||||
fprintf (fp, "\n");
|
||||
|
||||
@ -21,183 +21,195 @@
|
||||
|
||||
#define CPU_UNKNOWN_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
|
||||
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1 } }
|
||||
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1 } }
|
||||
|
||||
#define CPU_GENERIC32_FLAGS \
|
||||
{ { 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_GENERIC64_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0 } }
|
||||
{ { 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0 } }
|
||||
|
||||
#define CPU_NONE_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_I186_FLAGS \
|
||||
{ { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_I286_FLAGS \
|
||||
{ { 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_I386_FLAGS \
|
||||
{ { 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_I486_FLAGS \
|
||||
{ { 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_I586_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_I686_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_P2_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
{ { 1, 1, 1, 1, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_P3_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
{ { 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_P4_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
{ { 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_NOCONA_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0 } }
|
||||
{ { 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0 } }
|
||||
|
||||
#define CPU_CORE_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
{ { 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_CORE2_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 0, 0, 1, 0, 0, 0, 0, 1, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0 } }
|
||||
{ { 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 0, 0, 1, 0, 0, 0, 0, 1, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0 } }
|
||||
|
||||
#define CPU_COREI7_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 0, 0, 1, 0, 0, 0, 0, 1, 0, \
|
||||
0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0 } }
|
||||
|
||||
#define CPU_K6_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
{ { 1, 1, 1, 1, 1, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_K6_2_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 0, 0, 1, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
{ { 1, 1, 1, 1, 1, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_ATHLON_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 0, 1, 0, 1, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
{ { 1, 1, 1, 1, 1, 1, 0, 1, 1, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_K8_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0 } }
|
||||
{ { 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0 } }
|
||||
|
||||
#define CPU_AMDFAM10_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, \
|
||||
1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0 } }
|
||||
{ { 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, \
|
||||
1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0 } }
|
||||
|
||||
#define CPU_CLFLUSH_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_SYSCALL_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_MMX_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_SSE_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_SSE2_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_SSE3_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_SSSE3_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, 0, 0, 0, 0, 1, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, 0, 0, 0, 0, 1, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_SSE4_1_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, 0, 0, 0, 0, 1, \
|
||||
0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, 0, 0, 0, 0, 1, 0, \
|
||||
0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_SSE4_2_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, 0, 0, 0, 0, 1, \
|
||||
0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, 0, 0, 0, 0, 1, 0, \
|
||||
0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_VMX_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_SMX_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_XSAVE_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_AES_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, 0, 0, 0, 0, 1, \
|
||||
0, 0, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, 0, 0, 0, 0, 1, 0, \
|
||||
0, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_PCLMUL_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, 0, 0, 0, 0, 1, \
|
||||
0, 0, 1, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, 0, 0, 0, 0, 1, 0, \
|
||||
0, 1, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_FMA_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, 0, 0, 0, 0, 1, \
|
||||
0, 0, 1, 1, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, 0, 0, 0, 0, 1, 0, \
|
||||
0, 1, 1, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_MOVBE_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_RDTSCP_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_EPT_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_3DNOW_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_3DNOWA_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_PADLOCK_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_SVME_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_SSE4A_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, \
|
||||
1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 1, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_ABM_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_SSE5_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, \
|
||||
1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 1, \
|
||||
1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_AVX_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, 0, 0, 0, 0, 1, \
|
||||
0, 0, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, 0, 0, 0, 0, 1, 0, \
|
||||
0, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
|
||||
#define OPERAND_TYPE_NONE \
|
||||
|
||||
@ -42,14 +42,12 @@
|
||||
#define Cpu586 (Cpu486 + 1)
|
||||
/* i686 or better required */
|
||||
#define Cpu686 (Cpu586 + 1)
|
||||
/* Pentium4 or better required */
|
||||
#define CpuP4 (Cpu686 + 1)
|
||||
/* AMD K6 or better required*/
|
||||
#define CpuK6 (CpuP4 + 1)
|
||||
/* AMD K8 or better required */
|
||||
#define CpuK8 (CpuK6 + 1)
|
||||
/* CLFLUSH Instuction support required */
|
||||
#define CpuClflush (Cpu686 + 1)
|
||||
/* SYSCALL Instuctions support required */
|
||||
#define CpuSYSCALL (CpuClflush + 1)
|
||||
/* MMX support required */
|
||||
#define CpuMMX (CpuK8 + 1)
|
||||
#define CpuMMX (CpuSYSCALL + 1)
|
||||
/* SSE support required */
|
||||
#define CpuSSE (CpuMMX + 1)
|
||||
/* SSE2 support required */
|
||||
@ -126,9 +124,8 @@ typedef union i386_cpu_flags
|
||||
unsigned int cpui486:1;
|
||||
unsigned int cpui586:1;
|
||||
unsigned int cpui686:1;
|
||||
unsigned int cpup4:1;
|
||||
unsigned int cpuk6:1;
|
||||
unsigned int cpuk8:1;
|
||||
unsigned int cpuclflush:1;
|
||||
unsigned int cpusyscall:1;
|
||||
unsigned int cpummx:1;
|
||||
unsigned int cpusse:1;
|
||||
unsigned int cpusse2:1;
|
||||
|
||||
@ -909,11 +909,12 @@ fucompi, 1, 0xdfe8, None, 2, Cpu686, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|N
|
||||
|
||||
// Pentium4 extensions.
|
||||
|
||||
movnti, 2, 0xfc3, None, 2, CpuP4, Modrm|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
|
||||
clflush, 1, 0xfae, 0x7, 2, CpuP4, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Byte|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
|
||||
lfence, 0, 0xfae, 0xe8, 2, CpuP4, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { 0 }
|
||||
mfence, 0, 0xfae, 0xf0, 2, CpuP4, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { 0 }
|
||||
pause, 0, 0xf390, None, 2, CpuP4, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }
|
||||
movnti, 2, 0xfc3, None, 2, CpuSSE2, Modrm|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
|
||||
clflush, 1, 0xfae, 0x7, 2, CpuClflush, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Byte|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
|
||||
lfence, 0, 0xfae, 0xe8, 2, CpuSSE2, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { 0 }
|
||||
mfence, 0, 0xfae, 0xf0, 2, CpuSSE2, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { 0 }
|
||||
// Processors that do not support PAUSE treat this opcode as a NOP instruction.
|
||||
pause, 0, 0xf390, None, 2, Cpu186, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }
|
||||
|
||||
// MMX/SSE2 instructions.
|
||||
|
||||
@ -2488,9 +2489,9 @@ pmulhrw, 2, 0xf0f, 0xb7, 2, Cpu3dnow, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|N
|
||||
pswapd, 2, 0xf0f, 0xbb, 2, Cpu3dnowA, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX }
|
||||
|
||||
// AMD extensions.
|
||||
syscall, 0, 0xf05, None, 2, CpuK6, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }
|
||||
syscall, 0, 0xf05, None, 2, CpuSYSCALL, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }
|
||||
syscall, 0, 0xf05, None, 2, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }
|
||||
sysret, 0, 0xf07, None, 2, CpuK6, DefaultSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { 0 }
|
||||
sysret, 0, 0xf07, None, 2, CpuSYSCALL, DefaultSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { 0 }
|
||||
sysret, 0, 0xf07, None, 2, Cpu64, DefaultSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { 0 }
|
||||
swapgs, 0, 0xf01, 0xf8, 2, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { 0 }
|
||||
rdtscp, 0, 0xf01, 0xf9, 2, CpuRdtscp, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { 0 }
|
||||
|
||||
5822
opcodes/i386-tbl.h
5822
opcodes/i386-tbl.h
File diff suppressed because it is too large
Load Diff
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Reference in New Issue
Block a user