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Fix spurious check-ld failures on aarch64-elf

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ld/
	* testsuite/ld-aarch64/ifunc-1-local.d: Adjust regexps to match
	the offsets emitted by aarch64-elf configurations.
	* testsuite/ld-aarch64/ifunc-1.d: Likewise.
	* testsuite/ld-aarch64/ifunc-2-local.d: Likewise.
	* testsuite/ld-aarch64/ifunc-2.d: Likewise.
	* testsuite/ld-aarch64/ifunc-21.d: Likewise.
	* testsuite/ld-aarch64/ifunc-3a.d: Likewise.
This commit is contained in:
Roland McGrath 2018-08-01 13:36:51 -07:00
parent e256144888
commit c198a1ecf8
7 changed files with 24 additions and 14 deletions
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10
ld/ChangeLog
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@ -1,3 +1,13 @@
2018-08-01 Roland McGrath <mcgrathr@google.com>
* testsuite/ld-aarch64/ifunc-1-local.d: Adjust regexps to match
the offsets emitted by aarch64-elf configurations.
* testsuite/ld-aarch64/ifunc-1.d: Likewise.
* testsuite/ld-aarch64/ifunc-2-local.d: Likewise.
* testsuite/ld-aarch64/ifunc-2.d: Likewise.
* testsuite/ld-aarch64/ifunc-21.d: Likewise.
* testsuite/ld-aarch64/ifunc-3a.d: Likewise.
2018-08-01 Nick Clifton <nickc@redhat.com> 2018-08-01 Nick Clifton <nickc@redhat.com>
PR 23463 PR 23463

4
ld/testsuite/ld-aarch64/ifunc-1-local.d
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@ -3,7 +3,7 @@
#target: aarch64*-*-* #target: aarch64*-*-*
#... #...
0+(110|180) <__GI_foo>: 0+(110|180|1a0) <(__GI_)?foo>:
#... #...
[ \t0-9a-f]+:[ \t0-9a-f]+bl[ \t0-9a-f]+<\*ABS\*\+(0x110|0x180)@plt> [ \t0-9a-f]+:[ \t0-9a-f]+bl[ \t0-9a-f]+<\*ABS\*\+(0x110|0x180|0x1a0)@plt>
#pass #pass

4
ld/testsuite/ld-aarch64/ifunc-1.d
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@ -3,7 +3,7 @@
#target: aarch64*-*-* #target: aarch64*-*-*
#... #...
0+(130|1a0) <foo>: 0+(130|1a0|1c8) <foo>:
#... #...
[ \t0-9a-f]+:[ \t0-9a-f]+bl[ \t0-9a-f]+<\*ABS\*\+0x(130|1a0)@plt> [ \t0-9a-f]+:[ \t0-9a-f]+bl[ \t0-9a-f]+<\*ABS\*\+0x(130|1a0|1c8)@plt>
#pass #pass

6
ld/testsuite/ld-aarch64/ifunc-2-local.d
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@ -3,9 +3,9 @@
#target: aarch64*-*-* #target: aarch64*-*-*
#... #...
0+(110|180) <__GI_foo>: 0+(110|180|1a0) <__GI_foo>:
#... #...
[ \t0-9a-f]+:[ \t0-9a-f]+bl[ \t0-9a-f]+<\*ABS\*\+0x(110|180)@plt> [ \t0-9a-f]+:[ \t0-9a-f]+bl[ \t0-9a-f]+<\*ABS\*\+0x(110|180|1a0)@plt>
[ \t0-9a-f]+:[ \t0-9a-f]+adrp[ \t]+x0, 0 <.*> [ \t0-9a-f]+:[ \t0-9a-f]+adrp[ \t]+x0, 0 <.*>
[ \t0-9a-f]+:[ \t0-9a-f]+add[ \t]+x0, x0, #0x(100|170) [ \t0-9a-f]+:[ \t0-9a-f]+add[ \t]+x0, x0, #0x(100|170|190)
#pass #pass

6
ld/testsuite/ld-aarch64/ifunc-2.d
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@ -3,9 +3,9 @@
#target: aarch64*-*-* #target: aarch64*-*-*
#... #...
0+(130|1a0) <foo>: 0+(130|1a0|1c8) <foo>:
#... #...
[ \t0-9a-f]+:[ \t0-9a-f]+bl[ \t0-9a-f]+<\*ABS\*\+0x(130|1a0)@plt> [ \t0-9a-f]+:[ \t0-9a-f]+bl[ \t0-9a-f]+<\*ABS\*\+0x(130|1a0|1c8)@plt>
[ \t0-9a-f]+:[ \t0-9a-f]+adrp[ \t]+x0, 0 <.*> [ \t0-9a-f]+:[ \t0-9a-f]+adrp[ \t]+x0, 0 <.*>
[ \t0-9a-f]+:[ \t0-9a-f]+add[ \t]+x0, x0, #0x(120|190) [ \t0-9a-f]+:[ \t0-9a-f]+add[ \t]+x0, x0, #0x(120|190|1b8)
#pass #pass

4
ld/testsuite/ld-aarch64/ifunc-21.d
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@ -11,7 +11,7 @@ Contents of section .text:
[0-9a-f]+ .* [0-9a-f]+ .*
Contents of section .got.plt: Contents of section .got.plt:
[0-9a-f]+ 0+ 0+ 0+ 0+ .* [0-9a-f]+ 0+ 0+ 0+ 0+ .*
10298 0+ 0+ [0-9a-f]+ [0-9a-f]+ .* (10298|102b8) 0+ 0+ [0-9a-f]+ [0-9a-f]+ .*
Disassembly of section .text: Disassembly of section .text:
@ -20,7 +20,7 @@ Disassembly of section .text:
.* <bar>: .* <bar>:
.*: 90000080 adrp x0, 10000 <.*> .*: 90000080 adrp x0, 10000 <.*>
.*: .* ldr x0, \[x0, #672\] .*: .* ldr x0, \[x0, #(672|704)\]
.*: d65f03c0 ret .*: d65f03c0 ret
#pass #pass

4
ld/testsuite/ld-aarch64/ifunc-3a.d
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@ -4,7 +4,7 @@
#target: aarch64*-*-* #target: aarch64*-*-*
#... #...
0+(150|1d0) <__GI_foo>: 0+(150|1d0|1e8) <__GI_foo>:
#... #...
[ \t0-9a-f]+:[ \t0-9a-f]+bl[ \t0-9a-f]+<\*ABS\*\+0x(150|1d0)@plt> [ \t0-9a-f]+:[ \t0-9a-f]+bl[ \t0-9a-f]+<\*ABS\*\+0x(150|1d0|1e8)@plt>
#pass #pass