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aarch64: Fix PSEL opcode mask

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The opcode mask for PSEL was missing some bits, which meant
that some upcoming SME2 opcodes would be misinterpreted as PSELs.
This commit is contained in:
Richard Sandiford 2023-03-30 11:09:02 +01:00
parent 78addeae53
commit d346e1aafd
3 changed files with 9 additions and 1 deletions
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3
gas/testsuite/gas/aarch64/sme-9.d
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@ -71,3 +71,6 @@ Disassembly of section \.text:
f4: 44cbc544 uclamp z4.d, z10.d, z11.d
f8: 25277c61 psel p1, p15, p3.b\[w15, 0\]
fc: 252778a2 psel p2, p14, p5.b\[w15, 0\]
100: 25244200 \.inst 0x25244200 ; undefined
104: 25244010 \.inst 0x25244010 ; undefined
108: 25244210 \.inst 0x25244210 ; undefined

5
gas/testsuite/gas/aarch64/sme-9.s
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@ -84,3 +84,8 @@ foo .req p1
bar .req w15
psel foo, p15, p3.b[w15, 0]
psel p2, p14, p5.b[bar, 0]
// These were previously incorrectly decoded as PSELs.
.inst 0x25244200
.inst 0x25244010
.inst 0x25244210

2
opcodes/aarch64-tbl.h
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@ -5275,7 +5275,7 @@ const struct aarch64_opcode aarch64_opcode_table[] =
SME_INSNC ("revd", 0x52e8000, 0xffffe000, sme_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_QMQ, 0, C_SCAN_MOVPRFX, 0),
SME_INSNC ("sclamp", 0x4400c000, 0xff20fc00, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_BHSD, 0, C_SCAN_MOVPRFX, 0),
SME_INSNC ("uclamp", 0x4400c400, 0xff20fc00, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_BHSD, 0, C_SCAN_MOVPRFX, 0),
SME_INSN ("psel", 0x25204000, 0xff20c000, sme_misc, 0, OP3 (SVE_Pd, SVE_Pg4_10, SME_PnT_Wm_imm), OP_SVE_NN_BHSD, 0, 0),
SME_INSN ("psel", 0x25204000, 0xff20c210, sme_misc, 0, OP3 (SVE_Pd, SVE_Pg4_10, SME_PnT_Wm_imm), OP_SVE_NN_BHSD, 0, 0),
/* SIMD Dot Product (optional in v8.2-A). */
DOT_INSN ("udot", 0x2e009400, 0xbf20fc00, dotproduct, OP3 (Vd, Vn, Vm), QL_V3DOT, F_SIZEQ),