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sim: mips: clean up bad style/whitespace

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This doesn't fix all the problems, but grabs a bunch of the more
obvious ones.
This commit is contained in:
Mike Frysinger 2016-08-13 15:25:06 +08:00
parent efd811591c
commit d3eb0aa287
23 changed files with 345 additions and 345 deletions
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4
sim/mips/cp1.c
View File

@ -127,7 +127,7 @@ value_fpr (sim_cpu *cpu,
}
/* For values not yet accessed, set to the desired format. */
if (fmt < fmt_uninterpreted)
if (fmt < fmt_uninterpreted)
{
if (FPR_STATE[fpr] == fmt_uninterpreted)
{
@ -1119,7 +1119,7 @@ fp_binary_r(sim_cpu *cpu,
address_word cia,
int (*sim_fpu_op)(sim_fpu *, const sim_fpu *, const sim_fpu *),
unsigned64 op1,
unsigned64 op2)
unsigned64 op2)
{
sim_fpu wop1;
sim_fpu wop2;

2
sim/mips/cp1.h
View File

@ -23,7 +23,7 @@ along with this program. If not, see <http://www.gnu.org/licenses/>. */
#ifndef CP1_H
#define CP1_H
/* See sim-main.h for allocation of registers FCR0 and FCR31 (FCSR)
/* See sim-main.h for allocation of registers FCR0 and FCR31 (FCSR)
in CPU state (struct sim_cpu), and for FPU functions. */
#define fcsr_FCC_mask (0xFE800000)

8
sim/mips/dsp.igen
View File

@ -190,7 +190,7 @@
if (sat == 1)
{
if (setcond == 2)
h0 = 0x7fff;
h0 = 0x7fff;
else if (setcond == 1)
h0 = 0x8000;
}
@ -239,11 +239,11 @@
}
}
if (setcond == 2)
result = 0x7fffffff;
result = 0x7fffffff;
else if (setcond == 1)
result = 0x80000000;
else
result = v1 << shift;
result = v1 << shift;
GPR[rd] = EXTEND32 (result);
}
@ -1833,7 +1833,7 @@
result = 0x7fffffff;
else if (setcond == 2)
result = 0x80000000;
else
else
{
if (shift != 0)
result = ((result >> (shift - 1)) + 1) >> 1;

2
sim/mips/dsp2.igen
View File

@ -151,7 +151,7 @@
signed64 prod;
unsigned32 result;
w1 = (signed32) v1;
w2 = (signed32 )v2;
w2 = (signed32) v2;
if (w1 == (signed32) 0x80000000 && w2 == (signed32) 0x80000000)
{
DSPCR |= DSPCR_OUFLAG5;

34
sim/mips/dv-tx3904cpu.c
View File

@ -1,8 +1,8 @@
/* This file is part of the program GDB, the GNU debugger.
Copyright (C) 1998-2022 Free Software Foundation, Inc.
Contributed by Cygnus Solutions.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
@ -15,7 +15,7 @@
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
/* This must come before any other includes. */
@ -26,20 +26,20 @@
/* DEVICE
tx3904cpu - tx3904 cpu virtual device
DESCRIPTION
Implements the external tx3904 functionality. This includes the
delivery of of interrupts generated from other devices and the
handling of device specific registers.
PROPERTIES
none
@ -88,7 +88,7 @@ struct tx3904cpu {
/* input port ID's */
/* input port ID's */
enum {
RESET_PORT,
@ -170,13 +170,13 @@ deliver_tx3904cpu_interrupt (struct hw *me,
was cleared with a negative pending_level. */
CAUSE &= ~ (cause_IP_mask << cause_IP_shift);
if(controller->pending_level > 0) /* interrupt set */
if (controller->pending_level > 0) /* interrupt set */
{
/* set hardware-interrupt subfields of CAUSE register */
CAUSE |= (controller->pending_level & cause_IP_mask) << cause_IP_shift;
/* check for enabled / unmasked interrupts */
if((SR & status_IEc) &&
if ((SR & status_IEc) &&
(controller->pending_level & ((SR >> status_IM_shift) & status_IM_mask)))
{
controller->pending_level = 0;
@ -185,7 +185,7 @@ deliver_tx3904cpu_interrupt (struct hw *me,
else
{
/* reschedule soon */
if(controller->event != NULL)
if (controller->event != NULL)
hw_event_queue_deschedule(me, controller->event);
controller->event =
hw_event_queue_schedule (me, 1, deliver_tx3904cpu_interrupt, NULL);
@ -207,26 +207,26 @@ tx3904cpu_port_event (struct hw *me,
struct tx3904cpu *controller = hw_data (me);
switch (my_port)
{
{
case RESET_PORT:
controller->pending_reset = 1;
HW_TRACE ((me, "port-in reset"));
break;
case NMI_PORT:
controller->pending_nmi = 1;
HW_TRACE ((me, "port-in nmi"));
break;
case LEVEL_PORT:
/* level == 0 means that the interrupt was cleared */
if(level == 0)
if (level == 0)
controller->pending_level = -1; /* signal end of interrupt */
else
controller->pending_level = level;
HW_TRACE ((me, "port-in level=%d", level));
break;
default:
hw_abort (me, "bad switch");
break;
@ -234,7 +234,7 @@ tx3904cpu_port_event (struct hw *me,
/* Schedule an event to be delivered immediately after current
instruction. */
if(controller->event != NULL)
if (controller->event != NULL)
hw_event_queue_deschedule(me, controller->event);
controller->event =
hw_event_queue_schedule (me, 0, deliver_tx3904cpu_interrupt, NULL);

30
sim/mips/dv-tx3904irc.c
View File

@ -1,8 +1,8 @@
/* This file is part of the program GDB, the GNU debugger.
Copyright (C) 1998-2022 Free Software Foundation, Inc.
Contributed by Cygnus Solutions.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
@ -15,7 +15,7 @@
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
/* This must come before any other includes. */
@ -27,13 +27,13 @@
/* DEVICE
tx3904irc - tx3904 interrupt controller
DESCRIPTION
Implements the tx3904 interrupt controller described in the tx3904
user guide. It does not include the interrupt detection circuit
that preprocesses the eight external interrupts, so assumes that
@ -79,7 +79,7 @@
External interrupts. Level = 0 -> level interrupt cleared.
dmac0-3 (input)
DMA internal interrupts, correspond to DMA channels 0-3. Level = 0 -> level interrupt cleared.
@ -178,11 +178,11 @@ static const struct hw_port_descriptor tx3904irc_ports[] = {
struct tx3904irc {
address_word base_address; /* control register base */
unsigned_4 isr;
#define ISR_SET(c,s) ((c)->isr &= ~ (1 << (s)))
#define ISR_SET(c, s) ((c)->isr &= ~(1 << (s)))
unsigned_4 imr;
#define IMR_GET(c) ((c)->imr)
unsigned_4 ilr[4];
#define ILR_GET(c,s) LSEXTRACTED32((c)->ilr[(s)/4], (s) % 4 * 8 + 2, (s) % 4 * 8)
#define ILR_GET(c, s) LSEXTRACTED32((c)->ilr[(s) / 4], (s) % 4 * 8 + 2, (s) % 4 * 8)
};
@ -264,7 +264,7 @@ tx3904irc_port_event (struct hw *me,
struct tx3904irc *controller = hw_data (me);
/* handle deactivated interrupt */
if(level == 0)
if (level == 0)
{
HW_TRACE ((me, "interrupt cleared on port %d", my_port));
hw_port_event(me, IP_PORT, 0);
@ -273,7 +273,7 @@ tx3904irc_port_event (struct hw *me,
switch (my_port)
{
case INT0_PORT:
case INT0_PORT:
{
int ip_number = 32; /* compute IP[5:0] */
HW_TRACE ((me, "port-event INT[0]"));
@ -290,10 +290,10 @@ tx3904irc_port_event (struct hw *me,
HW_TRACE ((me, "interrupt asserted on port %d", source));
ISR_SET(controller, source);
if(ILR_GET(controller, source) > IMR_GET(controller))
if (ILR_GET(controller, source) > IMR_GET(controller))
{
int ip_number = 16 + source; /* compute IP[4:0] */
HW_TRACE ((me, "interrupt level %d", ILR_GET(controller,source)));
HW_TRACE ((me, "interrupt level %d", ILR_GET(controller, source)));
hw_port_event(me, IP_PORT, ip_number);
}
break;
@ -360,7 +360,7 @@ tx3904irc_io_read_buffer (struct hw *me,
}
return nr_bytes;
}
}
@ -405,7 +405,7 @@ tx3904irc_io_write_buffer (struct hw *me,
/* HW_TRACE ((me, "post: %08lx", (long) *register_ptr)); */
}
return nr_bytes;
}
}
const struct hw_descriptor dv_tx3904irc_descriptor[] = {

88
sim/mips/dv-tx3904sio.c
View File

@ -1,8 +1,8 @@
/* This file is part of the program GDB, the GNU debugger.
Copyright (C) 1998-2022 Free Software Foundation, Inc.
Contributed by Cygnus Solutions.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
@ -15,7 +15,7 @@
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
/* This must come before any other includes. */
@ -30,20 +30,20 @@
/* DEVICE
tx3904sio - tx3904 serial I/O
DESCRIPTION
Implements one tx3904 serial I/O controller described in the tx3904
user guide. Three instances are required for SIO0 and SIO1 within
the tx3904, at different base addresses.
Both internal and system clocks are synthesized as divided versions
of the simulator clock.
There is no support for:
- CTS/RTS flow control
- baud rate emulation - use infinite speed instead
@ -103,7 +103,7 @@ static void tx3904sio_poll(struct hw*, void* data);
/* register numbers; each is one word long */
enum
enum
{
SLCR_REG = 0,
SLSR_REG = 1,
@ -126,7 +126,7 @@ enum
};
static const struct hw_port_descriptor tx3904sio_ports[] =
static const struct hw_port_descriptor tx3904sio_ports[] =
{
{ "int", INT_PORT, 0, output_port, },
{ "reset", RESET_PORT, 0, input_port, },
@ -136,7 +136,7 @@ static const struct hw_port_descriptor tx3904sio_ports[] =
/* Generic FIFO */
struct tx3904sio_fifo
struct tx3904sio_fifo
{
int size, used;
unsigned_1 *buffer;
@ -147,7 +147,7 @@ struct tx3904sio_fifo
/* The timer/counter register internal state. Note that we store
state using the control register images, in host endian order. */
struct tx3904sio
struct tx3904sio
{
address_word base_address; /* control register base */
enum {sio_tcp, sio_stdio} backend; /* backend */
@ -226,12 +226,12 @@ attach_tx3904sio_regs (struct hw *me,
attach_space, attach_address, attach_size,
me);
if(hw_find_property(me, "backend") != NULL)
if (hw_find_property(me, "backend") != NULL)
{
const char* value = hw_find_string_property(me, "backend");
if(! strcmp(value, "tcp"))
if (!strcmp(value, "tcp"))
controller->backend = sio_tcp;
else if(! strcmp(value, "stdio"))
else if (!strcmp(value, "stdio"))
controller->backend = sio_stdio;
else
hw_abort(me, "illegal value for backend parameter `%s': use tcp or stdio", value);
@ -343,7 +343,7 @@ tx3904sio_io_read_buffer (struct hw *me,
case TFIFO_REG: register_value = 0; break;
case SFIFO_REG:
/* consume rx fifo for MS byte */
if(reg_offset == 0 && tx3904sio_fifo_nonempty(me, & controller->rx_fifo))
if (reg_offset == 0 && tx3904sio_fifo_nonempty(me, & controller->rx_fifo))
register_value = (tx3904sio_fifo_pop(me, & controller->rx_fifo) << 24);
else
register_value = 0;
@ -358,7 +358,7 @@ tx3904sio_io_read_buffer (struct hw *me,
}
return nr_bytes;
}
}
@ -394,7 +394,7 @@ tx3904sio_io_write_buffer (struct hw *me,
case SDICR_REG:
{
unsigned_4 last_int, next_int;
/* deassert interrupt upon clear */
last_int = controller->sdisr & controller->sdicr;
/* HW_TRACE ((me, "sdicr - sdisr %08x sdicr %08x",
@ -403,13 +403,13 @@ tx3904sio_io_write_buffer (struct hw *me,
/* HW_TRACE ((me, "sdicr + sdisr %08x sdicr %08x",
controller->sdisr, controller->sdicr)); */
next_int = controller->sdisr & controller->sdicr;
if(SDICR_GET_SDMAE(controller))
if (SDICR_GET_SDMAE(controller))
hw_abort(me, "Cannot support DMA-driven sio.");
if(~last_int & next_int) /* any bits set? */
if (~last_int & next_int) /* any bits set? */
hw_port_event(me, INT_PORT, 1);
if(last_int & ~next_int) /* any bits cleared? */
if (last_int & ~next_int) /* any bits cleared? */
hw_port_event(me, INT_PORT, 0);
}
break;
@ -420,41 +420,41 @@ tx3904sio_io_write_buffer (struct hw *me,
/* deassert interrupt upon clear */
last_int = controller->sdisr & controller->sdicr;
/* HW_TRACE ((me, "sdisr - sdisr %08x sdicr %08x",
/* HW_TRACE ((me, "sdisr - sdisr %08x sdicr %08x",
controller->sdisr, controller->sdicr)); */
SDISR_CLEAR_FLAG_BYTE(controller, reg_offset, write_byte);
/* HW_TRACE ((me, "sdisr + sdisr %08x sdicr %08x",
/* HW_TRACE ((me, "sdisr + sdisr %08x sdicr %08x",
controller->sdisr, controller->sdicr)); */
next_int = controller->sdisr & controller->sdicr;
if(~last_int & next_int) /* any bits set? */
if (~last_int & next_int) /* any bits set? */
hw_port_event(me, INT_PORT, 1);
if(last_int & ~next_int) /* any bits cleared? */
if (last_int & ~next_int) /* any bits cleared? */
hw_port_event(me, INT_PORT, 0);
}
break;
case SFCR_REG:
SFCR_SET_BYTE(controller, reg_offset, write_byte);
if(SFCR_GET_FRSTE(controller))
if (SFCR_GET_FRSTE(controller))
{
if(SFCR_GET_TFRST(controller)) tx3904sio_fifo_reset(me, & controller->tx_fifo);
if(SFCR_GET_RFRST(controller)) tx3904sio_fifo_reset(me, & controller->rx_fifo);
if (SFCR_GET_TFRST(controller)) tx3904sio_fifo_reset(me, & controller->tx_fifo);
if (SFCR_GET_RFRST(controller)) tx3904sio_fifo_reset(me, & controller->rx_fifo);
}
break;
case SBGR_REG:
SBGR_SET_BYTE(controller, reg_offset, write_byte);
break;
case SFIFO_REG: /* unwriteable */ break;
case TFIFO_REG:
if(reg_offset == 3) /* first byte */
case TFIFO_REG:
if (reg_offset == 3) /* first byte */
tx3904sio_fifo_push(me, & controller->tx_fifo, write_byte);
break;
default:
default:
HW_TRACE ((me, "write to illegal register %d", reg_number));
}
} /* loop over bytes */
@ -463,7 +463,7 @@ tx3904sio_io_write_buffer (struct hw *me,
tx3904sio_tickle(me);
return nr_bytes;
}
}
@ -481,7 +481,7 @@ tx3904sio_tickle(struct hw *me)
unsigned_4 last_int, next_int;
/* HW_TRACE ((me, "tickle backend: %02x", controller->backend)); */
switch(controller->backend)
switch (controller->backend)
{
case sio_tcp:
@ -529,20 +529,20 @@ tx3904sio_tickle(struct hw *me)
/* Update RDIS / TDIS flags */
last_int = controller->sdisr & controller->sdicr;
/* HW_TRACE ((me, "tickle - sdisr %08x sdicr %08x", controller->sdisr, controller->sdicr)); */
if(tx3904sio_fifo_nonempty(me, & controller->rx_fifo))
if (tx3904sio_fifo_nonempty(me, & controller->rx_fifo))
SDISR_SET_RDIS(controller);
if(! tx3904sio_fifo_nonempty(me, & controller->tx_fifo))
if (!tx3904sio_fifo_nonempty(me, & controller->tx_fifo))
SDISR_SET_TDIS(controller);
next_int = controller->sdisr & controller->sdicr;
/* HW_TRACE ((me, "tickle + sdisr %08x sdicr %08x", controller->sdisr, controller->sdicr)); */
if(~last_int & next_int) /* any bits set? */
if (~last_int & next_int) /* any bits set? */
hw_port_event(me, INT_PORT, 1);
if(last_int & ~next_int) /* any bits cleared? */
if (last_int & ~next_int) /* any bits cleared? */
hw_port_event(me, INT_PORT, 0);
/* Add periodic polling for this port, if it's not already going. */
if(controller->poll_event == NULL)
if (controller->poll_event == NULL)
{
controller->poll_event = hw_event_queue_schedule (me, 1000,
tx3904sio_poll, NULL);
@ -579,13 +579,13 @@ void
tx3904sio_fifo_push(struct hw* me, struct tx3904sio_fifo* fifo, char it)
{
/* HW_TRACE ((me, "push %02x -> fifo", it)); */
if(fifo->size == fifo->used) /* full */
if (fifo->size == fifo->used) /* full */
{
int next_size = fifo->size * 2 + 16;
unsigned_1* next_buf = zalloc(next_size);
memcpy(next_buf, fifo->buffer, fifo->used);
if(fifo->buffer != NULL) free(fifo->buffer);
if (fifo->buffer != NULL) free(fifo->buffer);
fifo->buffer = next_buf;
fifo->size = next_size;
}

118
sim/mips/dv-tx3904tmr.c
View File

@ -1,8 +1,8 @@
/* This file is part of the program GDB, the GNU debugger.
Copyright (C) 1998-2022 Free Software Foundation, Inc.
Contributed by Cygnus Solutions.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
@ -15,7 +15,7 @@
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
/* This must come before any other includes. */
@ -27,20 +27,20 @@
/* DEVICE
tx3904tmr - tx3904 timer
DESCRIPTION
Implements one tx3904 timer/counter described in the tx3904
user guide. Three instances are required for TMR0, TMR1, and
TMR3 within the tx3904, at different base addresses.
TMR3 within the tx3904, at different base addresses.
Both internal and system clocks are synthesized as divided versions
of the simulator clock.
There is no support for:
- edge sensitivity of external clock
- different mode restrictions for TMR0..2
@ -70,7 +70,7 @@
Rate of timer clock signal. This number is the number of simulator
ticks per clock signal tick. Default 1.
ext <ticks>
Rate of "external input clock signal", the other clock input of the
@ -108,7 +108,7 @@ static void deliver_tx3904tmr_tick (struct hw *me, void *data);
/* register numbers; each is one word long */
enum
enum
{
TCR_REG = 0,
TISR_REG = 1,
@ -133,7 +133,7 @@ enum
};
static const struct hw_port_descriptor tx3904tmr_ports[] =
static const struct hw_port_descriptor tx3904tmr_ports[] =
{
{ "int", INT_PORT, 0, output_port, },
{ "ff", FF_PORT, 0, output_port, },
@ -228,10 +228,10 @@ attach_tx3904tmr_regs (struct hw *me,
attach_space, attach_address, attach_size,
me);
if(hw_find_property(me, "clock") != NULL)
if (hw_find_property(me, "clock") != NULL)
controller->clock_ticks = (unsigned_4) hw_find_integer_property(me, "clock");
if(hw_find_property(me, "ext") != NULL)
if (hw_find_property(me, "ext") != NULL)
controller->ext_ticks = (unsigned_4) hw_find_integer_property(me, "ext");
controller->base_address = attach_address;
@ -258,12 +258,12 @@ tx3904tmr_finish (struct hw *me)
attach_tx3904tmr_regs (me, controller);
/* Initialize to reset state */
controller->tcr =
controller->tcr =
controller->itmr =
controller->ccdr =
controller->pmgr =
controller->pmgr =
controller->wtmr =
controller->tisr =
controller->tisr =
controller->trr = 0;
controller->cpra = controller->cprb = 0x00FFFFFF;
controller->ff = 0;
@ -293,16 +293,16 @@ tx3904tmr_port_event (struct hw *me,
/* preset flip-flop to FFI value */
controller->ff = GET_PMGR_FFI(controller);
controller->tcr =
controller->tcr =
controller->itmr =
controller->ccdr =
controller->pmgr =
controller->pmgr =
controller->wtmr =
controller->tisr =
controller->tisr =
controller->trr = 0;
controller->cpra = controller->cprb = 0x00FFFFFF;
controller->last_ticks = controller->roundoff_ticks = 0;
if(controller->event != NULL)
if (controller->event != NULL)
hw_event_queue_deschedule(me, controller->event);
controller->event = NULL;
break;
@ -355,7 +355,7 @@ tx3904tmr_io_read_buffer (struct hw *me,
}
return nr_bytes;
}
}
@ -381,13 +381,13 @@ tx3904tmr_io_write_buffer (struct hw *me,
switch (reg_number)
{
case TCR_REG:
if(reg_offset == 0) /* first byte */
if (reg_offset == 0) /* first byte */
{
/* update register, but mask out NOP bits */
controller->tcr = (unsigned_4) (write_byte & 0xef);
/* Reset counter value if timer suspended and CRE is set. */
if(GET_TCR_TCE(controller) == 0 &&
if (GET_TCR_TCE(controller) == 0 &&
GET_TCR_CRE(controller) == 1)
controller->trr = 0;
}
@ -395,11 +395,11 @@ tx3904tmr_io_write_buffer (struct hw *me,
break;
case ITMR_REG:
if(reg_offset == 1) /* second byte */
if (reg_offset == 1) /* second byte */
{
SET_ITMR_TIIE(controller, write_byte & 0x80);
}
else if(reg_offset == 0) /* first byte */
else if (reg_offset == 0) /* first byte */
{
SET_ITMR_TZCE(controller, write_byte & 0x01);
}
@ -407,7 +407,7 @@ tx3904tmr_io_write_buffer (struct hw *me,
break;
case CCDR_REG:
if(reg_offset == 0) /* first byte */
if (reg_offset == 0) /* first byte */
{
controller->ccdr = write_byte & 0x07;
}
@ -415,12 +415,12 @@ tx3904tmr_io_write_buffer (struct hw *me,
break;
case PMGR_REG:
if(reg_offset == 1) /* second byte */
if (reg_offset == 1) /* second byte */
{
SET_PMGR_TPIBE(controller, write_byte & 0x80);
SET_PMGR_TPIAE(controller, write_byte & 0x40);
}
else if(reg_offset == 0) /* first byte */
else if (reg_offset == 0) /* first byte */
{
SET_PMGR_FFI(controller, write_byte & 0x01);
}
@ -428,11 +428,11 @@ tx3904tmr_io_write_buffer (struct hw *me,
break;
case WTMR_REG:
if(reg_offset == 1) /* second byte */
if (reg_offset == 1) /* second byte */
{
SET_WTMR_TWIE(controller, write_byte & 0x80);
}
else if(reg_offset == 0) /* first byte */
else if (reg_offset == 0) /* first byte */
{
SET_WTMR_WDIS(controller, write_byte & 0x80);
SET_WTMR_TWC(controller, write_byte & 0x01);
@ -441,17 +441,17 @@ tx3904tmr_io_write_buffer (struct hw *me,
break;
case TISR_REG:
if(reg_offset == 0) /* first byte */
if (reg_offset == 0) /* first byte */
{
/* All bits must be zero in given byte, according to
spec. */
/* Send an "interrupt off" event on the interrupt port */
if(controller->tisr != 0) /* any interrupts active? */
if (controller->tisr != 0) /* any interrupts active? */
{
hw_port_event(me, INT_PORT, 0);
hw_port_event (me, INT_PORT, 0);
}
/* clear interrupt status register */
controller->tisr = 0;
}
@ -459,7 +459,7 @@ tx3904tmr_io_write_buffer (struct hw *me,
break;
case CPRA_REG:
if(reg_offset < 3) /* first, second, or third byte */
if (reg_offset < 3) /* first, second, or third byte */
{
MBLIT32(controller->cpra, (reg_offset*8)+7, (reg_offset*8), write_byte);
}
@ -467,14 +467,14 @@ tx3904tmr_io_write_buffer (struct hw *me,
break;
case CPRB_REG:
if(reg_offset < 3) /* first, second, or third byte */
if (reg_offset < 3) /* first, second, or third byte */
{
MBLIT32(controller->cprb, (reg_offset*8)+7, (reg_offset*8), write_byte);
}
/* HW_TRACE ((me, "cprb: %08lx", (long) controller->cprb)); */
break;
default:
default:
HW_TRACE ((me, "write to illegal register %d", reg_number));
}
} /* loop over bytes */
@ -484,7 +484,7 @@ tx3904tmr_io_write_buffer (struct hw *me,
hw_event_queue_schedule(me, 1, deliver_tx3904tmr_tick, NULL);
return nr_bytes;
}
}
@ -502,7 +502,7 @@ deliver_tx3904tmr_tick (struct hw *me,
signed_8 quotient, remainder;
/* compute simulation ticks between last tick and this tick */
if(controller->last_ticks != 0)
if (controller->last_ticks != 0)
warp = this_ticks - controller->last_ticks + controller->roundoff_ticks;
else
{
@ -510,31 +510,31 @@ deliver_tx3904tmr_tick (struct hw *me,
warp = controller->roundoff_ticks;
}
if(controller->event != NULL)
if (controller->event != NULL)
hw_event_queue_deschedule(me, controller->event);
controller->event = NULL;
/* Check whether the timer ticking is enabled at this moment. This
largely a function of the TCE bit, but is also slightly
mode-dependent. */
switch((int) GET_TCR_TMODE(controller))
switch ((int) GET_TCR_TMODE(controller))
{
case 0: /* interval */
/* do not advance counter if TCE = 0 or if holding at count = CPRA */
if(GET_TCR_TCE(controller) == 0 ||
if (GET_TCR_TCE(controller) == 0 ||
controller->trr == controller->cpra)
return;
break;
case 1: /* pulse generator */
/* do not advance counter if TCE = 0 */
if(GET_TCR_TCE(controller) == 0)
if (GET_TCR_TCE(controller) == 0)
return;
break;
case 2: /* watchdog */
/* do not advance counter if TCE = 0 and WDIS = 1 */
if(GET_TCR_TCE(controller) == 0 &&
if (GET_TCR_TCE(controller) == 0 &&
GET_WTMR_WDIS(controller) == 1)
return;
break;
@ -550,11 +550,11 @@ deliver_tx3904tmr_tick (struct hw *me,
reschedule dummy events here. */
/* find appropriate divisor etc. */
if(GET_TCR_CCS(controller) == 0) /* internal system clock */
/* find appropriate divisor etc. */
if (GET_TCR_CCS(controller) == 0) /* internal system clock */
{
/* apply internal clock divider */
if(GET_TCR_CCDE(controller)) /* divisor circuit enabled? */
if (GET_TCR_CCDE(controller)) /* divisor circuit enabled? */
divisor = controller->clock_ticks * (1 << (1 + GET_CCDR_CDR(controller)));
else
divisor = controller->clock_ticks;
@ -582,8 +582,8 @@ deliver_tx3904tmr_tick (struct hw *me,
/* next 24-bit counter value */
unsigned_4 next_trr = (controller->trr + 1) % (1 << 24);
quotient --;
switch((int) GET_TCR_TMODE(controller))
switch ((int) GET_TCR_TMODE(controller))
{
case 0: /* interval timer mode */
{
@ -591,11 +591,11 @@ deliver_tx3904tmr_tick (struct hw *me,
first case covers counter holding at maximum before
reset. The second case covers normal counting
behavior. */
if(controller->trr == controller->cpra ||
if (controller->trr == controller->cpra ||
next_trr == controller->cpra)
{
/* likely hold CPRA value */
if(controller->trr == controller->cpra)
if (controller->trr == controller->cpra)
next_trr = controller->cpra;
SET_TISR_TIIS(controller);
@ -603,14 +603,14 @@ deliver_tx3904tmr_tick (struct hw *me,
/* Signal an interrupt if it is enabled with TIIE,
and if we just arrived at CPRA. Don't repeatedly
interrupt if holding due to TZCE=0 */
if(GET_ITMR_TIIE(controller) &&
if (GET_ITMR_TIIE(controller) &&
next_trr != controller->trr)
{
hw_port_event(me, INT_PORT, 1);
}
/* Reset counter? */
if(GET_ITMR_TZCE(controller))
if (GET_ITMR_TZCE(controller))
{
next_trr = 0;
}
@ -621,7 +621,7 @@ deliver_tx3904tmr_tick (struct hw *me,
case 1: /* pulse generator mode */
{
/* first trip point */
if(next_trr == controller->cpra)
if (next_trr == controller->cpra)
{
/* flip flip-flop & report */
controller->ff ^= 1;
@ -629,14 +629,14 @@ deliver_tx3904tmr_tick (struct hw *me,
SET_TISR_TPIAS(controller);
/* signal interrupt */
if(GET_PMGR_TPIAE(controller))
if (GET_PMGR_TPIAE(controller))
{
hw_port_event(me, INT_PORT, 1);
}
}
/* second trip point */
else if(next_trr == controller->cprb)
else if (next_trr == controller->cprb)
{
/* flip flip-flop & report */
controller->ff ^= 1;
@ -644,7 +644,7 @@ deliver_tx3904tmr_tick (struct hw *me,
SET_TISR_TPIBS(controller);
/* signal interrupt */
if(GET_PMGR_TPIBE(controller))
if (GET_PMGR_TPIBE(controller))
{
hw_port_event(me, INT_PORT, 1);
}
@ -658,12 +658,12 @@ deliver_tx3904tmr_tick (struct hw *me,
case 2: /* watchdog timer mode */
{
/* watchdog timer expiry */
if(next_trr == controller->cpra)
if (next_trr == controller->cpra)
{
SET_TISR_TWIS(controller);
/* signal interrupt */
if(GET_WTMR_TWIE(controller))
if (GET_WTMR_TWIE(controller))
{
hw_port_event(me, INT_PORT, 1);
}

146
sim/mips/interp.c
View File

@ -69,7 +69,7 @@ char* pr_uword64 (uword64 addr);
#define RSVD_INSTRUCTION_MASK (0xFC00003F)
#define RSVD_INSTRUCTION_ARG_SHIFT 6
#define RSVD_INSTRUCTION_ARG_MASK 0xFFFFF
#define RSVD_INSTRUCTION_ARG_MASK 0xFFFFF
/* Bits in the Debug register */
@ -122,13 +122,13 @@ static void ColdReset (SIM_DESC sd);
#define K1SIZE (0x20000000)
/* Simple run-time monitor support.
We emulate the monitor by placing magic reserved instructions at
the monitor's entry points; when we hit these instructions, instead
of raising an exception (as we would normally), we look at the
instruction and perform the appropriate monitory operation.
`*_monitor_base' are the physical addresses at which the corresponding
`*_monitor_base' are the physical addresses at which the corresponding
monitor vectors are located. `0' means none. By default,
install all three.
The RSVD_INSTRUCTION... macros specify the magic instructions we
@ -245,7 +245,7 @@ Re-compile simulator with \"-DWITH_TRACE_ANY_P\" to enable this option.\n");
display_mem_info = 1;
break;
}
return SIM_RC_OK;
}
@ -288,7 +288,7 @@ static const OPTION mips_options[] =
'\0', NULL, "List configured memory regions", mips_option_handler },
{ { "memory-info", no_argument, NULL, OPTION_INFO_MEMORY },
'\0', NULL, NULL, mips_option_handler },
{ {NULL, no_argument, NULL, 0}, '\0', NULL, NULL, NULL }
};
@ -364,7 +364,7 @@ sim_open (SIM_OPEN_KIND kind, host_callback *cb,
CPU_MAX_INSNS (cpu) = nr_itable_entries;
STATE = 0;
if (sim_pre_argv_init (sd, argv[0]) != SIM_RC_OK)
return 0;
sim_add_option_table (sd, NULL, mips_options);
@ -430,7 +430,7 @@ sim_open (SIM_OPEN_KIND kind, host_callback *cb,
/* Delete old region. */
sim_do_commandf (sd, "memory delete %d:0x%" PRIxTW "@%d",
match->space, match->addr, match->level);
}
}
else if (mem_size == 0)
mem_size = MEM_SIZE;
/* Limit to KSEG1 size (512MB) */
@ -455,13 +455,13 @@ sim_open (SIM_OPEN_KIND kind, host_callback *cb,
/* ROM: 0x9FC0_0000 - 0x9FFF_FFFF and 0xBFC0_0000 - 0xBFFF_FFFF */
sim_do_commandf (sd, "memory alias 0x%x@1,0x%x,0x%0x",
0x9FC00000,
0x9FC00000,
4 * 1024 * 1024, /* 4 MB */
0xBFC00000);
/* SRAM: 0x8000_0000 - 0x803F_FFFF and 0xA000_0000 - 0xA03F_FFFF */
sim_do_commandf (sd, "memory alias 0x%x@1,0x%x,0x%0x",
0x80000000,
0x80000000,
4 * 1024 * 1024, /* 4 MB */
0xA0000000);
@ -470,8 +470,8 @@ sim_open (SIM_OPEN_KIND kind, host_callback *cb,
{
unsigned size = 4 * 1024 * 1024; /* 4 MB */
sim_do_commandf (sd, "memory alias 0x%x@1,0x%x,0x%0x",
0x88000000 + (i * size),
size,
0x88000000 + (i * size),
size,
0xA8000000 + (i * size));
}
}
@ -501,13 +501,13 @@ sim_open (SIM_OPEN_KIND kind, host_callback *cb,
/* ROM: 0x9FC0_0000 - 0x9FFF_FFFF and 0xBFC0_0000 - 0xBFFF_FFFF */
sim_do_commandf (sd, "memory alias 0x%x@1,0x%x,0x%0x",
0x9FC00000,
0x9FC00000,
4 * 1024 * 1024, /* 4 MB */
0xBFC00000);
/* SRAM: 0x8000_0000 - 0x803F_FFFF and 0xA000_0000 - 0xA03F_FFFF */
sim_do_commandf (sd, "memory alias 0x%x@1,0x%x,0x%0x",
0x80000000,
0x80000000,
4 * 1024 * 1024, /* 4 MB */
0xA0000000);
@ -516,8 +516,8 @@ sim_open (SIM_OPEN_KIND kind, host_callback *cb,
{
unsigned size = 4 * 1024 * 1024; /* 4 MB */
sim_do_commandf (sd, "memory alias 0x%x@1,0x%x,0x%0x",
0x88000000 + (i * size),
size,
0x88000000 + (i * size),
size,
0xA8000000 + (i * size));
}
@ -566,7 +566,7 @@ sim_open (SIM_OPEN_KIND kind, host_callback *cb,
sim_hw_parse (sd, "/tx3904sio@0xfffff400 > int sio1 /tx3904irc");
/* add PAL timer & I/O module */
if(! strcmp(board, BOARD_JMR3904_PAL))
if (!strcmp(board, BOARD_JMR3904_PAL))
{
/* the device */
sim_hw_parse (sd, "/pal@0xffff0000");
@ -578,7 +578,7 @@ sim_open (SIM_OPEN_KIND kind, host_callback *cb,
sim_hw_parse (sd, "/pal@0x31000000 > int int0 /tx3904irc");
}
if(! strcmp(board, BOARD_JMR3904_DEBUG))
if (!strcmp(board, BOARD_JMR3904_DEBUG))
{
/* -- DEBUG: glue interrupt generators --- */
sim_hw_parse (sd, "/glue@0xffff0000/reg 0xffff0000 0x50");
@ -688,9 +688,9 @@ sim_open (SIM_OPEN_KIND kind, host_callback *cb,
open_trace(sd);
/*
sim_io_eprintf (sd, "idt@%x pmon@%x lsipmon@%x\n",
sim_io_eprintf (sd, "idt@%x pmon@%x lsipmon@%x\n",
idt_monitor_base,
pmon_monitor_base,
pmon_monitor_base,
lsipmon_monitor_base);
*/
@ -783,8 +783,8 @@ sim_open (SIM_OPEN_KIND kind, host_callback *cb,
/* Write an abort sequence into the TRAP (common) exception vector
addresses. This is to catch code executing a TRAP (et.al.)
instruction without installing a trap handler. */
if ((idt_monitor_base != 0) ||
(pmon_monitor_base != 0) ||
if ((idt_monitor_base != 0) ||
(pmon_monitor_base != 0) ||
(lsipmon_monitor_base != 0))
{
unsigned32 halt[2] = { 0x2404002f /* addiu r4, r0, 47 */,
@ -868,7 +868,7 @@ mips_reg_store (SIM_CPU *cpu, int rn, unsigned char *memory, int length)
{
if (length == 8)
{
cpu->fgr[rn - FGR_BASE] =
cpu->fgr[rn - FGR_BASE] =
(unsigned32) T2H_8 (*(unsigned64*)memory);
return 8;
}
@ -1096,7 +1096,7 @@ sim_firmware_command (SIM_DESC sd, char *arg)
p ++; /* skip over @ */
address = strtoul (p, &q, 0);
if (*q != '\0')
if (*q != '\0')
{
sim_io_printf (sd, "Invalid address given to the"
"`sim firmware NAME@ADDRESS' command: %s\n",
@ -1152,7 +1152,7 @@ Recognized firmware names are: `idt', `pmon', `lsipmon', and `none'.\n",
arg);
return SIM_RC_FAIL;
}
return SIM_RC_OK;
}
@ -1340,7 +1340,7 @@ sim_monitor (SIM_DESC sd,
sim_memopt *entry, *match = NULL;
/* Search for memory region mapped to KSEG0 or KSEG1. */
for (entry = STATE_MEMOPT (sd);
for (entry = STATE_MEMOPT (sd);
entry != NULL;
entry = entry->next)
{
@ -1350,7 +1350,7 @@ sim_monitor (SIM_DESC sd,
else
{
sim_memopt *alias;
for (alias = entry->alias;
for (alias = entry->alias;
alias != NULL;
alias = alias->next)
if ((alias->addr == K0BASE || alias->addr == K1BASE)
@ -1374,7 +1374,7 @@ sim_monitor (SIM_DESC sd,
/* sim_io_eprintf (sd, "sim: get_mem_info() deprecated\n"); */
break;
}
case 158: /* PMON printf */
/* in: A0 = pointer to format string */
/* A1 = optional argument 1 */
@ -1666,11 +1666,11 @@ mips16_entry (SIM_DESC sd,
FPR_STATE[0] = fmt_uninterpreted;
FPR_STATE[1] = fmt_uninterpreted;
}
}
}
PC = RA;
}
}
/*-- trace support ----------------------------------------------------------*/
@ -1723,7 +1723,7 @@ dotrace (SIM_DESC sd,
{
if (STATE & simTRACE) {
va_list ap;
fprintf(tracefh,"%d %s ; width %d ; ",
fprintf(tracefh,"%d %s ; width %d ; ",
type,
pr_addr(address),
width);
@ -1764,19 +1764,19 @@ ColdReset (SIM_DESC sd)
/* RESET: Fixed PC address: */
PC = (unsigned_word) UNSIGNED64 (0xFFFFFFFFBFC00000);
/* The reset vector address is in the unmapped, uncached memory space. */
SR &= ~(status_SR | status_TS | status_RP);
SR |= (status_ERL | status_BEV);
/* Cheat and allow access to the complete register set immediately */
if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT
&& WITH_TARGET_WORD_BITSIZE == 64)
SR |= status_FR; /* 64bit registers */
/* Ensure that any instructions with pending register updates are
cleared: */
PENDING_INVALIDATE();
/* Initialise the FPU registers to the unknown state */
if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT)
{
@ -1784,7 +1784,7 @@ ColdReset (SIM_DESC sd)
for (rn = 0; (rn < 32); rn++)
FPR_STATE[rn] = fmt_uninterpreted;
}
/* Initialise the Config0 register. */
C0_CONFIG = 0x80000000 /* Config1 present */
| 2; /* KSEG0 uncached */
@ -1838,7 +1838,7 @@ signal_exception (SIM_DESC sd,
if (INDELAYSLOT())
{
CANCELDELAYSLOT();
Debug |= Debug_DBD; /* signaled from within in delay slot */
DEPC = cia - 4; /* reference the branch instruction */
}
@ -1847,7 +1847,7 @@ signal_exception (SIM_DESC sd,
Debug &= ~Debug_DBD; /* not signaled from within a delay slot */
DEPC = cia;
}
Debug |= Debug_DM; /* in debugging mode */
Debug |= Debug_DBp; /* raising a DBp exception */
PC = 0xBFC00200;
@ -1991,7 +1991,7 @@ signal_exception (SIM_DESC sd,
case FPE:
sim_engine_halt (SD, CPU, NULL, PC,
sim_stopped, SIM_SIGFPE);
case BreakPoint:
sim_engine_halt (SD, CPU, NULL, PC, sim_stopped, SIM_SIGTRAP);
break;
@ -2040,7 +2040,7 @@ signal_exception (SIM_DESC sd,
that are UNPREDICTABLE. ..." (MIPS64 Architecture for Programmers
Volume II, The MIPS64 Instruction Set. MIPS Document MD00087 revision
0.95, page 2.)
For UNPREDICTABLE behaviour, we print a message, if possible print
the offending instructions mips.igen instruction name (provided by
the caller), and stop the simulator.
@ -2106,7 +2106,7 @@ cop_ld (SIM_DESC sd,
{
#ifdef DEBUG
printf("DBG: COP_LD: coproc_num = %d, coproc_reg = %d, value = 0x%s : PC = 0x%s\n", coproc_num, coproc_reg, pr_uword64(memword), pr_addr(cia) );
printf("DBG: COP_LD: coproc_num = %d, coproc_reg = %d, value = 0x%s : PC = 0x%s\n", coproc_num, coproc_reg, pr_uword64(memword), pr_addr(cia));
#endif
switch (coproc_num) {
@ -2314,7 +2314,7 @@ decode_coproc (SIM_DESC sd,
/* 29 = TagHi R4000 VR4100 VR4300 */
/* 30 = ErrorEPC R4000 VR4100 VR4300 */
if (STATE_VERBOSE_P(SD))
sim_io_eprintf (SD,
sim_io_eprintf (SD,
"Warning: PC 0x%lx:interp.c decode_coproc DEADC0DE\n",
(unsigned long)cia);
GPR[rt] = 0xDEADC0DE; /* CPR[0,rd] */
@ -2343,10 +2343,10 @@ decode_coproc (SIM_DESC sd,
cfg = C0_CONFIG;
break;
case 1:
/* MIPS32 r/o Config1:
/* MIPS32 r/o Config1:
Config2 present */
cfg = 0x80000000;
/* MIPS16 implemented.
/* MIPS16 implemented.
XXX How to check configuration? */
cfg |= 0x0000004;
if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT)
@ -2354,12 +2354,12 @@ decode_coproc (SIM_DESC sd,
cfg |= 0x00000021;
break;
case 2:
/* MIPS32 r/o Config2:
/* MIPS32 r/o Config2:
Config3 present. */
cfg = 0x80000000;
break;
case 3:
/* MIPS32 r/o Config3:
/* MIPS32 r/o Config3:
SmartMIPS implemented. */
cfg = 0x00000002;
break;
@ -2408,26 +2408,26 @@ decode_coproc (SIM_DESC sd,
read/modify/write sequence fails. */
}
break;
case 2: /* co-processor 2 */
{
int handle = 0;
if(! handle)
if (!handle)
{
sim_io_eprintf(sd, "COP2 instruction 0x%08X at PC = 0x%s : No handler present\n",
instruction,pr_addr(cia));
}
}
break;
case 1: /* should not occur (FPU co-processor) */
case 3: /* should not occur (FPU co-processor) */
SignalException(ReservedInstruction,instruction);
break;
}
return;
}
@ -2445,14 +2445,14 @@ get_cell (void)
static int cell=0;
if (++cell>=NUMCELLS) cell=0;
return buf[cell];
}
}
/* Print routines to handle variable size regs, etc */
/* Eliminate warning from compiler on 32-bit systems */
static int thirty_two = 32;
static int thirty_two = 32;
char*
char*
pr_addr (SIM_ADDR addr)
{
char *paddr_str=get_cell();
@ -2474,7 +2474,7 @@ pr_addr (SIM_ADDR addr)
return paddr_str;
}
char*
char*
pr_uword64 (uword64 addr)
{
char *paddr_str=get_cell();
@ -2501,7 +2501,7 @@ mips_core_signal (SIM_DESC sd,
{
case sim_core_unmapped_signal:
sim_io_eprintf (sd, "mips-core: %d byte %s to unmapped address 0x%lx at 0x%lx\n",
nr_bytes, copy,
nr_bytes, copy,
(unsigned long) addr, (unsigned long) ip);
COP0_BADVADDR = addr;
SignalExceptionDataReference();
@ -2509,10 +2509,10 @@ mips_core_signal (SIM_DESC sd,
case sim_core_unaligned_signal:
sim_io_eprintf (sd, "mips-core: %d byte %s to unaligned address 0x%lx at 0x%lx\n",
nr_bytes, copy,
nr_bytes, copy,
(unsigned long) addr, (unsigned long) ip);
COP0_BADVADDR = addr;
if(transfer == read_transfer)
if (transfer == read_transfer)
SignalExceptionAddressLoad();
else
SignalExceptionAddressStore();
@ -2530,8 +2530,8 @@ mips_cpu_exception_trigger(SIM_DESC sd, sim_cpu* cpu, address_word cia)
{
ASSERT(cpu != NULL);
if(cpu->exc_suspended > 0)
sim_io_eprintf(sd, "Warning, nested exception triggered (%d)\n", cpu->exc_suspended);
if (cpu->exc_suspended > 0)
sim_io_eprintf(sd, "Warning, nested exception triggered (%d)\n", cpu->exc_suspended);
PC = cia;
memcpy(cpu->exc_trigger_registers, cpu->registers, sizeof(cpu->exc_trigger_registers));
@ -2543,9 +2543,9 @@ mips_cpu_exception_suspend(SIM_DESC sd, sim_cpu* cpu, int exception)
{
ASSERT(cpu != NULL);
if(cpu->exc_suspended > 0)
sim_io_eprintf(sd, "Warning, nested exception signal (%d then %d)\n",
cpu->exc_suspended, exception);
if (cpu->exc_suspended > 0)
sim_io_eprintf(sd, "Warning, nested exception signal (%d then %d)\n",
cpu->exc_suspended, exception);
memcpy(cpu->exc_suspend_registers, cpu->registers, sizeof(cpu->exc_suspend_registers));
memcpy(cpu->registers, cpu->exc_trigger_registers, sizeof(cpu->registers));
@ -2557,26 +2557,26 @@ mips_cpu_exception_resume(SIM_DESC sd, sim_cpu* cpu, int exception)
{
ASSERT(cpu != NULL);
if(exception == 0 && cpu->exc_suspended > 0)
if (exception == 0 && cpu->exc_suspended > 0)
{
/* warn not for breakpoints */
if(cpu->exc_suspended != sim_signal_to_host(sd, SIM_SIGTRAP))
if (cpu->exc_suspended != sim_signal_to_host(sd, SIM_SIGTRAP))
sim_io_eprintf(sd, "Warning, resuming but ignoring pending exception signal (%d)\n",
cpu->exc_suspended);
cpu->exc_suspended);
}
else if(exception != 0 && cpu->exc_suspended > 0)
else if (exception != 0 && cpu->exc_suspended > 0)
{
if(exception != cpu->exc_suspended)
if (exception != cpu->exc_suspended)
sim_io_eprintf(sd, "Warning, resuming with mismatched exception signal (%d vs %d)\n",
cpu->exc_suspended, exception);
memcpy(cpu->registers, cpu->exc_suspend_registers, sizeof(cpu->registers));
cpu->exc_suspended, exception);
memcpy(cpu->registers, cpu->exc_suspend_registers, sizeof(cpu->registers));
}
else if(exception != 0 && cpu->exc_suspended == 0)
else if (exception != 0 && cpu->exc_suspended == 0)
{
sim_io_eprintf(sd, "Warning, ignoring spontanous exception signal (%d)\n", exception);
sim_io_eprintf(sd, "Warning, ignoring spontanous exception signal (%d)\n", exception);
}
cpu->exc_suspended = 0;
cpu->exc_suspended = 0;
}

10
sim/mips/m16.igen
View File

@ -860,7 +860,7 @@
{
do_dsll (SD_, TRY, TRX, SHIFT);
}
11110,5.SHAMT_4_0,1.S5,00000 + 00110,3.RX,3.RY,000,01:EXT-SHIFT:16::DSLL
"dsll r<TRY>, r<TRX>, <SHAMT>"
*mips16:
@ -868,9 +868,9 @@
{
do_dsll (SD_, TRY, TRX, SHAMT);
}
11101,3.SHAMT,3.RY,01000:SHIFT64:16::DSRL
"dsrl r<TRY>, <SHIFT>"
*mips16:
@ -1043,7 +1043,7 @@
STATE &= ~simDELAYSLOT;
return target;
}
// compute basepc dependant on us being in a delay slot
:function:::address_word:basepc:
{

54
sim/mips/m16e.igen
View File

@ -2,11 +2,11 @@
// Simulator definition for the MIPS16e instructions.
// Copyright (C) 2005-2022 Free Software Foundation, Inc.
// Contributed by Nigel Stephens (nigel@mips.com) and
// Contributed by Nigel Stephens (nigel@mips.com) and
// David Ung (davidu@mips.com) of MIPS Technologies.
//
// This file is part of GDB, the GNU debugger.
//
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 3 of the License, or
@ -168,7 +168,7 @@
:function:::void:do_save:int xsregs, int aregs, int ras0s1, int framesize
{
unsigned_word temp;
unsigned_word temp;
int args, astatic;
temp = GPR[29];
@ -194,11 +194,11 @@
sim_engine_abort (SD, CPU, CIA, "save: aregs=%d causes unpredictable results\n", aregs);
}
if (args > 0) {
do_store (SD_, AccessLength_WORD, temp, 0, GPR[4]);
do_store (SD_, AccessLength_WORD, temp, 0, GPR[4]);
if (args > 1) {
do_store (SD_,AccessLength_WORD, temp, 4 , GPR[5]);
do_store (SD_,AccessLength_WORD, temp, 4 , GPR[5]);
if (args > 2) {
do_store (SD_,AccessLength_WORD, temp, 8 , GPR[6]);
do_store (SD_,AccessLength_WORD, temp, 8 , GPR[6]);
if (args > 3) {
do_store (SD_,AccessLength_WORD, temp, 12, GPR[7]);
}
@ -207,29 +207,29 @@
}
if (ras0s1 & 4)
do_store (SD_,AccessLength_WORD, temp -= 4, 0, GPR[31]);
do_store (SD_,AccessLength_WORD, temp -= 4, 0, GPR[31]);
switch (xsregs) {
case 7:
do_store (SD_,AccessLength_WORD, temp -= 4, 0, GPR[30]);
do_store (SD_,AccessLength_WORD, temp -= 4, 0, GPR[30]);
case 6:
do_store (SD_,AccessLength_WORD, temp -= 4, 0, GPR[23]);
do_store (SD_,AccessLength_WORD, temp -= 4, 0, GPR[23]);
case 5:
do_store (SD_,AccessLength_WORD, temp -= 4, 0, GPR[22]);
do_store (SD_,AccessLength_WORD, temp -= 4, 0, GPR[22]);
case 4:
do_store (SD_,AccessLength_WORD, temp -= 4, 0, GPR[21]);
do_store (SD_,AccessLength_WORD, temp -= 4, 0, GPR[21]);
case 3:
do_store (SD_,AccessLength_WORD, temp -= 4, 0, GPR[20]);
do_store (SD_,AccessLength_WORD, temp -= 4, 0, GPR[20]);
case 2:
do_store (SD_,AccessLength_WORD, temp -= 4, 0, GPR[19]);
do_store (SD_,AccessLength_WORD, temp -= 4, 0, GPR[19]);
case 1:
do_store (SD_,AccessLength_WORD, temp -= 4, 0, GPR[18]);
do_store (SD_,AccessLength_WORD, temp -= 4, 0, GPR[18]);
}
if (ras0s1 & 1)
do_store (SD_,AccessLength_WORD, temp -= 4, 0, GPR[17]);
do_store (SD_,AccessLength_WORD, temp -= 4, 0, GPR[17]);
if (ras0s1 & 2)
do_store (SD_,AccessLength_WORD, temp -= 4, 0, GPR[16]);
do_store (SD_,AccessLength_WORD, temp -= 4, 0, GPR[16]);
switch (aregs) {
case 0: case 4: case 8: case 12: case 14:
@ -285,7 +285,7 @@
:function:::void:do_restore:int xsregs, int aregs, int ras0s1, int framesize
*mips16e
{
unsigned_word temp, temp2;
unsigned_word temp, temp2;
int astatic;
temp = GPR[29] + framesize;
@ -298,25 +298,25 @@
switch (xsregs) {
case 7:
GPR[30] = EXTEND32 (do_load (SD_,AccessLength_WORD, temp -= 4, 0));
GPR[30] = EXTEND32 (do_load (SD_,AccessLength_WORD, temp -= 4, 0));
case 6:
GPR[23] = EXTEND32 (do_load (SD_,AccessLength_WORD, temp -= 4, 0));
GPR[23] = EXTEND32 (do_load (SD_,AccessLength_WORD, temp -= 4, 0));
case 5:
GPR[22] = EXTEND32 (do_load (SD_,AccessLength_WORD, temp -= 4, 0));
GPR[22] = EXTEND32 (do_load (SD_,AccessLength_WORD, temp -= 4, 0));
case 4:
GPR[21] = EXTEND32 (do_load (SD_,AccessLength_WORD, temp -= 4, 0));
GPR[21] = EXTEND32 (do_load (SD_,AccessLength_WORD, temp -= 4, 0));
case 3:
GPR[20] = EXTEND32 (do_load (SD_,AccessLength_WORD, temp -= 4, 0));
GPR[20] = EXTEND32 (do_load (SD_,AccessLength_WORD, temp -= 4, 0));
case 2:
GPR[19] = EXTEND32 (do_load (SD_,AccessLength_WORD, temp -= 4, 0));
GPR[19] = EXTEND32 (do_load (SD_,AccessLength_WORD, temp -= 4, 0));
case 1:
GPR[18] = EXTEND32 (do_load (SD_,AccessLength_WORD, temp -= 4, 0));
GPR[18] = EXTEND32 (do_load (SD_,AccessLength_WORD, temp -= 4, 0));
}
if (ras0s1 & 1)
GPR[17] = EXTEND32 (do_load (SD_,AccessLength_WORD, temp -= 4, 0));
GPR[17] = EXTEND32 (do_load (SD_,AccessLength_WORD, temp -= 4, 0));
if (ras0s1 & 2)
GPR[16] = EXTEND32 (do_load (SD_,AccessLength_WORD, temp -= 4, 0));
GPR[16] = EXTEND32 (do_load (SD_,AccessLength_WORD, temp -= 4, 0));
switch (aregs) {
case 0: case 4: case 8: case 12: case 14:
@ -356,7 +356,7 @@
01100,100,0,3.RAS,4.FS:I8:16::RESTORE
"restore %s<RAS>,<SFRAME>"
*mips16e
{
{
do_restore (SD_,0,0,RAS,SFRAME);
}

4
sim/mips/m16run.c
View File

@ -11,10 +11,10 @@
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, see <http://www.gnu.org/licenses/>.
*/
/* This must come before any other includes. */

16
sim/mips/mdmx.c
View File

@ -40,16 +40,16 @@ along with this program. If not, see <http://www.gnu.org/licenses/>. */
The 24-bit accumulators are signed and are represented as 32-bit
signed values, which are reduced to 24-bit signed values prior to
Round and Clamp operations.
A 16-bit packed halfword element (QH) is always signed.
The 48-bit accumulators are signed and are represented as 64-bit
signed values, which are reduced to 48-bit signed values prior to
Round and Clamp operations.
The code below assumes a 2's-complement representation of signed
quantities. Care is required to clear extended sign bits when
repacking fields.
The code (and the code for arithmetic shifts in mips.igen) also makes
the (not guaranteed portable) assumption that right shifts of signed
quantities in C do sign extension. */
@ -374,7 +374,7 @@ mdmx_cpr_op(sim_cpu *cpu,
int op,
unsigned64 op1,
int vt,
MX_fmtsel fmtsel)
MX_fmtsel fmtsel)
{
unsigned64 op2;
unsigned64 result = 0;
@ -849,7 +849,7 @@ mdmx_acc_op(sim_cpu *cpu,
int op,
unsigned64 op1,
int vt,
MX_fmtsel fmtsel)
MX_fmtsel fmtsel)
{
unsigned64 op2;
@ -897,7 +897,7 @@ unsigned64
mdmx_rac_op(sim_cpu *cpu,
address_word cia,
int op,
int fmt)
int fmt)
{
unsigned64 result;
unsigned int shift;
@ -935,7 +935,7 @@ mdmx_wacl(sim_cpu *cpu,
address_word cia,
int fmt,
unsigned64 vs,
unsigned64 vt)
unsigned64 vt)
{
int i;
@ -1330,7 +1330,7 @@ mdmx_round_op(sim_cpu *cpu,
address_word cia,
int rm,
int vt,
MX_fmtsel fmtsel)
MX_fmtsel fmtsel)
{
unsigned64 op2;
unsigned64 result = 0;

2
sim/mips/mdmx.igen
View File

@ -6,7 +6,7 @@
// Corporation (SiByte).
//
// This file is part of GDB, the GNU debugger.
//
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 3 of the License, or

6
sim/mips/micromips.igen
View File

@ -85,7 +85,7 @@
*micromips32:
*micromips64:
{
switch(reg)
switch (reg)
{
case 0: return 0;
case 1: return 17;
@ -1311,7 +1311,7 @@
{
if (lwmregs & 0x10)
{
switch(lwmregs & 0xf)
switch (lwmregs & 0xf)
{
case 0:
return "ra";
@ -1339,7 +1339,7 @@
}
else
{
switch(lwmregs & 0xf)
switch (lwmregs & 0xf)
{
case 1:
return "s0";

12
sim/mips/mips.igen
View File

@ -4921,7 +4921,7 @@
do_xori (SD_, RS, RT, IMMEDIATE);
}
//
// MIPS Architecture:
//
@ -5730,7 +5730,7 @@
PENDING_FILL (RT, v);
TRACE_ALU_RESULT (v);
}
010001,00000,5.RT,5.FS,00000000000:COP1:32,f::MFC1b
"mfc1 r<RT>, f<FS>"
*mipsIV:
@ -5742,7 +5742,7 @@
*vr4100:
*vr5000:
*r3900:
{
{
do_mfc1b (SD_, RT, FS);
}
@ -5851,14 +5851,14 @@
*mipsI:
*mipsII:
*mipsIII:
{
{
check_fpu (SD_);
if (SizeFGR () == 64)
PENDING_FILL ((FS + FGR_BASE), (SET64HI (0xDEADC0DE) | VL4_8 (GPR[RT])));
else
PENDING_FILL ((FS + FGR_BASE), VL4_8 (GPR[RT]));
TRACE_FP_RESULT (GPR[RT]);
}
}
010001,00100,5.RT,5.FS,00000000000:COP1:32,f::MTC1b
"mtc1 r<RT>, f<FS>"
@ -6229,7 +6229,7 @@
do_trunc_fmt (SD_, fmt_word, FMT, FD, FS);
}
//
// MIPS Architecture:
//

2
sim/mips/mips3264r2.igen
View File

@ -5,7 +5,7 @@
// Contributed by David Ung, of MIPS Technologies.
//
// This file is part of the MIPS sim.
//
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 3 of the License, or

2
sim/mips/mips3d.igen
View File

@ -6,7 +6,7 @@
// Corporation (SiByte).
//
// This file is part of GDB, the GNU debugger.
//
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 3 of the License, or

2
sim/mips/sb1.igen
View File

@ -6,7 +6,7 @@
// Corporation (SiByte).
//
// This file is part of GDB, the GNU debugger.
//
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 3 of the License, or

126
sim/mips/sim-main.c
View File

@ -82,7 +82,7 @@ load_memory (SIM_DESC SD,
}
dotrace (SD, CPU, tracefh,((IorD == isDATA) ? 0 : 2),(unsigned int)(pAddr&0xFFFFFFFF),(AccessLength + 1),"load%s",((IorD == isDATA) ? "" : " instruction"));
/* Read the specified number of bytes from memory. Adjust for
host/target byte ordering/ Align the least significant byte
read. */
@ -123,12 +123,12 @@ load_memory (SIM_DESC SD,
default:
abort ();
}
#ifdef DEBUG
printf("DBG: LoadMemory() : (offset %d) : value = 0x%s%s\n",
(int)(pAddr & LOADDRMASK),pr_uword64(value1),pr_uword64(value));
#endif /* DEBUG */
/* See also store_memory. Position data in correct byte lanes. */
if (AccessLength <= LOADDRMASK)
{
@ -141,12 +141,12 @@ load_memory (SIM_DESC SD,
is already in the correct postition. */
value <<= ((pAddr & LOADDRMASK) * 8);
}
#ifdef DEBUG
printf("DBG: LoadMemory() : shifted value = 0x%s%s\n",
pr_uword64(value1),pr_uword64(value));
#endif /* DEBUG */
*memvalp = value;
if (memval1p) *memval1p = value1;
}
@ -179,24 +179,24 @@ store_memory (SIM_DESC SD,
#ifdef DEBUG
sim_io_printf(sd,"DBG: StoreMemory(%d,%d,0x%s,0x%s,0x%s,0x%s)\n",CCA,AccessLength,pr_uword64(MemElem),pr_uword64(MemElem1),pr_addr(pAddr),pr_addr(vAddr));
#endif /* DEBUG */
#if defined(WARN_MEM)
if (CCA != uncached)
sim_io_eprintf(sd,"StoreMemory CCA (%d) is not uncached (currently all accesses treated as cached)\n",CCA);
#endif /* WARN_MEM */
if (((pAddr & LOADDRMASK) + AccessLength) > LOADDRMASK)
sim_io_error (SD, "STORE AccessLength of %d would extend over %d bit aligned boundary for physical address 0x%s\n",
AccessLength,
(LOADDRMASK + 1) << 3,
pr_addr(pAddr));
dotrace (SD, CPU, tracefh,1,(unsigned int)(pAddr&0xFFFFFFFF),(AccessLength + 1),"store");
#ifdef DEBUG
printf("DBG: StoreMemory: offset = %d MemElem = 0x%s%s\n",(unsigned int)(pAddr & LOADDRMASK),pr_uword64(MemElem1),pr_uword64(MemElem));
#endif /* DEBUG */
/* See also load_memory. Position data in correct byte lanes. */
if (AccessLength <= LOADDRMASK)
{
@ -209,11 +209,11 @@ store_memory (SIM_DESC SD,
is already in the correct postition. */
MemElem >>= ((pAddr & LOADDRMASK) * 8);
}
#ifdef DEBUG
printf("DBG: StoreMemory: shift = %d MemElem = 0x%s%s\n",shift,pr_uword64(MemElem1),pr_uword64(MemElem));
#endif /* DEBUG */
switch (AccessLength)
{
case AccessLength_QUADWORD:
@ -248,8 +248,8 @@ store_memory (SIM_DESC SD,
break;
default:
abort ();
}
}
return;
}
@ -375,7 +375,7 @@ cache_op (SIM_DESC SD,
case 3: /* Create Dirty */
case 4: /* Hit Invalidate */
case 5: /* Hit Writeback Invalidate */
case 6: /* Hit Writeback */
case 6: /* Hit Writeback */
if (!dcache_warning)
{
sim_io_eprintf(SD,"Data CACHE operation %d to be coded\n",(op >> 2));
@ -403,24 +403,24 @@ pending_tick (SIM_DESC SD,
sim_cpu *CPU,
address_word cia)
{
if (PENDING_TRACE)
sim_io_eprintf (SD, "PENDING_DRAIN - 0x%lx - pending_in = %d, pending_out = %d, pending_total = %d\n", (unsigned long) cia, PENDING_IN, PENDING_OUT, PENDING_TOTAL);
if (PENDING_OUT != PENDING_IN)
{
int loop;
int index = PENDING_OUT;
int total = PENDING_TOTAL;
if (PENDING_TOTAL == 0)
sim_engine_abort (SD, CPU, cia, "PENDING_DRAIN - Mis-match on pending update pointers\n");
if (PENDING_TRACE)
sim_io_eprintf (SD, "PENDING_DRAIN - 0x%lx - pending_in = %d, pending_out = %d, pending_total = %d\n", (unsigned long) cia, PENDING_IN, PENDING_OUT, PENDING_TOTAL);
if (PENDING_OUT != PENDING_IN)
{
int loop;
int index = PENDING_OUT;
int total = PENDING_TOTAL;
if (PENDING_TOTAL == 0)
sim_engine_abort (SD, CPU, cia, "PENDING_DRAIN - Mis-match on pending update pointers\n");
for (loop = 0, index = PENDING_OUT;
(loop < total);
loop++, index = (index + 1) % PSLOTS)
{
if (PENDING_SLOT_DEST[index] != NULL)
{
PENDING_SLOT_DELAY[index] -= 1;
if (PENDING_SLOT_DELAY[index] == 0)
{
{
if (PENDING_SLOT_DEST[index] != NULL)
{
PENDING_SLOT_DELAY[index] -= 1;
if (PENDING_SLOT_DELAY[index] == 0)
{
if (PENDING_TRACE)
sim_io_eprintf (SD, "PENDING_DRAIN - drained - index %d, dest %p, bit %d, val %" PRIx64 ", size %d\n",
index,
@ -428,45 +428,45 @@ pending_tick (SIM_DESC SD,
PENDING_SLOT_BIT[index],
PENDING_SLOT_VALUE[index],
PENDING_SLOT_SIZE[index]);
if (PENDING_SLOT_BIT[index] >= 0)
switch (PENDING_SLOT_SIZE[index])
{
if (PENDING_SLOT_BIT[index] >= 0)
switch (PENDING_SLOT_SIZE[index])
{
case 4:
if (PENDING_SLOT_VALUE[index])
*(unsigned32*)PENDING_SLOT_DEST[index] |=
BIT32 (PENDING_SLOT_BIT[index]);
else
*(unsigned32*)PENDING_SLOT_DEST[index] &=
BIT32 (PENDING_SLOT_BIT[index]);
break;
case 8:
if (PENDING_SLOT_VALUE[index])
*(unsigned64*)PENDING_SLOT_DEST[index] |=
BIT64 (PENDING_SLOT_BIT[index]);
else
*(unsigned64*)PENDING_SLOT_DEST[index] &=
BIT64 (PENDING_SLOT_BIT[index]);
break;
if (PENDING_SLOT_VALUE[index])
*(unsigned32*)PENDING_SLOT_DEST[index] |=
BIT32 (PENDING_SLOT_BIT[index]);
else
*(unsigned32*)PENDING_SLOT_DEST[index] &=
BIT32 (PENDING_SLOT_BIT[index]);
break;
case 8:
if (PENDING_SLOT_VALUE[index])
*(unsigned64*)PENDING_SLOT_DEST[index] |=
BIT64 (PENDING_SLOT_BIT[index]);
else
*(unsigned64*)PENDING_SLOT_DEST[index] &=
BIT64 (PENDING_SLOT_BIT[index]);
break;
}
else
switch (PENDING_SLOT_SIZE[index])
{
case 4:
*(unsigned32*)PENDING_SLOT_DEST[index] =
PENDING_SLOT_VALUE[index];
break;
case 8:
*(unsigned64*)PENDING_SLOT_DEST[index] =
PENDING_SLOT_VALUE[index];
break;
}
switch (PENDING_SLOT_SIZE[index])
{
case 4:
*(unsigned32*)PENDING_SLOT_DEST[index] =
PENDING_SLOT_VALUE[index];
break;
case 8:
*(unsigned64*)PENDING_SLOT_DEST[index] =
PENDING_SLOT_VALUE[index];
break;
}
if (PENDING_OUT == index)
{
PENDING_SLOT_DEST[index] = NULL;
PENDING_OUT = (PENDING_OUT + 1) % PSLOTS;
PENDING_TOTAL--;
}
}
}
else if (PENDING_TRACE && PENDING_SLOT_DELAY[index] > 0)
sim_io_eprintf (SD, "PENDING_DRAIN - queued - index %d, delay %d, dest %p, bit %d, val %" PRIx64 ", size %d\n",
index, PENDING_SLOT_DELAY[index],
@ -475,9 +475,9 @@ pending_tick (SIM_DESC SD,
PENDING_SLOT_VALUE[index],
PENDING_SLOT_SIZE[index]);
}
}
}
}
}
}
}

14
sim/mips/sim-main.h
View File

@ -238,7 +238,7 @@ enum float_operation
};
/* The internal representation of an MDMX accumulator.
/* The internal representation of an MDMX accumulator.
Note that 24 and 48 bit accumulator elements are represented in
32 or 64 bits. Since the accumulators are 2's complement with
overflow suppressed, high-order bits can be ignored in most contexts. */
@ -246,13 +246,13 @@ enum float_operation
typedef signed32 signed24;
typedef signed64 signed48;
typedef union {
typedef union {
signed24 ob[8];
signed48 qh[4];
signed48 qh[4];
} MDMX_accumulator;
/* Conventional system arguments. */
/* Conventional system arguments. */
#define SIM_STATE sim_cpu *cpu, address_word cia
#define SIM_ARGS CPU, cia
@ -446,7 +446,7 @@ struct _sim_cpu {
pending_write_queue pending;
/* The MDMX accumulator (used only for MDMX ASE). */
MDMX_accumulator acc;
MDMX_accumulator acc;
#define ACC ((CPU)->acc)
/* LLBIT = Load-Linked bit. A bit of "virtual" state used by atomic
@ -632,7 +632,7 @@ enum ExceptionCause {
/* The following break instructions are reserved for use by the
simulator. The first is used to halt the simulation. The second
is used by gdb for break-points. NOTE: Care must be taken, since
is used by gdb for break-points. NOTE: Care must be taken, since
this value may be used in later revisions of the MIPS ISA. */
#define HALT_INSTRUCTION_MASK (0x03FFFFC0)
@ -697,7 +697,7 @@ void decode_coproc (SIM_DESC sd, sim_cpu *cpu, address_word cia,
(rt), (rd), (sel))
int sim_monitor (SIM_DESC sd, sim_cpu *cpu, address_word cia, unsigned int arg);
/* FPR access. */
unsigned64 value_fpr (SIM_STATE, int fpr, FP_formats);

4
sim/mips/smartmips.igen
View File

@ -2,11 +2,11 @@
//
// Simulator definition for the SmartMIPS extensions.
// Copyright (C) 2005-2022 Free Software Foundation, Inc.
// Contributed by Nigel Stephens (nigel@mips.com) and
// Contributed by Nigel Stephens (nigel@mips.com) and
// David Ung (davidu@mips.com) of MIPS Technologies.
//
// This file is part of GDB, the GNU debugger.
//
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 3 of the License, or

4
sim/mips/tx.igen
View File

@ -16,7 +16,7 @@
LO = EXTEND32 (prod);
HI = EXTEND32 (VH4_8 (prod));
TRACE_ALU_RESULT2 (HI, LO);
if(RD != 0 )
if (RD != 0)
GPR[RD] = LO;
}
@ -34,7 +34,7 @@
LO = EXTEND32 (prod);
HI = EXTEND32 (VH4_8 (prod));
TRACE_ALU_RESULT2 (HI, LO);
if(RD != 0)
if (RD != 0)
GPR[RD] = LO;
}