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RISC-V: Add support for the Zvksc ISA extension

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Zvksc is part of the vector crypto extensions.

Zvksc is shorthand for the following set of extensions:
- Zvks
- Zvbc

bfd/ChangeLog:

	* elfxx-riscv.c: Define Zvksc extension.

gas/ChangeLog:

	* testsuite/gas/riscv/zvksc.d: New test.
	* testsuite/gas/riscv/zvksc.s: New test.

Signed-off-by: Nathan Huckleberry <nhuck@google.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
This commit is contained in:
Nathan Huckleberry 2023-06-30 22:44:42 +02:00 committed by Jeff Law
parent 937cc1c690
commit d556141eb1
3 changed files with 31 additions and 0 deletions
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3
bfd/elfxx-riscv.c
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@ -1169,6 +1169,8 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] =
{"zvks", "zvbb", check_implicit_always},
{"zvksg", "zvks", check_implicit_always},
{"zvksg", "zvkg", check_implicit_always},
{"zvksc", "zvks", check_implicit_always},
{"zvksc", "zvbc", check_implicit_always},
{"smaia", "ssaia", check_implicit_always},
{"smstateen", "ssstateen", check_implicit_always},
{"smepmp", "zicsr", check_implicit_always},
@ -1288,6 +1290,7 @@ static struct riscv_supported_ext riscv_supported_std_z_ext[] =
{"zvksh", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zvks", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zvksg", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zvksc", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zvl32b", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zvl64b", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zvl128b", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },

18
gas/testsuite/gas/riscv/zvksc.d Normal file
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@ -0,0 +1,18 @@
#as: -march=rv64gc_zvksc
#objdump: -dr
.*:[ ]+file format .*
Disassembly of section .text:
0+000 <.text>:
[ ]+[0-9a-f]+:[ ]+86802277[ ]+vsm4k.vi[ ]+v4,v8,0
[ ]+[0-9a-f]+:[ ]+ae802277[ ]+vsm3c.vi[ ]+v4,v8,0
[ ]+[0-9a-f]+:[ ]+32862257[ ]+vclmul.vv[ ]+v4,v8,v12
[ ]+[0-9a-f]+:[ ]+30862257[ ]+vclmul.vv[ ]+v4,v8,v12,v0.t
[ ]+[0-9a-f]+:[ ]+3285e257[ ]+vclmul.vx[ ]+v4,v8,a1
[ ]+[0-9a-f]+:[ ]+3085e257[ ]+vclmul.vx[ ]+v4,v8,a1,v0.t
[ ]+[0-9a-f]+:[ ]+36862257[ ]+vclmulh.vv[ ]+v4,v8,v12
[ ]+[0-9a-f]+:[ ]+34862257[ ]+vclmulh.vv[ ]+v4,v8,v12,v0.t
[ ]+[0-9a-f]+:[ ]+3685e257[ ]+vclmulh.vx[ ]+v4,v8,a1
[ ]+[0-9a-f]+:[ ]+3485e257[ ]+vclmulh.vx[ ]+v4,v8,a1,v0.t

10
gas/testsuite/gas/riscv/zvksc.s Normal file
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@ -0,0 +1,10 @@
vsm4k.vi v4, v8, 0
vsm3c.vi v4, v8, 0
vclmul.vv v4, v8, v12
vclmul.vv v4, v8, v12, v0.t
vclmul.vx v4, v8, a1
vclmul.vx v4, v8, a1, v0.t
vclmulh.vv v4, v8, v12
vclmulh.vv v4, v8, v12, v0.t
vclmulh.vx v4, v8, a1
vclmulh.vx v4, v8, a1, v0.t