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aarch64: Add new SVE dot-product instructions

Browse Source 
This patch adds the SVE FDOT, SDOT and UDOT instructions,
which are available when FEAT_SME2 is implemented.  The patch
also reorders the existing SVE_Zm3_22_INDEX to keep the
operands numerically sorted.
This commit is contained in:
Richard Sandiford 2023-03-30 11:09:17 +01:00
parent 6a245d9941
commit dfc12f9f53
16 changed files with 1111 additions and 854 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
gas/config/tc-aarch64.c
View File

@ -6732,6 +6732,7 @@ parse_operands (char *str, const aarch64_opcode *opcode)
case AARCH64_OPND_SVE_Zm3_INDEX:
case AARCH64_OPND_SVE_Zm3_22_INDEX:
case AARCH64_OPND_SVE_Zm3_19_INDEX:
case AARCH64_OPND_SVE_Zm3_11_INDEX:
case AARCH64_OPND_SVE_Zm4_11_INDEX:
case AARCH64_OPND_SVE_Zm4_INDEX:

16
gas/testsuite/gas/aarch64/sve-invalid.l
View File

@ -1155,14 +1155,10 @@
.*: Info: sdot z0\.d, z1\.h, z2\.h
.*: Error: operand mismatch -- `sdot z0\.h,z1\.h,z2\.h'
.*: Info: did you mean this\?
.*: Info: sdot z0\.d, z1\.h, z2\.h
.*: Info: other valid variant\(s\):
.*: Info: sdot z0\.s, z1\.b, z2\.b
.*: Info: sdot z0\.s, z1\.h, z2\.h
.*: Error: operand mismatch -- `sdot z0\.s,z1\.s,z2\.s'
.*: Info: did you mean this\?
.*: Info: sdot z0\.s, z1\.b, z2\.b
.*: Info: other valid variant\(s\):
.*: Info: sdot z0\.d, z1\.h, z2\.h
.*: Info: sdot z0\.s, z1\.h, z2\.h
.*: Error: operand mismatch -- `sdot z0\.d,z1\.d,z2\.d'
.*: Info: did you mean this\?
.*: Info: sdot z0\.d, z1\.h, z2\.h
@ -1187,14 +1183,10 @@
.*: Info: udot z0\.d, z1\.h, z2\.h
.*: Error: operand mismatch -- `udot z0\.h,z1\.h,z2\.h'
.*: Info: did you mean this\?
.*: Info: udot z0\.d, z1\.h, z2\.h
.*: Info: other valid variant\(s\):
.*: Info: udot z0\.s, z1\.b, z2\.b
.*: Info: udot z0\.s, z1\.h, z2\.h
.*: Error: operand mismatch -- `udot z0\.s,z1\.s,z2\.s'
.*: Info: did you mean this\?
.*: Info: udot z0\.s, z1\.b, z2\.b
.*: Info: other valid variant\(s\):
.*: Info: udot z0\.d, z1\.h, z2\.h
.*: Info: udot z0\.s, z1\.h, z2\.h
.*: Error: operand mismatch -- `udot z0\.d,z1\.d,z2\.d'
.*: Info: did you mean this\?
.*: Info: udot z0\.d, z1\.h, z2\.h

3
gas/testsuite/gas/aarch64/sve2-sme2-4-invalid.d Normal file
View File

@ -0,0 +1,3 @@
#as: -march=armv8-a+sme2
#source: sve2-sme2-4-invalid.s
#error_output: sve2-sme2-4-invalid.l

17
gas/testsuite/gas/aarch64/sve2-sme2-4-invalid.l Normal file
View File

@ -0,0 +1,17 @@
[^ :]+: Assembler messages:
[^ :]+:[0-9]+: Error: expected a register at operand 1 -- `fdot 0,z0\.h,z0\.h\[0\]'
[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `fdot z0\.s,0,z0\.h\[0\]'
[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `fdot z0\.s,z0\.h,0'
[^ :]+:[0-9]+: Error: z0-z7 expected at operand 3 -- `fdot z0\.s,z0\.h,z8\.h\[0\]'
[^ :]+:[0-9]+: Error: register element index out of range 0 to 3 at operand 3 -- `fdot z0\.s,z0\.h,z0\.h\[-1\]'
[^ :]+:[0-9]+: Error: register element index out of range 0 to 3 at operand 3 -- `fdot z0\.s,z0\.h,z0\.h\[4\]'
[^ :]+:[0-9]+: Error: operand mismatch -- `fdot z0\.h,z0\.h,z0\.h\[0\]'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: fdot z0\.s, z0\.h, z0\.h\[0\]
[^ :]+:[0-9]+: Error: operand mismatch -- `fdot z0\.d,z0\.h,z0\.h\[0\]'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: fdot z0\.s, z0\.h, z0\.h\[0\]
[^ :]+:[0-9]+: Warning: output register of preceding `movprfx' used as input at operand 2 -- `fdot z0\.s,z0\.h,z1\.h\[0\]'
[^ :]+:[0-9]+: Warning: output register of preceding `movprfx' not used in current instruction at operand 1 -- `fdot z0\.s,z1\.h,z2\.h\[0\]'
[^ :]+:[0-9]+: Warning: predicated instruction expected after `movprfx' -- `fdot z0\.s,z1\.h,z2\.h\[0\]'
[^ :]+:[0-9]+: Warning: predicated instruction expected after `movprfx' -- `fdot z0\.s,z1\.h,z2\.h\[0\]'

15
gas/testsuite/gas/aarch64/sve2-sme2-4-invalid.s Normal file
View File

@ -0,0 +1,15 @@
fdot 0, z0.h, z0.h[0]
fdot z0.s, 0, z0.h[0]
fdot z0.s, z0.h, 0
fdot z0.s, z0.h, z8.h[0]
fdot z0.s, z0.h, z0.h[-1]
fdot z0.s, z0.h, z0.h[4]
fdot z0.h, z0.h, z0.h[0]
fdot z0.d, z0.h, z0.h[0]
movprfx z0, z1; fdot z0.s, z0.h, z1.h[0]
movprfx z0, z1; fdot z0.s, z1.h, z0.h[0]
movprfx z3, z4; fdot z0.s, z1.h, z2.h[0]
movprfx z0.s, p0/m, z1.s; fdot z0.s, z1.h, z2.h[0]
movprfx z0.s, p0/z, z1.s; fdot z0.s, z1.h, z2.h[0]

3
gas/testsuite/gas/aarch64/sve2-sme2-4-noarch.d Normal file
View File

@ -0,0 +1,3 @@
#as: -march=armv8-a+sme
#source: sve2-sme2-4.s
#error_output: sve2-sme2-4-noarch.l

40
gas/testsuite/gas/aarch64/sve2-sme2-4-noarch.l Normal file
View File

@ -0,0 +1,40 @@
[^ :]+: Assembler messages:
[^ :]+:[0-9]+: Error: selected processor does not support `fdot z0\.s,z0\.h,z0\.h\[0\]'
[^ :]+:[0-9]+: Error: selected processor does not support `fdot Z0\.S,Z0\.H,Z0\.H\[0\]'
[^ :]+:[0-9]+: Error: selected processor does not support `fdot z31\.s,z0\.h,z0\.h\[0\]'
[^ :]+:[0-9]+: Error: selected processor does not support `fdot z0\.s,z31\.h,z0\.h\[0\]'
[^ :]+:[0-9]+: Error: selected processor does not support `fdot z0\.s,z0\.h,z7\.h\[0\]'
[^ :]+:[0-9]+: Error: selected processor does not support `fdot z0\.s,z0\.h,z0\.h\[3\]'
[^ :]+:[0-9]+: Error: selected processor does not support `fdot z0\.s,z1\.h,z1\.h\[0\]'
[^ :]+:[0-9]+: Error: selected processor does not support `fdot z0\.s,z0\.h,z0\.h'
[^ :]+:[0-9]+: Error: selected processor does not support `fdot z31\.s,z0\.h,z0\.h'
[^ :]+:[0-9]+: Error: selected processor does not support `fdot z0\.s,z31\.h,z0\.h'
[^ :]+:[0-9]+: Error: selected processor does not support `fdot z0\.s,z0\.h,z31\.h'
[^ :]+:[0-9]+: Error: selected processor does not support `fdot z14\.s,z26\.h,z9\.h'
[^ :]+:[0-9]+: Error: selected processor does not support `fdot z0\.s,z1\.h,z2\.h'
[^ :]+:[0-9]+: Error: selected processor does not support `sdot z0\.s,z0\.h,z0\.h\[0\]'
[^ :]+:[0-9]+: Error: selected processor does not support `sdot Z0\.S,Z0\.H,Z0\.H\[0\]'
[^ :]+:[0-9]+: Error: selected processor does not support `sdot z31\.s,z0\.h,z0\.h\[0\]'
[^ :]+:[0-9]+: Error: selected processor does not support `sdot z0\.s,z31\.h,z0\.h\[0\]'
[^ :]+:[0-9]+: Error: selected processor does not support `sdot z0\.s,z0\.h,z7\.h\[0\]'
[^ :]+:[0-9]+: Error: selected processor does not support `sdot z0\.s,z0\.h,z0\.h\[3\]'
[^ :]+:[0-9]+: Error: selected processor does not support `sdot z0\.s,z1\.h,z1\.h\[0\]'
[^ :]+:[0-9]+: Error: selected processor does not support `sdot z0\.s,z0\.h,z0\.h'
[^ :]+:[0-9]+: Error: selected processor does not support `sdot z31\.s,z0\.h,z0\.h'
[^ :]+:[0-9]+: Error: selected processor does not support `sdot z0\.s,z31\.h,z0\.h'
[^ :]+:[0-9]+: Error: selected processor does not support `sdot z0\.s,z0\.h,z31\.h'
[^ :]+:[0-9]+: Error: selected processor does not support `sdot z14\.s,z26\.h,z9\.h'
[^ :]+:[0-9]+: Error: selected processor does not support `sdot z0\.s,z1\.h,z2\.h'
[^ :]+:[0-9]+: Error: selected processor does not support `udot z0\.s,z0\.h,z0\.h\[0\]'
[^ :]+:[0-9]+: Error: selected processor does not support `udot Z0\.S,Z0\.H,Z0\.H\[0\]'
[^ :]+:[0-9]+: Error: selected processor does not support `udot z31\.s,z0\.h,z0\.h\[0\]'
[^ :]+:[0-9]+: Error: selected processor does not support `udot z0\.s,z31\.h,z0\.h\[0\]'
[^ :]+:[0-9]+: Error: selected processor does not support `udot z0\.s,z0\.h,z7\.h\[0\]'
[^ :]+:[0-9]+: Error: selected processor does not support `udot z0\.s,z0\.h,z0\.h\[3\]'
[^ :]+:[0-9]+: Error: selected processor does not support `udot z0\.s,z1\.h,z1\.h\[0\]'
[^ :]+:[0-9]+: Error: selected processor does not support `udot z0\.s,z0\.h,z0\.h'
[^ :]+:[0-9]+: Error: selected processor does not support `udot z31\.s,z0\.h,z0\.h'
[^ :]+:[0-9]+: Error: selected processor does not support `udot z0\.s,z31\.h,z0\.h'
[^ :]+:[0-9]+: Error: selected processor does not support `udot z0\.s,z0\.h,z31\.h'
[^ :]+:[0-9]+: Error: selected processor does not support `udot z14\.s,z26\.h,z9\.h'
[^ :]+:[0-9]+: Error: selected processor does not support `udot z0\.s,z1\.h,z2\.h'

54
gas/testsuite/gas/aarch64/sve2-sme2-4.d Normal file
View File

@ -0,0 +1,54 @@
#as: -march=armv8-a+sme2
#objdump: -dr
[^:]+: file format .*
[^:]+:
[^:]+:
[^:]+: 64204000 fdot z0\.s, z0\.h, z0\.h\[0\]
[^:]+: 64204000 fdot z0\.s, z0\.h, z0\.h\[0\]
[^:]+: 6420401f fdot z31\.s, z0\.h, z0\.h\[0\]
[^:]+: 642043e0 fdot z0\.s, z31\.h, z0\.h\[0\]
[^:]+: 64274000 fdot z0\.s, z0\.h, z7\.h\[0\]
[^:]+: 64384000 fdot z0\.s, z0\.h, z0\.h\[3\]
[^:]+: 0420bc20 movprfx z0, z1
[^:]+: 64214020 fdot z0\.s, z1\.h, z1\.h\[0\]
[^:]+: 64208000 fdot z0\.s, z0\.h, z0\.h
[^:]+: 6420801f fdot z31\.s, z0\.h, z0\.h
[^:]+: 642083e0 fdot z0\.s, z31\.h, z0\.h
[^:]+: 643f8000 fdot z0\.s, z0\.h, z31\.h
[^:]+: 6429834e fdot z14\.s, z26\.h, z9\.h
[^:]+: 0420bc20 movprfx z0, z1
[^:]+: 64228020 fdot z0\.s, z1\.h, z2\.h
[^:]+: 4480c800 sdot z0\.s, z0\.h, z0\.h\[0\]
[^:]+: 4480c800 sdot z0\.s, z0\.h, z0\.h\[0\]
[^:]+: 4480c81f sdot z31\.s, z0\.h, z0\.h\[0\]
[^:]+: 4480cbe0 sdot z0\.s, z31\.h, z0\.h\[0\]
[^:]+: 4487c800 sdot z0\.s, z0\.h, z7\.h\[0\]
[^:]+: 4498c800 sdot z0\.s, z0\.h, z0\.h\[3\]
[^:]+: 0420bc20 movprfx z0, z1
[^:]+: 4481c820 sdot z0\.s, z1\.h, z1\.h\[0\]
[^:]+: 4400c800 sdot z0\.s, z0\.h, z0\.h
[^:]+: 4400c81f sdot z31\.s, z0\.h, z0\.h
[^:]+: 4400cbe0 sdot z0\.s, z31\.h, z0\.h
[^:]+: 441fc800 sdot z0\.s, z0\.h, z31\.h
[^:]+: 4409cb4e sdot z14\.s, z26\.h, z9\.h
[^:]+: 0420bc20 movprfx z0, z1
[^:]+: 4402c820 sdot z0\.s, z1\.h, z2\.h
[^:]+: 4480cc00 udot z0\.s, z0\.h, z0\.h\[0\]
[^:]+: 4480cc00 udot z0\.s, z0\.h, z0\.h\[0\]
[^:]+: 4480cc1f udot z31\.s, z0\.h, z0\.h\[0\]
[^:]+: 4480cfe0 udot z0\.s, z31\.h, z0\.h\[0\]
[^:]+: 4487cc00 udot z0\.s, z0\.h, z7\.h\[0\]
[^:]+: 4498cc00 udot z0\.s, z0\.h, z0\.h\[3\]
[^:]+: 0420bc20 movprfx z0, z1
[^:]+: 4481cc20 udot z0\.s, z1\.h, z1\.h\[0\]
[^:]+: 4400cc00 udot z0\.s, z0\.h, z0\.h
[^:]+: 4400cc1f udot z31\.s, z0\.h, z0\.h
[^:]+: 4400cfe0 udot z0\.s, z31\.h, z0\.h
[^:]+: 441fcc00 udot z0\.s, z0\.h, z31\.h
[^:]+: 4409cf4e udot z14\.s, z26\.h, z9\.h
[^:]+: 0420bc20 movprfx z0, z1
[^:]+: 4402cc20 udot z0\.s, z1\.h, z2\.h

49
gas/testsuite/gas/aarch64/sve2-sme2-4.s Normal file
View File

@ -0,0 +1,49 @@
fdot z0.s, z0.h, z0.h[0]
FDOT Z0.S, Z0.H, Z0.H[0]
fdot z31.s, z0.h, z0.h[0]
fdot z0.s, z31.h, z0.h[0]
fdot z0.s, z0.h, z7.h[0]
fdot z0.s, z0.h, z0.h[3]
movprfx z0, z1; fdot z0.s, z1.h, z1.h[0]
fdot z0.s, z0.h, z0.h
fdot z31.s, z0.h, z0.h
fdot z0.s, z31.h, z0.h
fdot z0.s, z0.h, z31.h
fdot z14.s, z26.h, z9.h
movprfx z0, z1; fdot z0.s, z1.h, z2.h
sdot z0.s, z0.h, z0.h[0]
SDOT Z0.S, Z0.H, Z0.H[0]
sdot z31.s, z0.h, z0.h[0]
sdot z0.s, z31.h, z0.h[0]
sdot z0.s, z0.h, z7.h[0]
sdot z0.s, z0.h, z0.h[3]
movprfx z0, z1; sdot z0.s, z1.h, z1.h[0]
sdot z0.s, z0.h, z0.h
sdot z31.s, z0.h, z0.h
sdot z0.s, z31.h, z0.h
sdot z0.s, z0.h, z31.h
sdot z14.s, z26.h, z9.h
movprfx z0, z1; sdot z0.s, z1.h, z2.h
udot z0.s, z0.h, z0.h[0]
UDOT Z0.S, Z0.H, Z0.H[0]
udot z31.s, z0.h, z0.h[0]
udot z0.s, z31.h, z0.h[0]
udot z0.s, z0.h, z7.h[0]
udot z0.s, z0.h, z0.h[3]
movprfx z0, z1; udot z0.s, z1.h, z1.h[0]
udot z0.s, z0.h, z0.h
udot z31.s, z0.h, z0.h
udot z0.s, z31.h, z0.h
udot z0.s, z0.h, z31.h
udot z14.s, z26.h, z9.h
movprfx z0, z1; udot z0.s, z1.h, z2.h

3
include/opcode/aarch64.h
View File

@ -476,8 +476,9 @@ enum aarch64_opnd
AARCH64_OPND_SVE_Zm_5, /* SVE vector register in Zm, bits [9,5]. */
AARCH64_OPND_SVE_Zm_16, /* SVE vector register in Zm, bits [20,16]. */
AARCH64_OPND_SVE_Zm3_INDEX, /* z0-z7[0-3] in Zm, bits [20,16]. */
AARCH64_OPND_SVE_Zm3_22_INDEX, /* z0-z7[0-7] in Zm3_INDEX plus bit 22. */
AARCH64_OPND_SVE_Zm3_11_INDEX, /* z0-z7[0-7] in Zm3_INDEX plus bit 11. */
AARCH64_OPND_SVE_Zm3_19_INDEX, /* z0-z7[0-3] in Zm3_INDEX plus bit 19. */
AARCH64_OPND_SVE_Zm3_22_INDEX, /* z0-z7[0-7] in Zm3_INDEX plus bit 22. */
AARCH64_OPND_SVE_Zm4_11_INDEX, /* z0-z15[0-3] in Zm plus bit 11. */
AARCH64_OPND_SVE_Zm4_INDEX, /* z0-z15[0-1] in Zm, bits [20,16]. */
AARCH64_OPND_SVE_Zn, /* SVE vector register in Zn. */

69
opcodes/aarch64-asm-2.c
View File

@ -665,15 +665,15 @@ aarch64_insert_operand (const aarch64_operand *self,
case 201:
case 202:
case 203:
case 209:
case 212:
case 216:
case 223:
case 210:
case 213:
case 217:
case 224:
case 231:
case 225:
case 232:
case 233:
case 234:
case 235:
return aarch64_ins_regno (self, info, code, inst, errors);
case 15:
return aarch64_ins_reg_extended (self, info, code, inst, errors);
@ -685,7 +685,7 @@ aarch64_insert_operand (const aarch64_operand *self,
case 33:
case 34:
case 35:
case 270:
case 271:
return aarch64_ins_reglane (self, info, code, inst, errors);
case 36:
return aarch64_ins_reglist (self, info, code, inst, errors);
@ -730,13 +730,13 @@ aarch64_insert_operand (const aarch64_operand *self,
case 192:
case 193:
case 194:
case 237:
case 264:
case 238:
case 265:
case 267:
case 269:
case 274:
case 266:
case 268:
case 270:
case 275:
case 276:
return aarch64_ins_imm (self, info, code, inst, errors);
case 44:
case 45:
@ -805,8 +805,8 @@ aarch64_insert_operand (const aarch64_operand *self,
case 107:
return aarch64_ins_prfop (self, info, code, inst, errors);
case 108:
case 266:
case 268:
case 267:
case 269:
return aarch64_ins_none (self, info, code, inst, errors);
case 109:
return aarch64_ins_hint (self, info, code, inst, errors);
@ -886,41 +886,41 @@ aarch64_insert_operand (const aarch64_operand *self,
case 184:
case 185:
case 186:
case 250:
case 251:
return aarch64_ins_sve_shrimm (self, info, code, inst, errors);
case 204:
case 205:
case 206:
case 207:
case 208:
case 209:
return aarch64_ins_sve_quad_index (self, info, code, inst, errors);
case 210:
return aarch64_ins_sve_index (self, info, code, inst, errors);
case 211:
case 213:
case 230:
return aarch64_ins_sve_reglist (self, info, code, inst, errors);
return aarch64_ins_sve_index (self, info, code, inst, errors);
case 212:
case 214:
case 231:
return aarch64_ins_sve_reglist (self, info, code, inst, errors);
case 215:
case 217:
case 216:
case 218:
case 219:
case 220:
case 229:
return aarch64_ins_sve_aligned_reglist (self, info, code, inst, errors);
case 221:
case 230:
return aarch64_ins_sve_aligned_reglist (self, info, code, inst, errors);
case 222:
case 223:
return aarch64_ins_sve_strided_reglist (self, info, code, inst, errors);
case 225:
case 227:
case 238:
return aarch64_ins_sme_za_hv_tiles (self, info, code, inst, errors);
case 226:
case 228:
case 239:
return aarch64_ins_sme_za_hv_tiles (self, info, code, inst, errors);
case 227:
case 229:
return aarch64_ins_sme_za_hv_tiles_range (self, info, code, inst, errors);
case 235:
case 236:
case 251:
case 237:
case 252:
case 253:
case 254:
@ -933,26 +933,27 @@ aarch64_insert_operand (const aarch64_operand *self,
case 261:
case 262:
case 263:
case 264:
return aarch64_ins_simple_index (self, info, code, inst, errors);
case 239:
case 240:
case 241:
case 242:
case 243:
case 244:
case 245:
return aarch64_ins_sme_za_array (self, info, code, inst, errors);
case 246:
return aarch64_ins_sme_addr_ri_u4xvl (self, info, code, inst, errors);
return aarch64_ins_sme_za_array (self, info, code, inst, errors);
case 247:
return aarch64_ins_sme_sm_za (self, info, code, inst, errors);
return aarch64_ins_sme_addr_ri_u4xvl (self, info, code, inst, errors);
case 248:
return aarch64_ins_sme_pred_reg_with_index (self, info, code, inst, errors);
return aarch64_ins_sme_sm_za (self, info, code, inst, errors);
case 249:
return aarch64_ins_sme_pred_reg_with_index (self, info, code, inst, errors);
case 250:
return aarch64_ins_plain_shrimm (self, info, code, inst, errors);
case 271:
case 272:
case 273:
case 274:
return aarch64_ins_x0_to_x30 (self, info, code, inst, errors);
default: assert (0); abort ();
}

1673
opcodes/aarch64-dis-2.c
View File

File diff suppressed because it is too large Load Diff

3
opcodes/aarch64-opc-2.c
View File

@ -229,8 +229,9 @@ const struct aarch64_operand aarch64_operands[] =
{AARCH64_OPND_CLASS_SVE_REG, "SVE_Zm_5", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zm_5}, "an SVE vector register"},
{AARCH64_OPND_CLASS_SVE_REG, "SVE_Zm_16", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zm_16}, "an SVE vector register"},
{AARCH64_OPND_CLASS_SVE_REG, "SVE_Zm3_INDEX", 3 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zm_16}, "an indexed SVE vector register"},
{AARCH64_OPND_CLASS_SVE_REG, "SVE_Zm3_22_INDEX", 3 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_i3h, FLD_SVE_Zm_16}, "an indexed SVE vector register"},
{AARCH64_OPND_CLASS_SVE_REG, "SVE_Zm3_11_INDEX", 3 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_i3h2, FLD_SVE_i3l, FLD_SVE_imm3}, "an indexed SVE vector register"},
{AARCH64_OPND_CLASS_SVE_REG, "SVE_Zm3_19_INDEX", 3 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm2_19, FLD_SVE_imm3}, "an indexed SVE vector register"},
{AARCH64_OPND_CLASS_SVE_REG, "SVE_Zm3_22_INDEX", 3 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_i3h, FLD_SVE_Zm_16}, "an indexed SVE vector register"},
{AARCH64_OPND_CLASS_SVE_REG, "SVE_Zm4_11_INDEX", 4 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_i2h, FLD_SVE_i3l, FLD_SVE_imm4}, "an indexed SVE vector register"},
{AARCH64_OPND_CLASS_SVE_REG, "SVE_Zm4_INDEX", 4 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zm_16}, "an indexed SVE vector register"},
{AARCH64_OPND_CLASS_SVE_REG, "SVE_Zn", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zn}, "an SVE vector register"},

3
opcodes/aarch64-opc.c
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@ -332,6 +332,7 @@ const aarch64_field fields[] =
{ 10, 2 }, /* imm2_10: 2-bit immediate, bits [11:10] */
{ 15, 2 }, /* imm2_15: 2-bit immediate, bits [16:15] */
{ 16, 2 }, /* imm2_16: 2-bit immediate, bits [17:16] */
{ 19, 2 }, /* imm2_19: 2-bit immediate, bits [20:19] */
{ 0, 3 }, /* imm3_0: general immediate in bits [2:0]. */
{ 5, 3 }, /* imm3_5: general immediate in bits [7:5]. */
{ 10, 3 }, /* imm3_10: in add/sub extended reg instructions. */
@ -1735,6 +1736,7 @@ operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx,
{
case AARCH64_OPND_SVE_Zm3_INDEX:
case AARCH64_OPND_SVE_Zm3_22_INDEX:
case AARCH64_OPND_SVE_Zm3_19_INDEX:
case AARCH64_OPND_SVE_Zm3_11_INDEX:
case AARCH64_OPND_SVE_Zm4_11_INDEX:
case AARCH64_OPND_SVE_Zm4_INDEX:
@ -3977,6 +3979,7 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc,
case AARCH64_OPND_SVE_Zm3_INDEX:
case AARCH64_OPND_SVE_Zm3_22_INDEX:
case AARCH64_OPND_SVE_Zm3_19_INDEX:
case AARCH64_OPND_SVE_Zm3_11_INDEX:
case AARCH64_OPND_SVE_Zm4_11_INDEX:
case AARCH64_OPND_SVE_Zm4_INDEX:

1
opcodes/aarch64-opc.h
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@ -153,6 +153,7 @@ enum aarch64_field_kind
FLD_imm2_10,
FLD_imm2_15,
FLD_imm2_16,
FLD_imm2_19,
FLD_imm3_0,
FLD_imm3_5,
FLD_imm3_10,

15
opcodes/aarch64-tbl.h
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@ -5364,6 +5364,12 @@ const struct aarch64_opcode aarch64_opcode_table[] =
SME2_INSNC ("bfmlslb", 0x64e0a000, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_SHH, 0, C_SCAN_MOVPRFX, 0),
SME2_INSNC ("bfmlslt", 0x64e06400, 0xffe0f400, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_11_INDEX), OP_SVE_SHH, 0, C_SCAN_MOVPRFX, 0),
SME2_INSNC ("bfmlslt", 0x64e0a400, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_SHH, 0, C_SCAN_MOVPRFX, 0),
SME2_INSNC ("fdot", 0x64204000, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_19_INDEX), OP_SVE_SHH, 0, C_SCAN_MOVPRFX, 0),
SME2_INSNC ("fdot", 0x64208000, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_SHH, 0, C_SCAN_MOVPRFX, 0),
SME2_INSNC ("sdot", 0x4480c800, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_19_INDEX), OP_SVE_SHH, 0, C_SCAN_MOVPRFX, 0),
SME2_INSNC ("sdot", 0x4400c800, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_SHH, 0, C_SCAN_MOVPRFX, 0),
SME2_INSNC ("udot", 0x4480cc00, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_19_INDEX), OP_SVE_SHH, 0, C_SCAN_MOVPRFX, 0),
SME2_INSNC ("udot", 0x4400cc00, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_SHH, 0, C_SCAN_MOVPRFX, 0),
SME2_INSN ("whilege", 0x25205010, 0xff20fc11, sme_size_22, 0, OP3 (SME_Pdx2, Rn, Rm), OP_SVE_VXX_BHSD, 0, 0),
SME2_INSN ("whilegt", 0x25205011, 0xff20fc11, sme_size_22, 0, OP3 (SME_Pdx2, Rn, Rm), OP_SVE_VXX_BHSD, 0, 0),
SME2_INSN ("whilehi", 0x25205811, 0xff20fc11, sme_size_22, 0, OP3 (SME_Pdx2, Rn, Rm), OP_SVE_VXX_BHSD, 0, 0),
@ -6486,12 +6492,15 @@ const struct aarch64_opcode aarch64_opcode_table[] =
Y(SVE_REG, sve_quad_index, "SVE_Zm3_INDEX", \
3 << OPD_F_OD_LSB, F(FLD_SVE_Zm_16), \
"an indexed SVE vector register") \
Y(SVE_REG, sve_quad_index, "SVE_Zm3_22_INDEX", \
3 << OPD_F_OD_LSB, F(FLD_SVE_i3h, FLD_SVE_Zm_16), \
"an indexed SVE vector register") \
Y(SVE_REG, sve_quad_index, "SVE_Zm3_11_INDEX", \
3 << OPD_F_OD_LSB, F(FLD_SVE_i3h2, FLD_SVE_i3l, FLD_SVE_imm3), \
"an indexed SVE vector register") \
Y(SVE_REG, sve_quad_index, "SVE_Zm3_19_INDEX", \
3 << OPD_F_OD_LSB, F(FLD_imm2_19, FLD_SVE_imm3), \
"an indexed SVE vector register") \
Y(SVE_REG, sve_quad_index, "SVE_Zm3_22_INDEX", \
3 << OPD_F_OD_LSB, F(FLD_SVE_i3h, FLD_SVE_Zm_16), \
"an indexed SVE vector register") \
Y(SVE_REG, sve_quad_index, "SVE_Zm4_11_INDEX", \
4 << OPD_F_OD_LSB, F(FLD_SVE_i2h, FLD_SVE_i3l, FLD_SVE_imm4), \
"an indexed SVE vector register") \