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LoongArch: update test cases about TLS

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This commit is contained in:
Nick Clifton 2024-01-29 11:22:39 +00:00
parent 70d424aaf8
commit e28726c4fd
17 changed files with 126 additions and 65 deletions
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61
bfd/elfnn-loongarch.c
View File

@ -145,14 +145,12 @@ struct loongarch_elf_link_hash_table
#define elf_backend_rela_normal 1 #define elf_backend_rela_normal 1
#define elf_backend_default_execstack 0 #define elf_backend_default_execstack 0
#define IS_LOONGARCH_TLS_DESC_RELOC(R_TYPE) \ #define IS_LOONGARCH_TLS_TRANS_RELOC(R_TYPE) \
((R_TYPE) == R_LARCH_TLS_DESC_PC_HI20 \ ((R_TYPE) == R_LARCH_TLS_DESC_PC_HI20 \
|| (R_TYPE) == R_LARCH_TLS_DESC_PC_LO12 \ || (R_TYPE) == R_LARCH_TLS_DESC_PC_LO12 \
|| (R_TYPE) == R_LARCH_TLS_DESC_LD \ || (R_TYPE) == R_LARCH_TLS_DESC_LD \
|| (R_TYPE) == R_LARCH_TLS_DESC_CALL) || (R_TYPE) == R_LARCH_TLS_DESC_CALL \
|| (R_TYPE) == R_LARCH_TLS_IE_PC_HI20 \
#define IS_LOONGARCH_TLS_IE_RELOC(R_TYPE) \
((R_TYPE) == R_LARCH_TLS_IE_PC_HI20 \
|| (R_TYPE) == R_LARCH_TLS_IE_PC_LO12) || (R_TYPE) == R_LARCH_TLS_IE_PC_LO12)
/* Generate a PLT header. */ /* Generate a PLT header. */
@ -642,15 +640,20 @@ loongarch_reloc_got_type (unsigned int r_type)
/* Return true if tls type transition can be performed. */ /* Return true if tls type transition can be performed. */
static bool static bool
loongarch_can_relax_tls (struct bfd_link_info *info, unsigned int r_type, loongarch_can_trans_tls (bfd *input_bfd,
struct elf_link_hash_entry *h, bfd *input_bfd, struct bfd_link_info *info,
unsigned long r_symndx) struct elf_link_hash_entry *h,
const Elf_Internal_Rela *rel,
unsigned int r_type)
{ {
char symbol_tls_type; char symbol_tls_type;
unsigned int reloc_got_type; unsigned int reloc_got_type;
unsigned int r_symndx = ELFNN_R_SYM (rel->r_info);
if (! (IS_LOONGARCH_TLS_DESC_RELOC (r_type) /* Only TLS DESC/IE in normal code mode will perform type
|| IS_LOONGARCH_TLS_IE_RELOC (r_type))) transition. */
if (! (IS_LOONGARCH_TLS_TRANS_RELOC (r_type)
&& ELFNN_R_TYPE (rel[1].r_info) == R_LARCH_RELAX))
return false; return false;
symbol_tls_type = _bfd_loongarch_elf_tls_type (input_bfd, h, r_symndx); symbol_tls_type = _bfd_loongarch_elf_tls_type (input_bfd, h, r_symndx);
@ -707,11 +710,13 @@ loongarch_tls_transition_without_check (struct bfd_link_info *info,
} }
static unsigned int static unsigned int
loongarch_tls_transition (struct bfd_link_info *info, unsigned int r_type, loongarch_tls_transition (bfd *input_bfd,
struct elf_link_hash_entry *h, bfd *input_bfd, struct bfd_link_info *info,
unsigned long r_symndx) struct elf_link_hash_entry *h,
const Elf_Internal_Rela *rel,
unsigned int r_type)
{ {
if (! loongarch_can_relax_tls (info, r_type, h, input_bfd,r_symndx)) if (! loongarch_can_trans_tls (input_bfd, info, h, rel, r_type))
return r_type; return r_type;
return loongarch_tls_transition_without_check (info, r_type, h); return loongarch_tls_transition_without_check (info, r_type, h);
@ -818,7 +823,10 @@ loongarch_elf_check_relocs (bfd *abfd, struct bfd_link_info *info,
int need_dynreloc = 0; int need_dynreloc = 0;
int only_need_pcrel = 0; int only_need_pcrel = 0;
r_type = loongarch_tls_transition (info, r_type, h, abfd, r_symndx); /* Type transitions are only possible with relocations accompanied
by R_LARCH_RELAX. */
if (rel + 1 != relocs + sec->reloc_count)
r_type = loongarch_tls_transition (abfd, info, h, rel, r_type);
switch (r_type) switch (r_type)
{ {
case R_LARCH_GOT_PC_HI20: case R_LARCH_GOT_PC_HI20:
@ -2538,7 +2546,7 @@ loongarch_reloc_is_fatal (struct bfd_link_info *info,
/* Transition instruction sequence to relax instruction sequence. */ /* Transition instruction sequence to relax instruction sequence. */
static bool static bool
loongarch_tls_relax (bfd *abfd, asection *sec, Elf_Internal_Rela *rel, loongarch_tls_perform_trans (bfd *abfd, asection *sec, Elf_Internal_Rela *rel,
int r_type, struct elf_link_hash_entry *h, int r_type, struct elf_link_hash_entry *h,
struct bfd_link_info *info) struct bfd_link_info *info)
{ {
@ -2659,7 +2667,7 @@ loongarch_elf_relocate_section (bfd *output_bfd, struct bfd_link_info *info,
const char *name; const char *name;
bfd_reloc_status_type r = bfd_reloc_ok; bfd_reloc_status_type r = bfd_reloc_ok;
bool is_ie, is_desc, is_undefweak, unresolved_reloc, defined_local; bool is_ie, is_desc, is_undefweak, unresolved_reloc, defined_local;
unsigned int relaxed_r_type; unsigned int trans_r_type = r_type;
bool resolved_local, resolved_dynly, resolved_to_const; bool resolved_local, resolved_dynly, resolved_to_const;
char tls_type; char tls_type;
bfd_vma relocation, off, ie_off, desc_off; bfd_vma relocation, off, ie_off, desc_off;
@ -2791,14 +2799,17 @@ loongarch_elf_relocate_section (bfd *output_bfd, struct bfd_link_info *info,
BFD_ASSERT (!resolved_local || defined_local); BFD_ASSERT (!resolved_local || defined_local);
relaxed_r_type = loongarch_tls_transition (info, r_type, h, input_bfd, r_symndx); if (rel + 1 != relend)
if (relaxed_r_type != r_type) trans_r_type = loongarch_tls_transition (input_bfd, info, h,
rel, r_type);
if (trans_r_type != r_type)
{ {
howto = loongarch_elf_rtype_to_howto (input_bfd, relaxed_r_type); howto = loongarch_elf_rtype_to_howto (input_bfd, trans_r_type);
BFD_ASSERT (howto != NULL); BFD_ASSERT (howto != NULL);
if (loongarch_tls_relax (input_bfd, input_section, rel, r_type, h, info)) if (loongarch_tls_perform_trans (input_bfd, input_section,
r_type = relaxed_r_type; rel, r_type, h, info))
r_type = trans_r_type;
} }
is_desc = false; is_desc = false;
@ -4553,7 +4564,8 @@ loongarch_elf_relax_section (bfd *abfd, asection *sec,
|| R_LARCH_TLS_GD_PC_HI20 == r_type || R_LARCH_TLS_GD_PC_HI20 == r_type
|| R_LARCH_TLS_DESC_PC_HI20 == r_type) || R_LARCH_TLS_DESC_PC_HI20 == r_type)
{ {
if (loongarch_can_relax_tls (info, r_type, h, abfd, r_symndx)) if (i + 1 != sec->reloc_count
&& loongarch_can_trans_tls (abfd, info, h, rel, r_type))
continue; continue;
else else
{ {
@ -4597,7 +4609,8 @@ loongarch_elf_relax_section (bfd *abfd, asection *sec,
|| R_LARCH_TLS_GD_PC_HI20 == r_type || R_LARCH_TLS_GD_PC_HI20 == r_type
|| R_LARCH_TLS_DESC_PC_HI20 == r_type) || R_LARCH_TLS_DESC_PC_HI20 == r_type)
{ {
if (loongarch_can_relax_tls (info, r_type, h, abfd, r_symndx)) if (i + 1 != sec->reloc_count
&& loongarch_can_trans_tls (abfd, info, h, rel, r_type))
continue; continue;
else else
{ {

19
gas/config/tc-loongarch.c
View File

@ -724,8 +724,12 @@ loongarch_args_parser_can_match_arg_helper (char esc_ch1, char esc_ch2,
} }
/* Only one register macros (used in normal code model) /* Only one register macros (used in normal code model)
emit R_LARCH_RELAX. */ emit R_LARCH_RELAX.
LARCH_opts.ase_labs and LARCH_opts.ase_gabs are used
to generate the code model of absolute addresses, and
we do not relax this code model. */
if (LARCH_opts.relax && (ip->expand_from_macro & 1) if (LARCH_opts.relax && (ip->expand_from_macro & 1)
&& ! (LARCH_opts.ase_labs | LARCH_opts.ase_gabs)
&& (BFD_RELOC_LARCH_PCALA_HI20 == reloc_type && (BFD_RELOC_LARCH_PCALA_HI20 == reloc_type
|| BFD_RELOC_LARCH_PCALA_LO12 == reloc_type || BFD_RELOC_LARCH_PCALA_LO12 == reloc_type
|| BFD_RELOC_LARCH_GOT_PC_HI20 == reloc_type || BFD_RELOC_LARCH_GOT_PC_HI20 == reloc_type
@ -733,7 +737,11 @@ loongarch_args_parser_can_match_arg_helper (char esc_ch1, char esc_ch2,
|| BFD_RELOC_LARCH_TLS_LD_PC_HI20 == reloc_type || BFD_RELOC_LARCH_TLS_LD_PC_HI20 == reloc_type
|| BFD_RELOC_LARCH_TLS_GD_PC_HI20 == reloc_type || BFD_RELOC_LARCH_TLS_GD_PC_HI20 == reloc_type
|| BFD_RELOC_LARCH_TLS_DESC_PC_HI20 == reloc_type || BFD_RELOC_LARCH_TLS_DESC_PC_HI20 == reloc_type
|| BFD_RELOC_LARCH_TLS_DESC_PC_LO12 == reloc_type)) || BFD_RELOC_LARCH_TLS_DESC_PC_LO12 == reloc_type
|| BFD_RELOC_LARCH_TLS_DESC_LD == reloc_type
|| BFD_RELOC_LARCH_TLS_DESC_CALL == reloc_type
|| BFD_RELOC_LARCH_TLS_IE_PC_HI20 == reloc_type
|| BFD_RELOC_LARCH_TLS_IE_PC_LO12 == reloc_type))
{ {
ip->reloc_info[ip->reloc_num].type = BFD_RELOC_LARCH_RELAX; ip->reloc_info[ip->reloc_num].type = BFD_RELOC_LARCH_RELAX;
ip->reloc_info[ip->reloc_num].value = const_0; ip->reloc_info[ip->reloc_num].value = const_0;
@ -1088,7 +1096,12 @@ append_fixp_and_insn (struct loongarch_cl_insn *ip)
|| BFD_RELOC_LARCH_TLS_LE_ADD_R == reloc_info[0].type || BFD_RELOC_LARCH_TLS_LE_ADD_R == reloc_info[0].type
|| BFD_RELOC_LARCH_TLS_LD_PC_HI20 == reloc_info[0].type || BFD_RELOC_LARCH_TLS_LD_PC_HI20 == reloc_info[0].type
|| BFD_RELOC_LARCH_TLS_GD_PC_HI20 == reloc_info[0].type || BFD_RELOC_LARCH_TLS_GD_PC_HI20 == reloc_info[0].type
|| BFD_RELOC_LARCH_TLS_DESC_PC_HI20 == reloc_info[0].type)) || BFD_RELOC_LARCH_TLS_DESC_PC_HI20 == reloc_info[0].type
|| BFD_RELOC_LARCH_TLS_DESC_PC_LO12 == reloc_info[0].type
|| BFD_RELOC_LARCH_TLS_DESC_LD == reloc_info[0].type
|| BFD_RELOC_LARCH_TLS_DESC_CALL == reloc_info[0].type
|| BFD_RELOC_LARCH_TLS_IE_PC_HI20 == reloc_info[0].type
|| BFD_RELOC_LARCH_TLS_IE_PC_LO12 == reloc_info[0].type))
{ {
frag_wane (frag_now); frag_wane (frag_now);
frag_new (0); frag_new (0);

2
gas/testsuite/gas/loongarch/macro_op.d
View File

@ -57,8 +57,10 @@ Disassembly of section .text:
4c: R_LARCH_TLS_LE_LO12 TLS1 4c: R_LARCH_TLS_LE_LO12 TLS1
50: 1a000004 pcalau12i \$a0, 0 50: 1a000004 pcalau12i \$a0, 0
50: R_LARCH_TLS_IE_PC_HI20 TLS1 50: R_LARCH_TLS_IE_PC_HI20 TLS1
50: R_LARCH_RELAX \*ABS\*
54: 28c00084 ld.d \$a0, \$a0, 0 54: 28c00084 ld.d \$a0, \$a0, 0
54: R_LARCH_TLS_IE_PC_LO12 TLS1 54: R_LARCH_TLS_IE_PC_LO12 TLS1
54: R_LARCH_RELAX \*ABS\*
58: 1a000004 pcalau12i \$a0, 0 58: 1a000004 pcalau12i \$a0, 0
58: R_LARCH_TLS_LD_PC_HI20 TLS1 58: R_LARCH_TLS_LD_PC_HI20 TLS1
58: R_LARCH_RELAX \*ABS\* 58: R_LARCH_RELAX \*ABS\*

2
gas/testsuite/gas/loongarch/macro_op_32.d
View File

@ -53,8 +53,10 @@ Disassembly of section .text:
44: R_LARCH_TLS_LE_LO12 TLS1 44: R_LARCH_TLS_LE_LO12 TLS1
48: 1a000004 pcalau12i \$a0, 0 48: 1a000004 pcalau12i \$a0, 0
48: R_LARCH_TLS_IE_PC_HI20 TLS1 48: R_LARCH_TLS_IE_PC_HI20 TLS1
48: R_LARCH_RELAX \*ABS\*
4c: 28800084 ld.w \$a0, \$a0, 0 4c: 28800084 ld.w \$a0, \$a0, 0
4c: R_LARCH_TLS_IE_PC_LO12 TLS1 4c: R_LARCH_TLS_IE_PC_LO12 TLS1
4c: R_LARCH_RELAX \*ABS\*
50: 1a000004 pcalau12i \$a0, 0 50: 1a000004 pcalau12i \$a0, 0
50: R_LARCH_TLS_LD_PC_HI20 TLS1 50: R_LARCH_TLS_LD_PC_HI20 TLS1
50: R_LARCH_RELAX \*ABS\* 50: R_LARCH_RELAX \*ABS\*

2
gas/testsuite/gas/loongarch/macro_op_extreme_abs.d
View File

@ -28,10 +28,8 @@ Disassembly of section .text:
1c: R_LARCH_ABS64_HI12 .L1 1c: R_LARCH_ABS64_HI12 .L1
20: 1a000004 pcalau12i \$a0, 0 20: 1a000004 pcalau12i \$a0, 0
20: R_LARCH_PCALA_HI20 .L1 20: R_LARCH_PCALA_HI20 .L1
20: R_LARCH_RELAX \*ABS\*
24: 02c00084 addi.d \$a0, \$a0, 0 24: 02c00084 addi.d \$a0, \$a0, 0
24: R_LARCH_PCALA_LO12 .L1 24: R_LARCH_PCALA_LO12 .L1
24: R_LARCH_RELAX \*ABS\*
28: 14000004 lu12i.w \$a0, 0 28: 14000004 lu12i.w \$a0, 0
28: R_LARCH_GOT_HI20 .L1 28: R_LARCH_GOT_HI20 .L1
2c: 03800084 ori \$a0, \$a0, 0x0 2c: 03800084 ori \$a0, \$a0, 0x0

2
gas/testsuite/gas/loongarch/tlsdesc_32.d
View File

@ -23,5 +23,7 @@ Disassembly of section .text:
14: R_LARCH_RELAX \*ABS\* 14: R_LARCH_RELAX \*ABS\*
18: 28800081 ld.w \$ra, \$a0, 0 18: 28800081 ld.w \$ra, \$a0, 0
18: R_LARCH_TLS_DESC_LD var 18: R_LARCH_TLS_DESC_LD var
18: R_LARCH_RELAX \*ABS\*
1c: 4c000021 jirl \$ra, \$ra, 0 1c: 4c000021 jirl \$ra, \$ra, 0
1c: R_LARCH_TLS_DESC_CALL var 1c: R_LARCH_TLS_DESC_CALL var
1c: R_LARCH_RELAX \*ABS\*

2
gas/testsuite/gas/loongarch/tlsdesc_32.s
View File

@ -8,5 +8,5 @@
# R_LARCH_TLS_DESC_CALL var # R_LARCH_TLS_DESC_CALL var
jirl $ra,$ra,%desc_call(var) jirl $ra,$ra,%desc_call(var)
# test macro, pcalau12i + addi.w => pcaddi # with R_LARCH_RELAX
la.tls.desc $a0,var la.tls.desc $a0,var

2
gas/testsuite/gas/loongarch/tlsdesc_64.d
View File

@ -24,5 +24,7 @@ Disassembly of section .text:
14: R_LARCH_RELAX \*ABS\* 14: R_LARCH_RELAX \*ABS\*
18: 28c00081 ld.d \$ra, \$a0, 0 18: 28c00081 ld.d \$ra, \$a0, 0
18: R_LARCH_TLS_DESC_LD var 18: R_LARCH_TLS_DESC_LD var
18: R_LARCH_RELAX \*ABS\*
1c: 4c000021 jirl \$ra, \$ra, 0 1c: 4c000021 jirl \$ra, \$ra, 0
1c: R_LARCH_TLS_DESC_CALL var 1c: R_LARCH_TLS_DESC_CALL var
1c: R_LARCH_RELAX \*ABS\*

2
gas/testsuite/gas/loongarch/tlsdesc_64.s
View File

@ -8,5 +8,5 @@
# R_LARCH_TLS_DESC_CALL var # R_LARCH_TLS_DESC_CALL var
jirl $ra,$ra,%desc_call(var) jirl $ra,$ra,%desc_call(var)
# test macro, pcalau12i + addi.d => pcaddi # with R_LARCH_RELAX
la.tls.desc $a0,var la.tls.desc $a0,var

29
ld/testsuite/ld-loongarch-elf/desc-ie.d
View File

@ -1,16 +1,29 @@
#as: #as:
#ld: -shared -z norelro -e 0x0 --hash-style=both #ld: -shared -z norelro -e0 --hash-style=both
#objdump: -dr #objdump: -dr
#skip: loongarch32-*-* #skip: loongarch32-*-*
.*: file format .* .*: file format .*
Disassembly of section .text: Disassembly of section .text:
0+230 <fn1>: [0-9a-f]+ <fn1>:
230: 1a000084 pcalau12i \$a0, 4 +[0-9a-f]+: 1a000084 pcalau12i \$a0, .*
234: 28cd6084 ld.d \$a0, \$a0, 856 +[0-9a-f]+: 28ce2084 ld.d \$a0, \$a0, .*
238: 03400000 nop.* +[0-9a-f]+: 03400000 nop
23c: 03400000 nop.* +[0-9a-f]+: 03400000 nop
240: 1a000084 pcalau12i \$a0, 4 +[0-9a-f]+: 1a000084 pcalau12i \$a0, .*
244: 28cd6081 ld.d \$ra, \$a0, 856 +[0-9a-f]+: 28ce2084 ld.d \$a0, \$a0, .*
+[0-9a-f]+: 1a000084 pcalau12i \$a0, .*
+[0-9a-f]+: 02ce2005 li.d \$a1, .*
+[0-9a-f]+: 16000005 lu32i.d \$a1, 0
+[0-9a-f]+: 030000a5 lu52i.d \$a1, \$a1, .*
+[0-9a-f]+: 00109484 add.d \$a0, \$a0, \$a1
+[0-9a-f]+: 28c00081 ld.d \$ra, \$a0, 0
+[0-9a-f]+: 4c000021 jirl \$ra, \$ra, 0
+[0-9a-f]+: 1a000084 pcalau12i \$a0, .*
+[0-9a-f]+: 02ce2005 li.d \$a1, .*
+[0-9a-f]+: 16000005 lu32i.d \$a1, .*
+[0-9a-f]+: 030000a5 lu52i.d \$a1, \$a1, .*
+[0-9a-f]+: 380c1484 ldx.d \$a0, \$a0, \$a1

11
ld/testsuite/ld-loongarch-elf/desc-ie.s
View File

@ -9,10 +9,9 @@ fn1:
# Use DESC and IE to access the same symbol, # Use DESC and IE to access the same symbol,
# DESC will relax to IE. # DESC will relax to IE.
pcalau12i $a0,%desc_pc_hi20(var) la.tls.desc $a0,var
addi.d $a0,$a0,%desc_pc_lo12(var) la.tls.ie $a0,var
ld.d $ra,$a0,%desc_ld(var)
jirl $ra,$ra,%desc_call(var)
pcalau12i $a0,%ie_pc_hi20(var) # extreme cmodel do not do transition.
ld.d $ra,$a0,%ie_pc_lo12(var) la.tls.desc $a0,$a1,var
la.tls.ie $a0,$a1,var

19
ld/testsuite/ld-loongarch-elf/desc-le.d
View File

@ -1,5 +1,5 @@
#as: #as:
#ld: -z norelro -e 0x0 #ld: -z norelro -e0
#objdump: -dr #objdump: -dr
#skip: loongarch32-*-* #skip: loongarch32-*-*
@ -8,8 +8,15 @@
Disassembly of section .text: Disassembly of section .text:
0+1200000e8 <fn1>: [0-9a-f]+ <fn1>:
1200000e8: 14000004 lu12i.w \$a0, 0 +[0-9a-f]+: 14000004 lu12i.w \$a0, .*
1200000ec: 03800084 ori \$a0, \$a0, 0x0 +[0-9a-f]+: 03800084 ori \$a0, \$a0, .*
1200000f0: 03400000 nop.* +[0-9a-f]+: 03400000 nop
1200000f4: 03400000 nop.* +[0-9a-f]+: 03400000 nop
+[0-9a-f]+: 1a000084 pcalau12i \$a0, .*
+[0-9a-f]+: 02c4e005 li.d \$a1, .*
+[0-9a-f]+: 16000005 lu32i.d \$a1, .*
+[0-9a-f]+: 030000a5 lu52i.d \$a1, \$a1, .*
+[0-9a-f]+: 00109484 add.d \$a0, \$a0, \$a1
+[0-9a-f]+: 28c00081 ld.d \$ra, \$a0, 0
+[0-9a-f]+: 4c000021 jirl \$ra, \$ra, 0

8
ld/testsuite/ld-loongarch-elf/desc-le.s
View File

@ -8,7 +8,7 @@ var:
fn1: fn1:
# DESC will relax to LE. # DESC will relax to LE.
pcalau12i $a0,%desc_pc_hi20(var) la.tls.desc $a0,var
addi.d $a0,$a0,%desc_pc_lo12(var)
ld.d $ra,$a0,%desc_ld(var) # extreme cmodel do not do transition.
jirl $ra,$ra,%desc_call(var) la.tls.desc $a0,$a1,var

13
ld/testsuite/ld-loongarch-elf/ie-le.d
View File

@ -1,5 +1,5 @@
#as: #as:
#ld: -z norelro -e 0x0 #ld: -z norelro -e0
#objdump: -dr #objdump: -dr
#skip: loongarch32-*-* #skip: loongarch32-*-*
@ -8,6 +8,11 @@
Disassembly of section .text: Disassembly of section .text:
0+1200000e8 <fn1>: [0-9a-f]+ <fn1>:
1200000e8: 14000004 lu12i.w \$a0, 0 +[0-9a-f]+: 14000004 lu12i.w \$a0, .*
1200000ec: 03800084 ori \$a0, \$a0, 0x0 +[0-9a-f]+: 03800084 ori \$a0, \$a0, .*
+[0-9a-f]+: 1a000084 pcalau12i \$a0, .*
+[0-9a-f]+: 02c44005 li.d \$a1, .*
+[0-9a-f]+: 16000005 lu32i.d \$a1, .*
+[0-9a-f]+: 030000a5 lu52i.d \$a1, \$a1, .*
+[0-9a-f]+: 380c1484 ldx.d \$a0, \$a0, \$a1

7
ld/testsuite/ld-loongarch-elf/ie-le.s
View File

@ -6,6 +6,7 @@ var:
.global fn1 .global fn1
.type gn1,@function .type gn1,@function
fn1: fn1:
# expect IE to relax LE. # expect IE to relax LE in nomal cmodel.
pcalau12i $a0,%ie_pc_hi20(var) la.tls.ie $a0,var
ld.d $a0,$a0,%ie_pc_lo12(var) # extreme cmodel do not do transition.
la.tls.ie $a0,$a1,var

2
ld/testsuite/ld-loongarch-elf/macro_op.d
View File

@ -144,8 +144,10 @@ Disassembly of section .text:
[ ]+f8: R_LARCH_TLS_LE_LO12[ ]+TLS1 [ ]+f8: R_LARCH_TLS_LE_LO12[ ]+TLS1
[ ]+fc:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0, 0 [ ]+fc:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0, 0
[ ]+fc: R_LARCH_TLS_IE_PC_HI20[ ]+TLS1 [ ]+fc: R_LARCH_TLS_IE_PC_HI20[ ]+TLS1
[ ]+fc: R_LARCH_RELAX[ ]+\*ABS\*
[ ]+100:[ ]+28c00084[ ]+ld.d[ ]+\$a0, \$a0, 0 [ ]+100:[ ]+28c00084[ ]+ld.d[ ]+\$a0, \$a0, 0
[ ]+100: R_LARCH_TLS_IE_PC_LO12[ ]+TLS1 [ ]+100: R_LARCH_TLS_IE_PC_LO12[ ]+TLS1
[ ]+100: R_LARCH_RELAX[ ]+\*ABS\*
[ ]+104:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0, 0 [ ]+104:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0, 0
[ ]+104: R_LARCH_TLS_IE_PC_HI20[ ]+TLS1 [ ]+104: R_LARCH_TLS_IE_PC_HI20[ ]+TLS1
[ ]+108:[ ]+02c00005[ ]+li.d[ ]+\$a1, 0 [ ]+108:[ ]+02c00005[ ]+li.d[ ]+\$a1, 0

2
ld/testsuite/ld-loongarch-elf/macro_op_32.d
View File

@ -53,8 +53,10 @@ Disassembly of section .text:
44: R_LARCH_TLS_LE_LO12 TLS1 44: R_LARCH_TLS_LE_LO12 TLS1
48: 1a000004 pcalau12i \$a0, 0 48: 1a000004 pcalau12i \$a0, 0
48: R_LARCH_TLS_IE_PC_HI20 TLS1 48: R_LARCH_TLS_IE_PC_HI20 TLS1
48: R_LARCH_RELAX \*ABS\*
4c: 28800084 ld.w \$a0, \$a0, 0 4c: 28800084 ld.w \$a0, \$a0, 0
4c: R_LARCH_TLS_IE_PC_LO12 TLS1 4c: R_LARCH_TLS_IE_PC_LO12 TLS1
4c: R_LARCH_RELAX \*ABS\*
50: 1a000004 pcalau12i \$a0, 0 50: 1a000004 pcalau12i \$a0, 0
50: R_LARCH_TLS_LD_PC_HI20 TLS1 50: R_LARCH_TLS_LD_PC_HI20 TLS1
50: R_LARCH_RELAX \*ABS\* 50: R_LARCH_RELAX \*ABS\*